drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info, size;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         size = EDID_LENGTH * (raw[0x7e] + 1);
 460         edid = kmalloc(size, GFP_KERNEL);
 461         if (edid == NULL)
 462                 return false;
 463
 464         memcpy((unsigned char *)edid, raw, size);
 465
 466         if (!drm_edid_is_valid(edid)) {
 467                 kfree(edid);
 468                 return false;
 469         }
 470
 471         rdev->mode_info.bios_hardcoded_edid = edid;
 472         rdev->mode_info.bios_hardcoded_edid_size = size;
 473         return true;
 474 }
 475
 476 /* this is used for atom LCDs as well */
 477 struct edid *
 478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 479 {
 480         struct edid *edid;
 481
 482         if (rdev->mode_info.bios_hardcoded_edid) {
 483                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 484                 if (edid) {
 485                         memcpy((unsigned char *)edid,
 486                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 487                                rdev->mode_info.bios_hardcoded_edid_size);
 488                         return edid;
 489                 }
 490         }
 491         return NULL;
 492 }
 493
 494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 495                                                        enum radeon_combios_ddc ddc,
 496                                                        u32 clk_mask,
 497                                                        u32 data_mask)
 498 {
 499         struct radeon_i2c_bus_rec i2c;
 500         int ddc_line = 0;
 501
 502         /* ddc id            = mask reg
 503          * DDC_NONE_DETECTED = none
 504          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 505          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 506          * DDC_LCD           = RADEON_GPIOPAD_MASK
 507          * DDC_GPIO          = RADEON_MDGPIO_MASK
 508          * r1xx/r2xx
 509          * DDC_MONID         = RADEON_GPIO_MONID
 510          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 511          * r3xx
 512          * DDC_MONID         = RADEON_GPIO_MONID
 513          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 514          * rs3xx/rs4xx
 515          * DDC_MONID         = RADEON_GPIOPAD_MASK
 516          * DDC_CRT2          = RADEON_GPIO_MONID
 517          */
 518         switch (ddc) {
 519         case DDC_NONE_DETECTED:
 520         default:
 521                 ddc_line = 0;
 522                 break;
 523         case DDC_DVI:
 524                 ddc_line = RADEON_GPIO_DVI_DDC;
 525                 break;
 526         case DDC_VGA:
 527                 ddc_line = RADEON_GPIO_VGA_DDC;
 528                 break;
 529         case DDC_LCD:
 530                 ddc_line = RADEON_GPIOPAD_MASK;
 531                 break;
 532         case DDC_GPIO:
 533                 ddc_line = RADEON_MDGPIO_MASK;
 534                 break;
 535         case DDC_MONID:
 536                 if (rdev->family == CHIP_RS300 ||
 537                     rdev->family == CHIP_RS400 ||
 538                     rdev->family == CHIP_RS480)
 539                         ddc_line = RADEON_GPIOPAD_MASK;
 540                 else
 541                         ddc_line = RADEON_GPIO_MONID;
 542                 break;
 543         case DDC_CRT2:
 544                 if (rdev->family == CHIP_RS300 ||
 545                     rdev->family == CHIP_RS400 ||
 546                     rdev->family == CHIP_RS480)
 547                         ddc_line = RADEON_GPIO_MONID;
 548                 else if (rdev->family >= CHIP_R300) {
 549                         ddc_line = RADEON_GPIO_DVI_DDC;
 550                         ddc = DDC_DVI;
 551                 } else
 552                         ddc_line = RADEON_GPIO_CRT2_DDC;
 553                 break;
 554         }
 555
 556         if (ddc_line == RADEON_GPIOPAD_MASK) {
 557                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 558                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 559                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 560                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 561                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 562                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 563                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 564                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 565         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 566                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 567                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 568                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 569                 i2c.a_data_reg = RADEON_MDGPIO_A;
 570                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 571                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 572                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 573                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 574         } else {
 575                 i2c.mask_clk_reg = ddc_line;
 576                 i2c.mask_data_reg = ddc_line;
 577                 i2c.a_clk_reg = ddc_line;
 578                 i2c.a_data_reg = ddc_line;
 579                 i2c.en_clk_reg = ddc_line;
 580                 i2c.en_data_reg = ddc_line;
 581                 i2c.y_clk_reg = ddc_line;
 582                 i2c.y_data_reg = ddc_line;
 583         }
 584
 585         if (clk_mask && data_mask) {
 586                 /* system specific masks */
 587                 i2c.mask_clk_mask = clk_mask;
 588                 i2c.mask_data_mask = data_mask;
 589                 i2c.a_clk_mask = clk_mask;
 590                 i2c.a_data_mask = data_mask;
 591                 i2c.en_clk_mask = clk_mask;
 592                 i2c.en_data_mask = data_mask;
 593                 i2c.y_clk_mask = clk_mask;
 594                 i2c.y_data_mask = data_mask;
 595         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 596                    (ddc_line == RADEON_MDGPIO_MASK)) {
 597                 /* default gpiopad masks */
 598                 i2c.mask_clk_mask = (0x20 << 8);
 599                 i2c.mask_data_mask = 0x80;
 600                 i2c.a_clk_mask = (0x20 << 8);
 601                 i2c.a_data_mask = 0x80;
 602                 i2c.en_clk_mask = (0x20 << 8);
 603                 i2c.en_data_mask = 0x80;
 604                 i2c.y_clk_mask = (0x20 << 8);
 605                 i2c.y_data_mask = 0x80;
 606         } else {
 607                 /* default masks for ddc pads */
 608                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 609                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 610                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 611                 i2c.a_data_mask = RADEON_GPIO_A_0;
 612                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 613                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 614                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 615                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 616         }
 617
 618         switch (rdev->family) {
 619         case CHIP_R100:
 620         case CHIP_RV100:
 621         case CHIP_RS100:
 622         case CHIP_RV200:
 623         case CHIP_RS200:
 624         case CHIP_RS300:
 625                 switch (ddc_line) {
 626                 case RADEON_GPIO_DVI_DDC:
 627                         i2c.hw_capable = true;
 628                         break;
 629                 default:
 630                         i2c.hw_capable = false;
 631                         break;
 632                 }
 633                 break;
 634         case CHIP_R200:
 635                 switch (ddc_line) {
 636                 case RADEON_GPIO_DVI_DDC:
 637                 case RADEON_GPIO_MONID:
 638                         i2c.hw_capable = true;
 639                         break;
 640                 default:
 641                         i2c.hw_capable = false;
 642                         break;
 643                 }
 644                 break;
 645         case CHIP_RV250:
 646         case CHIP_RV280:
 647                 switch (ddc_line) {
 648                 case RADEON_GPIO_VGA_DDC:
 649                 case RADEON_GPIO_DVI_DDC:
 650                 case RADEON_GPIO_CRT2_DDC:
 651                         i2c.hw_capable = true;
 652                         break;
 653                 default:
 654                         i2c.hw_capable = false;
 655                         break;
 656                 }
 657                 break;
 658         case CHIP_R300:
 659         case CHIP_R350:
 660                 switch (ddc_line) {
 661                 case RADEON_GPIO_VGA_DDC:
 662                 case RADEON_GPIO_DVI_DDC:
 663                         i2c.hw_capable = true;
 664                         break;
 665                 default:
 666                         i2c.hw_capable = false;
 667                         break;
 668                 }
 669                 break;
 670         case CHIP_RV350:
 671         case CHIP_RV380:
 672         case CHIP_RS400:
 673         case CHIP_RS480:
 674                 switch (ddc_line) {
 675                 case RADEON_GPIO_VGA_DDC:
 676                 case RADEON_GPIO_DVI_DDC:
 677                         i2c.hw_capable = true;
 678                         break;
 679                 case RADEON_GPIO_MONID:
 680                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 681                          * reliably on some pre-r4xx hardware; not sure why.
 682                          */
 683                         i2c.hw_capable = false;
 684                         break;
 685                 default:
 686                         i2c.hw_capable = false;
 687                         break;
 688                 }
 689                 break;
 690         default:
 691                 i2c.hw_capable = false;
 692                 break;
 693         }
 694         i2c.mm_i2c = false;
 695
 696         i2c.i2c_id = ddc;
 697         i2c.hpd = RADEON_HPD_NONE;
 698
 699         if (ddc_line)
 700                 i2c.valid = true;
 701         else
 702                 i2c.valid = false;
 703
 704         return i2c;
 705 }
 706
 707 void radeon_combios_i2c_init(struct radeon_device *rdev)
 708 {
 709         struct drm_device *dev = rdev->ddev;
 710         struct radeon_i2c_bus_rec i2c;
 711
 712
 713         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 714         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 715
 716         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 717         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 718
 719         i2c.valid = true;
 720         i2c.hw_capable = true;
 721         i2c.mm_i2c = true;
 722         i2c.i2c_id = 0xa0;
 723         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 724
 725         if (rdev->family == CHIP_RS300 ||
 726             rdev->family == CHIP_RS400 ||
 727             rdev->family == CHIP_RS480) {
 728                 u16 offset;
 729                 u8 id, blocks, clk, data;
 730                 int i;
 731
 732                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 733                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 734
 735                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 736                 if (offset) {
 737                         blocks = RBIOS8(offset + 2);
 738                         for (i = 0; i < blocks; i++) {
 739                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 740                                 if (id == 136) {
 741                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 742                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 743                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 744                                                                     (1 << clk), (1 << data));
 745                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 746                                         break;
 747                                 }
 748                         }
 749                 }
 750
 751         } else if (rdev->family >= CHIP_R300) {
 752                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 753                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 754         } else {
 755                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 756                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 757
 758                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 759                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 760         }
 761 }
 762
 763 bool radeon_combios_get_clock_info(struct drm_device *dev)
 764 {
 765         struct radeon_device *rdev = dev->dev_private;
 766         uint16_t pll_info;
 767         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 768         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 769         struct radeon_pll *spll = &rdev->clock.spll;
 770         struct radeon_pll *mpll = &rdev->clock.mpll;
 771         int8_t rev;
 772         uint16_t sclk, mclk;
 773
 774         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 775         if (pll_info) {
 776                 rev = RBIOS8(pll_info);
 777
 778                 /* pixel clocks */
 779                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 780                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 781                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 782                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 783                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 784                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 785
 786                 if (rev > 9) {
 787                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 788                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 789                 } else {
 790                         p1pll->pll_in_min = 40;
 791                         p1pll->pll_in_max = 500;
 792                 }
 793                 *p2pll = *p1pll;
 794
 795                 /* system clock */
 796                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 797                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 798                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 799                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 800
 801                 if (rev > 10) {
 802                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 803                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 804                 } else {
 805                         /* ??? */
 806                         spll->pll_in_min = 40;
 807                         spll->pll_in_max = 500;
 808                 }
 809
 810                 /* memory clock */
 811                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 812                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 813                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 814                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 815
 816                 if (rev > 10) {
 817                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 818                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 819                 } else {
 820                         /* ??? */
 821                         mpll->pll_in_min = 40;
 822                         mpll->pll_in_max = 500;
 823                 }
 824
 825                 /* default sclk/mclk */
 826                 sclk = RBIOS16(pll_info + 0xa);
 827                 mclk = RBIOS16(pll_info + 0x8);
 828                 if (sclk == 0)
 829                         sclk = 200 * 100;
 830                 if (mclk == 0)
 831                         mclk = 200 * 100;
 832
 833                 rdev->clock.default_sclk = sclk;
 834                 rdev->clock.default_mclk = mclk;
 835
 836                 return true;
 837         }
 838         return false;
 839 }
 840
 841 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 842 {
 843         struct drm_device *dev = rdev->ddev;
 844         u16 igp_info;
 845
 846         /* sideport is AMD only */
 847         if (rdev->family == CHIP_RS400)
 848                 return false;
 849
 850         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 851
 852         if (igp_info) {
 853                 if (RBIOS16(igp_info + 0x4))
 854                         return true;
 855         }
 856         return false;
 857 }
 858
 859 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 860         0x00000808,             /* r100  */
 861         0x00000808,             /* rv100 */
 862         0x00000808,             /* rs100 */
 863         0x00000808,             /* rv200 */
 864         0x00000808,             /* rs200 */
 865         0x00000808,             /* r200  */
 866         0x00000808,             /* rv250 */
 867         0x00000000,             /* rs300 */
 868         0x00000808,             /* rv280 */
 869         0x00000808,             /* r300  */
 870         0x00000808,             /* r350  */
 871         0x00000808,             /* rv350 */
 872         0x00000808,             /* rv380 */
 873         0x00000808,             /* r420  */
 874         0x00000808,             /* r423  */
 875         0x00000808,             /* rv410 */
 876         0x00000000,             /* rs400 */
 877         0x00000000,             /* rs480 */
 878 };
 879
 880 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 881                                                           struct radeon_encoder_primary_dac *p_dac)
 882 {
 883         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 884         return;
 885 }
 886
 887 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 888                                                                        radeon_encoder
 889                                                                        *encoder)
 890 {
 891         struct drm_device *dev = encoder->base.dev;
 892         struct radeon_device *rdev = dev->dev_private;
 893         uint16_t dac_info;
 894         uint8_t rev, bg, dac;
 895         struct radeon_encoder_primary_dac *p_dac = NULL;
 896         int found = 0;
 897
 898         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 899                         GFP_KERNEL);
 900
 901         if (!p_dac)
 902                 return NULL;
 903
 904         /* check CRT table */
 905         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 906         if (dac_info) {
 907                 rev = RBIOS8(dac_info) & 0x3;
 908                 if (rev < 2) {
 909                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 910                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 911                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 912                 } else {
 913                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 914                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 915                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 916                 }
 917                 /* if the values are all zeros, use the table */
 918                 if (p_dac->ps2_pdac_adj)
 919                         found = 1;
 920         }
 921
 922         if (!found) /* fallback to defaults */
 923                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 924
 925         return p_dac;
 926 }
 927
 928 enum radeon_tv_std
 929 radeon_combios_get_tv_info(struct radeon_device *rdev)
 930 {
 931         struct drm_device *dev = rdev->ddev;
 932         uint16_t tv_info;
 933         enum radeon_tv_std tv_std = TV_STD_NTSC;
 934
 935         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 936         if (tv_info) {
 937                 if (RBIOS8(tv_info + 6) == 'T') {
 938                         switch (RBIOS8(tv_info + 7) & 0xf) {
 939                         case 1:
 940                                 tv_std = TV_STD_NTSC;
 941                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 942                                 break;
 943                         case 2:
 944                                 tv_std = TV_STD_PAL;
 945                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 946                                 break;
 947                         case 3:
 948                                 tv_std = TV_STD_PAL_M;
 949                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 950                                 break;
 951                         case 4:
 952                                 tv_std = TV_STD_PAL_60;
 953                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 954                                 break;
 955                         case 5:
 956                                 tv_std = TV_STD_NTSC_J;
 957                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 958                                 break;
 959                         case 6:
 960                                 tv_std = TV_STD_SCART_PAL;
 961                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 962                                 break;
 963                         default:
 964                                 tv_std = TV_STD_NTSC;
 965                                 DRM_DEBUG_KMS
 966                                     ("Unknown TV standard; defaulting to NTSC\n");
 967                                 break;
 968                         }
 969
 970                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 971                         case 0:
 972                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 973                                 break;
 974                         case 1:
 975                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 976                                 break;
 977                         case 2:
 978                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 979                                 break;
 980                         case 3:
 981                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 982                                 break;
 983                         default:
 984                                 break;
 985                         }
 986                 }
 987         }
 988         return tv_std;
 989 }
 990
 991 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 992         0x00000000,             /* r100  */
 993         0x00280000,             /* rv100 */
 994         0x00000000,             /* rs100 */
 995         0x00880000,             /* rv200 */
 996         0x00000000,             /* rs200 */
 997         0x00000000,             /* r200  */
 998         0x00770000,             /* rv250 */
 999         0x00290000,             /* rs300 */
1000         0x00560000,             /* rv280 */
1001         0x00780000,             /* r300  */
1002         0x00770000,             /* r350  */
1003         0x00780000,             /* rv350 */
1004         0x00780000,             /* rv380 */
1005         0x01080000,             /* r420  */
1006         0x01080000,             /* r423  */
1007         0x01080000,             /* rv410 */
1008         0x00780000,             /* rs400 */
1009         0x00780000,             /* rs480 */
1010 };
1011
1012 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1013                                                      struct radeon_encoder_tv_dac *tv_dac)
1014 {
1015         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1016         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1017                 tv_dac->ps2_tvdac_adj = 0x00880000;
1018         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1019         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1020         return;
1021 }
1022
1023 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1024                                                              radeon_encoder
1025                                                              *encoder)
1026 {
1027         struct drm_device *dev = encoder->base.dev;
1028         struct radeon_device *rdev = dev->dev_private;
1029         uint16_t dac_info;
1030         uint8_t rev, bg, dac;
1031         struct radeon_encoder_tv_dac *tv_dac = NULL;
1032         int found = 0;
1033
1034         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1035         if (!tv_dac)
1036                 return NULL;
1037
1038         /* first check TV table */
1039         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1040         if (dac_info) {
1041                 rev = RBIOS8(dac_info + 0x3);
1042                 if (rev > 4) {
1043                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1044                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1045                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1046
1047                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1048                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1049                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1050
1051                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1052                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1053                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1054                         /* if the values are all zeros, use the table */
1055                         if (tv_dac->ps2_tvdac_adj)
1056                                 found = 1;
1057                 } else if (rev > 1) {
1058                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1059                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1060                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1061
1062                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1063                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1064                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1065
1066                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1067                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1068                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1069                         /* if the values are all zeros, use the table */
1070                         if (tv_dac->ps2_tvdac_adj)
1071                                 found = 1;
1072                 }
1073                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1074         }
1075         if (!found) {
1076                 /* then check CRT table */
1077                 dac_info =
1078                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1079                 if (dac_info) {
1080                         rev = RBIOS8(dac_info) & 0x3;
1081                         if (rev < 2) {
1082                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1083                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1084                                 tv_dac->ps2_tvdac_adj =
1085                                     (bg << 16) | (dac << 20);
1086                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1088                                 /* if the values are all zeros, use the table */
1089                                 if (tv_dac->ps2_tvdac_adj)
1090                                         found = 1;
1091                         } else {
1092                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1093                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1094                                 tv_dac->ps2_tvdac_adj =
1095                                     (bg << 16) | (dac << 20);
1096                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1097                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1098                                 /* if the values are all zeros, use the table */
1099                                 if (tv_dac->ps2_tvdac_adj)
1100                                         found = 1;
1101                         }
1102                 } else {
1103                         DRM_INFO("No TV DAC info found in BIOS\n");
1104                 }
1105         }
1106
1107         if (!found) /* fallback to defaults */
1108                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1109
1110         return tv_dac;
1111 }
1112
1113 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1114                                                                          radeon_device
1115                                                                          *rdev)
1116 {
1117         struct radeon_encoder_lvds *lvds = NULL;
1118         uint32_t fp_vert_stretch, fp_horz_stretch;
1119         uint32_t ppll_div_sel, ppll_val;
1120         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1121
1122         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1123
1124         if (!lvds)
1125                 return NULL;
1126
1127         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1128         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1129
1130         /* These should be fail-safe defaults, fingers crossed */
1131         lvds->panel_pwr_delay = 200;
1132         lvds->panel_vcc_delay = 2000;
1133
1134         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1135         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1136         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1137
1138         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1139                 lvds->native_mode.vdisplay =
1140                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1141                      RADEON_VERT_PANEL_SHIFT) + 1;
1142         else
1143                 lvds->native_mode.vdisplay =
1144                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1145
1146         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1147                 lvds->native_mode.hdisplay =
1148                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1149                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1150         else
1151                 lvds->native_mode.hdisplay =
1152                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1153
1154         if ((lvds->native_mode.hdisplay < 640) ||
1155             (lvds->native_mode.vdisplay < 480)) {
1156                 lvds->native_mode.hdisplay = 640;
1157                 lvds->native_mode.vdisplay = 480;
1158         }
1159
1160         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1161         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1162         if ((ppll_val & 0x000707ff) == 0x1bb)
1163                 lvds->use_bios_dividers = false;
1164         else {
1165                 lvds->panel_ref_divider =
1166                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1167                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1168                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1169
1170                 if ((lvds->panel_ref_divider != 0) &&
1171                     (lvds->panel_fb_divider > 3))
1172                         lvds->use_bios_dividers = true;
1173         }
1174         lvds->panel_vcc_delay = 200;
1175
1176         DRM_INFO("Panel info derived from registers\n");
1177         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1178                  lvds->native_mode.vdisplay);
1179
1180         return lvds;
1181 }
1182
1183 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1184                                                          *encoder)
1185 {
1186         struct drm_device *dev = encoder->base.dev;
1187         struct radeon_device *rdev = dev->dev_private;
1188         uint16_t lcd_info;
1189         uint32_t panel_setup;
1190         char stmp[30];
1191         int tmp, i;
1192         struct radeon_encoder_lvds *lvds = NULL;
1193
1194         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1195
1196         if (lcd_info) {
1197                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1198
1199                 if (!lvds)
1200                         return NULL;
1201
1202                 for (i = 0; i < 24; i++)
1203                         stmp[i] = RBIOS8(lcd_info + i + 1);
1204                 stmp[24] = 0;
1205
1206                 DRM_INFO("Panel ID String: %s\n", stmp);
1207
1208                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1209                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1210
1211                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1212                          lvds->native_mode.vdisplay);
1213
1214                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1215                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1216
1217                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1218                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1219                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1220
1221                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1222                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1223                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1224                 if ((lvds->panel_ref_divider != 0) &&
1225                     (lvds->panel_fb_divider > 3))
1226                         lvds->use_bios_dividers = true;
1227
1228                 panel_setup = RBIOS32(lcd_info + 0x39);
1229                 lvds->lvds_gen_cntl = 0xff00;
1230                 if (panel_setup & 0x1)
1231                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1232
1233                 if ((panel_setup >> 4) & 0x1)
1234                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1235
1236                 switch ((panel_setup >> 8) & 0x7) {
1237                 case 0:
1238                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1239                         break;
1240                 case 1:
1241                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1242                         break;
1243                 case 2:
1244                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1245                         break;
1246                 default:
1247                         break;
1248                 }
1249
1250                 if ((panel_setup >> 16) & 0x1)
1251                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1252
1253                 if ((panel_setup >> 17) & 0x1)
1254                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1255
1256                 if ((panel_setup >> 18) & 0x1)
1257                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1258
1259                 if ((panel_setup >> 23) & 0x1)
1260                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1261
1262                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1263
1264                 for (i = 0; i < 32; i++) {
1265                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1266                         if (tmp == 0)
1267                                 break;
1268
1269                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1270                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1271                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1272                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1273                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1274                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1275                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1276                                         (RBIOS8(tmp + 23) * 8);
1277
1278                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1279                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1280                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1281                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1282                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1283                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1284
1285                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1286                                 lvds->native_mode.flags = 0;
1287                                 /* set crtc values */
1288                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1289
1290                         }
1291                 }
1292         } else {
1293                 DRM_INFO("No panel info found in BIOS\n");
1294                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1295         }
1296
1297         if (lvds)
1298                 encoder->native_mode = lvds->native_mode;
1299         return lvds;
1300 }
1301
1302 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1303         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1304         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1305         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1306         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1307         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1308         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1309         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1310         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1311         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1312         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1313         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1314         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1315         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1316         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1317         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1318         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1319         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1320         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1321 };
1322
1323 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1324                                             struct radeon_encoder_int_tmds *tmds)
1325 {
1326         struct drm_device *dev = encoder->base.dev;
1327         struct radeon_device *rdev = dev->dev_private;
1328         int i;
1329
1330         for (i = 0; i < 4; i++) {
1331                 tmds->tmds_pll[i].value =
1332                         default_tmds_pll[rdev->family][i].value;
1333                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1334         }
1335
1336         return true;
1337 }
1338
1339 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1340                                               struct radeon_encoder_int_tmds *tmds)
1341 {
1342         struct drm_device *dev = encoder->base.dev;
1343         struct radeon_device *rdev = dev->dev_private;
1344         uint16_t tmds_info;
1345         int i, n;
1346         uint8_t ver;
1347
1348         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1349
1350         if (tmds_info) {
1351                 ver = RBIOS8(tmds_info);
1352                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1353                 if (ver == 3) {
1354                         n = RBIOS8(tmds_info + 5) + 1;
1355                         if (n > 4)
1356                                 n = 4;
1357                         for (i = 0; i < n; i++) {
1358                                 tmds->tmds_pll[i].value =
1359                                     RBIOS32(tmds_info + i * 10 + 0x08);
1360                                 tmds->tmds_pll[i].freq =
1361                                     RBIOS16(tmds_info + i * 10 + 0x10);
1362                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1363                                           tmds->tmds_pll[i].freq,
1364                                           tmds->tmds_pll[i].value);
1365                         }
1366                 } else if (ver == 4) {
1367                         int stride = 0;
1368                         n = RBIOS8(tmds_info + 5) + 1;
1369                         if (n > 4)
1370                                 n = 4;
1371                         for (i = 0; i < n; i++) {
1372                                 tmds->tmds_pll[i].value =
1373                                     RBIOS32(tmds_info + stride + 0x08);
1374                                 tmds->tmds_pll[i].freq =
1375                                     RBIOS16(tmds_info + stride + 0x10);
1376                                 if (i == 0)
1377                                         stride += 10;
1378                                 else
1379                                         stride += 6;
1380                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1381                                           tmds->tmds_pll[i].freq,
1382                                           tmds->tmds_pll[i].value);
1383                         }
1384                 }
1385         } else {
1386                 DRM_INFO("No TMDS info found in BIOS\n");
1387                 return false;
1388         }
1389         return true;
1390 }
1391
1392 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1393                                                 struct radeon_encoder_ext_tmds *tmds)
1394 {
1395         struct drm_device *dev = encoder->base.dev;
1396         struct radeon_device *rdev = dev->dev_private;
1397         struct radeon_i2c_bus_rec i2c_bus;
1398
1399         /* default for macs */
1400         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1401         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1402
1403         /* XXX some macs have duallink chips */
1404         switch (rdev->mode_info.connector_table) {
1405         case CT_POWERBOOK_EXTERNAL:
1406         case CT_MINI_EXTERNAL:
1407         default:
1408                 tmds->dvo_chip = DVO_SIL164;
1409                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1410                 break;
1411         }
1412
1413         return true;
1414 }
1415
1416 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1417                                                   struct radeon_encoder_ext_tmds *tmds)
1418 {
1419         struct drm_device *dev = encoder->base.dev;
1420         struct radeon_device *rdev = dev->dev_private;
1421         uint16_t offset;
1422         uint8_t ver;
1423         enum radeon_combios_ddc gpio;
1424         struct radeon_i2c_bus_rec i2c_bus;
1425
1426         tmds->i2c_bus = NULL;
1427         if (rdev->flags & RADEON_IS_IGP) {
1428                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1429                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1430                 tmds->dvo_chip = DVO_SIL164;
1431                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1432         } else {
1433                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1434                 if (offset) {
1435                         ver = RBIOS8(offset);
1436                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1437                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1438                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1439                         gpio = RBIOS8(offset + 4 + 3);
1440                         if (gpio == DDC_LCD) {
1441                                 /* MM i2c */
1442                                 i2c_bus.valid = true;
1443                                 i2c_bus.hw_capable = true;
1444                                 i2c_bus.mm_i2c = true;
1445                                 i2c_bus.i2c_id = 0xa0;
1446                         } else
1447                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1448                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1449                 }
1450         }
1451
1452         if (!tmds->i2c_bus) {
1453                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1454                 return false;
1455         }
1456
1457         return true;
1458 }
1459
1460 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1461 {
1462         struct radeon_device *rdev = dev->dev_private;
1463         struct radeon_i2c_bus_rec ddc_i2c;
1464         struct radeon_hpd hpd;
1465
1466         rdev->mode_info.connector_table = radeon_connector_table;
1467         if (rdev->mode_info.connector_table == CT_NONE) {
1468 #ifdef CONFIG_PPC_PMAC
1469                 if (of_machine_is_compatible("PowerBook3,3")) {
1470                         /* powerbook with VGA */
1471                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1472                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1473                            of_machine_is_compatible("PowerBook3,5")) {
1474                         /* powerbook with internal tmds */
1475                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1476                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1477                            of_machine_is_compatible("PowerBook5,2") ||
1478                            of_machine_is_compatible("PowerBook5,3") ||
1479                            of_machine_is_compatible("PowerBook5,4") ||
1480                            of_machine_is_compatible("PowerBook5,5")) {
1481                         /* powerbook with external single link tmds (sil164) */
1482                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1483                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1484                         /* powerbook with external dual or single link tmds */
1485                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1486                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1487                            of_machine_is_compatible("PowerBook5,8") ||
1488                            of_machine_is_compatible("PowerBook5,9")) {
1489                         /* PowerBook6,2 ? */
1490                         /* powerbook with external dual link tmds (sil1178?) */
1491                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1492                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1493                            of_machine_is_compatible("PowerBook4,2") ||
1494                            of_machine_is_compatible("PowerBook4,3") ||
1495                            of_machine_is_compatible("PowerBook6,3") ||
1496                            of_machine_is_compatible("PowerBook6,5") ||
1497                            of_machine_is_compatible("PowerBook6,7")) {
1498                         /* ibook */
1499                         rdev->mode_info.connector_table = CT_IBOOK;
1500                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1501                         /* emac */
1502                         rdev->mode_info.connector_table = CT_EMAC;
1503                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1504                         /* mini with internal tmds */
1505                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1506                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1507                         /* mini with external tmds */
1508                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1509                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1510                         /* PowerMac8,1 ? */
1511                         /* imac g5 isight */
1512                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1513                 } else if ((rdev->pdev->device == 0x4a48) &&
1514                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1515                            (rdev->pdev->subsystem_device == 0x4a48)) {
1516                         /* Mac X800 */
1517                         rdev->mode_info.connector_table = CT_MAC_X800;
1518                 } else if ((rdev->pdev->device == 0x4150) &&
1519                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1520                            (rdev->pdev->subsystem_device == 0x4150)) {
1521                         /* Mac G5 9600 */
1522                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1523                 } else
1524 #endif /* CONFIG_PPC_PMAC */
1525 #ifdef CONFIG_PPC64
1526                 if (ASIC_IS_RN50(rdev))
1527                         rdev->mode_info.connector_table = CT_RN50_POWER;
1528                 else
1529 #endif
1530                         rdev->mode_info.connector_table = CT_GENERIC;
1531         }
1532
1533         switch (rdev->mode_info.connector_table) {
1534         case CT_GENERIC:
1535                 DRM_INFO("Connector Table: %d (generic)\n",
1536                          rdev->mode_info.connector_table);
1537                 /* these are the most common settings */
1538                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1539                         /* VGA - primary dac */
1540                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1541                         hpd.hpd = RADEON_HPD_NONE;
1542                         radeon_add_legacy_encoder(dev,
1543                                                   radeon_get_encoder_enum(dev,
1544                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1545                                                                         1),
1546                                                   ATOM_DEVICE_CRT1_SUPPORT);
1547                         radeon_add_legacy_connector(dev, 0,
1548                                                     ATOM_DEVICE_CRT1_SUPPORT,
1549                                                     DRM_MODE_CONNECTOR_VGA,
1550                                                     &ddc_i2c,
1551                                                     CONNECTOR_OBJECT_ID_VGA,
1552                                                     &hpd);
1553                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1554                         /* LVDS */
1555                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1556                         hpd.hpd = RADEON_HPD_NONE;
1557                         radeon_add_legacy_encoder(dev,
1558                                                   radeon_get_encoder_enum(dev,
1559                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1560                                                                         0),
1561                                                   ATOM_DEVICE_LCD1_SUPPORT);
1562                         radeon_add_legacy_connector(dev, 0,
1563                                                     ATOM_DEVICE_LCD1_SUPPORT,
1564                                                     DRM_MODE_CONNECTOR_LVDS,
1565                                                     &ddc_i2c,
1566                                                     CONNECTOR_OBJECT_ID_LVDS,
1567                                                     &hpd);
1568
1569                         /* VGA - primary dac */
1570                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1571                         hpd.hpd = RADEON_HPD_NONE;
1572                         radeon_add_legacy_encoder(dev,
1573                                                   radeon_get_encoder_enum(dev,
1574                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1575                                                                         1),
1576                                                   ATOM_DEVICE_CRT1_SUPPORT);
1577                         radeon_add_legacy_connector(dev, 1,
1578                                                     ATOM_DEVICE_CRT1_SUPPORT,
1579                                                     DRM_MODE_CONNECTOR_VGA,
1580                                                     &ddc_i2c,
1581                                                     CONNECTOR_OBJECT_ID_VGA,
1582                                                     &hpd);
1583                 } else {
1584                         /* DVI-I - tv dac, int tmds */
1585                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1586                         hpd.hpd = RADEON_HPD_1;
1587                         radeon_add_legacy_encoder(dev,
1588                                                   radeon_get_encoder_enum(dev,
1589                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1590                                                                         0),
1591                                                   ATOM_DEVICE_DFP1_SUPPORT);
1592                         radeon_add_legacy_encoder(dev,
1593                                                   radeon_get_encoder_enum(dev,
1594                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1595                                                                         2),
1596                                                   ATOM_DEVICE_CRT2_SUPPORT);
1597                         radeon_add_legacy_connector(dev, 0,
1598                                                     ATOM_DEVICE_DFP1_SUPPORT |
1599                                                     ATOM_DEVICE_CRT2_SUPPORT,
1600                                                     DRM_MODE_CONNECTOR_DVII,
1601                                                     &ddc_i2c,
1602                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1603                                                     &hpd);
1604
1605                         /* VGA - primary dac */
1606                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1607                         hpd.hpd = RADEON_HPD_NONE;
1608                         radeon_add_legacy_encoder(dev,
1609                                                   radeon_get_encoder_enum(dev,
1610                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1611                                                                         1),
1612                                                   ATOM_DEVICE_CRT1_SUPPORT);
1613                         radeon_add_legacy_connector(dev, 1,
1614                                                     ATOM_DEVICE_CRT1_SUPPORT,
1615                                                     DRM_MODE_CONNECTOR_VGA,
1616                                                     &ddc_i2c,
1617                                                     CONNECTOR_OBJECT_ID_VGA,
1618                                                     &hpd);
1619                 }
1620
1621                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1622                         /* TV - tv dac */
1623                         ddc_i2c.valid = false;
1624                         hpd.hpd = RADEON_HPD_NONE;
1625                         radeon_add_legacy_encoder(dev,
1626                                                   radeon_get_encoder_enum(dev,
1627                                                                         ATOM_DEVICE_TV1_SUPPORT,
1628                                                                         2),
1629                                                   ATOM_DEVICE_TV1_SUPPORT);
1630                         radeon_add_legacy_connector(dev, 2,
1631                                                     ATOM_DEVICE_TV1_SUPPORT,
1632                                                     DRM_MODE_CONNECTOR_SVIDEO,
1633                                                     &ddc_i2c,
1634                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1635                                                     &hpd);
1636                 }
1637                 break;
1638         case CT_IBOOK:
1639                 DRM_INFO("Connector Table: %d (ibook)\n",
1640                          rdev->mode_info.connector_table);
1641                 /* LVDS */
1642                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1643                 hpd.hpd = RADEON_HPD_NONE;
1644                 radeon_add_legacy_encoder(dev,
1645                                           radeon_get_encoder_enum(dev,
1646                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1647                                                                 0),
1648                                           ATOM_DEVICE_LCD1_SUPPORT);
1649                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1650                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1651                                             CONNECTOR_OBJECT_ID_LVDS,
1652                                             &hpd);
1653                 /* VGA - TV DAC */
1654                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1655                 hpd.hpd = RADEON_HPD_NONE;
1656                 radeon_add_legacy_encoder(dev,
1657                                           radeon_get_encoder_enum(dev,
1658                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1659                                                                 2),
1660                                           ATOM_DEVICE_CRT2_SUPPORT);
1661                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1662                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1663                                             CONNECTOR_OBJECT_ID_VGA,
1664                                             &hpd);
1665                 /* TV - TV DAC */
1666                 ddc_i2c.valid = false;
1667                 hpd.hpd = RADEON_HPD_NONE;
1668                 radeon_add_legacy_encoder(dev,
1669                                           radeon_get_encoder_enum(dev,
1670                                                                 ATOM_DEVICE_TV1_SUPPORT,
1671                                                                 2),
1672                                           ATOM_DEVICE_TV1_SUPPORT);
1673                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1674                                             DRM_MODE_CONNECTOR_SVIDEO,
1675                                             &ddc_i2c,
1676                                             CONNECTOR_OBJECT_ID_SVIDEO,
1677                                             &hpd);
1678                 break;
1679         case CT_POWERBOOK_EXTERNAL:
1680                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1681                          rdev->mode_info.connector_table);
1682                 /* LVDS */
1683                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1684                 hpd.hpd = RADEON_HPD_NONE;
1685                 radeon_add_legacy_encoder(dev,
1686                                           radeon_get_encoder_enum(dev,
1687                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1688                                                                 0),
1689                                           ATOM_DEVICE_LCD1_SUPPORT);
1690                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1691                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1692                                             CONNECTOR_OBJECT_ID_LVDS,
1693                                             &hpd);
1694                 /* DVI-I - primary dac, ext tmds */
1695                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1696                 hpd.hpd = RADEON_HPD_2; /* ??? */
1697                 radeon_add_legacy_encoder(dev,
1698                                           radeon_get_encoder_enum(dev,
1699                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1700                                                                 0),
1701                                           ATOM_DEVICE_DFP2_SUPPORT);
1702                 radeon_add_legacy_encoder(dev,
1703                                           radeon_get_encoder_enum(dev,
1704                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1705                                                                 1),
1706                                           ATOM_DEVICE_CRT1_SUPPORT);
1707                 /* XXX some are SL */
1708                 radeon_add_legacy_connector(dev, 1,
1709                                             ATOM_DEVICE_DFP2_SUPPORT |
1710                                             ATOM_DEVICE_CRT1_SUPPORT,
1711                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1712                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1713                                             &hpd);
1714                 /* TV - TV DAC */
1715                 ddc_i2c.valid = false;
1716                 hpd.hpd = RADEON_HPD_NONE;
1717                 radeon_add_legacy_encoder(dev,
1718                                           radeon_get_encoder_enum(dev,
1719                                                                 ATOM_DEVICE_TV1_SUPPORT,
1720                                                                 2),
1721                                           ATOM_DEVICE_TV1_SUPPORT);
1722                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1723                                             DRM_MODE_CONNECTOR_SVIDEO,
1724                                             &ddc_i2c,
1725                                             CONNECTOR_OBJECT_ID_SVIDEO,
1726                                             &hpd);
1727                 break;
1728         case CT_POWERBOOK_INTERNAL:
1729                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1730                          rdev->mode_info.connector_table);
1731                 /* LVDS */
1732                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1733                 hpd.hpd = RADEON_HPD_NONE;
1734                 radeon_add_legacy_encoder(dev,
1735                                           radeon_get_encoder_enum(dev,
1736                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1737                                                                 0),
1738                                           ATOM_DEVICE_LCD1_SUPPORT);
1739                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1740                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1741                                             CONNECTOR_OBJECT_ID_LVDS,
1742                                             &hpd);
1743                 /* DVI-I - primary dac, int tmds */
1744                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1745                 hpd.hpd = RADEON_HPD_1; /* ??? */
1746                 radeon_add_legacy_encoder(dev,
1747                                           radeon_get_encoder_enum(dev,
1748                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1749                                                                 0),
1750                                           ATOM_DEVICE_DFP1_SUPPORT);
1751                 radeon_add_legacy_encoder(dev,
1752                                           radeon_get_encoder_enum(dev,
1753                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1754                                                                 1),
1755                                           ATOM_DEVICE_CRT1_SUPPORT);
1756                 radeon_add_legacy_connector(dev, 1,
1757                                             ATOM_DEVICE_DFP1_SUPPORT |
1758                                             ATOM_DEVICE_CRT1_SUPPORT,
1759                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1760                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1761                                             &hpd);
1762                 /* TV - TV DAC */
1763                 ddc_i2c.valid = false;
1764                 hpd.hpd = RADEON_HPD_NONE;
1765                 radeon_add_legacy_encoder(dev,
1766                                           radeon_get_encoder_enum(dev,
1767                                                                 ATOM_DEVICE_TV1_SUPPORT,
1768                                                                 2),
1769                                           ATOM_DEVICE_TV1_SUPPORT);
1770                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1771                                             DRM_MODE_CONNECTOR_SVIDEO,
1772                                             &ddc_i2c,
1773                                             CONNECTOR_OBJECT_ID_SVIDEO,
1774                                             &hpd);
1775                 break;
1776         case CT_POWERBOOK_VGA:
1777                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1778                          rdev->mode_info.connector_table);
1779                 /* LVDS */
1780                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1781                 hpd.hpd = RADEON_HPD_NONE;
1782                 radeon_add_legacy_encoder(dev,
1783                                           radeon_get_encoder_enum(dev,
1784                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1785                                                                 0),
1786                                           ATOM_DEVICE_LCD1_SUPPORT);
1787                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1788                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1789                                             CONNECTOR_OBJECT_ID_LVDS,
1790                                             &hpd);
1791                 /* VGA - primary dac */
1792                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1793                 hpd.hpd = RADEON_HPD_NONE;
1794                 radeon_add_legacy_encoder(dev,
1795                                           radeon_get_encoder_enum(dev,
1796                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1797                                                                 1),
1798                                           ATOM_DEVICE_CRT1_SUPPORT);
1799                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1800                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1801                                             CONNECTOR_OBJECT_ID_VGA,
1802                                             &hpd);
1803                 /* TV - TV DAC */
1804                 ddc_i2c.valid = false;
1805                 hpd.hpd = RADEON_HPD_NONE;
1806                 radeon_add_legacy_encoder(dev,
1807                                           radeon_get_encoder_enum(dev,
1808                                                                 ATOM_DEVICE_TV1_SUPPORT,
1809                                                                 2),
1810                                           ATOM_DEVICE_TV1_SUPPORT);
1811                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1812                                             DRM_MODE_CONNECTOR_SVIDEO,
1813                                             &ddc_i2c,
1814                                             CONNECTOR_OBJECT_ID_SVIDEO,
1815                                             &hpd);
1816                 break;
1817         case CT_MINI_EXTERNAL:
1818                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1819                          rdev->mode_info.connector_table);
1820                 /* DVI-I - tv dac, ext tmds */
1821                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1822                 hpd.hpd = RADEON_HPD_2; /* ??? */
1823                 radeon_add_legacy_encoder(dev,
1824                                           radeon_get_encoder_enum(dev,
1825                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1826                                                                 0),
1827                                           ATOM_DEVICE_DFP2_SUPPORT);
1828                 radeon_add_legacy_encoder(dev,
1829                                           radeon_get_encoder_enum(dev,
1830                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1831                                                                 2),
1832                                           ATOM_DEVICE_CRT2_SUPPORT);
1833                 /* XXX are any DL? */
1834                 radeon_add_legacy_connector(dev, 0,
1835                                             ATOM_DEVICE_DFP2_SUPPORT |
1836                                             ATOM_DEVICE_CRT2_SUPPORT,
1837                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1838                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1839                                             &hpd);
1840                 /* TV - TV DAC */
1841                 ddc_i2c.valid = false;
1842                 hpd.hpd = RADEON_HPD_NONE;
1843                 radeon_add_legacy_encoder(dev,
1844                                           radeon_get_encoder_enum(dev,
1845                                                                 ATOM_DEVICE_TV1_SUPPORT,
1846                                                                 2),
1847                                           ATOM_DEVICE_TV1_SUPPORT);
1848                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1849                                             DRM_MODE_CONNECTOR_SVIDEO,
1850                                             &ddc_i2c,
1851                                             CONNECTOR_OBJECT_ID_SVIDEO,
1852                                             &hpd);
1853                 break;
1854         case CT_MINI_INTERNAL:
1855                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1856                          rdev->mode_info.connector_table);
1857                 /* DVI-I - tv dac, int tmds */
1858                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1859                 hpd.hpd = RADEON_HPD_1; /* ??? */
1860                 radeon_add_legacy_encoder(dev,
1861                                           radeon_get_encoder_enum(dev,
1862                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1863                                                                 0),
1864                                           ATOM_DEVICE_DFP1_SUPPORT);
1865                 radeon_add_legacy_encoder(dev,
1866                                           radeon_get_encoder_enum(dev,
1867                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1868                                                                 2),
1869                                           ATOM_DEVICE_CRT2_SUPPORT);
1870                 radeon_add_legacy_connector(dev, 0,
1871                                             ATOM_DEVICE_DFP1_SUPPORT |
1872                                             ATOM_DEVICE_CRT2_SUPPORT,
1873                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1874                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1875                                             &hpd);
1876                 /* TV - TV DAC */
1877                 ddc_i2c.valid = false;
1878                 hpd.hpd = RADEON_HPD_NONE;
1879                 radeon_add_legacy_encoder(dev,
1880                                           radeon_get_encoder_enum(dev,
1881                                                                 ATOM_DEVICE_TV1_SUPPORT,
1882                                                                 2),
1883                                           ATOM_DEVICE_TV1_SUPPORT);
1884                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1885                                             DRM_MODE_CONNECTOR_SVIDEO,
1886                                             &ddc_i2c,
1887                                             CONNECTOR_OBJECT_ID_SVIDEO,
1888                                             &hpd);
1889                 break;
1890         case CT_IMAC_G5_ISIGHT:
1891                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1892                          rdev->mode_info.connector_table);
1893                 /* DVI-D - int tmds */
1894                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1895                 hpd.hpd = RADEON_HPD_1; /* ??? */
1896                 radeon_add_legacy_encoder(dev,
1897                                           radeon_get_encoder_enum(dev,
1898                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1899                                                                 0),
1900                                           ATOM_DEVICE_DFP1_SUPPORT);
1901                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1902                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1903                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1904                                             &hpd);
1905                 /* VGA - tv dac */
1906                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1907                 hpd.hpd = RADEON_HPD_NONE;
1908                 radeon_add_legacy_encoder(dev,
1909                                           radeon_get_encoder_enum(dev,
1910                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1911                                                                 2),
1912                                           ATOM_DEVICE_CRT2_SUPPORT);
1913                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1914                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1915                                             CONNECTOR_OBJECT_ID_VGA,
1916                                             &hpd);
1917                 /* TV - TV DAC */
1918                 ddc_i2c.valid = false;
1919                 hpd.hpd = RADEON_HPD_NONE;
1920                 radeon_add_legacy_encoder(dev,
1921                                           radeon_get_encoder_enum(dev,
1922                                                                 ATOM_DEVICE_TV1_SUPPORT,
1923                                                                 2),
1924                                           ATOM_DEVICE_TV1_SUPPORT);
1925                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1926                                             DRM_MODE_CONNECTOR_SVIDEO,
1927                                             &ddc_i2c,
1928                                             CONNECTOR_OBJECT_ID_SVIDEO,
1929                                             &hpd);
1930                 break;
1931         case CT_EMAC:
1932                 DRM_INFO("Connector Table: %d (emac)\n",
1933                          rdev->mode_info.connector_table);
1934                 /* VGA - primary dac */
1935                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1936                 hpd.hpd = RADEON_HPD_NONE;
1937                 radeon_add_legacy_encoder(dev,
1938                                           radeon_get_encoder_enum(dev,
1939                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1940                                                                 1),
1941                                           ATOM_DEVICE_CRT1_SUPPORT);
1942                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1943                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1944                                             CONNECTOR_OBJECT_ID_VGA,
1945                                             &hpd);
1946                 /* VGA - tv dac */
1947                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1948                 hpd.hpd = RADEON_HPD_NONE;
1949                 radeon_add_legacy_encoder(dev,
1950                                           radeon_get_encoder_enum(dev,
1951                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1952                                                                 2),
1953                                           ATOM_DEVICE_CRT2_SUPPORT);
1954                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1955                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1956                                             CONNECTOR_OBJECT_ID_VGA,
1957                                             &hpd);
1958                 /* TV - TV DAC */
1959                 ddc_i2c.valid = false;
1960                 hpd.hpd = RADEON_HPD_NONE;
1961                 radeon_add_legacy_encoder(dev,
1962                                           radeon_get_encoder_enum(dev,
1963                                                                 ATOM_DEVICE_TV1_SUPPORT,
1964                                                                 2),
1965                                           ATOM_DEVICE_TV1_SUPPORT);
1966                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1967                                             DRM_MODE_CONNECTOR_SVIDEO,
1968                                             &ddc_i2c,
1969                                             CONNECTOR_OBJECT_ID_SVIDEO,
1970                                             &hpd);
1971                 break;
1972         case CT_RN50_POWER:
1973                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1974                          rdev->mode_info.connector_table);
1975                 /* VGA - primary dac */
1976                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1977                 hpd.hpd = RADEON_HPD_NONE;
1978                 radeon_add_legacy_encoder(dev,
1979                                           radeon_get_encoder_enum(dev,
1980                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1981                                                                 1),
1982                                           ATOM_DEVICE_CRT1_SUPPORT);
1983                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1984                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1985                                             CONNECTOR_OBJECT_ID_VGA,
1986                                             &hpd);
1987                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1988                 hpd.hpd = RADEON_HPD_NONE;
1989                 radeon_add_legacy_encoder(dev,
1990                                           radeon_get_encoder_enum(dev,
1991                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1992                                                                 2),
1993                                           ATOM_DEVICE_CRT2_SUPPORT);
1994                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1995                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1996                                             CONNECTOR_OBJECT_ID_VGA,
1997                                             &hpd);
1998                 break;
1999         case CT_MAC_X800:
2000                 DRM_INFO("Connector Table: %d (mac x800)\n",
2001                          rdev->mode_info.connector_table);
2002                 /* DVI - primary dac, internal tmds */
2003                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2004                 hpd.hpd = RADEON_HPD_1; /* ??? */
2005                 radeon_add_legacy_encoder(dev,
2006                                           radeon_get_encoder_enum(dev,
2007                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2008                                                                   0),
2009                                           ATOM_DEVICE_DFP1_SUPPORT);
2010                 radeon_add_legacy_encoder(dev,
2011                                           radeon_get_encoder_enum(dev,
2012                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2013                                                                   1),
2014                                           ATOM_DEVICE_CRT1_SUPPORT);
2015                 radeon_add_legacy_connector(dev, 0,
2016                                             ATOM_DEVICE_DFP1_SUPPORT |
2017                                             ATOM_DEVICE_CRT1_SUPPORT,
2018                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2019                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2020                                             &hpd);
2021                 /* DVI - tv dac, dvo */
2022                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2023                 hpd.hpd = RADEON_HPD_2; /* ??? */
2024                 radeon_add_legacy_encoder(dev,
2025                                           radeon_get_encoder_enum(dev,
2026                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2027                                                                   0),
2028                                           ATOM_DEVICE_DFP2_SUPPORT);
2029                 radeon_add_legacy_encoder(dev,
2030                                           radeon_get_encoder_enum(dev,
2031                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2032                                                                   2),
2033                                           ATOM_DEVICE_CRT2_SUPPORT);
2034                 radeon_add_legacy_connector(dev, 1,
2035                                             ATOM_DEVICE_DFP2_SUPPORT |
2036                                             ATOM_DEVICE_CRT2_SUPPORT,
2037                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2038                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2039                                             &hpd);
2040                 break;
2041         case CT_MAC_G5_9600:
2042                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2043                          rdev->mode_info.connector_table);
2044                 /* DVI - tv dac, dvo */
2045                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2046                 hpd.hpd = RADEON_HPD_1; /* ??? */
2047                 radeon_add_legacy_encoder(dev,
2048                                           radeon_get_encoder_enum(dev,
2049                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2050                                                                   0),
2051                                           ATOM_DEVICE_DFP2_SUPPORT);
2052                 radeon_add_legacy_encoder(dev,
2053                                           radeon_get_encoder_enum(dev,
2054                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2055                                                                   2),
2056                                           ATOM_DEVICE_CRT2_SUPPORT);
2057                 radeon_add_legacy_connector(dev, 0,
2058                                             ATOM_DEVICE_DFP2_SUPPORT |
2059                                             ATOM_DEVICE_CRT2_SUPPORT,
2060                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2061                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2062                                             &hpd);
2063                 /* ADC - primary dac, internal tmds */
2064                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2065                 hpd.hpd = RADEON_HPD_2; /* ??? */
2066                 radeon_add_legacy_encoder(dev,
2067                                           radeon_get_encoder_enum(dev,
2068                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2069                                                                   0),
2070                                           ATOM_DEVICE_DFP1_SUPPORT);
2071                 radeon_add_legacy_encoder(dev,
2072                                           radeon_get_encoder_enum(dev,
2073                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2074                                                                   1),
2075                                           ATOM_DEVICE_CRT1_SUPPORT);
2076                 radeon_add_legacy_connector(dev, 1,
2077                                             ATOM_DEVICE_DFP1_SUPPORT |
2078                                             ATOM_DEVICE_CRT1_SUPPORT,
2079                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2080                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2081                                             &hpd);
2082                 break;
2083         default:
2084                 DRM_INFO("Connector table: %d (invalid)\n",
2085                          rdev->mode_info.connector_table);
2086                 return false;
2087         }
2088
2089         radeon_link_encoder_connector(dev);
2090
2091         return true;
2092 }
2093
2094 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2095                                        int bios_index,
2096                                        enum radeon_combios_connector
2097                                        *legacy_connector,
2098                                        struct radeon_i2c_bus_rec *ddc_i2c,
2099                                        struct radeon_hpd *hpd)
2100 {
2101
2102         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2103            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2104         if (dev->pdev->device == 0x515e &&
2105             dev->pdev->subsystem_vendor == 0x1014) {
2106                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2107                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2108                         return false;
2109         }
2110
2111         /* X300 card with extra non-existent DVI port */
2112         if (dev->pdev->device == 0x5B60 &&
2113             dev->pdev->subsystem_vendor == 0x17af &&
2114             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2115                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2116                         return false;
2117         }
2118
2119         return true;
2120 }
2121
2122 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2123 {
2124         /* Acer 5102 has non-existent TV port */
2125         if (dev->pdev->device == 0x5975 &&
2126             dev->pdev->subsystem_vendor == 0x1025 &&
2127             dev->pdev->subsystem_device == 0x009f)
2128                 return false;
2129
2130         /* HP dc5750 has non-existent TV port */
2131         if (dev->pdev->device == 0x5974 &&
2132             dev->pdev->subsystem_vendor == 0x103c &&
2133             dev->pdev->subsystem_device == 0x280a)
2134                 return false;
2135
2136         /* MSI S270 has non-existent TV port */
2137         if (dev->pdev->device == 0x5955 &&
2138             dev->pdev->subsystem_vendor == 0x1462 &&
2139             dev->pdev->subsystem_device == 0x0131)
2140                 return false;
2141
2142         return true;
2143 }
2144
2145 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2146 {
2147         struct radeon_device *rdev = dev->dev_private;
2148         uint32_t ext_tmds_info;
2149
2150         if (rdev->flags & RADEON_IS_IGP) {
2151                 if (is_dvi_d)
2152                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2153                 else
2154                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2155         }
2156         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2157         if (ext_tmds_info) {
2158                 uint8_t rev = RBIOS8(ext_tmds_info);
2159                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2160                 if (rev >= 3) {
2161                         if (is_dvi_d)
2162                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2163                         else
2164                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2165                 } else {
2166                         if (flags & 1) {
2167                                 if (is_dvi_d)
2168                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2169                                 else
2170                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2171                         }
2172                 }
2173         }
2174         if (is_dvi_d)
2175                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2176         else
2177                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2178 }
2179
2180 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2181 {
2182         struct radeon_device *rdev = dev->dev_private;
2183         uint32_t conn_info, entry, devices;
2184         uint16_t tmp, connector_object_id;
2185         enum radeon_combios_ddc ddc_type;
2186         enum radeon_combios_connector connector;
2187         int i = 0;
2188         struct radeon_i2c_bus_rec ddc_i2c;
2189         struct radeon_hpd hpd;
2190
2191         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2192         if (conn_info) {
2193                 for (i = 0; i < 4; i++) {
2194                         entry = conn_info + 2 + i * 2;
2195
2196                         if (!RBIOS16(entry))
2197                                 break;
2198
2199                         tmp = RBIOS16(entry);
2200
2201                         connector = (tmp >> 12) & 0xf;
2202
2203                         ddc_type = (tmp >> 8) & 0xf;
2204                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2205
2206                         switch (connector) {
2207                         case CONNECTOR_PROPRIETARY_LEGACY:
2208                         case CONNECTOR_DVI_I_LEGACY:
2209                         case CONNECTOR_DVI_D_LEGACY:
2210                                 if ((tmp >> 4) & 0x1)
2211                                         hpd.hpd = RADEON_HPD_2;
2212                                 else
2213                                         hpd.hpd = RADEON_HPD_1;
2214                                 break;
2215                         default:
2216                                 hpd.hpd = RADEON_HPD_NONE;
2217                                 break;
2218                         }
2219
2220                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2221                                                         &ddc_i2c, &hpd))
2222                                 continue;
2223
2224                         switch (connector) {
2225                         case CONNECTOR_PROPRIETARY_LEGACY:
2226                                 if ((tmp >> 4) & 0x1)
2227                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2228                                 else
2229                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2230                                 radeon_add_legacy_encoder(dev,
2231                                                           radeon_get_encoder_enum
2232                                                           (dev, devices, 0),
2233                                                           devices);
2234                                 radeon_add_legacy_connector(dev, i, devices,
2235                                                             legacy_connector_convert
2236                                                             [connector],
2237                                                             &ddc_i2c,
2238                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2239                                                             &hpd);
2240                                 break;
2241                         case CONNECTOR_CRT_LEGACY:
2242                                 if (tmp & 0x1) {
2243                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2244                                         radeon_add_legacy_encoder(dev,
2245                                                                   radeon_get_encoder_enum
2246                                                                   (dev,
2247                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2248                                                                    2),
2249                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2250                                 } else {
2251                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2252                                         radeon_add_legacy_encoder(dev,
2253                                                                   radeon_get_encoder_enum
2254                                                                   (dev,
2255                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2256                                                                    1),
2257                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2258                                 }
2259                                 radeon_add_legacy_connector(dev,
2260                                                             i,
2261                                                             devices,
2262                                                             legacy_connector_convert
2263                                                             [connector],
2264                                                             &ddc_i2c,
2265                                                             CONNECTOR_OBJECT_ID_VGA,
2266                                                             &hpd);
2267                                 break;
2268                         case CONNECTOR_DVI_I_LEGACY:
2269                                 devices = 0;
2270                                 if (tmp & 0x1) {
2271                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2272                                         radeon_add_legacy_encoder(dev,
2273                                                                   radeon_get_encoder_enum
2274                                                                   (dev,
2275                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2276                                                                    2),
2277                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2278                                 } else {
2279                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2280                                         radeon_add_legacy_encoder(dev,
2281                                                                   radeon_get_encoder_enum
2282                                                                   (dev,
2283                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2284                                                                    1),
2285                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2286                                 }
2287                                 if ((tmp >> 4) & 0x1) {
2288                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2289                                         radeon_add_legacy_encoder(dev,
2290                                                                   radeon_get_encoder_enum
2291                                                                   (dev,
2292                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2293                                                                    0),
2294                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2295                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2296                                 } else {
2297                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2298                                         radeon_add_legacy_encoder(dev,
2299                                                                   radeon_get_encoder_enum
2300                                                                   (dev,
2301                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2302                                                                    0),
2303                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2304                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2305                                 }
2306                                 radeon_add_legacy_connector(dev,
2307                                                             i,
2308                                                             devices,
2309                                                             legacy_connector_convert
2310                                                             [connector],
2311                                                             &ddc_i2c,
2312                                                             connector_object_id,
2313                                                             &hpd);
2314                                 break;
2315                         case CONNECTOR_DVI_D_LEGACY:
2316                                 if ((tmp >> 4) & 0x1) {
2317                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2318                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2319                                 } else {
2320                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2321                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2322                                 }
2323                                 radeon_add_legacy_encoder(dev,
2324                                                           radeon_get_encoder_enum
2325                                                           (dev, devices, 0),
2326                                                           devices);
2327                                 radeon_add_legacy_connector(dev, i, devices,
2328                                                             legacy_connector_convert
2329                                                             [connector],
2330                                                             &ddc_i2c,
2331                                                             connector_object_id,
2332                                                             &hpd);
2333                                 break;
2334                         case CONNECTOR_CTV_LEGACY:
2335                         case CONNECTOR_STV_LEGACY:
2336                                 radeon_add_legacy_encoder(dev,
2337                                                           radeon_get_encoder_enum
2338                                                           (dev,
2339                                                            ATOM_DEVICE_TV1_SUPPORT,
2340                                                            2),
2341                                                           ATOM_DEVICE_TV1_SUPPORT);
2342                                 radeon_add_legacy_connector(dev, i,
2343                                                             ATOM_DEVICE_TV1_SUPPORT,
2344                                                             legacy_connector_convert
2345                                                             [connector],
2346                                                             &ddc_i2c,
2347                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2348                                                             &hpd);
2349                                 break;
2350                         default:
2351                                 DRM_ERROR("Unknown connector type: %d\n",
2352                                           connector);
2353                                 continue;
2354                         }
2355
2356                 }
2357         } else {
2358                 uint16_t tmds_info =
2359                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2360                 if (tmds_info) {
2361                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2362
2363                         radeon_add_legacy_encoder(dev,
2364                                                   radeon_get_encoder_enum(dev,
2365                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2366                                                                         1),
2367                                                   ATOM_DEVICE_CRT1_SUPPORT);
2368                         radeon_add_legacy_encoder(dev,
2369                                                   radeon_get_encoder_enum(dev,
2370                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2371                                                                         0),
2372                                                   ATOM_DEVICE_DFP1_SUPPORT);
2373
2374                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2375                         hpd.hpd = RADEON_HPD_1;
2376                         radeon_add_legacy_connector(dev,
2377                                                     0,
2378                                                     ATOM_DEVICE_CRT1_SUPPORT |
2379                                                     ATOM_DEVICE_DFP1_SUPPORT,
2380                                                     DRM_MODE_CONNECTOR_DVII,
2381                                                     &ddc_i2c,
2382                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2383                                                     &hpd);
2384                 } else {
2385                         uint16_t crt_info =
2386                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2387                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2388                         if (crt_info) {
2389                                 radeon_add_legacy_encoder(dev,
2390                                                           radeon_get_encoder_enum(dev,
2391                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2392                                                                                 1),
2393                                                           ATOM_DEVICE_CRT1_SUPPORT);
2394                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2395                                 hpd.hpd = RADEON_HPD_NONE;
2396                                 radeon_add_legacy_connector(dev,
2397                                                             0,
2398                                                             ATOM_DEVICE_CRT1_SUPPORT,
2399                                                             DRM_MODE_CONNECTOR_VGA,
2400                                                             &ddc_i2c,
2401                                                             CONNECTOR_OBJECT_ID_VGA,
2402                                                             &hpd);
2403                         } else {
2404                                 DRM_DEBUG_KMS("No connector info found\n");
2405                                 return false;
2406                         }
2407                 }
2408         }
2409
2410         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2411                 uint16_t lcd_info =
2412                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2413                 if (lcd_info) {
2414                         uint16_t lcd_ddc_info =
2415                             combios_get_table_offset(dev,
2416                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2417
2418                         radeon_add_legacy_encoder(dev,
2419                                                   radeon_get_encoder_enum(dev,
2420                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2421                                                                         0),
2422                                                   ATOM_DEVICE_LCD1_SUPPORT);
2423
2424                         if (lcd_ddc_info) {
2425                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2426                                 switch (ddc_type) {
2427                                 case DDC_LCD:
2428                                         ddc_i2c =
2429                                                 combios_setup_i2c_bus(rdev,
2430                                                                       DDC_LCD,
2431                                                                       RBIOS32(lcd_ddc_info + 3),
2432                                                                       RBIOS32(lcd_ddc_info + 7));
2433                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2434                                         break;
2435                                 case DDC_GPIO:
2436                                         ddc_i2c =
2437                                                 combios_setup_i2c_bus(rdev,
2438                                                                       DDC_GPIO,
2439                                                                       RBIOS32(lcd_ddc_info + 3),
2440                                                                       RBIOS32(lcd_ddc_info + 7));
2441                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2442                                         break;
2443                                 default:
2444                                         ddc_i2c =
2445                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2446                                         break;
2447                                 }
2448                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2449                         } else
2450                                 ddc_i2c.valid = false;
2451
2452                         hpd.hpd = RADEON_HPD_NONE;
2453                         radeon_add_legacy_connector(dev,
2454                                                     5,
2455                                                     ATOM_DEVICE_LCD1_SUPPORT,
2456                                                     DRM_MODE_CONNECTOR_LVDS,
2457                                                     &ddc_i2c,
2458                                                     CONNECTOR_OBJECT_ID_LVDS,
2459                                                     &hpd);
2460                 }
2461         }
2462
2463         /* check TV table */
2464         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2465                 uint32_t tv_info =
2466                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2467                 if (tv_info) {
2468                         if (RBIOS8(tv_info + 6) == 'T') {
2469                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2470                                         hpd.hpd = RADEON_HPD_NONE;
2471                                         ddc_i2c.valid = false;
2472                                         radeon_add_legacy_encoder(dev,
2473                                                                   radeon_get_encoder_enum
2474                                                                   (dev,
2475                                                                    ATOM_DEVICE_TV1_SUPPORT,
2476                                                                    2),
2477                                                                   ATOM_DEVICE_TV1_SUPPORT);
2478                                         radeon_add_legacy_connector(dev, 6,
2479                                                                     ATOM_DEVICE_TV1_SUPPORT,
2480                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2481                                                                     &ddc_i2c,
2482                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2483                                                                     &hpd);
2484                                 }
2485                         }
2486                 }
2487         }
2488
2489         radeon_link_encoder_connector(dev);
2490
2491         return true;
2492 }
2493
2494 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2495 {
2496         struct drm_device *dev = rdev->ddev;
2497         u16 offset, misc, misc2 = 0;
2498         u8 rev, blocks, tmp;
2499         int state_index = 0;
2500
2501         rdev->pm.default_power_state_index = -1;
2502
2503         /* allocate 2 power states */
2504         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2505         if (!rdev->pm.power_state) {
2506                 rdev->pm.default_power_state_index = state_index;
2507                 rdev->pm.num_power_states = 0;
2508
2509                 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2510                 rdev->pm.current_clock_mode_index = 0;
2511                 return;
2512         }
2513
2514         if (rdev->flags & RADEON_IS_MOBILITY) {
2515                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2516                 if (offset) {
2517                         rev = RBIOS8(offset);
2518                         blocks = RBIOS8(offset + 0x2);
2519                         /* power mode 0 tends to be the only valid one */
2520                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2521                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2522                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2523                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2524                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2525                                 goto default_mode;
2526                         rdev->pm.power_state[state_index].type =
2527                                 POWER_STATE_TYPE_BATTERY;
2528                         misc = RBIOS16(offset + 0x5 + 0x0);
2529                         if (rev > 4)
2530                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2531                         rdev->pm.power_state[state_index].misc = misc;
2532                         rdev->pm.power_state[state_index].misc2 = misc2;
2533                         if (misc & 0x4) {
2534                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2535                                 if (misc & 0x8)
2536                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2537                                                 true;
2538                                 else
2539                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2540                                                 false;
2541                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2542                                 if (rev < 6) {
2543                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2544                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2545                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2546                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2547                                 } else {
2548                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2549                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2550                                         if (entries && voltage_table_offset) {
2551                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2552                                                         RBIOS16(voltage_table_offset) * 4;
2553                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2554                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2555                                         } else
2556                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2557                                 }
2558                                 switch ((misc2 & 0x700) >> 8) {
2559                                 case 0:
2560                                 default:
2561                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2562                                         break;
2563                                 case 1:
2564                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2565                                         break;
2566                                 case 2:
2567                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2568                                         break;
2569                                 case 3:
2570                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2571                                         break;
2572                                 case 4:
2573                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2574                                         break;
2575                                 }
2576                         } else
2577                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2578                         if (rev > 6)
2579                                 rdev->pm.power_state[state_index].pcie_lanes =
2580                                         RBIOS8(offset + 0x5 + 0x10);
2581                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2582                         state_index++;
2583                 } else {
2584                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2585                 }
2586         } else {
2587                 /* XXX figure out some good default low power mode for desktop cards */
2588         }
2589
2590 default_mode:
2591         /* add the default mode */
2592         rdev->pm.power_state[state_index].type =
2593                 POWER_STATE_TYPE_DEFAULT;
2594         rdev->pm.power_state[state_index].num_clock_modes = 1;
2595         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2596         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2597         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2598         if ((state_index > 0) &&
2599             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2600                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2601                         rdev->pm.power_state[0].clock_info[0].voltage;
2602         else
2603                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2604         rdev->pm.power_state[state_index].pcie_lanes = 16;
2605         rdev->pm.power_state[state_index].flags = 0;
2606         rdev->pm.default_power_state_index = state_index;
2607         rdev->pm.num_power_states = state_index + 1;
2608
2609         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2610         rdev->pm.current_clock_mode_index = 0;
2611 }
2612
2613 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2614 {
2615         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2616         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2617
2618         if (!tmds)
2619                 return;
2620
2621         switch (tmds->dvo_chip) {
2622         case DVO_SIL164:
2623                 /* sil 164 */
2624                 radeon_i2c_put_byte(tmds->i2c_bus,
2625                                     tmds->slave_addr,
2626                                     0x08, 0x30);
2627                 radeon_i2c_put_byte(tmds->i2c_bus,
2628                                        tmds->slave_addr,
2629                                        0x09, 0x00);
2630                 radeon_i2c_put_byte(tmds->i2c_bus,
2631                                     tmds->slave_addr,
2632                                     0x0a, 0x90);
2633                 radeon_i2c_put_byte(tmds->i2c_bus,
2634                                     tmds->slave_addr,
2635                                     0x0c, 0x89);
2636                 radeon_i2c_put_byte(tmds->i2c_bus,
2637                                        tmds->slave_addr,
2638                                        0x08, 0x3b);
2639                 break;
2640         case DVO_SIL1178:
2641                 /* sil 1178 - untested */
2642                 /*
2643                  * 0x0f, 0x44
2644                  * 0x0f, 0x4c
2645                  * 0x0e, 0x01
2646                  * 0x0a, 0x80
2647                  * 0x09, 0x30
2648                  * 0x0c, 0xc9
2649                  * 0x0d, 0x70
2650                  * 0x08, 0x32
2651                  * 0x08, 0x33
2652                  */
2653                 break;
2654         default:
2655                 break;
2656         }
2657
2658 }
2659
2660 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2661 {
2662         struct drm_device *dev = encoder->dev;
2663         struct radeon_device *rdev = dev->dev_private;
2664         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2665         uint16_t offset;
2666         uint8_t blocks, slave_addr, rev;
2667         uint32_t index, id;
2668         uint32_t reg, val, and_mask, or_mask;
2669         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2670
2671         if (!tmds)
2672                 return false;
2673
2674         if (rdev->flags & RADEON_IS_IGP) {
2675                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2676                 rev = RBIOS8(offset);
2677                 if (offset) {
2678                         rev = RBIOS8(offset);
2679                         if (rev > 1) {
2680                                 blocks = RBIOS8(offset + 3);
2681                                 index = offset + 4;
2682                                 while (blocks > 0) {
2683                                         id = RBIOS16(index);
2684                                         index += 2;
2685                                         switch (id >> 13) {
2686                                         case 0:
2687                                                 reg = (id & 0x1fff) * 4;
2688                                                 val = RBIOS32(index);
2689                                                 index += 4;
2690                                                 WREG32(reg, val);
2691                                                 break;
2692                                         case 2:
2693                                                 reg = (id & 0x1fff) * 4;
2694                                                 and_mask = RBIOS32(index);
2695                                                 index += 4;
2696                                                 or_mask = RBIOS32(index);
2697                                                 index += 4;
2698                                                 val = RREG32(reg);
2699                                                 val = (val & and_mask) | or_mask;
2700                                                 WREG32(reg, val);
2701                                                 break;
2702                                         case 3:
2703                                                 val = RBIOS16(index);
2704                                                 index += 2;
2705                                                 udelay(val);
2706                                                 break;
2707                                         case 4:
2708                                                 val = RBIOS16(index);
2709                                                 index += 2;
2710                                                 udelay(val * 1000);
2711                                                 break;
2712                                         case 6:
2713                                                 slave_addr = id & 0xff;
2714                                                 slave_addr >>= 1; /* 7 bit addressing */
2715                                                 index++;
2716                                                 reg = RBIOS8(index);
2717                                                 index++;
2718                                                 val = RBIOS8(index);
2719                                                 index++;
2720                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2721                                                                     slave_addr,
2722                                                                     reg, val);
2723                                                 break;
2724                                         default:
2725                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2726                                                 break;
2727                                         }
2728                                         blocks--;
2729                                 }
2730                                 return true;
2731                         }
2732                 }
2733         } else {
2734                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2735                 if (offset) {
2736                         index = offset + 10;
2737                         id = RBIOS16(index);
2738                         while (id != 0xffff) {
2739                                 index += 2;
2740                                 switch (id >> 13) {
2741                                 case 0:
2742                                         reg = (id & 0x1fff) * 4;
2743                                         val = RBIOS32(index);
2744                                         WREG32(reg, val);
2745                                         break;
2746                                 case 2:
2747                                         reg = (id & 0x1fff) * 4;
2748                                         and_mask = RBIOS32(index);
2749                                         index += 4;
2750                                         or_mask = RBIOS32(index);
2751                                         index += 4;
2752                                         val = RREG32(reg);
2753                                         val = (val & and_mask) | or_mask;
2754                                         WREG32(reg, val);
2755                                         break;
2756                                 case 4:
2757                                         val = RBIOS16(index);
2758                                         index += 2;
2759                                         udelay(val);
2760                                         break;
2761                                 case 5:
2762                                         reg = id & 0x1fff;
2763                                         and_mask = RBIOS32(index);
2764                                         index += 4;
2765                                         or_mask = RBIOS32(index);
2766                                         index += 4;
2767                                         val = RREG32_PLL(reg);
2768                                         val = (val & and_mask) | or_mask;
2769                                         WREG32_PLL(reg, val);
2770                                         break;
2771                                 case 6:
2772                                         reg = id & 0x1fff;
2773                                         val = RBIOS8(index);
2774                                         index += 1;
2775                                         radeon_i2c_put_byte(tmds->i2c_bus,
2776                                                             tmds->slave_addr,
2777                                                             reg, val);
2778                                         break;
2779                                 default:
2780                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2781                                         break;
2782                                 }
2783                                 id = RBIOS16(index);
2784                         }
2785                         return true;
2786                 }
2787         }
2788         return false;
2789 }
2790
2791 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2792 {
2793         struct radeon_device *rdev = dev->dev_private;
2794
2795         if (offset) {
2796                 while (RBIOS16(offset)) {
2797                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2798                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2799                         uint32_t val, and_mask, or_mask;
2800                         uint32_t tmp;
2801
2802                         offset += 2;
2803                         switch (cmd) {
2804                         case 0:
2805                                 val = RBIOS32(offset);
2806                                 offset += 4;
2807                                 WREG32(addr, val);
2808                                 break;
2809                         case 1:
2810                                 val = RBIOS32(offset);
2811                                 offset += 4;
2812                                 WREG32(addr, val);
2813                                 break;
2814                         case 2:
2815                                 and_mask = RBIOS32(offset);
2816                                 offset += 4;
2817                                 or_mask = RBIOS32(offset);
2818                                 offset += 4;
2819                                 tmp = RREG32(addr);
2820                                 tmp &= and_mask;
2821                                 tmp |= or_mask;
2822                                 WREG32(addr, tmp);
2823                                 break;
2824                         case 3:
2825                                 and_mask = RBIOS32(offset);
2826                                 offset += 4;
2827                                 or_mask = RBIOS32(offset);
2828                                 offset += 4;
2829                                 tmp = RREG32(addr);
2830                                 tmp &= and_mask;
2831                                 tmp |= or_mask;
2832                                 WREG32(addr, tmp);
2833                                 break;
2834                         case 4:
2835                                 val = RBIOS16(offset);
2836                                 offset += 2;
2837                                 udelay(val);
2838                                 break;
2839                         case 5:
2840                                 val = RBIOS16(offset);
2841                                 offset += 2;
2842                                 switch (addr) {
2843                                 case 8:
2844                                         while (val--) {
2845                                                 if (!
2846                                                     (RREG32_PLL
2847                                                      (RADEON_CLK_PWRMGT_CNTL) &
2848                                                      RADEON_MC_BUSY))
2849                                                         break;
2850                                         }
2851                                         break;
2852                                 case 9:
2853                                         while (val--) {
2854                                                 if ((RREG32(RADEON_MC_STATUS) &
2855                                                      RADEON_MC_IDLE))
2856                                                         break;
2857                                         }
2858                                         break;
2859                                 default:
2860                                         break;
2861                                 }
2862                                 break;
2863                         default:
2864                                 break;
2865                         }
2866                 }
2867         }
2868 }
2869
2870 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2871 {
2872         struct radeon_device *rdev = dev->dev_private;
2873
2874         if (offset) {
2875                 while (RBIOS8(offset)) {
2876                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2877                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2878                         uint32_t val, shift, tmp;
2879                         uint32_t and_mask, or_mask;
2880
2881                         offset++;
2882                         switch (cmd) {
2883                         case 0:
2884                                 val = RBIOS32(offset);
2885                                 offset += 4;
2886                                 WREG32_PLL(addr, val);
2887                                 break;
2888                         case 1:
2889                                 shift = RBIOS8(offset) * 8;
2890                                 offset++;
2891                                 and_mask = RBIOS8(offset) << shift;
2892                                 and_mask |= ~(0xff << shift);
2893                                 offset++;
2894                                 or_mask = RBIOS8(offset) << shift;
2895                                 offset++;
2896                                 tmp = RREG32_PLL(addr);
2897                                 tmp &= and_mask;
2898                                 tmp |= or_mask;
2899                                 WREG32_PLL(addr, tmp);
2900                                 break;
2901                         case 2:
2902                         case 3:
2903                                 tmp = 1000;
2904                                 switch (addr) {
2905                                 case 1:
2906                                         udelay(150);
2907                                         break;
2908                                 case 2:
2909                                         udelay(1000);
2910                                         break;
2911                                 case 3:
2912                                         while (tmp--) {
2913                                                 if (!
2914                                                     (RREG32_PLL
2915                                                      (RADEON_CLK_PWRMGT_CNTL) &
2916                                                      RADEON_MC_BUSY))
2917                                                         break;
2918                                         }
2919                                         break;
2920                                 case 4:
2921                                         while (tmp--) {
2922                                                 if (RREG32_PLL
2923                                                     (RADEON_CLK_PWRMGT_CNTL) &
2924                                                     RADEON_DLL_READY)
2925                                                         break;
2926                                         }
2927                                         break;
2928                                 case 5:
2929                                         tmp =
2930                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2931                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2932 #if 0
2933                                                 uint32_t mclk_cntl =
2934                                                     RREG32_PLL
2935                                                     (RADEON_MCLK_CNTL);
2936                                                 mclk_cntl &= 0xffff0000;
2937                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2938                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2939                                                            mclk_cntl);
2940                                                 udelay(10000);
2941 #endif
2942                                                 WREG32_PLL
2943                                                     (RADEON_CLK_PWRMGT_CNTL,
2944                                                      tmp &
2945                                                      ~RADEON_CG_NO1_DEBUG_0);
2946                                                 udelay(10000);
2947                                         }
2948                                         break;
2949                                 default:
2950                                         break;
2951                                 }
2952                                 break;
2953                         default:
2954                                 break;
2955                         }
2956                 }
2957         }
2958 }
2959
2960 static void combios_parse_ram_reset_table(struct drm_device *dev,
2961                                           uint16_t offset)
2962 {
2963         struct radeon_device *rdev = dev->dev_private;
2964         uint32_t tmp;
2965
2966         if (offset) {
2967                 uint8_t val = RBIOS8(offset);
2968                 while (val != 0xff) {
2969                         offset++;
2970
2971                         if (val == 0x0f) {
2972                                 uint32_t channel_complete_mask;
2973
2974                                 if (ASIC_IS_R300(rdev))
2975                                         channel_complete_mask =
2976                                             R300_MEM_PWRUP_COMPLETE;
2977                                 else
2978                                         channel_complete_mask =
2979                                             RADEON_MEM_PWRUP_COMPLETE;
2980                                 tmp = 20000;
2981                                 while (tmp--) {
2982                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2983                                              channel_complete_mask) ==
2984                                             channel_complete_mask)
2985                                                 break;
2986                                 }
2987                         } else {
2988                                 uint32_t or_mask = RBIOS16(offset);
2989                                 offset += 2;
2990
2991                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2992                                 tmp &= RADEON_SDRAM_MODE_MASK;
2993                                 tmp |= or_mask;
2994                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2995
2996                                 or_mask = val << 24;
2997                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2998                                 tmp &= RADEON_B3MEM_RESET_MASK;
2999                                 tmp |= or_mask;
3000                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3001                         }
3002                         val = RBIOS8(offset);
3003                 }
3004         }
3005 }
3006
3007 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3008                                    int mem_addr_mapping)
3009 {
3010         struct radeon_device *rdev = dev->dev_private;
3011         uint32_t mem_cntl;
3012         uint32_t mem_size;
3013         uint32_t addr = 0;
3014
3015         mem_cntl = RREG32(RADEON_MEM_CNTL);
3016         if (mem_cntl & RV100_HALF_MODE)
3017                 ram /= 2;
3018         mem_size = ram;
3019         mem_cntl &= ~(0xff << 8);
3020         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3021         WREG32(RADEON_MEM_CNTL, mem_cntl);
3022         RREG32(RADEON_MEM_CNTL);
3023
3024         /* sdram reset ? */
3025
3026         /* something like this????  */
3027         while (ram--) {
3028                 addr = ram * 1024 * 1024;
3029                 /* write to each page */
3030                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3031                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3032                 /* read back and verify */
3033                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3034                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3035                         return 0;
3036         }
3037
3038         return mem_size;
3039 }
3040
3041 static void combios_write_ram_size(struct drm_device *dev)
3042 {
3043         struct radeon_device *rdev = dev->dev_private;
3044         uint8_t rev;
3045         uint16_t offset;
3046         uint32_t mem_size = 0;
3047         uint32_t mem_cntl = 0;
3048
3049         /* should do something smarter here I guess... */
3050         if (rdev->flags & RADEON_IS_IGP)
3051                 return;
3052
3053         /* first check detected mem table */
3054         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3055         if (offset) {
3056                 rev = RBIOS8(offset);
3057                 if (rev < 3) {
3058                         mem_cntl = RBIOS32(offset + 1);
3059                         mem_size = RBIOS16(offset + 5);
3060                         if ((rdev->family < CHIP_R200) &&
3061                             !ASIC_IS_RN50(rdev))
3062                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3063                 }
3064         }
3065
3066         if (!mem_size) {
3067                 offset =
3068                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3069                 if (offset) {
3070                         rev = RBIOS8(offset - 1);
3071                         if (rev < 1) {
3072                                 if ((rdev->family < CHIP_R200)
3073                                     && !ASIC_IS_RN50(rdev)) {
3074                                         int ram = 0;
3075                                         int mem_addr_mapping = 0;
3076
3077                                         while (RBIOS8(offset)) {
3078                                                 ram = RBIOS8(offset);
3079                                                 mem_addr_mapping =
3080                                                     RBIOS8(offset + 1);
3081                                                 if (mem_addr_mapping != 0x25)
3082                                                         ram *= 2;
3083                                                 mem_size =
3084                                                     combios_detect_ram(dev, ram,
3085                                                                        mem_addr_mapping);
3086                                                 if (mem_size)
3087                                                         break;
3088                                                 offset += 2;
3089                                         }
3090                                 } else
3091                                         mem_size = RBIOS8(offset);
3092                         } else {
3093                                 mem_size = RBIOS8(offset);
3094                                 mem_size *= 2;  /* convert to MB */
3095                         }
3096                 }
3097         }
3098
3099         mem_size *= (1024 * 1024);      /* convert to bytes */
3100         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3101 }
3102
3103 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3104 {
3105         uint16_t dyn_clk_info =
3106             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3107
3108         if (dyn_clk_info)
3109                 combios_parse_pll_table(dev, dyn_clk_info);
3110 }
3111
3112 void radeon_combios_asic_init(struct drm_device *dev)
3113 {
3114         struct radeon_device *rdev = dev->dev_private;
3115         uint16_t table;
3116
3117         /* port hardcoded mac stuff from radeonfb */
3118         if (rdev->bios == NULL)
3119                 return;
3120
3121         /* ASIC INIT 1 */
3122         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3123         if (table)
3124                 combios_parse_mmio_table(dev, table);
3125
3126         /* PLL INIT */
3127         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3128         if (table)
3129                 combios_parse_pll_table(dev, table);
3130
3131         /* ASIC INIT 2 */
3132         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3133         if (table)
3134                 combios_parse_mmio_table(dev, table);
3135
3136         if (!(rdev->flags & RADEON_IS_IGP)) {
3137                 /* ASIC INIT 4 */
3138                 table =
3139                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3140                 if (table)
3141                         combios_parse_mmio_table(dev, table);
3142
3143                 /* RAM RESET */
3144                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3145                 if (table)
3146                         combios_parse_ram_reset_table(dev, table);
3147
3148                 /* ASIC INIT 3 */
3149                 table =
3150                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3151                 if (table)
3152                         combios_parse_mmio_table(dev, table);
3153
3154                 /* write CONFIG_MEMSIZE */
3155                 combios_write_ram_size(dev);
3156         }
3157
3158         /* quirk for rs4xx HP nx6125 laptop to make it resume
3159          * - it hangs on resume inside the dynclk 1 table.
3160          */
3161         if (rdev->family == CHIP_RS480 &&
3162             rdev->pdev->subsystem_vendor == 0x103c &&
3163             rdev->pdev->subsystem_device == 0x308b)
3164                 return;
3165
3166         /* quirk for rs4xx HP dv5000 laptop to make it resume
3167          * - it hangs on resume inside the dynclk 1 table.
3168          */
3169         if (rdev->family == CHIP_RS480 &&
3170             rdev->pdev->subsystem_vendor == 0x103c &&
3171             rdev->pdev->subsystem_device == 0x30a4)
3172                 return;
3173
3174         /* DYN CLK 1 */
3175         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3176         if (table)
3177                 combios_parse_pll_table(dev, table);
3178
3179 }
3180
3181 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3182 {
3183         struct radeon_device *rdev = dev->dev_private;
3184         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3185
3186         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3187         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3188         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3189
3190         /* let the bios control the backlight */
3191         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3192
3193         /* tell the bios not to handle mode switching */
3194         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3195                            RADEON_ACC_MODE_CHANGE);
3196
3197         /* tell the bios a driver is loaded */
3198         bios_7_scratch |= RADEON_DRV_LOADED;
3199
3200         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3201         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3202         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3203 }
3204
3205 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3206 {
3207         struct drm_device *dev = encoder->dev;
3208         struct radeon_device *rdev = dev->dev_private;
3209         uint32_t bios_6_scratch;
3210
3211         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3212
3213         if (lock)
3214                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3215         else
3216                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3217
3218         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3219 }
3220
3221 void
3222 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3223                                       struct drm_encoder *encoder,
3224                                       bool connected)
3225 {
3226         struct drm_device *dev = connector->dev;
3227         struct radeon_device *rdev = dev->dev_private;
3228         struct radeon_connector *radeon_connector =
3229             to_radeon_connector(connector);
3230         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3231         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3232         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3233
3234         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3235             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3236                 if (connected) {
3237                         DRM_DEBUG_KMS("TV1 connected\n");
3238                         /* fix me */
3239                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3240                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3241                         bios_5_scratch |= RADEON_TV1_ON;
3242                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3243                 } else {
3244                         DRM_DEBUG_KMS("TV1 disconnected\n");
3245                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3246                         bios_5_scratch &= ~RADEON_TV1_ON;
3247                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3248                 }
3249         }
3250         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3251             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3252                 if (connected) {
3253                         DRM_DEBUG_KMS("LCD1 connected\n");
3254                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3255                         bios_5_scratch |= RADEON_LCD1_ON;
3256                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3257                 } else {
3258                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3259                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3260                         bios_5_scratch &= ~RADEON_LCD1_ON;
3261                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3262                 }
3263         }
3264         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3265             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3266                 if (connected) {
3267                         DRM_DEBUG_KMS("CRT1 connected\n");
3268                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3269                         bios_5_scratch |= RADEON_CRT1_ON;
3270                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3271                 } else {
3272                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3273                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3274                         bios_5_scratch &= ~RADEON_CRT1_ON;
3275                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3276                 }
3277         }
3278         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3279             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3280                 if (connected) {
3281                         DRM_DEBUG_KMS("CRT2 connected\n");
3282                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3283                         bios_5_scratch |= RADEON_CRT2_ON;
3284                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3285                 } else {
3286                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3287                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3288                         bios_5_scratch &= ~RADEON_CRT2_ON;
3289                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3290                 }
3291         }
3292         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3293             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3294                 if (connected) {
3295                         DRM_DEBUG_KMS("DFP1 connected\n");
3296                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3297                         bios_5_scratch |= RADEON_DFP1_ON;
3298                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3299                 } else {
3300                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3301                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3302                         bios_5_scratch &= ~RADEON_DFP1_ON;
3303                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3304                 }
3305         }
3306         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3307             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3308                 if (connected) {
3309                         DRM_DEBUG_KMS("DFP2 connected\n");
3310                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3311                         bios_5_scratch |= RADEON_DFP2_ON;
3312                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3313                 } else {
3314                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3315                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3316                         bios_5_scratch &= ~RADEON_DFP2_ON;
3317                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3318                 }
3319         }
3320         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3321         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3322 }
3323
3324 void
3325 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3326 {
3327         struct drm_device *dev = encoder->dev;
3328         struct radeon_device *rdev = dev->dev_private;
3329         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3330         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3331
3332         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3333                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3334                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3335         }
3336         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3337                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3338                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3339         }
3340         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3341                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3342                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3343         }
3344         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3345                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3346                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3347         }
3348         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3349                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3350                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3351         }
3352         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3353                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3354                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3355         }
3356         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3357 }
3358
3359 void
3360 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3361 {
3362         struct drm_device *dev = encoder->dev;
3363         struct radeon_device *rdev = dev->dev_private;
3364         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3365         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3366
3367         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3368                 if (on)
3369                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3370                 else
3371                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3372         }
3373         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3374                 if (on)
3375                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3376                 else
3377                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3378         }
3379         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3380                 if (on)
3381                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3382                 else
3383                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3384         }
3385         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3386                 if (on)
3387                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3388                 else
3389                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3390         }
3391         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3392 }