drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info, size;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         size = EDID_LENGTH * (raw[0x7e] + 1);
 460         edid = kmalloc(size, GFP_KERNEL);
 461         if (edid == NULL)
 462                 return false;
 463
 464         memcpy((unsigned char *)edid, raw, size);
 465
 466         if (!drm_edid_is_valid(edid)) {
 467                 kfree(edid);
 468                 return false;
 469         }
 470
 471         rdev->mode_info.bios_hardcoded_edid = edid;
 472         rdev->mode_info.bios_hardcoded_edid_size = size;
 473         return true;
 474 }
 475
 476 /* this is used for atom LCDs as well */
 477 struct edid *
 478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 479 {
 480         struct edid *edid;
 481
 482         if (rdev->mode_info.bios_hardcoded_edid) {
 483                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 484                 if (edid) {
 485                         memcpy((unsigned char *)edid,
 486                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 487                                rdev->mode_info.bios_hardcoded_edid_size);
 488                         return edid;
 489                 }
 490         }
 491         return NULL;
 492 }
 493
 494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 495                                                        enum radeon_combios_ddc ddc,
 496                                                        u32 clk_mask,
 497                                                        u32 data_mask)
 498 {
 499         struct radeon_i2c_bus_rec i2c;
 500         int ddc_line = 0;
 501
 502         /* ddc id            = mask reg
 503          * DDC_NONE_DETECTED = none
 504          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 505          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 506          * DDC_LCD           = RADEON_GPIOPAD_MASK
 507          * DDC_GPIO          = RADEON_MDGPIO_MASK
 508          * r1xx
 509          * DDC_MONID         = RADEON_GPIO_MONID
 510          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 511          * r200
 512          * DDC_MONID         = RADEON_GPIO_MONID
 513          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 514          * r300/r350
 515          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 516          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 517          * rv2xx/rv3xx
 518          * DDC_MONID         = RADEON_GPIO_MONID
 519          * DDC_CRT2          = RADEON_GPIO_MONID
 520          * rs3xx/rs4xx
 521          * DDC_MONID         = RADEON_GPIOPAD_MASK
 522          * DDC_CRT2          = RADEON_GPIO_MONID
 523          */
 524         switch (ddc) {
 525         case DDC_NONE_DETECTED:
 526         default:
 527                 ddc_line = 0;
 528                 break;
 529         case DDC_DVI:
 530                 ddc_line = RADEON_GPIO_DVI_DDC;
 531                 break;
 532         case DDC_VGA:
 533                 ddc_line = RADEON_GPIO_VGA_DDC;
 534                 break;
 535         case DDC_LCD:
 536                 ddc_line = RADEON_GPIOPAD_MASK;
 537                 break;
 538         case DDC_GPIO:
 539                 ddc_line = RADEON_MDGPIO_MASK;
 540                 break;
 541         case DDC_MONID:
 542                 if (rdev->family == CHIP_RS300 ||
 543                     rdev->family == CHIP_RS400 ||
 544                     rdev->family == CHIP_RS480)
 545                         ddc_line = RADEON_GPIOPAD_MASK;
 546                 else if (rdev->family == CHIP_R300 ||
 547                          rdev->family == CHIP_R350) {
 548                         ddc_line = RADEON_GPIO_DVI_DDC;
 549                         ddc = DDC_DVI;
 550                 } else
 551                         ddc_line = RADEON_GPIO_MONID;
 552                 break;
 553         case DDC_CRT2:
 554                 if (rdev->family == CHIP_R200 ||
 555                     rdev->family == CHIP_R300 ||
 556                     rdev->family == CHIP_R350) {
 557                         ddc_line = RADEON_GPIO_DVI_DDC;
 558                         ddc = DDC_DVI;
 559                 } else if (rdev->family == CHIP_RS300 ||
 560                            rdev->family == CHIP_RS400 ||
 561                            rdev->family == CHIP_RS480)
 562                         ddc_line = RADEON_GPIO_MONID;
 563                 else if (rdev->family >= CHIP_RV350) {
 564                         ddc_line = RADEON_GPIO_MONID;
 565                         ddc = DDC_MONID;
 566                 } else
 567                         ddc_line = RADEON_GPIO_CRT2_DDC;
 568                 break;
 569         }
 570
 571         if (ddc_line == RADEON_GPIOPAD_MASK) {
 572                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 573                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 574                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 575                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 576                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 577                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 578                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 579                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 580         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 581                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 582                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 583                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 584                 i2c.a_data_reg = RADEON_MDGPIO_A;
 585                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 586                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 587                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 588                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 589         } else {
 590                 i2c.mask_clk_reg = ddc_line;
 591                 i2c.mask_data_reg = ddc_line;
 592                 i2c.a_clk_reg = ddc_line;
 593                 i2c.a_data_reg = ddc_line;
 594                 i2c.en_clk_reg = ddc_line;
 595                 i2c.en_data_reg = ddc_line;
 596                 i2c.y_clk_reg = ddc_line;
 597                 i2c.y_data_reg = ddc_line;
 598         }
 599
 600         if (clk_mask && data_mask) {
 601                 /* system specific masks */
 602                 i2c.mask_clk_mask = clk_mask;
 603                 i2c.mask_data_mask = data_mask;
 604                 i2c.a_clk_mask = clk_mask;
 605                 i2c.a_data_mask = data_mask;
 606                 i2c.en_clk_mask = clk_mask;
 607                 i2c.en_data_mask = data_mask;
 608                 i2c.y_clk_mask = clk_mask;
 609                 i2c.y_data_mask = data_mask;
 610         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 611                    (ddc_line == RADEON_MDGPIO_MASK)) {
 612                 /* default gpiopad masks */
 613                 i2c.mask_clk_mask = (0x20 << 8);
 614                 i2c.mask_data_mask = 0x80;
 615                 i2c.a_clk_mask = (0x20 << 8);
 616                 i2c.a_data_mask = 0x80;
 617                 i2c.en_clk_mask = (0x20 << 8);
 618                 i2c.en_data_mask = 0x80;
 619                 i2c.y_clk_mask = (0x20 << 8);
 620                 i2c.y_data_mask = 0x80;
 621         } else {
 622                 /* default masks for ddc pads */
 623                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 624                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 625                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 626                 i2c.a_data_mask = RADEON_GPIO_A_0;
 627                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 628                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 629                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 630                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 631         }
 632
 633         switch (rdev->family) {
 634         case CHIP_R100:
 635         case CHIP_RV100:
 636         case CHIP_RS100:
 637         case CHIP_RV200:
 638         case CHIP_RS200:
 639         case CHIP_RS300:
 640                 switch (ddc_line) {
 641                 case RADEON_GPIO_DVI_DDC:
 642                         i2c.hw_capable = true;
 643                         break;
 644                 default:
 645                         i2c.hw_capable = false;
 646                         break;
 647                 }
 648                 break;
 649         case CHIP_R200:
 650                 switch (ddc_line) {
 651                 case RADEON_GPIO_DVI_DDC:
 652                 case RADEON_GPIO_MONID:
 653                         i2c.hw_capable = true;
 654                         break;
 655                 default:
 656                         i2c.hw_capable = false;
 657                         break;
 658                 }
 659                 break;
 660         case CHIP_RV250:
 661         case CHIP_RV280:
 662                 switch (ddc_line) {
 663                 case RADEON_GPIO_VGA_DDC:
 664                 case RADEON_GPIO_DVI_DDC:
 665                 case RADEON_GPIO_CRT2_DDC:
 666                         i2c.hw_capable = true;
 667                         break;
 668                 default:
 669                         i2c.hw_capable = false;
 670                         break;
 671                 }
 672                 break;
 673         case CHIP_R300:
 674         case CHIP_R350:
 675                 switch (ddc_line) {
 676                 case RADEON_GPIO_VGA_DDC:
 677                 case RADEON_GPIO_DVI_DDC:
 678                         i2c.hw_capable = true;
 679                         break;
 680                 default:
 681                         i2c.hw_capable = false;
 682                         break;
 683                 }
 684                 break;
 685         case CHIP_RV350:
 686         case CHIP_RV380:
 687         case CHIP_RS400:
 688         case CHIP_RS480:
 689                 switch (ddc_line) {
 690                 case RADEON_GPIO_VGA_DDC:
 691                 case RADEON_GPIO_DVI_DDC:
 692                         i2c.hw_capable = true;
 693                         break;
 694                 case RADEON_GPIO_MONID:
 695                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 696                          * reliably on some pre-r4xx hardware; not sure why.
 697                          */
 698                         i2c.hw_capable = false;
 699                         break;
 700                 default:
 701                         i2c.hw_capable = false;
 702                         break;
 703                 }
 704                 break;
 705         default:
 706                 i2c.hw_capable = false;
 707                 break;
 708         }
 709         i2c.mm_i2c = false;
 710
 711         i2c.i2c_id = ddc;
 712         i2c.hpd = RADEON_HPD_NONE;
 713
 714         if (ddc_line)
 715                 i2c.valid = true;
 716         else
 717                 i2c.valid = false;
 718
 719         return i2c;
 720 }
 721
 722 void radeon_combios_i2c_init(struct radeon_device *rdev)
 723 {
 724         struct drm_device *dev = rdev->ddev;
 725         struct radeon_i2c_bus_rec i2c;
 726
 727         /* actual hw pads
 728          * r1xx/rs2xx/rs3xx
 729          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 730          * r200
 731          * 0x60, 0x64, 0x68, mm
 732          * r300/r350
 733          * 0x60, 0x64, mm
 734          * rv2xx/rv3xx/rs4xx
 735          * 0x60, 0x64, 0x68, gpiopads, mm
 736          */
 737
 738         /* 0x60 */
 739         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 740         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 741         /* 0x64 */
 742         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 743         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 744
 745         /* mm i2c */
 746         i2c.valid = true;
 747         i2c.hw_capable = true;
 748         i2c.mm_i2c = true;
 749         i2c.i2c_id = 0xa0;
 750         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 751
 752         if (rdev->family == CHIP_R300 ||
 753             rdev->family == CHIP_R350) {
 754                 /* only 2 sw i2c pads */
 755         } else if (rdev->family == CHIP_RS300 ||
 756                    rdev->family == CHIP_RS400 ||
 757                    rdev->family == CHIP_RS480) {
 758                 u16 offset;
 759                 u8 id, blocks, clk, data;
 760                 int i;
 761
 762                 /* 0x68 */
 763                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 764                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 765
 766                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 767                 if (offset) {
 768                         blocks = RBIOS8(offset + 2);
 769                         for (i = 0; i < blocks; i++) {
 770                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 771                                 if (id == 136) {
 772                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 773                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 774                                         /* gpiopad */
 775                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 776                                                                     (1 << clk), (1 << data));
 777                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 778                                         break;
 779                                 }
 780                         }
 781                 }
 782         } else if (rdev->family >= CHIP_R200) {
 783                 /* 0x68 */
 784                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 785                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 786         } else {
 787                 /* 0x68 */
 788                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 789                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 790                 /* 0x6c */
 791                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 792                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 793         }
 794 }
 795
 796 bool radeon_combios_get_clock_info(struct drm_device *dev)
 797 {
 798         struct radeon_device *rdev = dev->dev_private;
 799         uint16_t pll_info;
 800         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 801         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 802         struct radeon_pll *spll = &rdev->clock.spll;
 803         struct radeon_pll *mpll = &rdev->clock.mpll;
 804         int8_t rev;
 805         uint16_t sclk, mclk;
 806
 807         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 808         if (pll_info) {
 809                 rev = RBIOS8(pll_info);
 810
 811                 /* pixel clocks */
 812                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 813                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 814                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 815                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 816                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 817                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 818
 819                 if (rev > 9) {
 820                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 821                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 822                 } else {
 823                         p1pll->pll_in_min = 40;
 824                         p1pll->pll_in_max = 500;
 825                 }
 826                 *p2pll = *p1pll;
 827
 828                 /* system clock */
 829                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 830                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 831                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 832                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 833
 834                 if (rev > 10) {
 835                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 836                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 837                 } else {
 838                         /* ??? */
 839                         spll->pll_in_min = 40;
 840                         spll->pll_in_max = 500;
 841                 }
 842
 843                 /* memory clock */
 844                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 845                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 846                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 847                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 848
 849                 if (rev > 10) {
 850                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 851                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 852                 } else {
 853                         /* ??? */
 854                         mpll->pll_in_min = 40;
 855                         mpll->pll_in_max = 500;
 856                 }
 857
 858                 /* default sclk/mclk */
 859                 sclk = RBIOS16(pll_info + 0xa);
 860                 mclk = RBIOS16(pll_info + 0x8);
 861                 if (sclk == 0)
 862                         sclk = 200 * 100;
 863                 if (mclk == 0)
 864                         mclk = 200 * 100;
 865
 866                 rdev->clock.default_sclk = sclk;
 867                 rdev->clock.default_mclk = mclk;
 868
 869                 return true;
 870         }
 871         return false;
 872 }
 873
 874 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 875 {
 876         struct drm_device *dev = rdev->ddev;
 877         u16 igp_info;
 878
 879         /* sideport is AMD only */
 880         if (rdev->family == CHIP_RS400)
 881                 return false;
 882
 883         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 884
 885         if (igp_info) {
 886                 if (RBIOS16(igp_info + 0x4))
 887                         return true;
 888         }
 889         return false;
 890 }
 891
 892 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 893         0x00000808,             /* r100  */
 894         0x00000808,             /* rv100 */
 895         0x00000808,             /* rs100 */
 896         0x00000808,             /* rv200 */
 897         0x00000808,             /* rs200 */
 898         0x00000808,             /* r200  */
 899         0x00000808,             /* rv250 */
 900         0x00000000,             /* rs300 */
 901         0x00000808,             /* rv280 */
 902         0x00000808,             /* r300  */
 903         0x00000808,             /* r350  */
 904         0x00000808,             /* rv350 */
 905         0x00000808,             /* rv380 */
 906         0x00000808,             /* r420  */
 907         0x00000808,             /* r423  */
 908         0x00000808,             /* rv410 */
 909         0x00000000,             /* rs400 */
 910         0x00000000,             /* rs480 */
 911 };
 912
 913 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 914                                                           struct radeon_encoder_primary_dac *p_dac)
 915 {
 916         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 917         return;
 918 }
 919
 920 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 921                                                                        radeon_encoder
 922                                                                        *encoder)
 923 {
 924         struct drm_device *dev = encoder->base.dev;
 925         struct radeon_device *rdev = dev->dev_private;
 926         uint16_t dac_info;
 927         uint8_t rev, bg, dac;
 928         struct radeon_encoder_primary_dac *p_dac = NULL;
 929         int found = 0;
 930
 931         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 932                         GFP_KERNEL);
 933
 934         if (!p_dac)
 935                 return NULL;
 936
 937         /* check CRT table */
 938         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 939         if (dac_info) {
 940                 rev = RBIOS8(dac_info) & 0x3;
 941                 if (rev < 2) {
 942                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 943                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 944                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 945                 } else {
 946                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 947                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 948                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 949                 }
 950                 /* if the values are all zeros, use the table */
 951                 if (p_dac->ps2_pdac_adj)
 952                         found = 1;
 953         }
 954
 955         if (!found) /* fallback to defaults */
 956                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 957
 958         return p_dac;
 959 }
 960
 961 enum radeon_tv_std
 962 radeon_combios_get_tv_info(struct radeon_device *rdev)
 963 {
 964         struct drm_device *dev = rdev->ddev;
 965         uint16_t tv_info;
 966         enum radeon_tv_std tv_std = TV_STD_NTSC;
 967
 968         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 969         if (tv_info) {
 970                 if (RBIOS8(tv_info + 6) == 'T') {
 971                         switch (RBIOS8(tv_info + 7) & 0xf) {
 972                         case 1:
 973                                 tv_std = TV_STD_NTSC;
 974                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 975                                 break;
 976                         case 2:
 977                                 tv_std = TV_STD_PAL;
 978                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 979                                 break;
 980                         case 3:
 981                                 tv_std = TV_STD_PAL_M;
 982                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 983                                 break;
 984                         case 4:
 985                                 tv_std = TV_STD_PAL_60;
 986                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 987                                 break;
 988                         case 5:
 989                                 tv_std = TV_STD_NTSC_J;
 990                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 991                                 break;
 992                         case 6:
 993                                 tv_std = TV_STD_SCART_PAL;
 994                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 995                                 break;
 996                         default:
 997                                 tv_std = TV_STD_NTSC;
 998                                 DRM_DEBUG_KMS
 999                                     ("Unknown TV standard; defaulting to NTSC\n");
1000                                 break;
1001                         }
1002
1003                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1004                         case 0:
1005                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1006                                 break;
1007                         case 1:
1008                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1009                                 break;
1010                         case 2:
1011                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1012                                 break;
1013                         case 3:
1014                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1015                                 break;
1016                         default:
1017                                 break;
1018                         }
1019                 }
1020         }
1021         return tv_std;
1022 }
1023
1024 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1025         0x00000000,             /* r100  */
1026         0x00280000,             /* rv100 */
1027         0x00000000,             /* rs100 */
1028         0x00880000,             /* rv200 */
1029         0x00000000,             /* rs200 */
1030         0x00000000,             /* r200  */
1031         0x00770000,             /* rv250 */
1032         0x00290000,             /* rs300 */
1033         0x00560000,             /* rv280 */
1034         0x00780000,             /* r300  */
1035         0x00770000,             /* r350  */
1036         0x00780000,             /* rv350 */
1037         0x00780000,             /* rv380 */
1038         0x01080000,             /* r420  */
1039         0x01080000,             /* r423  */
1040         0x01080000,             /* rv410 */
1041         0x00780000,             /* rs400 */
1042         0x00780000,             /* rs480 */
1043 };
1044
1045 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1046                                                      struct radeon_encoder_tv_dac *tv_dac)
1047 {
1048         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1049         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1050                 tv_dac->ps2_tvdac_adj = 0x00880000;
1051         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1052         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1053         return;
1054 }
1055
1056 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1057                                                              radeon_encoder
1058                                                              *encoder)
1059 {
1060         struct drm_device *dev = encoder->base.dev;
1061         struct radeon_device *rdev = dev->dev_private;
1062         uint16_t dac_info;
1063         uint8_t rev, bg, dac;
1064         struct radeon_encoder_tv_dac *tv_dac = NULL;
1065         int found = 0;
1066
1067         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1068         if (!tv_dac)
1069                 return NULL;
1070
1071         /* first check TV table */
1072         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1073         if (dac_info) {
1074                 rev = RBIOS8(dac_info + 0x3);
1075                 if (rev > 4) {
1076                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1077                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1078                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1079
1080                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1081                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1082                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1083
1084                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1085                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1086                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1087                         /* if the values are all zeros, use the table */
1088                         if (tv_dac->ps2_tvdac_adj)
1089                                 found = 1;
1090                 } else if (rev > 1) {
1091                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1092                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1093                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1094
1095                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1096                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1097                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1098
1099                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1100                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1101                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1102                         /* if the values are all zeros, use the table */
1103                         if (tv_dac->ps2_tvdac_adj)
1104                                 found = 1;
1105                 }
1106                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1107         }
1108         if (!found) {
1109                 /* then check CRT table */
1110                 dac_info =
1111                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1112                 if (dac_info) {
1113                         rev = RBIOS8(dac_info) & 0x3;
1114                         if (rev < 2) {
1115                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1116                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1117                                 tv_dac->ps2_tvdac_adj =
1118                                     (bg << 16) | (dac << 20);
1119                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1120                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1121                                 /* if the values are all zeros, use the table */
1122                                 if (tv_dac->ps2_tvdac_adj)
1123                                         found = 1;
1124                         } else {
1125                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1126                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1127                                 tv_dac->ps2_tvdac_adj =
1128                                     (bg << 16) | (dac << 20);
1129                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1130                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1131                                 /* if the values are all zeros, use the table */
1132                                 if (tv_dac->ps2_tvdac_adj)
1133                                         found = 1;
1134                         }
1135                 } else {
1136                         DRM_INFO("No TV DAC info found in BIOS\n");
1137                 }
1138         }
1139
1140         if (!found) /* fallback to defaults */
1141                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1142
1143         return tv_dac;
1144 }
1145
1146 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1147                                                                          radeon_device
1148                                                                          *rdev)
1149 {
1150         struct radeon_encoder_lvds *lvds = NULL;
1151         uint32_t fp_vert_stretch, fp_horz_stretch;
1152         uint32_t ppll_div_sel, ppll_val;
1153         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1154
1155         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1156
1157         if (!lvds)
1158                 return NULL;
1159
1160         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1161         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1162
1163         /* These should be fail-safe defaults, fingers crossed */
1164         lvds->panel_pwr_delay = 200;
1165         lvds->panel_vcc_delay = 2000;
1166
1167         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1168         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1169         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1170
1171         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1172                 lvds->native_mode.vdisplay =
1173                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1174                      RADEON_VERT_PANEL_SHIFT) + 1;
1175         else
1176                 lvds->native_mode.vdisplay =
1177                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1178
1179         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1180                 lvds->native_mode.hdisplay =
1181                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1182                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1183         else
1184                 lvds->native_mode.hdisplay =
1185                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1186
1187         if ((lvds->native_mode.hdisplay < 640) ||
1188             (lvds->native_mode.vdisplay < 480)) {
1189                 lvds->native_mode.hdisplay = 640;
1190                 lvds->native_mode.vdisplay = 480;
1191         }
1192
1193         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1194         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1195         if ((ppll_val & 0x000707ff) == 0x1bb)
1196                 lvds->use_bios_dividers = false;
1197         else {
1198                 lvds->panel_ref_divider =
1199                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1200                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1201                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1202
1203                 if ((lvds->panel_ref_divider != 0) &&
1204                     (lvds->panel_fb_divider > 3))
1205                         lvds->use_bios_dividers = true;
1206         }
1207         lvds->panel_vcc_delay = 200;
1208
1209         DRM_INFO("Panel info derived from registers\n");
1210         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1211                  lvds->native_mode.vdisplay);
1212
1213         return lvds;
1214 }
1215
1216 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1217                                                          *encoder)
1218 {
1219         struct drm_device *dev = encoder->base.dev;
1220         struct radeon_device *rdev = dev->dev_private;
1221         uint16_t lcd_info;
1222         uint32_t panel_setup;
1223         char stmp[30];
1224         int tmp, i;
1225         struct radeon_encoder_lvds *lvds = NULL;
1226
1227         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1228
1229         if (lcd_info) {
1230                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1231
1232                 if (!lvds)
1233                         return NULL;
1234
1235                 for (i = 0; i < 24; i++)
1236                         stmp[i] = RBIOS8(lcd_info + i + 1);
1237                 stmp[24] = 0;
1238
1239                 DRM_INFO("Panel ID String: %s\n", stmp);
1240
1241                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1242                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1243
1244                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1245                          lvds->native_mode.vdisplay);
1246
1247                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1248                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1249
1250                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1251                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1252                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1253
1254                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1255                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1256                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1257                 if ((lvds->panel_ref_divider != 0) &&
1258                     (lvds->panel_fb_divider > 3))
1259                         lvds->use_bios_dividers = true;
1260
1261                 panel_setup = RBIOS32(lcd_info + 0x39);
1262                 lvds->lvds_gen_cntl = 0xff00;
1263                 if (panel_setup & 0x1)
1264                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1265
1266                 if ((panel_setup >> 4) & 0x1)
1267                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1268
1269                 switch ((panel_setup >> 8) & 0x7) {
1270                 case 0:
1271                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1272                         break;
1273                 case 1:
1274                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1275                         break;
1276                 case 2:
1277                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1278                         break;
1279                 default:
1280                         break;
1281                 }
1282
1283                 if ((panel_setup >> 16) & 0x1)
1284                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1285
1286                 if ((panel_setup >> 17) & 0x1)
1287                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1288
1289                 if ((panel_setup >> 18) & 0x1)
1290                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1291
1292                 if ((panel_setup >> 23) & 0x1)
1293                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1294
1295                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1296
1297                 for (i = 0; i < 32; i++) {
1298                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1299                         if (tmp == 0)
1300                                 break;
1301
1302                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1303                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1304                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1305                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1306                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1307                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1308                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1309                                         (RBIOS8(tmp + 23) * 8);
1310
1311                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1312                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1313                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1314                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1315                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1316                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1317
1318                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1319                                 lvds->native_mode.flags = 0;
1320                                 /* set crtc values */
1321                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1322
1323                         }
1324                 }
1325         } else {
1326                 DRM_INFO("No panel info found in BIOS\n");
1327                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1328         }
1329
1330         if (lvds)
1331                 encoder->native_mode = lvds->native_mode;
1332         return lvds;
1333 }
1334
1335 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1336         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1337         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1338         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1339         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1340         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1341         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1342         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1343         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1344         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1345         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1346         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1347         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1348         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1349         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1350         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1351         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1352         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1353         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1354 };
1355
1356 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1357                                             struct radeon_encoder_int_tmds *tmds)
1358 {
1359         struct drm_device *dev = encoder->base.dev;
1360         struct radeon_device *rdev = dev->dev_private;
1361         int i;
1362
1363         for (i = 0; i < 4; i++) {
1364                 tmds->tmds_pll[i].value =
1365                         default_tmds_pll[rdev->family][i].value;
1366                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1367         }
1368
1369         return true;
1370 }
1371
1372 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1373                                               struct radeon_encoder_int_tmds *tmds)
1374 {
1375         struct drm_device *dev = encoder->base.dev;
1376         struct radeon_device *rdev = dev->dev_private;
1377         uint16_t tmds_info;
1378         int i, n;
1379         uint8_t ver;
1380
1381         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1382
1383         if (tmds_info) {
1384                 ver = RBIOS8(tmds_info);
1385                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1386                 if (ver == 3) {
1387                         n = RBIOS8(tmds_info + 5) + 1;
1388                         if (n > 4)
1389                                 n = 4;
1390                         for (i = 0; i < n; i++) {
1391                                 tmds->tmds_pll[i].value =
1392                                     RBIOS32(tmds_info + i * 10 + 0x08);
1393                                 tmds->tmds_pll[i].freq =
1394                                     RBIOS16(tmds_info + i * 10 + 0x10);
1395                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1396                                           tmds->tmds_pll[i].freq,
1397                                           tmds->tmds_pll[i].value);
1398                         }
1399                 } else if (ver == 4) {
1400                         int stride = 0;
1401                         n = RBIOS8(tmds_info + 5) + 1;
1402                         if (n > 4)
1403                                 n = 4;
1404                         for (i = 0; i < n; i++) {
1405                                 tmds->tmds_pll[i].value =
1406                                     RBIOS32(tmds_info + stride + 0x08);
1407                                 tmds->tmds_pll[i].freq =
1408                                     RBIOS16(tmds_info + stride + 0x10);
1409                                 if (i == 0)
1410                                         stride += 10;
1411                                 else
1412                                         stride += 6;
1413                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1414                                           tmds->tmds_pll[i].freq,
1415                                           tmds->tmds_pll[i].value);
1416                         }
1417                 }
1418         } else {
1419                 DRM_INFO("No TMDS info found in BIOS\n");
1420                 return false;
1421         }
1422         return true;
1423 }
1424
1425 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1426                                                 struct radeon_encoder_ext_tmds *tmds)
1427 {
1428         struct drm_device *dev = encoder->base.dev;
1429         struct radeon_device *rdev = dev->dev_private;
1430         struct radeon_i2c_bus_rec i2c_bus;
1431
1432         /* default for macs */
1433         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1434         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1435
1436         /* XXX some macs have duallink chips */
1437         switch (rdev->mode_info.connector_table) {
1438         case CT_POWERBOOK_EXTERNAL:
1439         case CT_MINI_EXTERNAL:
1440         default:
1441                 tmds->dvo_chip = DVO_SIL164;
1442                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1443                 break;
1444         }
1445
1446         return true;
1447 }
1448
1449 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1450                                                   struct radeon_encoder_ext_tmds *tmds)
1451 {
1452         struct drm_device *dev = encoder->base.dev;
1453         struct radeon_device *rdev = dev->dev_private;
1454         uint16_t offset;
1455         uint8_t ver;
1456         enum radeon_combios_ddc gpio;
1457         struct radeon_i2c_bus_rec i2c_bus;
1458
1459         tmds->i2c_bus = NULL;
1460         if (rdev->flags & RADEON_IS_IGP) {
1461                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1462                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1463                 tmds->dvo_chip = DVO_SIL164;
1464                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1465         } else {
1466                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1467                 if (offset) {
1468                         ver = RBIOS8(offset);
1469                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1470                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1471                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1472                         gpio = RBIOS8(offset + 4 + 3);
1473                         if (gpio == DDC_LCD) {
1474                                 /* MM i2c */
1475                                 i2c_bus.valid = true;
1476                                 i2c_bus.hw_capable = true;
1477                                 i2c_bus.mm_i2c = true;
1478                                 i2c_bus.i2c_id = 0xa0;
1479                         } else
1480                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1481                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1482                 }
1483         }
1484
1485         if (!tmds->i2c_bus) {
1486                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1487                 return false;
1488         }
1489
1490         return true;
1491 }
1492
1493 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1494 {
1495         struct radeon_device *rdev = dev->dev_private;
1496         struct radeon_i2c_bus_rec ddc_i2c;
1497         struct radeon_hpd hpd;
1498
1499         rdev->mode_info.connector_table = radeon_connector_table;
1500         if (rdev->mode_info.connector_table == CT_NONE) {
1501 #ifdef CONFIG_PPC_PMAC
1502                 if (of_machine_is_compatible("PowerBook3,3")) {
1503                         /* powerbook with VGA */
1504                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1505                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1506                            of_machine_is_compatible("PowerBook3,5")) {
1507                         /* powerbook with internal tmds */
1508                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1509                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1510                            of_machine_is_compatible("PowerBook5,2") ||
1511                            of_machine_is_compatible("PowerBook5,3") ||
1512                            of_machine_is_compatible("PowerBook5,4") ||
1513                            of_machine_is_compatible("PowerBook5,5")) {
1514                         /* powerbook with external single link tmds (sil164) */
1515                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1516                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1517                         /* powerbook with external dual or single link tmds */
1518                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1519                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1520                            of_machine_is_compatible("PowerBook5,8") ||
1521                            of_machine_is_compatible("PowerBook5,9")) {
1522                         /* PowerBook6,2 ? */
1523                         /* powerbook with external dual link tmds (sil1178?) */
1524                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1525                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1526                            of_machine_is_compatible("PowerBook4,2") ||
1527                            of_machine_is_compatible("PowerBook4,3") ||
1528                            of_machine_is_compatible("PowerBook6,3") ||
1529                            of_machine_is_compatible("PowerBook6,5") ||
1530                            of_machine_is_compatible("PowerBook6,7")) {
1531                         /* ibook */
1532                         rdev->mode_info.connector_table = CT_IBOOK;
1533                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1534                         /* emac */
1535                         rdev->mode_info.connector_table = CT_EMAC;
1536                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1537                         /* mini with internal tmds */
1538                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1539                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1540                         /* mini with external tmds */
1541                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1542                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1543                         /* PowerMac8,1 ? */
1544                         /* imac g5 isight */
1545                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1546                 } else if ((rdev->pdev->device == 0x4a48) &&
1547                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1548                            (rdev->pdev->subsystem_device == 0x4a48)) {
1549                         /* Mac X800 */
1550                         rdev->mode_info.connector_table = CT_MAC_X800;
1551                 } else if ((rdev->pdev->device == 0x4150) &&
1552                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1553                            (rdev->pdev->subsystem_device == 0x4150)) {
1554                         /* Mac G5 9600 */
1555                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1556                 } else
1557 #endif /* CONFIG_PPC_PMAC */
1558 #ifdef CONFIG_PPC64
1559                 if (ASIC_IS_RN50(rdev))
1560                         rdev->mode_info.connector_table = CT_RN50_POWER;
1561                 else
1562 #endif
1563                         rdev->mode_info.connector_table = CT_GENERIC;
1564         }
1565
1566         switch (rdev->mode_info.connector_table) {
1567         case CT_GENERIC:
1568                 DRM_INFO("Connector Table: %d (generic)\n",
1569                          rdev->mode_info.connector_table);
1570                 /* these are the most common settings */
1571                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1572                         /* VGA - primary dac */
1573                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1574                         hpd.hpd = RADEON_HPD_NONE;
1575                         radeon_add_legacy_encoder(dev,
1576                                                   radeon_get_encoder_enum(dev,
1577                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1578                                                                         1),
1579                                                   ATOM_DEVICE_CRT1_SUPPORT);
1580                         radeon_add_legacy_connector(dev, 0,
1581                                                     ATOM_DEVICE_CRT1_SUPPORT,
1582                                                     DRM_MODE_CONNECTOR_VGA,
1583                                                     &ddc_i2c,
1584                                                     CONNECTOR_OBJECT_ID_VGA,
1585                                                     &hpd);
1586                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1587                         /* LVDS */
1588                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1589                         hpd.hpd = RADEON_HPD_NONE;
1590                         radeon_add_legacy_encoder(dev,
1591                                                   radeon_get_encoder_enum(dev,
1592                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1593                                                                         0),
1594                                                   ATOM_DEVICE_LCD1_SUPPORT);
1595                         radeon_add_legacy_connector(dev, 0,
1596                                                     ATOM_DEVICE_LCD1_SUPPORT,
1597                                                     DRM_MODE_CONNECTOR_LVDS,
1598                                                     &ddc_i2c,
1599                                                     CONNECTOR_OBJECT_ID_LVDS,
1600                                                     &hpd);
1601
1602                         /* VGA - primary dac */
1603                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1604                         hpd.hpd = RADEON_HPD_NONE;
1605                         radeon_add_legacy_encoder(dev,
1606                                                   radeon_get_encoder_enum(dev,
1607                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1608                                                                         1),
1609                                                   ATOM_DEVICE_CRT1_SUPPORT);
1610                         radeon_add_legacy_connector(dev, 1,
1611                                                     ATOM_DEVICE_CRT1_SUPPORT,
1612                                                     DRM_MODE_CONNECTOR_VGA,
1613                                                     &ddc_i2c,
1614                                                     CONNECTOR_OBJECT_ID_VGA,
1615                                                     &hpd);
1616                 } else {
1617                         /* DVI-I - tv dac, int tmds */
1618                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1619                         hpd.hpd = RADEON_HPD_1;
1620                         radeon_add_legacy_encoder(dev,
1621                                                   radeon_get_encoder_enum(dev,
1622                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1623                                                                         0),
1624                                                   ATOM_DEVICE_DFP1_SUPPORT);
1625                         radeon_add_legacy_encoder(dev,
1626                                                   radeon_get_encoder_enum(dev,
1627                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1628                                                                         2),
1629                                                   ATOM_DEVICE_CRT2_SUPPORT);
1630                         radeon_add_legacy_connector(dev, 0,
1631                                                     ATOM_DEVICE_DFP1_SUPPORT |
1632                                                     ATOM_DEVICE_CRT2_SUPPORT,
1633                                                     DRM_MODE_CONNECTOR_DVII,
1634                                                     &ddc_i2c,
1635                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1636                                                     &hpd);
1637
1638                         /* VGA - primary dac */
1639                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1640                         hpd.hpd = RADEON_HPD_NONE;
1641                         radeon_add_legacy_encoder(dev,
1642                                                   radeon_get_encoder_enum(dev,
1643                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1644                                                                         1),
1645                                                   ATOM_DEVICE_CRT1_SUPPORT);
1646                         radeon_add_legacy_connector(dev, 1,
1647                                                     ATOM_DEVICE_CRT1_SUPPORT,
1648                                                     DRM_MODE_CONNECTOR_VGA,
1649                                                     &ddc_i2c,
1650                                                     CONNECTOR_OBJECT_ID_VGA,
1651                                                     &hpd);
1652                 }
1653
1654                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1655                         /* TV - tv dac */
1656                         ddc_i2c.valid = false;
1657                         hpd.hpd = RADEON_HPD_NONE;
1658                         radeon_add_legacy_encoder(dev,
1659                                                   radeon_get_encoder_enum(dev,
1660                                                                         ATOM_DEVICE_TV1_SUPPORT,
1661                                                                         2),
1662                                                   ATOM_DEVICE_TV1_SUPPORT);
1663                         radeon_add_legacy_connector(dev, 2,
1664                                                     ATOM_DEVICE_TV1_SUPPORT,
1665                                                     DRM_MODE_CONNECTOR_SVIDEO,
1666                                                     &ddc_i2c,
1667                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1668                                                     &hpd);
1669                 }
1670                 break;
1671         case CT_IBOOK:
1672                 DRM_INFO("Connector Table: %d (ibook)\n",
1673                          rdev->mode_info.connector_table);
1674                 /* LVDS */
1675                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1676                 hpd.hpd = RADEON_HPD_NONE;
1677                 radeon_add_legacy_encoder(dev,
1678                                           radeon_get_encoder_enum(dev,
1679                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1680                                                                 0),
1681                                           ATOM_DEVICE_LCD1_SUPPORT);
1682                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1683                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1684                                             CONNECTOR_OBJECT_ID_LVDS,
1685                                             &hpd);
1686                 /* VGA - TV DAC */
1687                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1688                 hpd.hpd = RADEON_HPD_NONE;
1689                 radeon_add_legacy_encoder(dev,
1690                                           radeon_get_encoder_enum(dev,
1691                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1692                                                                 2),
1693                                           ATOM_DEVICE_CRT2_SUPPORT);
1694                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1695                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1696                                             CONNECTOR_OBJECT_ID_VGA,
1697                                             &hpd);
1698                 /* TV - TV DAC */
1699                 ddc_i2c.valid = false;
1700                 hpd.hpd = RADEON_HPD_NONE;
1701                 radeon_add_legacy_encoder(dev,
1702                                           radeon_get_encoder_enum(dev,
1703                                                                 ATOM_DEVICE_TV1_SUPPORT,
1704                                                                 2),
1705                                           ATOM_DEVICE_TV1_SUPPORT);
1706                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1707                                             DRM_MODE_CONNECTOR_SVIDEO,
1708                                             &ddc_i2c,
1709                                             CONNECTOR_OBJECT_ID_SVIDEO,
1710                                             &hpd);
1711                 break;
1712         case CT_POWERBOOK_EXTERNAL:
1713                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1714                          rdev->mode_info.connector_table);
1715                 /* LVDS */
1716                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1717                 hpd.hpd = RADEON_HPD_NONE;
1718                 radeon_add_legacy_encoder(dev,
1719                                           radeon_get_encoder_enum(dev,
1720                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1721                                                                 0),
1722                                           ATOM_DEVICE_LCD1_SUPPORT);
1723                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1724                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1725                                             CONNECTOR_OBJECT_ID_LVDS,
1726                                             &hpd);
1727                 /* DVI-I - primary dac, ext tmds */
1728                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1729                 hpd.hpd = RADEON_HPD_2; /* ??? */
1730                 radeon_add_legacy_encoder(dev,
1731                                           radeon_get_encoder_enum(dev,
1732                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1733                                                                 0),
1734                                           ATOM_DEVICE_DFP2_SUPPORT);
1735                 radeon_add_legacy_encoder(dev,
1736                                           radeon_get_encoder_enum(dev,
1737                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1738                                                                 1),
1739                                           ATOM_DEVICE_CRT1_SUPPORT);
1740                 /* XXX some are SL */
1741                 radeon_add_legacy_connector(dev, 1,
1742                                             ATOM_DEVICE_DFP2_SUPPORT |
1743                                             ATOM_DEVICE_CRT1_SUPPORT,
1744                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1745                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1746                                             &hpd);
1747                 /* TV - TV DAC */
1748                 ddc_i2c.valid = false;
1749                 hpd.hpd = RADEON_HPD_NONE;
1750                 radeon_add_legacy_encoder(dev,
1751                                           radeon_get_encoder_enum(dev,
1752                                                                 ATOM_DEVICE_TV1_SUPPORT,
1753                                                                 2),
1754                                           ATOM_DEVICE_TV1_SUPPORT);
1755                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1756                                             DRM_MODE_CONNECTOR_SVIDEO,
1757                                             &ddc_i2c,
1758                                             CONNECTOR_OBJECT_ID_SVIDEO,
1759                                             &hpd);
1760                 break;
1761         case CT_POWERBOOK_INTERNAL:
1762                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1763                          rdev->mode_info.connector_table);
1764                 /* LVDS */
1765                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1766                 hpd.hpd = RADEON_HPD_NONE;
1767                 radeon_add_legacy_encoder(dev,
1768                                           radeon_get_encoder_enum(dev,
1769                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1770                                                                 0),
1771                                           ATOM_DEVICE_LCD1_SUPPORT);
1772                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1773                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1774                                             CONNECTOR_OBJECT_ID_LVDS,
1775                                             &hpd);
1776                 /* DVI-I - primary dac, int tmds */
1777                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1778                 hpd.hpd = RADEON_HPD_1; /* ??? */
1779                 radeon_add_legacy_encoder(dev,
1780                                           radeon_get_encoder_enum(dev,
1781                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1782                                                                 0),
1783                                           ATOM_DEVICE_DFP1_SUPPORT);
1784                 radeon_add_legacy_encoder(dev,
1785                                           radeon_get_encoder_enum(dev,
1786                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1787                                                                 1),
1788                                           ATOM_DEVICE_CRT1_SUPPORT);
1789                 radeon_add_legacy_connector(dev, 1,
1790                                             ATOM_DEVICE_DFP1_SUPPORT |
1791                                             ATOM_DEVICE_CRT1_SUPPORT,
1792                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1793                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1794                                             &hpd);
1795                 /* TV - TV DAC */
1796                 ddc_i2c.valid = false;
1797                 hpd.hpd = RADEON_HPD_NONE;
1798                 radeon_add_legacy_encoder(dev,
1799                                           radeon_get_encoder_enum(dev,
1800                                                                 ATOM_DEVICE_TV1_SUPPORT,
1801                                                                 2),
1802                                           ATOM_DEVICE_TV1_SUPPORT);
1803                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1804                                             DRM_MODE_CONNECTOR_SVIDEO,
1805                                             &ddc_i2c,
1806                                             CONNECTOR_OBJECT_ID_SVIDEO,
1807                                             &hpd);
1808                 break;
1809         case CT_POWERBOOK_VGA:
1810                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1811                          rdev->mode_info.connector_table);
1812                 /* LVDS */
1813                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1814                 hpd.hpd = RADEON_HPD_NONE;
1815                 radeon_add_legacy_encoder(dev,
1816                                           radeon_get_encoder_enum(dev,
1817                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1818                                                                 0),
1819                                           ATOM_DEVICE_LCD1_SUPPORT);
1820                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1821                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1822                                             CONNECTOR_OBJECT_ID_LVDS,
1823                                             &hpd);
1824                 /* VGA - primary dac */
1825                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1826                 hpd.hpd = RADEON_HPD_NONE;
1827                 radeon_add_legacy_encoder(dev,
1828                                           radeon_get_encoder_enum(dev,
1829                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1830                                                                 1),
1831                                           ATOM_DEVICE_CRT1_SUPPORT);
1832                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1833                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1834                                             CONNECTOR_OBJECT_ID_VGA,
1835                                             &hpd);
1836                 /* TV - TV DAC */
1837                 ddc_i2c.valid = false;
1838                 hpd.hpd = RADEON_HPD_NONE;
1839                 radeon_add_legacy_encoder(dev,
1840                                           radeon_get_encoder_enum(dev,
1841                                                                 ATOM_DEVICE_TV1_SUPPORT,
1842                                                                 2),
1843                                           ATOM_DEVICE_TV1_SUPPORT);
1844                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1845                                             DRM_MODE_CONNECTOR_SVIDEO,
1846                                             &ddc_i2c,
1847                                             CONNECTOR_OBJECT_ID_SVIDEO,
1848                                             &hpd);
1849                 break;
1850         case CT_MINI_EXTERNAL:
1851                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1852                          rdev->mode_info.connector_table);
1853                 /* DVI-I - tv dac, ext tmds */
1854                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1855                 hpd.hpd = RADEON_HPD_2; /* ??? */
1856                 radeon_add_legacy_encoder(dev,
1857                                           radeon_get_encoder_enum(dev,
1858                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1859                                                                 0),
1860                                           ATOM_DEVICE_DFP2_SUPPORT);
1861                 radeon_add_legacy_encoder(dev,
1862                                           radeon_get_encoder_enum(dev,
1863                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1864                                                                 2),
1865                                           ATOM_DEVICE_CRT2_SUPPORT);
1866                 /* XXX are any DL? */
1867                 radeon_add_legacy_connector(dev, 0,
1868                                             ATOM_DEVICE_DFP2_SUPPORT |
1869                                             ATOM_DEVICE_CRT2_SUPPORT,
1870                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1871                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1872                                             &hpd);
1873                 /* TV - TV DAC */
1874                 ddc_i2c.valid = false;
1875                 hpd.hpd = RADEON_HPD_NONE;
1876                 radeon_add_legacy_encoder(dev,
1877                                           radeon_get_encoder_enum(dev,
1878                                                                 ATOM_DEVICE_TV1_SUPPORT,
1879                                                                 2),
1880                                           ATOM_DEVICE_TV1_SUPPORT);
1881                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1882                                             DRM_MODE_CONNECTOR_SVIDEO,
1883                                             &ddc_i2c,
1884                                             CONNECTOR_OBJECT_ID_SVIDEO,
1885                                             &hpd);
1886                 break;
1887         case CT_MINI_INTERNAL:
1888                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1889                          rdev->mode_info.connector_table);
1890                 /* DVI-I - tv dac, int tmds */
1891                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1892                 hpd.hpd = RADEON_HPD_1; /* ??? */
1893                 radeon_add_legacy_encoder(dev,
1894                                           radeon_get_encoder_enum(dev,
1895                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1896                                                                 0),
1897                                           ATOM_DEVICE_DFP1_SUPPORT);
1898                 radeon_add_legacy_encoder(dev,
1899                                           radeon_get_encoder_enum(dev,
1900                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1901                                                                 2),
1902                                           ATOM_DEVICE_CRT2_SUPPORT);
1903                 radeon_add_legacy_connector(dev, 0,
1904                                             ATOM_DEVICE_DFP1_SUPPORT |
1905                                             ATOM_DEVICE_CRT2_SUPPORT,
1906                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1907                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1908                                             &hpd);
1909                 /* TV - TV DAC */
1910                 ddc_i2c.valid = false;
1911                 hpd.hpd = RADEON_HPD_NONE;
1912                 radeon_add_legacy_encoder(dev,
1913                                           radeon_get_encoder_enum(dev,
1914                                                                 ATOM_DEVICE_TV1_SUPPORT,
1915                                                                 2),
1916                                           ATOM_DEVICE_TV1_SUPPORT);
1917                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1918                                             DRM_MODE_CONNECTOR_SVIDEO,
1919                                             &ddc_i2c,
1920                                             CONNECTOR_OBJECT_ID_SVIDEO,
1921                                             &hpd);
1922                 break;
1923         case CT_IMAC_G5_ISIGHT:
1924                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1925                          rdev->mode_info.connector_table);
1926                 /* DVI-D - int tmds */
1927                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1928                 hpd.hpd = RADEON_HPD_1; /* ??? */
1929                 radeon_add_legacy_encoder(dev,
1930                                           radeon_get_encoder_enum(dev,
1931                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1932                                                                 0),
1933                                           ATOM_DEVICE_DFP1_SUPPORT);
1934                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1935                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1936                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1937                                             &hpd);
1938                 /* VGA - tv dac */
1939                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1940                 hpd.hpd = RADEON_HPD_NONE;
1941                 radeon_add_legacy_encoder(dev,
1942                                           radeon_get_encoder_enum(dev,
1943                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1944                                                                 2),
1945                                           ATOM_DEVICE_CRT2_SUPPORT);
1946                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1947                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1948                                             CONNECTOR_OBJECT_ID_VGA,
1949                                             &hpd);
1950                 /* TV - TV DAC */
1951                 ddc_i2c.valid = false;
1952                 hpd.hpd = RADEON_HPD_NONE;
1953                 radeon_add_legacy_encoder(dev,
1954                                           radeon_get_encoder_enum(dev,
1955                                                                 ATOM_DEVICE_TV1_SUPPORT,
1956                                                                 2),
1957                                           ATOM_DEVICE_TV1_SUPPORT);
1958                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1959                                             DRM_MODE_CONNECTOR_SVIDEO,
1960                                             &ddc_i2c,
1961                                             CONNECTOR_OBJECT_ID_SVIDEO,
1962                                             &hpd);
1963                 break;
1964         case CT_EMAC:
1965                 DRM_INFO("Connector Table: %d (emac)\n",
1966                          rdev->mode_info.connector_table);
1967                 /* VGA - primary dac */
1968                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1969                 hpd.hpd = RADEON_HPD_NONE;
1970                 radeon_add_legacy_encoder(dev,
1971                                           radeon_get_encoder_enum(dev,
1972                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1973                                                                 1),
1974                                           ATOM_DEVICE_CRT1_SUPPORT);
1975                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1976                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1977                                             CONNECTOR_OBJECT_ID_VGA,
1978                                             &hpd);
1979                 /* VGA - tv dac */
1980                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1981                 hpd.hpd = RADEON_HPD_NONE;
1982                 radeon_add_legacy_encoder(dev,
1983                                           radeon_get_encoder_enum(dev,
1984                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1985                                                                 2),
1986                                           ATOM_DEVICE_CRT2_SUPPORT);
1987                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1988                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1989                                             CONNECTOR_OBJECT_ID_VGA,
1990                                             &hpd);
1991                 /* TV - TV DAC */
1992                 ddc_i2c.valid = false;
1993                 hpd.hpd = RADEON_HPD_NONE;
1994                 radeon_add_legacy_encoder(dev,
1995                                           radeon_get_encoder_enum(dev,
1996                                                                 ATOM_DEVICE_TV1_SUPPORT,
1997                                                                 2),
1998                                           ATOM_DEVICE_TV1_SUPPORT);
1999                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2000                                             DRM_MODE_CONNECTOR_SVIDEO,
2001                                             &ddc_i2c,
2002                                             CONNECTOR_OBJECT_ID_SVIDEO,
2003                                             &hpd);
2004                 break;
2005         case CT_RN50_POWER:
2006                 DRM_INFO("Connector Table: %d (rn50-power)\n",
2007                          rdev->mode_info.connector_table);
2008                 /* VGA - primary dac */
2009                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2010                 hpd.hpd = RADEON_HPD_NONE;
2011                 radeon_add_legacy_encoder(dev,
2012                                           radeon_get_encoder_enum(dev,
2013                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2014                                                                 1),
2015                                           ATOM_DEVICE_CRT1_SUPPORT);
2016                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2017                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2018                                             CONNECTOR_OBJECT_ID_VGA,
2019                                             &hpd);
2020                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2021                 hpd.hpd = RADEON_HPD_NONE;
2022                 radeon_add_legacy_encoder(dev,
2023                                           radeon_get_encoder_enum(dev,
2024                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2025                                                                 2),
2026                                           ATOM_DEVICE_CRT2_SUPPORT);
2027                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2028                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2029                                             CONNECTOR_OBJECT_ID_VGA,
2030                                             &hpd);
2031                 break;
2032         case CT_MAC_X800:
2033                 DRM_INFO("Connector Table: %d (mac x800)\n",
2034                          rdev->mode_info.connector_table);
2035                 /* DVI - primary dac, internal tmds */
2036                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2037                 hpd.hpd = RADEON_HPD_1; /* ??? */
2038                 radeon_add_legacy_encoder(dev,
2039                                           radeon_get_encoder_enum(dev,
2040                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2041                                                                   0),
2042                                           ATOM_DEVICE_DFP1_SUPPORT);
2043                 radeon_add_legacy_encoder(dev,
2044                                           radeon_get_encoder_enum(dev,
2045                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2046                                                                   1),
2047                                           ATOM_DEVICE_CRT1_SUPPORT);
2048                 radeon_add_legacy_connector(dev, 0,
2049                                             ATOM_DEVICE_DFP1_SUPPORT |
2050                                             ATOM_DEVICE_CRT1_SUPPORT,
2051                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2052                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2053                                             &hpd);
2054                 /* DVI - tv dac, dvo */
2055                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2056                 hpd.hpd = RADEON_HPD_2; /* ??? */
2057                 radeon_add_legacy_encoder(dev,
2058                                           radeon_get_encoder_enum(dev,
2059                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2060                                                                   0),
2061                                           ATOM_DEVICE_DFP2_SUPPORT);
2062                 radeon_add_legacy_encoder(dev,
2063                                           radeon_get_encoder_enum(dev,
2064                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2065                                                                   2),
2066                                           ATOM_DEVICE_CRT2_SUPPORT);
2067                 radeon_add_legacy_connector(dev, 1,
2068                                             ATOM_DEVICE_DFP2_SUPPORT |
2069                                             ATOM_DEVICE_CRT2_SUPPORT,
2070                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2071                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2072                                             &hpd);
2073                 break;
2074         case CT_MAC_G5_9600:
2075                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2076                          rdev->mode_info.connector_table);
2077                 /* DVI - tv dac, dvo */
2078                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2079                 hpd.hpd = RADEON_HPD_1; /* ??? */
2080                 radeon_add_legacy_encoder(dev,
2081                                           radeon_get_encoder_enum(dev,
2082                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2083                                                                   0),
2084                                           ATOM_DEVICE_DFP2_SUPPORT);
2085                 radeon_add_legacy_encoder(dev,
2086                                           radeon_get_encoder_enum(dev,
2087                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2088                                                                   2),
2089                                           ATOM_DEVICE_CRT2_SUPPORT);
2090                 radeon_add_legacy_connector(dev, 0,
2091                                             ATOM_DEVICE_DFP2_SUPPORT |
2092                                             ATOM_DEVICE_CRT2_SUPPORT,
2093                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2094                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2095                                             &hpd);
2096                 /* ADC - primary dac, internal tmds */
2097                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2098                 hpd.hpd = RADEON_HPD_2; /* ??? */
2099                 radeon_add_legacy_encoder(dev,
2100                                           radeon_get_encoder_enum(dev,
2101                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2102                                                                   0),
2103                                           ATOM_DEVICE_DFP1_SUPPORT);
2104                 radeon_add_legacy_encoder(dev,
2105                                           radeon_get_encoder_enum(dev,
2106                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2107                                                                   1),
2108                                           ATOM_DEVICE_CRT1_SUPPORT);
2109                 radeon_add_legacy_connector(dev, 1,
2110                                             ATOM_DEVICE_DFP1_SUPPORT |
2111                                             ATOM_DEVICE_CRT1_SUPPORT,
2112                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2113                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2114                                             &hpd);
2115                 /* TV - TV DAC */
2116                 ddc_i2c.valid = false;
2117                 hpd.hpd = RADEON_HPD_NONE;
2118                 radeon_add_legacy_encoder(dev,
2119                                           radeon_get_encoder_enum(dev,
2120                                                                 ATOM_DEVICE_TV1_SUPPORT,
2121                                                                 2),
2122                                           ATOM_DEVICE_TV1_SUPPORT);
2123                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2124                                             DRM_MODE_CONNECTOR_SVIDEO,
2125                                             &ddc_i2c,
2126                                             CONNECTOR_OBJECT_ID_SVIDEO,
2127                                             &hpd);
2128                 break;
2129         default:
2130                 DRM_INFO("Connector table: %d (invalid)\n",
2131                          rdev->mode_info.connector_table);
2132                 return false;
2133         }
2134
2135         radeon_link_encoder_connector(dev);
2136
2137         return true;
2138 }
2139
2140 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2141                                        int bios_index,
2142                                        enum radeon_combios_connector
2143                                        *legacy_connector,
2144                                        struct radeon_i2c_bus_rec *ddc_i2c,
2145                                        struct radeon_hpd *hpd)
2146 {
2147
2148         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2149            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2150         if (dev->pdev->device == 0x515e &&
2151             dev->pdev->subsystem_vendor == 0x1014) {
2152                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2153                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2154                         return false;
2155         }
2156
2157         /* X300 card with extra non-existent DVI port */
2158         if (dev->pdev->device == 0x5B60 &&
2159             dev->pdev->subsystem_vendor == 0x17af &&
2160             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2161                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2162                         return false;
2163         }
2164
2165         return true;
2166 }
2167
2168 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2169 {
2170         /* Acer 5102 has non-existent TV port */
2171         if (dev->pdev->device == 0x5975 &&
2172             dev->pdev->subsystem_vendor == 0x1025 &&
2173             dev->pdev->subsystem_device == 0x009f)
2174                 return false;
2175
2176         /* HP dc5750 has non-existent TV port */
2177         if (dev->pdev->device == 0x5974 &&
2178             dev->pdev->subsystem_vendor == 0x103c &&
2179             dev->pdev->subsystem_device == 0x280a)
2180                 return false;
2181
2182         /* MSI S270 has non-existent TV port */
2183         if (dev->pdev->device == 0x5955 &&
2184             dev->pdev->subsystem_vendor == 0x1462 &&
2185             dev->pdev->subsystem_device == 0x0131)
2186                 return false;
2187
2188         return true;
2189 }
2190
2191 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2192 {
2193         struct radeon_device *rdev = dev->dev_private;
2194         uint32_t ext_tmds_info;
2195
2196         if (rdev->flags & RADEON_IS_IGP) {
2197                 if (is_dvi_d)
2198                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2199                 else
2200                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2201         }
2202         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2203         if (ext_tmds_info) {
2204                 uint8_t rev = RBIOS8(ext_tmds_info);
2205                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2206                 if (rev >= 3) {
2207                         if (is_dvi_d)
2208                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2209                         else
2210                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2211                 } else {
2212                         if (flags & 1) {
2213                                 if (is_dvi_d)
2214                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2215                                 else
2216                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2217                         }
2218                 }
2219         }
2220         if (is_dvi_d)
2221                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2222         else
2223                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2224 }
2225
2226 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2227 {
2228         struct radeon_device *rdev = dev->dev_private;
2229         uint32_t conn_info, entry, devices;
2230         uint16_t tmp, connector_object_id;
2231         enum radeon_combios_ddc ddc_type;
2232         enum radeon_combios_connector connector;
2233         int i = 0;
2234         struct radeon_i2c_bus_rec ddc_i2c;
2235         struct radeon_hpd hpd;
2236
2237         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2238         if (conn_info) {
2239                 for (i = 0; i < 4; i++) {
2240                         entry = conn_info + 2 + i * 2;
2241
2242                         if (!RBIOS16(entry))
2243                                 break;
2244
2245                         tmp = RBIOS16(entry);
2246
2247                         connector = (tmp >> 12) & 0xf;
2248
2249                         ddc_type = (tmp >> 8) & 0xf;
2250                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2251
2252                         switch (connector) {
2253                         case CONNECTOR_PROPRIETARY_LEGACY:
2254                         case CONNECTOR_DVI_I_LEGACY:
2255                         case CONNECTOR_DVI_D_LEGACY:
2256                                 if ((tmp >> 4) & 0x1)
2257                                         hpd.hpd = RADEON_HPD_2;
2258                                 else
2259                                         hpd.hpd = RADEON_HPD_1;
2260                                 break;
2261                         default:
2262                                 hpd.hpd = RADEON_HPD_NONE;
2263                                 break;
2264                         }
2265
2266                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2267                                                         &ddc_i2c, &hpd))
2268                                 continue;
2269
2270                         switch (connector) {
2271                         case CONNECTOR_PROPRIETARY_LEGACY:
2272                                 if ((tmp >> 4) & 0x1)
2273                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2274                                 else
2275                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2276                                 radeon_add_legacy_encoder(dev,
2277                                                           radeon_get_encoder_enum
2278                                                           (dev, devices, 0),
2279                                                           devices);
2280                                 radeon_add_legacy_connector(dev, i, devices,
2281                                                             legacy_connector_convert
2282                                                             [connector],
2283                                                             &ddc_i2c,
2284                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2285                                                             &hpd);
2286                                 break;
2287                         case CONNECTOR_CRT_LEGACY:
2288                                 if (tmp & 0x1) {
2289                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2290                                         radeon_add_legacy_encoder(dev,
2291                                                                   radeon_get_encoder_enum
2292                                                                   (dev,
2293                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2294                                                                    2),
2295                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2296                                 } else {
2297                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2298                                         radeon_add_legacy_encoder(dev,
2299                                                                   radeon_get_encoder_enum
2300                                                                   (dev,
2301                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2302                                                                    1),
2303                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2304                                 }
2305                                 radeon_add_legacy_connector(dev,
2306                                                             i,
2307                                                             devices,
2308                                                             legacy_connector_convert
2309                                                             [connector],
2310                                                             &ddc_i2c,
2311                                                             CONNECTOR_OBJECT_ID_VGA,
2312                                                             &hpd);
2313                                 break;
2314                         case CONNECTOR_DVI_I_LEGACY:
2315                                 devices = 0;
2316                                 if (tmp & 0x1) {
2317                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2318                                         radeon_add_legacy_encoder(dev,
2319                                                                   radeon_get_encoder_enum
2320                                                                   (dev,
2321                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2322                                                                    2),
2323                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2324                                 } else {
2325                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2326                                         radeon_add_legacy_encoder(dev,
2327                                                                   radeon_get_encoder_enum
2328                                                                   (dev,
2329                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2330                                                                    1),
2331                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2332                                 }
2333                                 if ((tmp >> 4) & 0x1) {
2334                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2335                                         radeon_add_legacy_encoder(dev,
2336                                                                   radeon_get_encoder_enum
2337                                                                   (dev,
2338                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2339                                                                    0),
2340                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2341                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2342                                 } else {
2343                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2344                                         radeon_add_legacy_encoder(dev,
2345                                                                   radeon_get_encoder_enum
2346                                                                   (dev,
2347                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2348                                                                    0),
2349                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2350                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2351                                 }
2352                                 radeon_add_legacy_connector(dev,
2353                                                             i,
2354                                                             devices,
2355                                                             legacy_connector_convert
2356                                                             [connector],
2357                                                             &ddc_i2c,
2358                                                             connector_object_id,
2359                                                             &hpd);
2360                                 break;
2361                         case CONNECTOR_DVI_D_LEGACY:
2362                                 if ((tmp >> 4) & 0x1) {
2363                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2364                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2365                                 } else {
2366                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2367                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2368                                 }
2369                                 radeon_add_legacy_encoder(dev,
2370                                                           radeon_get_encoder_enum
2371                                                           (dev, devices, 0),
2372                                                           devices);
2373                                 radeon_add_legacy_connector(dev, i, devices,
2374                                                             legacy_connector_convert
2375                                                             [connector],
2376                                                             &ddc_i2c,
2377                                                             connector_object_id,
2378                                                             &hpd);
2379                                 break;
2380                         case CONNECTOR_CTV_LEGACY:
2381                         case CONNECTOR_STV_LEGACY:
2382                                 radeon_add_legacy_encoder(dev,
2383                                                           radeon_get_encoder_enum
2384                                                           (dev,
2385                                                            ATOM_DEVICE_TV1_SUPPORT,
2386                                                            2),
2387                                                           ATOM_DEVICE_TV1_SUPPORT);
2388                                 radeon_add_legacy_connector(dev, i,
2389                                                             ATOM_DEVICE_TV1_SUPPORT,
2390                                                             legacy_connector_convert
2391                                                             [connector],
2392                                                             &ddc_i2c,
2393                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2394                                                             &hpd);
2395                                 break;
2396                         default:
2397                                 DRM_ERROR("Unknown connector type: %d\n",
2398                                           connector);
2399                                 continue;
2400                         }
2401
2402                 }
2403         } else {
2404                 uint16_t tmds_info =
2405                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2406                 if (tmds_info) {
2407                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2408
2409                         radeon_add_legacy_encoder(dev,
2410                                                   radeon_get_encoder_enum(dev,
2411                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2412                                                                         1),
2413                                                   ATOM_DEVICE_CRT1_SUPPORT);
2414                         radeon_add_legacy_encoder(dev,
2415                                                   radeon_get_encoder_enum(dev,
2416                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2417                                                                         0),
2418                                                   ATOM_DEVICE_DFP1_SUPPORT);
2419
2420                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2421                         hpd.hpd = RADEON_HPD_1;
2422                         radeon_add_legacy_connector(dev,
2423                                                     0,
2424                                                     ATOM_DEVICE_CRT1_SUPPORT |
2425                                                     ATOM_DEVICE_DFP1_SUPPORT,
2426                                                     DRM_MODE_CONNECTOR_DVII,
2427                                                     &ddc_i2c,
2428                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2429                                                     &hpd);
2430                 } else {
2431                         uint16_t crt_info =
2432                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2433                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2434                         if (crt_info) {
2435                                 radeon_add_legacy_encoder(dev,
2436                                                           radeon_get_encoder_enum(dev,
2437                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2438                                                                                 1),
2439                                                           ATOM_DEVICE_CRT1_SUPPORT);
2440                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2441                                 hpd.hpd = RADEON_HPD_NONE;
2442                                 radeon_add_legacy_connector(dev,
2443                                                             0,
2444                                                             ATOM_DEVICE_CRT1_SUPPORT,
2445                                                             DRM_MODE_CONNECTOR_VGA,
2446                                                             &ddc_i2c,
2447                                                             CONNECTOR_OBJECT_ID_VGA,
2448                                                             &hpd);
2449                         } else {
2450                                 DRM_DEBUG_KMS("No connector info found\n");
2451                                 return false;
2452                         }
2453                 }
2454         }
2455
2456         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2457                 uint16_t lcd_info =
2458                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2459                 if (lcd_info) {
2460                         uint16_t lcd_ddc_info =
2461                             combios_get_table_offset(dev,
2462                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2463
2464                         radeon_add_legacy_encoder(dev,
2465                                                   radeon_get_encoder_enum(dev,
2466                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2467                                                                         0),
2468                                                   ATOM_DEVICE_LCD1_SUPPORT);
2469
2470                         if (lcd_ddc_info) {
2471                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2472                                 switch (ddc_type) {
2473                                 case DDC_LCD:
2474                                         ddc_i2c =
2475                                                 combios_setup_i2c_bus(rdev,
2476                                                                       DDC_LCD,
2477                                                                       RBIOS32(lcd_ddc_info + 3),
2478                                                                       RBIOS32(lcd_ddc_info + 7));
2479                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2480                                         break;
2481                                 case DDC_GPIO:
2482                                         ddc_i2c =
2483                                                 combios_setup_i2c_bus(rdev,
2484                                                                       DDC_GPIO,
2485                                                                       RBIOS32(lcd_ddc_info + 3),
2486                                                                       RBIOS32(lcd_ddc_info + 7));
2487                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2488                                         break;
2489                                 default:
2490                                         ddc_i2c =
2491                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2492                                         break;
2493                                 }
2494                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2495                         } else
2496                                 ddc_i2c.valid = false;
2497
2498                         hpd.hpd = RADEON_HPD_NONE;
2499                         radeon_add_legacy_connector(dev,
2500                                                     5,
2501                                                     ATOM_DEVICE_LCD1_SUPPORT,
2502                                                     DRM_MODE_CONNECTOR_LVDS,
2503                                                     &ddc_i2c,
2504                                                     CONNECTOR_OBJECT_ID_LVDS,
2505                                                     &hpd);
2506                 }
2507         }
2508
2509         /* check TV table */
2510         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2511                 uint32_t tv_info =
2512                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2513                 if (tv_info) {
2514                         if (RBIOS8(tv_info + 6) == 'T') {
2515                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2516                                         hpd.hpd = RADEON_HPD_NONE;
2517                                         ddc_i2c.valid = false;
2518                                         radeon_add_legacy_encoder(dev,
2519                                                                   radeon_get_encoder_enum
2520                                                                   (dev,
2521                                                                    ATOM_DEVICE_TV1_SUPPORT,
2522                                                                    2),
2523                                                                   ATOM_DEVICE_TV1_SUPPORT);
2524                                         radeon_add_legacy_connector(dev, 6,
2525                                                                     ATOM_DEVICE_TV1_SUPPORT,
2526                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2527                                                                     &ddc_i2c,
2528                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2529                                                                     &hpd);
2530                                 }
2531                         }
2532                 }
2533         }
2534
2535         radeon_link_encoder_connector(dev);
2536
2537         return true;
2538 }
2539
2540 static const char *thermal_controller_names[] = {
2541         "NONE",
2542         "lm63",
2543         "adm1032",
2544 };
2545
2546 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2547 {
2548         struct drm_device *dev = rdev->ddev;
2549         u16 offset, misc, misc2 = 0;
2550         u8 rev, blocks, tmp;
2551         int state_index = 0;
2552
2553         rdev->pm.default_power_state_index = -1;
2554
2555         /* allocate 2 power states */
2556         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2557         if (!rdev->pm.power_state) {
2558                 rdev->pm.default_power_state_index = state_index;
2559                 rdev->pm.num_power_states = 0;
2560
2561                 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2562                 rdev->pm.current_clock_mode_index = 0;
2563                 return;
2564         }
2565
2566         /* check for a thermal chip */
2567         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2568         if (offset) {
2569                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2570                 struct radeon_i2c_bus_rec i2c_bus;
2571
2572                 rev = RBIOS8(offset);
2573
2574                 if (rev == 0) {
2575                         thermal_controller = RBIOS8(offset + 3);
2576                         gpio = RBIOS8(offset + 4) & 0x3f;
2577                         i2c_addr = RBIOS8(offset + 5);
2578                 } else if (rev == 1) {
2579                         thermal_controller = RBIOS8(offset + 4);
2580                         gpio = RBIOS8(offset + 5) & 0x3f;
2581                         i2c_addr = RBIOS8(offset + 6);
2582                 } else if (rev == 2) {
2583                         thermal_controller = RBIOS8(offset + 4);
2584                         gpio = RBIOS8(offset + 5) & 0x3f;
2585                         i2c_addr = RBIOS8(offset + 6);
2586                         clk_bit = RBIOS8(offset + 0xa);
2587                         data_bit = RBIOS8(offset + 0xb);
2588                 }
2589                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2590                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2591                                  thermal_controller_names[thermal_controller],
2592                                  i2c_addr >> 1);
2593                         if (gpio == DDC_LCD) {
2594                                 /* MM i2c */
2595                                 i2c_bus.valid = true;
2596                                 i2c_bus.hw_capable = true;
2597                                 i2c_bus.mm_i2c = true;
2598                                 i2c_bus.i2c_id = 0xa0;
2599                         } else if (gpio == DDC_GPIO)
2600                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2601                         else
2602                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2603                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2604                         if (rdev->pm.i2c_bus) {
2605                                 struct i2c_board_info info = { };
2606                                 const char *name = thermal_controller_names[thermal_controller];
2607                                 info.addr = i2c_addr >> 1;
2608                                 strlcpy(info.type, name, sizeof(info.type));
2609                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2610                         }
2611                 }
2612         }
2613
2614         if (rdev->flags & RADEON_IS_MOBILITY) {
2615                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2616                 if (offset) {
2617                         rev = RBIOS8(offset);
2618                         blocks = RBIOS8(offset + 0x2);
2619                         /* power mode 0 tends to be the only valid one */
2620                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2621                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2622                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2623                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2624                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2625                                 goto default_mode;
2626                         rdev->pm.power_state[state_index].type =
2627                                 POWER_STATE_TYPE_BATTERY;
2628                         misc = RBIOS16(offset + 0x5 + 0x0);
2629                         if (rev > 4)
2630                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2631                         rdev->pm.power_state[state_index].misc = misc;
2632                         rdev->pm.power_state[state_index].misc2 = misc2;
2633                         if (misc & 0x4) {
2634                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2635                                 if (misc & 0x8)
2636                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2637                                                 true;
2638                                 else
2639                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2640                                                 false;
2641                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2642                                 if (rev < 6) {
2643                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2644                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2645                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2646                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2647                                 } else {
2648                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2649                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2650                                         if (entries && voltage_table_offset) {
2651                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2652                                                         RBIOS16(voltage_table_offset) * 4;
2653                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2654                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2655                                         } else
2656                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2657                                 }
2658                                 switch ((misc2 & 0x700) >> 8) {
2659                                 case 0:
2660                                 default:
2661                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2662                                         break;
2663                                 case 1:
2664                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2665                                         break;
2666                                 case 2:
2667                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2668                                         break;
2669                                 case 3:
2670                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2671                                         break;
2672                                 case 4:
2673                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2674                                         break;
2675                                 }
2676                         } else
2677                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2678                         if (rev > 6)
2679                                 rdev->pm.power_state[state_index].pcie_lanes =
2680                                         RBIOS8(offset + 0x5 + 0x10);
2681                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2682                         state_index++;
2683                 } else {
2684                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2685                 }
2686         } else {
2687                 /* XXX figure out some good default low power mode for desktop cards */
2688         }
2689
2690 default_mode:
2691         /* add the default mode */
2692         rdev->pm.power_state[state_index].type =
2693                 POWER_STATE_TYPE_DEFAULT;
2694         rdev->pm.power_state[state_index].num_clock_modes = 1;
2695         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2696         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2697         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2698         if ((state_index > 0) &&
2699             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2700                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2701                         rdev->pm.power_state[0].clock_info[0].voltage;
2702         else
2703                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2704         rdev->pm.power_state[state_index].pcie_lanes = 16;
2705         rdev->pm.power_state[state_index].flags = 0;
2706         rdev->pm.default_power_state_index = state_index;
2707         rdev->pm.num_power_states = state_index + 1;
2708
2709         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2710         rdev->pm.current_clock_mode_index = 0;
2711 }
2712
2713 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2714 {
2715         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2716         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2717
2718         if (!tmds)
2719                 return;
2720
2721         switch (tmds->dvo_chip) {
2722         case DVO_SIL164:
2723                 /* sil 164 */
2724                 radeon_i2c_put_byte(tmds->i2c_bus,
2725                                     tmds->slave_addr,
2726                                     0x08, 0x30);
2727                 radeon_i2c_put_byte(tmds->i2c_bus,
2728                                        tmds->slave_addr,
2729                                        0x09, 0x00);
2730                 radeon_i2c_put_byte(tmds->i2c_bus,
2731                                     tmds->slave_addr,
2732                                     0x0a, 0x90);
2733                 radeon_i2c_put_byte(tmds->i2c_bus,
2734                                     tmds->slave_addr,
2735                                     0x0c, 0x89);
2736                 radeon_i2c_put_byte(tmds->i2c_bus,
2737                                        tmds->slave_addr,
2738                                        0x08, 0x3b);
2739                 break;
2740         case DVO_SIL1178:
2741                 /* sil 1178 - untested */
2742                 /*
2743                  * 0x0f, 0x44
2744                  * 0x0f, 0x4c
2745                  * 0x0e, 0x01
2746                  * 0x0a, 0x80
2747                  * 0x09, 0x30
2748                  * 0x0c, 0xc9
2749                  * 0x0d, 0x70
2750                  * 0x08, 0x32
2751                  * 0x08, 0x33
2752                  */
2753                 break;
2754         default:
2755                 break;
2756         }
2757
2758 }
2759
2760 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2761 {
2762         struct drm_device *dev = encoder->dev;
2763         struct radeon_device *rdev = dev->dev_private;
2764         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2765         uint16_t offset;
2766         uint8_t blocks, slave_addr, rev;
2767         uint32_t index, id;
2768         uint32_t reg, val, and_mask, or_mask;
2769         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2770
2771         if (!tmds)
2772                 return false;
2773
2774         if (rdev->flags & RADEON_IS_IGP) {
2775                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2776                 rev = RBIOS8(offset);
2777                 if (offset) {
2778                         rev = RBIOS8(offset);
2779                         if (rev > 1) {
2780                                 blocks = RBIOS8(offset + 3);
2781                                 index = offset + 4;
2782                                 while (blocks > 0) {
2783                                         id = RBIOS16(index);
2784                                         index += 2;
2785                                         switch (id >> 13) {
2786                                         case 0:
2787                                                 reg = (id & 0x1fff) * 4;
2788                                                 val = RBIOS32(index);
2789                                                 index += 4;
2790                                                 WREG32(reg, val);
2791                                                 break;
2792                                         case 2:
2793                                                 reg = (id & 0x1fff) * 4;
2794                                                 and_mask = RBIOS32(index);
2795                                                 index += 4;
2796                                                 or_mask = RBIOS32(index);
2797                                                 index += 4;
2798                                                 val = RREG32(reg);
2799                                                 val = (val & and_mask) | or_mask;
2800                                                 WREG32(reg, val);
2801                                                 break;
2802                                         case 3:
2803                                                 val = RBIOS16(index);
2804                                                 index += 2;
2805                                                 udelay(val);
2806                                                 break;
2807                                         case 4:
2808                                                 val = RBIOS16(index);
2809                                                 index += 2;
2810                                                 udelay(val * 1000);
2811                                                 break;
2812                                         case 6:
2813                                                 slave_addr = id & 0xff;
2814                                                 slave_addr >>= 1; /* 7 bit addressing */
2815                                                 index++;
2816                                                 reg = RBIOS8(index);
2817                                                 index++;
2818                                                 val = RBIOS8(index);
2819                                                 index++;
2820                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2821                                                                     slave_addr,
2822                                                                     reg, val);
2823                                                 break;
2824                                         default:
2825                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2826                                                 break;
2827                                         }
2828                                         blocks--;
2829                                 }
2830                                 return true;
2831                         }
2832                 }
2833         } else {
2834                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2835                 if (offset) {
2836                         index = offset + 10;
2837                         id = RBIOS16(index);
2838                         while (id != 0xffff) {
2839                                 index += 2;
2840                                 switch (id >> 13) {
2841                                 case 0:
2842                                         reg = (id & 0x1fff) * 4;
2843                                         val = RBIOS32(index);
2844                                         WREG32(reg, val);
2845                                         break;
2846                                 case 2:
2847                                         reg = (id & 0x1fff) * 4;
2848                                         and_mask = RBIOS32(index);
2849                                         index += 4;
2850                                         or_mask = RBIOS32(index);
2851                                         index += 4;
2852                                         val = RREG32(reg);
2853                                         val = (val & and_mask) | or_mask;
2854                                         WREG32(reg, val);
2855                                         break;
2856                                 case 4:
2857                                         val = RBIOS16(index);
2858                                         index += 2;
2859                                         udelay(val);
2860                                         break;
2861                                 case 5:
2862                                         reg = id & 0x1fff;
2863                                         and_mask = RBIOS32(index);
2864                                         index += 4;
2865                                         or_mask = RBIOS32(index);
2866                                         index += 4;
2867                                         val = RREG32_PLL(reg);
2868                                         val = (val & and_mask) | or_mask;
2869                                         WREG32_PLL(reg, val);
2870                                         break;
2871                                 case 6:
2872                                         reg = id & 0x1fff;
2873                                         val = RBIOS8(index);
2874                                         index += 1;
2875                                         radeon_i2c_put_byte(tmds->i2c_bus,
2876                                                             tmds->slave_addr,
2877                                                             reg, val);
2878                                         break;
2879                                 default:
2880                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2881                                         break;
2882                                 }
2883                                 id = RBIOS16(index);
2884                         }
2885                         return true;
2886                 }
2887         }
2888         return false;
2889 }
2890
2891 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2892 {
2893         struct radeon_device *rdev = dev->dev_private;
2894
2895         if (offset) {
2896                 while (RBIOS16(offset)) {
2897                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2898                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2899                         uint32_t val, and_mask, or_mask;
2900                         uint32_t tmp;
2901
2902                         offset += 2;
2903                         switch (cmd) {
2904                         case 0:
2905                                 val = RBIOS32(offset);
2906                                 offset += 4;
2907                                 WREG32(addr, val);
2908                                 break;
2909                         case 1:
2910                                 val = RBIOS32(offset);
2911                                 offset += 4;
2912                                 WREG32(addr, val);
2913                                 break;
2914                         case 2:
2915                                 and_mask = RBIOS32(offset);
2916                                 offset += 4;
2917                                 or_mask = RBIOS32(offset);
2918                                 offset += 4;
2919                                 tmp = RREG32(addr);
2920                                 tmp &= and_mask;
2921                                 tmp |= or_mask;
2922                                 WREG32(addr, tmp);
2923                                 break;
2924                         case 3:
2925                                 and_mask = RBIOS32(offset);
2926                                 offset += 4;
2927                                 or_mask = RBIOS32(offset);
2928                                 offset += 4;
2929                                 tmp = RREG32(addr);
2930                                 tmp &= and_mask;
2931                                 tmp |= or_mask;
2932                                 WREG32(addr, tmp);
2933                                 break;
2934                         case 4:
2935                                 val = RBIOS16(offset);
2936                                 offset += 2;
2937                                 udelay(val);
2938                                 break;
2939                         case 5:
2940                                 val = RBIOS16(offset);
2941                                 offset += 2;
2942                                 switch (addr) {
2943                                 case 8:
2944                                         while (val--) {
2945                                                 if (!
2946                                                     (RREG32_PLL
2947                                                      (RADEON_CLK_PWRMGT_CNTL) &
2948                                                      RADEON_MC_BUSY))
2949                                                         break;
2950                                         }
2951                                         break;
2952                                 case 9:
2953                                         while (val--) {
2954                                                 if ((RREG32(RADEON_MC_STATUS) &
2955                                                      RADEON_MC_IDLE))
2956                                                         break;
2957                                         }
2958                                         break;
2959                                 default:
2960                                         break;
2961                                 }
2962                                 break;
2963                         default:
2964                                 break;
2965                         }
2966                 }
2967         }
2968 }
2969
2970 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2971 {
2972         struct radeon_device *rdev = dev->dev_private;
2973
2974         if (offset) {
2975                 while (RBIOS8(offset)) {
2976                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2977                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2978                         uint32_t val, shift, tmp;
2979                         uint32_t and_mask, or_mask;
2980
2981                         offset++;
2982                         switch (cmd) {
2983                         case 0:
2984                                 val = RBIOS32(offset);
2985                                 offset += 4;
2986                                 WREG32_PLL(addr, val);
2987                                 break;
2988                         case 1:
2989                                 shift = RBIOS8(offset) * 8;
2990                                 offset++;
2991                                 and_mask = RBIOS8(offset) << shift;
2992                                 and_mask |= ~(0xff << shift);
2993                                 offset++;
2994                                 or_mask = RBIOS8(offset) << shift;
2995                                 offset++;
2996                                 tmp = RREG32_PLL(addr);
2997                                 tmp &= and_mask;
2998                                 tmp |= or_mask;
2999                                 WREG32_PLL(addr, tmp);
3000                                 break;
3001                         case 2:
3002                         case 3:
3003                                 tmp = 1000;
3004                                 switch (addr) {
3005                                 case 1:
3006                                         udelay(150);
3007                                         break;
3008                                 case 2:
3009                                         udelay(1000);
3010                                         break;
3011                                 case 3:
3012                                         while (tmp--) {
3013                                                 if (!
3014                                                     (RREG32_PLL
3015                                                      (RADEON_CLK_PWRMGT_CNTL) &
3016                                                      RADEON_MC_BUSY))
3017                                                         break;
3018                                         }
3019                                         break;
3020                                 case 4:
3021                                         while (tmp--) {
3022                                                 if (RREG32_PLL
3023                                                     (RADEON_CLK_PWRMGT_CNTL) &
3024                                                     RADEON_DLL_READY)
3025                                                         break;
3026                                         }
3027                                         break;
3028                                 case 5:
3029                                         tmp =
3030                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3031                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3032 #if 0
3033                                                 uint32_t mclk_cntl =
3034                                                     RREG32_PLL
3035                                                     (RADEON_MCLK_CNTL);
3036                                                 mclk_cntl &= 0xffff0000;
3037                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3038                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3039                                                            mclk_cntl);
3040                                                 udelay(10000);
3041 #endif
3042                                                 WREG32_PLL
3043                                                     (RADEON_CLK_PWRMGT_CNTL,
3044                                                      tmp &
3045                                                      ~RADEON_CG_NO1_DEBUG_0);
3046                                                 udelay(10000);
3047                                         }
3048                                         break;
3049                                 default:
3050                                         break;
3051                                 }
3052                                 break;
3053                         default:
3054                                 break;
3055                         }
3056                 }
3057         }
3058 }
3059
3060 static void combios_parse_ram_reset_table(struct drm_device *dev,
3061                                           uint16_t offset)
3062 {
3063         struct radeon_device *rdev = dev->dev_private;
3064         uint32_t tmp;
3065
3066         if (offset) {
3067                 uint8_t val = RBIOS8(offset);
3068                 while (val != 0xff) {
3069                         offset++;
3070
3071                         if (val == 0x0f) {
3072                                 uint32_t channel_complete_mask;
3073
3074                                 if (ASIC_IS_R300(rdev))
3075                                         channel_complete_mask =
3076                                             R300_MEM_PWRUP_COMPLETE;
3077                                 else
3078                                         channel_complete_mask =
3079                                             RADEON_MEM_PWRUP_COMPLETE;
3080                                 tmp = 20000;
3081                                 while (tmp--) {
3082                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3083                                              channel_complete_mask) ==
3084                                             channel_complete_mask)
3085                                                 break;
3086                                 }
3087                         } else {
3088                                 uint32_t or_mask = RBIOS16(offset);
3089                                 offset += 2;
3090
3091                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3092                                 tmp &= RADEON_SDRAM_MODE_MASK;
3093                                 tmp |= or_mask;
3094                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3095
3096                                 or_mask = val << 24;
3097                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3098                                 tmp &= RADEON_B3MEM_RESET_MASK;
3099                                 tmp |= or_mask;
3100                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3101                         }
3102                         val = RBIOS8(offset);
3103                 }
3104         }
3105 }
3106
3107 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3108                                    int mem_addr_mapping)
3109 {
3110         struct radeon_device *rdev = dev->dev_private;
3111         uint32_t mem_cntl;
3112         uint32_t mem_size;
3113         uint32_t addr = 0;
3114
3115         mem_cntl = RREG32(RADEON_MEM_CNTL);
3116         if (mem_cntl & RV100_HALF_MODE)
3117                 ram /= 2;
3118         mem_size = ram;
3119         mem_cntl &= ~(0xff << 8);
3120         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3121         WREG32(RADEON_MEM_CNTL, mem_cntl);
3122         RREG32(RADEON_MEM_CNTL);
3123
3124         /* sdram reset ? */
3125
3126         /* something like this????  */
3127         while (ram--) {
3128                 addr = ram * 1024 * 1024;
3129                 /* write to each page */
3130                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3131                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3132                 /* read back and verify */
3133                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3134                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3135                         return 0;
3136         }
3137
3138         return mem_size;
3139 }
3140
3141 static void combios_write_ram_size(struct drm_device *dev)
3142 {
3143         struct radeon_device *rdev = dev->dev_private;
3144         uint8_t rev;
3145         uint16_t offset;
3146         uint32_t mem_size = 0;
3147         uint32_t mem_cntl = 0;
3148
3149         /* should do something smarter here I guess... */
3150         if (rdev->flags & RADEON_IS_IGP)
3151                 return;
3152
3153         /* first check detected mem table */
3154         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3155         if (offset) {
3156                 rev = RBIOS8(offset);
3157                 if (rev < 3) {
3158                         mem_cntl = RBIOS32(offset + 1);
3159                         mem_size = RBIOS16(offset + 5);
3160                         if ((rdev->family < CHIP_R200) &&
3161                             !ASIC_IS_RN50(rdev))
3162                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3163                 }
3164         }
3165
3166         if (!mem_size) {
3167                 offset =
3168                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3169                 if (offset) {
3170                         rev = RBIOS8(offset - 1);
3171                         if (rev < 1) {
3172                                 if ((rdev->family < CHIP_R200)
3173                                     && !ASIC_IS_RN50(rdev)) {
3174                                         int ram = 0;
3175                                         int mem_addr_mapping = 0;
3176
3177                                         while (RBIOS8(offset)) {
3178                                                 ram = RBIOS8(offset);
3179                                                 mem_addr_mapping =
3180                                                     RBIOS8(offset + 1);
3181                                                 if (mem_addr_mapping != 0x25)
3182                                                         ram *= 2;
3183                                                 mem_size =
3184                                                     combios_detect_ram(dev, ram,
3185                                                                        mem_addr_mapping);
3186                                                 if (mem_size)
3187                                                         break;
3188                                                 offset += 2;
3189                                         }
3190                                 } else
3191                                         mem_size = RBIOS8(offset);
3192                         } else {
3193                                 mem_size = RBIOS8(offset);
3194                                 mem_size *= 2;  /* convert to MB */
3195                         }
3196                 }
3197         }
3198
3199         mem_size *= (1024 * 1024);      /* convert to bytes */
3200         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3201 }
3202
3203 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3204 {
3205         uint16_t dyn_clk_info =
3206             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3207
3208         if (dyn_clk_info)
3209                 combios_parse_pll_table(dev, dyn_clk_info);
3210 }
3211
3212 void radeon_combios_asic_init(struct drm_device *dev)
3213 {
3214         struct radeon_device *rdev = dev->dev_private;
3215         uint16_t table;
3216
3217         /* port hardcoded mac stuff from radeonfb */
3218         if (rdev->bios == NULL)
3219                 return;
3220
3221         /* ASIC INIT 1 */
3222         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3223         if (table)
3224                 combios_parse_mmio_table(dev, table);
3225
3226         /* PLL INIT */
3227         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3228         if (table)
3229                 combios_parse_pll_table(dev, table);
3230
3231         /* ASIC INIT 2 */
3232         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3233         if (table)
3234                 combios_parse_mmio_table(dev, table);
3235
3236         if (!(rdev->flags & RADEON_IS_IGP)) {
3237                 /* ASIC INIT 4 */
3238                 table =
3239                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3240                 if (table)
3241                         combios_parse_mmio_table(dev, table);
3242
3243                 /* RAM RESET */
3244                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3245                 if (table)
3246                         combios_parse_ram_reset_table(dev, table);
3247
3248                 /* ASIC INIT 3 */
3249                 table =
3250                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3251                 if (table)
3252                         combios_parse_mmio_table(dev, table);
3253
3254                 /* write CONFIG_MEMSIZE */
3255                 combios_write_ram_size(dev);
3256         }
3257
3258         /* quirk for rs4xx HP nx6125 laptop to make it resume
3259          * - it hangs on resume inside the dynclk 1 table.
3260          */
3261         if (rdev->family == CHIP_RS480 &&
3262             rdev->pdev->subsystem_vendor == 0x103c &&
3263             rdev->pdev->subsystem_device == 0x308b)
3264                 return;
3265
3266         /* quirk for rs4xx HP dv5000 laptop to make it resume
3267          * - it hangs on resume inside the dynclk 1 table.
3268          */
3269         if (rdev->family == CHIP_RS480 &&
3270             rdev->pdev->subsystem_vendor == 0x103c &&
3271             rdev->pdev->subsystem_device == 0x30a4)
3272                 return;
3273
3274         /* DYN CLK 1 */
3275         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3276         if (table)
3277                 combios_parse_pll_table(dev, table);
3278
3279 }
3280
3281 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3282 {
3283         struct radeon_device *rdev = dev->dev_private;
3284         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3285
3286         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3287         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3288         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3289
3290         /* let the bios control the backlight */
3291         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3292
3293         /* tell the bios not to handle mode switching */
3294         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3295                            RADEON_ACC_MODE_CHANGE);
3296
3297         /* tell the bios a driver is loaded */
3298         bios_7_scratch |= RADEON_DRV_LOADED;
3299
3300         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3301         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3302         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3303 }
3304
3305 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3306 {
3307         struct drm_device *dev = encoder->dev;
3308         struct radeon_device *rdev = dev->dev_private;
3309         uint32_t bios_6_scratch;
3310
3311         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3312
3313         if (lock)
3314                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3315         else
3316                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3317
3318         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3319 }
3320
3321 void
3322 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3323                                       struct drm_encoder *encoder,
3324                                       bool connected)
3325 {
3326         struct drm_device *dev = connector->dev;
3327         struct radeon_device *rdev = dev->dev_private;
3328         struct radeon_connector *radeon_connector =
3329             to_radeon_connector(connector);
3330         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3331         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3332         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3333
3334         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3335             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3336                 if (connected) {
3337                         DRM_DEBUG_KMS("TV1 connected\n");
3338                         /* fix me */
3339                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3340                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3341                         bios_5_scratch |= RADEON_TV1_ON;
3342                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3343                 } else {
3344                         DRM_DEBUG_KMS("TV1 disconnected\n");
3345                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3346                         bios_5_scratch &= ~RADEON_TV1_ON;
3347                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3348                 }
3349         }
3350         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3351             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3352                 if (connected) {
3353                         DRM_DEBUG_KMS("LCD1 connected\n");
3354                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3355                         bios_5_scratch |= RADEON_LCD1_ON;
3356                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3357                 } else {
3358                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3359                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3360                         bios_5_scratch &= ~RADEON_LCD1_ON;
3361                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3362                 }
3363         }
3364         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3365             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3366                 if (connected) {
3367                         DRM_DEBUG_KMS("CRT1 connected\n");
3368                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3369                         bios_5_scratch |= RADEON_CRT1_ON;
3370                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3371                 } else {
3372                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3373                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3374                         bios_5_scratch &= ~RADEON_CRT1_ON;
3375                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3376                 }
3377         }
3378         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3379             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3380                 if (connected) {
3381                         DRM_DEBUG_KMS("CRT2 connected\n");
3382                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3383                         bios_5_scratch |= RADEON_CRT2_ON;
3384                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3385                 } else {
3386                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3387                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3388                         bios_5_scratch &= ~RADEON_CRT2_ON;
3389                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3390                 }
3391         }
3392         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3393             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3394                 if (connected) {
3395                         DRM_DEBUG_KMS("DFP1 connected\n");
3396                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3397                         bios_5_scratch |= RADEON_DFP1_ON;
3398                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3399                 } else {
3400                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3401                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3402                         bios_5_scratch &= ~RADEON_DFP1_ON;
3403                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3404                 }
3405         }
3406         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3407             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3408                 if (connected) {
3409                         DRM_DEBUG_KMS("DFP2 connected\n");
3410                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3411                         bios_5_scratch |= RADEON_DFP2_ON;
3412                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3413                 } else {
3414                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3415                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3416                         bios_5_scratch &= ~RADEON_DFP2_ON;
3417                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3418                 }
3419         }
3420         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3421         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3422 }
3423
3424 void
3425 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3426 {
3427         struct drm_device *dev = encoder->dev;
3428         struct radeon_device *rdev = dev->dev_private;
3429         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3430         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3431
3432         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3433                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3434                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3435         }
3436         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3437                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3438                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3439         }
3440         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3441                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3442                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3443         }
3444         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3445                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3446                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3447         }
3448         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3449                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3450                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3451         }
3452         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3453                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3454                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3455         }
3456         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3457 }
3458
3459 void
3460 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3461 {
3462         struct drm_device *dev = encoder->dev;
3463         struct radeon_device *rdev = dev->dev_private;
3464         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3465         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3466
3467         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3468                 if (on)
3469                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3470                 else
3471                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3472         }
3473         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3474                 if (on)
3475                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3476                 else
3477                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3478         }
3479         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3480                 if (on)
3481                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3482                 else
3483                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3484         }
3485         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3486                 if (on)
3487                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3488                 else
3489                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3490         }
3491         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3492 }