drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  89                         if ((rdev->family == CHIP_R420) ||
  90                             (rdev->family == CHIP_R423) ||
  91                             (rdev->family == CHIP_RV410)) {
  92                                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  93                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  94                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  95                                         gpio->ucClkMaskShift = 0x19;
  96                                         gpio->ucDataMaskShift = 0x18;
  97                                 }
  98                         }
  99
 100                         /* some evergreen boards have bad data for this entry */
 101                         if (ASIC_IS_DCE4(rdev)) {
 102                                 if ((i == 7) &&
 103                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
 104                                     (gpio->sucI2cId.ucAccess == 0)) {
 105                                         gpio->sucI2cId.ucAccess = 0x97;
 106                                         gpio->ucDataMaskShift = 8;
 107                                         gpio->ucDataEnShift = 8;
 108                                         gpio->ucDataY_Shift = 8;
 109                                         gpio->ucDataA_Shift = 8;
 110                                 }
 111                         }
 112
 113                         /* some DCE3 boards have bad data for this entry */
 114                         if (ASIC_IS_DCE3(rdev)) {
 115                                 if ((i == 4) &&
 116                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 117                                     (gpio->sucI2cId.ucAccess == 0x94))
 118                                         gpio->sucI2cId.ucAccess = 0x14;
 119                         }
 120
 121                         if (gpio->sucI2cId.ucAccess == id) {
 122                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 123                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 124                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 125                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 126                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 127                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 128                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 129                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 130                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 131                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 132                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 133                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 134                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 135                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 136                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 137                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 138
 139                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 140                                         i2c.hw_capable = true;
 141                                 else
 142                                         i2c.hw_capable = false;
 143
 144                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 145                                         i2c.mm_i2c = true;
 146                                 else
 147                                         i2c.mm_i2c = false;
 148
 149                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 150
 151                                 if (i2c.mask_clk_reg)
 152                                         i2c.valid = true;
 153                                 break;
 154                         }
 155                 }
 156         }
 157
 158         return i2c;
 159 }
 160
 161 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 162 {
 163         struct atom_context *ctx = rdev->mode_info.atom_context;
 164         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 165         struct radeon_i2c_bus_rec i2c;
 166         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 167         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 168         uint16_t data_offset, size;
 169         int i, num_indices;
 170         char stmp[32];
 171
 172         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 173
 174         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 175                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 176
 177                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 178                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 179
 180                 for (i = 0; i < num_indices; i++) {
 181                         gpio = &i2c_info->asGPIO_Info[i];
 182                         i2c.valid = false;
 183
 184                         /* some evergreen boards have bad data for this entry */
 185                         if (ASIC_IS_DCE4(rdev)) {
 186                                 if ((i == 7) &&
 187                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
 188                                     (gpio->sucI2cId.ucAccess == 0)) {
 189                                         gpio->sucI2cId.ucAccess = 0x97;
 190                                         gpio->ucDataMaskShift = 8;
 191                                         gpio->ucDataEnShift = 8;
 192                                         gpio->ucDataY_Shift = 8;
 193                                         gpio->ucDataA_Shift = 8;
 194                                 }
 195                         }
 196
 197                         /* some DCE3 boards have bad data for this entry */
 198                         if (ASIC_IS_DCE3(rdev)) {
 199                                 if ((i == 4) &&
 200                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 201                                     (gpio->sucI2cId.ucAccess == 0x94))
 202                                         gpio->sucI2cId.ucAccess = 0x14;
 203                         }
 204
 205                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 206                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 207                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 208                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 209                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 210                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 211                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 212                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 213                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 214                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 215                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 216                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 217                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 218                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 219                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 220                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 221
 222                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 223                                 i2c.hw_capable = true;
 224                         else
 225                                 i2c.hw_capable = false;
 226
 227                         if (gpio->sucI2cId.ucAccess == 0xa0)
 228                                 i2c.mm_i2c = true;
 229                         else
 230                                 i2c.mm_i2c = false;
 231
 232                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 233
 234                         if (i2c.mask_clk_reg) {
 235                                 i2c.valid = true;
 236                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 237                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 238                         }
 239                 }
 240         }
 241 }
 242
 243 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 244                                                         u8 id)
 245 {
 246         struct atom_context *ctx = rdev->mode_info.atom_context;
 247         struct radeon_gpio_rec gpio;
 248         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 249         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 250         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 251         u16 data_offset, size;
 252         int i, num_indices;
 253
 254         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 255         gpio.valid = false;
 256
 257         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 258                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 259
 260                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 261                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 262
 263                 for (i = 0; i < num_indices; i++) {
 264                         pin = &gpio_info->asGPIO_Pin[i];
 265                         if (id == pin->ucGPIO_ID) {
 266                                 gpio.id = pin->ucGPIO_ID;
 267                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 268                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 269                                 gpio.valid = true;
 270                                 break;
 271                         }
 272                 }
 273         }
 274
 275         return gpio;
 276 }
 277
 278 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 279                                                             struct radeon_gpio_rec *gpio)
 280 {
 281         struct radeon_hpd hpd;
 282         u32 reg;
 283
 284         memset(&hpd, 0, sizeof(struct radeon_hpd));
 285
 286         if (ASIC_IS_DCE4(rdev))
 287                 reg = EVERGREEN_DC_GPIO_HPD_A;
 288         else
 289                 reg = AVIVO_DC_GPIO_HPD_A;
 290
 291         hpd.gpio = *gpio;
 292         if (gpio->reg == reg) {
 293                 switch(gpio->mask) {
 294                 case (1 << 0):
 295                         hpd.hpd = RADEON_HPD_1;
 296                         break;
 297                 case (1 << 8):
 298                         hpd.hpd = RADEON_HPD_2;
 299                         break;
 300                 case (1 << 16):
 301                         hpd.hpd = RADEON_HPD_3;
 302                         break;
 303                 case (1 << 24):
 304                         hpd.hpd = RADEON_HPD_4;
 305                         break;
 306                 case (1 << 26):
 307                         hpd.hpd = RADEON_HPD_5;
 308                         break;
 309                 case (1 << 28):
 310                         hpd.hpd = RADEON_HPD_6;
 311                         break;
 312                 default:
 313                         hpd.hpd = RADEON_HPD_NONE;
 314                         break;
 315                 }
 316         } else
 317                 hpd.hpd = RADEON_HPD_NONE;
 318         return hpd;
 319 }
 320
 321 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 322                                      uint32_t supported_device,
 323                                      int *connector_type,
 324                                      struct radeon_i2c_bus_rec *i2c_bus,
 325                                      uint16_t *line_mux,
 326                                      struct radeon_hpd *hpd)
 327 {
 328
 329         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 330         if ((dev->pdev->device == 0x791e) &&
 331             (dev->pdev->subsystem_vendor == 0x1043) &&
 332             (dev->pdev->subsystem_device == 0x826d)) {
 333                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 334                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 335                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 336         }
 337
 338         /* Asrock RS600 board lists the DVI port as HDMI */
 339         if ((dev->pdev->device == 0x7941) &&
 340             (dev->pdev->subsystem_vendor == 0x1849) &&
 341             (dev->pdev->subsystem_device == 0x7941)) {
 342                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 343                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 344                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 345         }
 346
 347         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 348         if ((dev->pdev->device == 0x796e) &&
 349             (dev->pdev->subsystem_vendor == 0x1462) &&
 350             (dev->pdev->subsystem_device == 0x7302)) {
 351                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 352                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 353                         return false;
 354         }
 355
 356         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 357         if ((dev->pdev->device == 0x7941) &&
 358             (dev->pdev->subsystem_vendor == 0x147b) &&
 359             (dev->pdev->subsystem_device == 0x2412)) {
 360                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 361                         return false;
 362         }
 363
 364         /* Falcon NW laptop lists vga ddc line for LVDS */
 365         if ((dev->pdev->device == 0x5653) &&
 366             (dev->pdev->subsystem_vendor == 0x1462) &&
 367             (dev->pdev->subsystem_device == 0x0291)) {
 368                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 369                         i2c_bus->valid = false;
 370                         *line_mux = 53;
 371                 }
 372         }
 373
 374         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 375         if ((dev->pdev->device == 0x7146) &&
 376             (dev->pdev->subsystem_vendor == 0x17af) &&
 377             (dev->pdev->subsystem_device == 0x2058)) {
 378                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 379                         return false;
 380         }
 381
 382         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 383         if ((dev->pdev->device == 0x7142) &&
 384             (dev->pdev->subsystem_vendor == 0x1458) &&
 385             (dev->pdev->subsystem_device == 0x2134)) {
 386                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 387                         return false;
 388         }
 389
 390
 391         /* Funky macbooks */
 392         if ((dev->pdev->device == 0x71C5) &&
 393             (dev->pdev->subsystem_vendor == 0x106b) &&
 394             (dev->pdev->subsystem_device == 0x0080)) {
 395                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 396                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 397                         return false;
 398                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 399                         *line_mux = 0x90;
 400         }
 401
 402         /* mac rv630, rv730, others */
 403         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 404             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 405                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 406                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 407         }
 408
 409         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 410         if ((dev->pdev->device == 0x9598) &&
 411             (dev->pdev->subsystem_vendor == 0x1043) &&
 412             (dev->pdev->subsystem_device == 0x01da)) {
 413                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 414                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 415                 }
 416         }
 417
 418         /* ASUS HD 3600 board lists the DVI port as HDMI */
 419         if ((dev->pdev->device == 0x9598) &&
 420             (dev->pdev->subsystem_vendor == 0x1043) &&
 421             (dev->pdev->subsystem_device == 0x01e4)) {
 422                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 423                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 424                 }
 425         }
 426
 427         /* ASUS HD 3450 board lists the DVI port as HDMI */
 428         if ((dev->pdev->device == 0x95C5) &&
 429             (dev->pdev->subsystem_vendor == 0x1043) &&
 430             (dev->pdev->subsystem_device == 0x01e2)) {
 431                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 432                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 433                 }
 434         }
 435
 436         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 437          * HDMI + VGA reporting as HDMI
 438          */
 439         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 440                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 441                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 442                         *line_mux = 0;
 443                 }
 444         }
 445
 446         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 447          * on the laptop and a DVI port on the docking station and
 448          * both share the same encoder, hpd pin, and ddc line.
 449          * So while the bios table is technically correct,
 450          * we drop the DVI port here since xrandr has no concept of
 451          * encoders and will try and drive both connectors
 452          * with different crtcs which isn't possible on the hardware
 453          * side and leaves no crtcs for LVDS or VGA.
 454          */
 455         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 456             (dev->pdev->subsystem_vendor == 0x1025) &&
 457             (dev->pdev->subsystem_device == 0x013c)) {
 458                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 459                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 460                         /* actually it's a DVI-D port not DVI-I */
 461                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 462                         return false;
 463                 }
 464         }
 465
 466         /* XFX Pine Group device rv730 reports no VGA DDC lines
 467          * even though they are wired up to record 0x93
 468          */
 469         if ((dev->pdev->device == 0x9498) &&
 470             (dev->pdev->subsystem_vendor == 0x1682) &&
 471             (dev->pdev->subsystem_device == 0x2452)) {
 472                 struct radeon_device *rdev = dev->dev_private;
 473                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 474         }
 475         return true;
 476 }
 477
 478 const int supported_devices_connector_convert[] = {
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_VGA,
 481         DRM_MODE_CONNECTOR_DVII,
 482         DRM_MODE_CONNECTOR_DVID,
 483         DRM_MODE_CONNECTOR_DVIA,
 484         DRM_MODE_CONNECTOR_SVIDEO,
 485         DRM_MODE_CONNECTOR_Composite,
 486         DRM_MODE_CONNECTOR_LVDS,
 487         DRM_MODE_CONNECTOR_Unknown,
 488         DRM_MODE_CONNECTOR_Unknown,
 489         DRM_MODE_CONNECTOR_HDMIA,
 490         DRM_MODE_CONNECTOR_HDMIB,
 491         DRM_MODE_CONNECTOR_Unknown,
 492         DRM_MODE_CONNECTOR_Unknown,
 493         DRM_MODE_CONNECTOR_9PinDIN,
 494         DRM_MODE_CONNECTOR_DisplayPort
 495 };
 496
 497 const uint16_t supported_devices_connector_object_id_convert[] = {
 498         CONNECTOR_OBJECT_ID_NONE,
 499         CONNECTOR_OBJECT_ID_VGA,
 500         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 501         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 502         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 503         CONNECTOR_OBJECT_ID_COMPOSITE,
 504         CONNECTOR_OBJECT_ID_SVIDEO,
 505         CONNECTOR_OBJECT_ID_LVDS,
 506         CONNECTOR_OBJECT_ID_9PIN_DIN,
 507         CONNECTOR_OBJECT_ID_9PIN_DIN,
 508         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 509         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 510         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 511         CONNECTOR_OBJECT_ID_SVIDEO
 512 };
 513
 514 const int object_connector_convert[] = {
 515         DRM_MODE_CONNECTOR_Unknown,
 516         DRM_MODE_CONNECTOR_DVII,
 517         DRM_MODE_CONNECTOR_DVII,
 518         DRM_MODE_CONNECTOR_DVID,
 519         DRM_MODE_CONNECTOR_DVID,
 520         DRM_MODE_CONNECTOR_VGA,
 521         DRM_MODE_CONNECTOR_Composite,
 522         DRM_MODE_CONNECTOR_SVIDEO,
 523         DRM_MODE_CONNECTOR_Unknown,
 524         DRM_MODE_CONNECTOR_Unknown,
 525         DRM_MODE_CONNECTOR_9PinDIN,
 526         DRM_MODE_CONNECTOR_Unknown,
 527         DRM_MODE_CONNECTOR_HDMIA,
 528         DRM_MODE_CONNECTOR_HDMIB,
 529         DRM_MODE_CONNECTOR_LVDS,
 530         DRM_MODE_CONNECTOR_9PinDIN,
 531         DRM_MODE_CONNECTOR_Unknown,
 532         DRM_MODE_CONNECTOR_Unknown,
 533         DRM_MODE_CONNECTOR_Unknown,
 534         DRM_MODE_CONNECTOR_DisplayPort,
 535         DRM_MODE_CONNECTOR_eDP,
 536         DRM_MODE_CONNECTOR_Unknown
 537 };
 538
 539 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 540 {
 541         struct radeon_device *rdev = dev->dev_private;
 542         struct radeon_mode_info *mode_info = &rdev->mode_info;
 543         struct atom_context *ctx = mode_info->atom_context;
 544         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 545         u16 size, data_offset;
 546         u8 frev, crev;
 547         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 548         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 549         ATOM_OBJECT_TABLE *router_obj;
 550         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 551         ATOM_OBJECT_HEADER *obj_header;
 552         int i, j, k, path_size, device_support;
 553         int connector_type;
 554         u16 igp_lane_info, conn_id, connector_object_id;
 555         struct radeon_i2c_bus_rec ddc_bus;
 556         struct radeon_router router;
 557         struct radeon_gpio_rec gpio;
 558         struct radeon_hpd hpd;
 559
 560         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 561                 return false;
 562
 563         if (crev < 2)
 564                 return false;
 565
 566         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 567         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 568             (ctx->bios + data_offset +
 569              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 570         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 571             (ctx->bios + data_offset +
 572              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 573         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 574             (ctx->bios + data_offset +
 575              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 576         router_obj = (ATOM_OBJECT_TABLE *)
 577                 (ctx->bios + data_offset +
 578                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 579         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 580
 581         path_size = 0;
 582         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 583                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 584                 ATOM_DISPLAY_OBJECT_PATH *path;
 585                 addr += path_size;
 586                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 587                 path_size += le16_to_cpu(path->usSize);
 588
 589                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 590                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 591
 592                         con_obj_id =
 593                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 594                             >> OBJECT_ID_SHIFT;
 595                         con_obj_num =
 596                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 597                             >> ENUM_ID_SHIFT;
 598                         con_obj_type =
 599                             (le16_to_cpu(path->usConnObjectId) &
 600                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 601
 602                         /* TODO CV support */
 603                         if (le16_to_cpu(path->usDeviceTag) ==
 604                                 ATOM_DEVICE_CV_SUPPORT)
 605                                 continue;
 606
 607                         /* IGP chips */
 608                         if ((rdev->flags & RADEON_IS_IGP) &&
 609                             (con_obj_id ==
 610                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 611                                 uint16_t igp_offset = 0;
 612                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 613
 614                                 index =
 615                                     GetIndexIntoMasterTable(DATA,
 616                                                             IntegratedSystemInfo);
 617
 618                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 619                                                            &crev, &igp_offset)) {
 620
 621                                         if (crev >= 2) {
 622                                                 igp_obj =
 623                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 624                                                          *) (ctx->bios + igp_offset);
 625
 626                                                 if (igp_obj) {
 627                                                         uint32_t slot_config, ct;
 628
 629                                                         if (con_obj_num == 1)
 630                                                                 slot_config =
 631                                                                         igp_obj->
 632                                                                         ulDDISlot1Config;
 633                                                         else
 634                                                                 slot_config =
 635                                                                         igp_obj->
 636                                                                         ulDDISlot2Config;
 637
 638                                                         ct = (slot_config >> 16) & 0xff;
 639                                                         connector_type =
 640                                                                 object_connector_convert
 641                                                                 [ct];
 642                                                         connector_object_id = ct;
 643                                                         igp_lane_info =
 644                                                                 slot_config & 0xffff;
 645                                                 } else
 646                                                         continue;
 647                                         } else
 648                                                 continue;
 649                                 } else {
 650                                         igp_lane_info = 0;
 651                                         connector_type =
 652                                                 object_connector_convert[con_obj_id];
 653                                         connector_object_id = con_obj_id;
 654                                 }
 655                         } else {
 656                                 igp_lane_info = 0;
 657                                 connector_type =
 658                                     object_connector_convert[con_obj_id];
 659                                 connector_object_id = con_obj_id;
 660                         }
 661
 662                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 663                                 continue;
 664
 665                         router.ddc_valid = false;
 666                         router.cd_valid = false;
 667                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 668                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 669
 670                                 grph_obj_id =
 671                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 672                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 673                                 grph_obj_num =
 674                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 675                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 676                                 grph_obj_type =
 677                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 678                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 679
 680                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 681                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 682                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 683                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 684                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 685                                                                 (ctx->bios + data_offset +
 686                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 687                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 688                                                         u16 caps = 0;
 689
 690                                                         while (record->ucRecordSize > 0 &&
 691                                                                record->ucRecordType > 0 &&
 692                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 693                                                                 switch (record->ucRecordType) {
 694                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 695                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 696                                                                                 record;
 697                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 698                                                                         break;
 699                                                                 }
 700                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 701                                                                         ((char *)record + record->ucRecordSize);
 702                                                         }
 703                                                         radeon_add_atom_encoder(dev,
 704                                                                                 encoder_obj,
 705                                                                                 le16_to_cpu
 706                                                                                 (path->
 707                                                                                  usDeviceTag),
 708                                                                                 caps);
 709                                                 }
 710                                         }
 711                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 712                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 713                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 714                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 715                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 716                                                                 (ctx->bios + data_offset +
 717                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 718                                                         ATOM_I2C_RECORD *i2c_record;
 719                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 720                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 721                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 722                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 723                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 724                                                                 (ctx->bios + data_offset +
 725                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 726                                                         int enum_id;
 727
 728                                                         router.router_id = router_obj_id;
 729                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 730                                                              enum_id++) {
 731                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 732                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 733                                                                         break;
 734                                                         }
 735
 736                                                         while (record->ucRecordSize > 0 &&
 737                                                                record->ucRecordType > 0 &&
 738                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 739                                                                 switch (record->ucRecordType) {
 740                                                                 case ATOM_I2C_RECORD_TYPE:
 741                                                                         i2c_record =
 742                                                                                 (ATOM_I2C_RECORD *)
 743                                                                                 record;
 744                                                                         i2c_config =
 745                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 746                                                                                 &i2c_record->sucI2cId;
 747                                                                         router.i2c_info =
 748                                                                                 radeon_lookup_i2c_gpio(rdev,
 749                                                                                                        i2c_config->
 750                                                                                                        ucAccess);
 751                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 752                                                                         break;
 753                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 754                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 755                                                                                 record;
 756                                                                         router.ddc_valid = true;
 757                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 758                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 759                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 760                                                                         break;
 761                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 762                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 763                                                                                 record;
 764                                                                         router.cd_valid = true;
 765                                                                         router.cd_mux_type = cd_path->ucMuxType;
 766                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 767                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 768                                                                         break;
 769                                                                 }
 770                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 771                                                                         ((char *)record + record->ucRecordSize);
 772                                                         }
 773                                                 }
 774                                         }
 775                                 }
 776                         }
 777
 778                         /* look up gpio for ddc, hpd */
 779                         ddc_bus.valid = false;
 780                         hpd.hpd = RADEON_HPD_NONE;
 781                         if ((le16_to_cpu(path->usDeviceTag) &
 782                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 783                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 784                                         if (le16_to_cpu(path->usConnObjectId) ==
 785                                             le16_to_cpu(con_obj->asObjects[j].
 786                                                         usObjectID)) {
 787                                                 ATOM_COMMON_RECORD_HEADER
 788                                                     *record =
 789                                                     (ATOM_COMMON_RECORD_HEADER
 790                                                      *)
 791                                                     (ctx->bios + data_offset +
 792                                                      le16_to_cpu(con_obj->
 793                                                                  asObjects[j].
 794                                                                  usRecordOffset));
 795                                                 ATOM_I2C_RECORD *i2c_record;
 796                                                 ATOM_HPD_INT_RECORD *hpd_record;
 797                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 798
 799                                                 while (record->ucRecordSize > 0 &&
 800                                                        record->ucRecordType > 0 &&
 801                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 802                                                         switch (record->ucRecordType) {
 803                                                         case ATOM_I2C_RECORD_TYPE:
 804                                                                 i2c_record =
 805                                                                     (ATOM_I2C_RECORD *)
 806                                                                         record;
 807                                                                 i2c_config =
 808                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 809                                                                         &i2c_record->sucI2cId;
 810                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 811                                                                                                  i2c_config->
 812                                                                                                  ucAccess);
 813                                                                 break;
 814                                                         case ATOM_HPD_INT_RECORD_TYPE:
 815                                                                 hpd_record =
 816                                                                         (ATOM_HPD_INT_RECORD *)
 817                                                                         record;
 818                                                                 gpio = radeon_lookup_gpio(rdev,
 819                                                                                           hpd_record->ucHPDIntGPIOID);
 820                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 821                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 822                                                                 break;
 823                                                         }
 824                                                         record =
 825                                                             (ATOM_COMMON_RECORD_HEADER
 826                                                              *) ((char *)record
 827                                                                  +
 828                                                                  record->
 829                                                                  ucRecordSize);
 830                                                 }
 831                                                 break;
 832                                         }
 833                                 }
 834                         }
 835
 836                         /* needed for aux chan transactions */
 837                         ddc_bus.hpd = hpd.hpd;
 838
 839                         conn_id = le16_to_cpu(path->usConnObjectId);
 840
 841                         if (!radeon_atom_apply_quirks
 842                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 843                              &ddc_bus, &conn_id, &hpd))
 844                                 continue;
 845
 846                         radeon_add_atom_connector(dev,
 847                                                   conn_id,
 848                                                   le16_to_cpu(path->
 849                                                               usDeviceTag),
 850                                                   connector_type, &ddc_bus,
 851                                                   igp_lane_info,
 852                                                   connector_object_id,
 853                                                   &hpd,
 854                                                   &router);
 855
 856                 }
 857         }
 858
 859         radeon_link_encoder_connector(dev);
 860
 861         return true;
 862 }
 863
 864 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 865                                                  int connector_type,
 866                                                  uint16_t devices)
 867 {
 868         struct radeon_device *rdev = dev->dev_private;
 869
 870         if (rdev->flags & RADEON_IS_IGP) {
 871                 return supported_devices_connector_object_id_convert
 872                         [connector_type];
 873         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 874                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 875                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 876                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 877                 struct atom_context *ctx = mode_info->atom_context;
 878                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 879                 uint16_t size, data_offset;
 880                 uint8_t frev, crev;
 881                 ATOM_XTMDS_INFO *xtmds;
 882
 883                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 884                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 885
 886                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 887                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 888                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 889                                 else
 890                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 891                         } else {
 892                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 893                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 894                                 else
 895                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 896                         }
 897                 } else
 898                         return supported_devices_connector_object_id_convert
 899                                 [connector_type];
 900         } else {
 901                 return supported_devices_connector_object_id_convert
 902                         [connector_type];
 903         }
 904 }
 905
 906 struct bios_connector {
 907         bool valid;
 908         uint16_t line_mux;
 909         uint16_t devices;
 910         int connector_type;
 911         struct radeon_i2c_bus_rec ddc_bus;
 912         struct radeon_hpd hpd;
 913 };
 914
 915 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 916                                                                  drm_device
 917                                                                  *dev)
 918 {
 919         struct radeon_device *rdev = dev->dev_private;
 920         struct radeon_mode_info *mode_info = &rdev->mode_info;
 921         struct atom_context *ctx = mode_info->atom_context;
 922         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 923         uint16_t size, data_offset;
 924         uint8_t frev, crev;
 925         uint16_t device_support;
 926         uint8_t dac;
 927         union atom_supported_devices *supported_devices;
 928         int i, j, max_device;
 929         struct bios_connector *bios_connectors;
 930         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 931         struct radeon_router router;
 932
 933         router.ddc_valid = false;
 934         router.cd_valid = false;
 935
 936         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 937         if (!bios_connectors)
 938                 return false;
 939
 940         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 941                                     &data_offset)) {
 942                 kfree(bios_connectors);
 943                 return false;
 944         }
 945
 946         supported_devices =
 947             (union atom_supported_devices *)(ctx->bios + data_offset);
 948
 949         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 950
 951         if (frev > 1)
 952                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 953         else
 954                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 955
 956         for (i = 0; i < max_device; i++) {
 957                 ATOM_CONNECTOR_INFO_I2C ci =
 958                     supported_devices->info.asConnInfo[i];
 959
 960                 bios_connectors[i].valid = false;
 961
 962                 if (!(device_support & (1 << i))) {
 963                         continue;
 964                 }
 965
 966                 if (i == ATOM_DEVICE_CV_INDEX) {
 967                         DRM_DEBUG_KMS("Skipping Component Video\n");
 968                         continue;
 969                 }
 970
 971                 bios_connectors[i].connector_type =
 972                     supported_devices_connector_convert[ci.sucConnectorInfo.
 973                                                         sbfAccess.
 974                                                         bfConnectorType];
 975
 976                 if (bios_connectors[i].connector_type ==
 977                     DRM_MODE_CONNECTOR_Unknown)
 978                         continue;
 979
 980                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 981
 982                 bios_connectors[i].line_mux =
 983                         ci.sucI2cId.ucAccess;
 984
 985                 /* give tv unique connector ids */
 986                 if (i == ATOM_DEVICE_TV1_INDEX) {
 987                         bios_connectors[i].ddc_bus.valid = false;
 988                         bios_connectors[i].line_mux = 50;
 989                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 990                         bios_connectors[i].ddc_bus.valid = false;
 991                         bios_connectors[i].line_mux = 51;
 992                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 993                         bios_connectors[i].ddc_bus.valid = false;
 994                         bios_connectors[i].line_mux = 52;
 995                 } else
 996                         bios_connectors[i].ddc_bus =
 997                             radeon_lookup_i2c_gpio(rdev,
 998                                                    bios_connectors[i].line_mux);
 999
1000                 if ((crev > 1) && (frev > 1)) {
1001                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
1002                         switch (isb) {
1003                         case 0x4:
1004                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1005                                 break;
1006                         case 0xa:
1007                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1008                                 break;
1009                         default:
1010                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1011                                 break;
1012                         }
1013                 } else {
1014                         if (i == ATOM_DEVICE_DFP1_INDEX)
1015                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1016                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1017                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1018                         else
1019                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1020                 }
1021
1022                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1023                  * shared with a DVI port, we'll pick up the DVI connector when we
1024                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1025                  */
1026                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1027                         bios_connectors[i].connector_type =
1028                             DRM_MODE_CONNECTOR_VGA;
1029
1030                 if (!radeon_atom_apply_quirks
1031                     (dev, (1 << i), &bios_connectors[i].connector_type,
1032                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1033                      &bios_connectors[i].hpd))
1034                         continue;
1035
1036                 bios_connectors[i].valid = true;
1037                 bios_connectors[i].devices = (1 << i);
1038
1039                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1040                         radeon_add_atom_encoder(dev,
1041                                                 radeon_get_encoder_enum(dev,
1042                                                                       (1 << i),
1043                                                                       dac),
1044                                                 (1 << i),
1045                                                 0);
1046                 else
1047                         radeon_add_legacy_encoder(dev,
1048                                                   radeon_get_encoder_enum(dev,
1049                                                                         (1 << i),
1050                                                                         dac),
1051                                                   (1 << i));
1052         }
1053
1054         /* combine shared connectors */
1055         for (i = 0; i < max_device; i++) {
1056                 if (bios_connectors[i].valid) {
1057                         for (j = 0; j < max_device; j++) {
1058                                 if (bios_connectors[j].valid && (i != j)) {
1059                                         if (bios_connectors[i].line_mux ==
1060                                             bios_connectors[j].line_mux) {
1061                                                 /* make sure not to combine LVDS */
1062                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1063                                                         bios_connectors[i].line_mux = 53;
1064                                                         bios_connectors[i].ddc_bus.valid = false;
1065                                                         continue;
1066                                                 }
1067                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1068                                                         bios_connectors[j].line_mux = 53;
1069                                                         bios_connectors[j].ddc_bus.valid = false;
1070                                                         continue;
1071                                                 }
1072                                                 /* combine analog and digital for DVI-I */
1073                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1074                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1075                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1076                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1077                                                         bios_connectors[i].devices |=
1078                                                                 bios_connectors[j].devices;
1079                                                         bios_connectors[i].connector_type =
1080                                                                 DRM_MODE_CONNECTOR_DVII;
1081                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1082                                                                 bios_connectors[i].hpd =
1083                                                                         bios_connectors[j].hpd;
1084                                                         bios_connectors[j].valid = false;
1085                                                 }
1086                                         }
1087                                 }
1088                         }
1089                 }
1090         }
1091
1092         /* add the connectors */
1093         for (i = 0; i < max_device; i++) {
1094                 if (bios_connectors[i].valid) {
1095                         uint16_t connector_object_id =
1096                                 atombios_get_connector_object_id(dev,
1097                                                       bios_connectors[i].connector_type,
1098                                                       bios_connectors[i].devices);
1099                         radeon_add_atom_connector(dev,
1100                                                   bios_connectors[i].line_mux,
1101                                                   bios_connectors[i].devices,
1102                                                   bios_connectors[i].
1103                                                   connector_type,
1104                                                   &bios_connectors[i].ddc_bus,
1105                                                   0,
1106                                                   connector_object_id,
1107                                                   &bios_connectors[i].hpd,
1108                                                   &router);
1109                 }
1110         }
1111
1112         radeon_link_encoder_connector(dev);
1113
1114         kfree(bios_connectors);
1115         return true;
1116 }
1117
1118 union firmware_info {
1119         ATOM_FIRMWARE_INFO info;
1120         ATOM_FIRMWARE_INFO_V1_2 info_12;
1121         ATOM_FIRMWARE_INFO_V1_3 info_13;
1122         ATOM_FIRMWARE_INFO_V1_4 info_14;
1123         ATOM_FIRMWARE_INFO_V2_1 info_21;
1124         ATOM_FIRMWARE_INFO_V2_2 info_22;
1125 };
1126
1127 bool radeon_atom_get_clock_info(struct drm_device *dev)
1128 {
1129         struct radeon_device *rdev = dev->dev_private;
1130         struct radeon_mode_info *mode_info = &rdev->mode_info;
1131         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1132         union firmware_info *firmware_info;
1133         uint8_t frev, crev;
1134         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1135         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1136         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1137         struct radeon_pll *spll = &rdev->clock.spll;
1138         struct radeon_pll *mpll = &rdev->clock.mpll;
1139         uint16_t data_offset;
1140
1141         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1142                                    &frev, &crev, &data_offset)) {
1143                 firmware_info =
1144                         (union firmware_info *)(mode_info->atom_context->bios +
1145                                                 data_offset);
1146                 /* pixel clocks */
1147                 p1pll->reference_freq =
1148                     le16_to_cpu(firmware_info->info.usReferenceClock);
1149                 p1pll->reference_div = 0;
1150
1151                 if (crev < 2)
1152                         p1pll->pll_out_min =
1153                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1154                 else
1155                         p1pll->pll_out_min =
1156                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1157                 p1pll->pll_out_max =
1158                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1159
1160                 if (crev >= 4) {
1161                         p1pll->lcd_pll_out_min =
1162                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1163                         if (p1pll->lcd_pll_out_min == 0)
1164                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1165                         p1pll->lcd_pll_out_max =
1166                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1167                         if (p1pll->lcd_pll_out_max == 0)
1168                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1169                 } else {
1170                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1171                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1172                 }
1173
1174                 if (p1pll->pll_out_min == 0) {
1175                         if (ASIC_IS_AVIVO(rdev))
1176                                 p1pll->pll_out_min = 64800;
1177                         else
1178                                 p1pll->pll_out_min = 20000;
1179                 }
1180
1181                 p1pll->pll_in_min =
1182                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1183                 p1pll->pll_in_max =
1184                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1185
1186                 *p2pll = *p1pll;
1187
1188                 /* system clock */
1189                 if (ASIC_IS_DCE4(rdev))
1190                         spll->reference_freq =
1191                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1192                 else
1193                         spll->reference_freq =
1194                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1195                 spll->reference_div = 0;
1196
1197                 spll->pll_out_min =
1198                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1199                 spll->pll_out_max =
1200                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1201
1202                 /* ??? */
1203                 if (spll->pll_out_min == 0) {
1204                         if (ASIC_IS_AVIVO(rdev))
1205                                 spll->pll_out_min = 64800;
1206                         else
1207                                 spll->pll_out_min = 20000;
1208                 }
1209
1210                 spll->pll_in_min =
1211                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1212                 spll->pll_in_max =
1213                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1214
1215                 /* memory clock */
1216                 if (ASIC_IS_DCE4(rdev))
1217                         mpll->reference_freq =
1218                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1219                 else
1220                         mpll->reference_freq =
1221                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1222                 mpll->reference_div = 0;
1223
1224                 mpll->pll_out_min =
1225                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1226                 mpll->pll_out_max =
1227                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1228
1229                 /* ??? */
1230                 if (mpll->pll_out_min == 0) {
1231                         if (ASIC_IS_AVIVO(rdev))
1232                                 mpll->pll_out_min = 64800;
1233                         else
1234                                 mpll->pll_out_min = 20000;
1235                 }
1236
1237                 mpll->pll_in_min =
1238                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1239                 mpll->pll_in_max =
1240                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1241
1242                 rdev->clock.default_sclk =
1243                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1244                 rdev->clock.default_mclk =
1245                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1246
1247                 if (ASIC_IS_DCE4(rdev)) {
1248                         rdev->clock.default_dispclk =
1249                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1250                         if (rdev->clock.default_dispclk == 0) {
1251                                 if (ASIC_IS_DCE5(rdev))
1252                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1253                                 else
1254                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1255                         }
1256                         rdev->clock.dp_extclk =
1257                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1258                 }
1259                 *dcpll = *p1pll;
1260
1261                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1262                 if (rdev->clock.max_pixel_clock == 0)
1263                         rdev->clock.max_pixel_clock = 40000;
1264
1265                 return true;
1266         }
1267
1268         return false;
1269 }
1270
1271 union igp_info {
1272         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1273         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1274 };
1275
1276 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1277 {
1278         struct radeon_mode_info *mode_info = &rdev->mode_info;
1279         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1280         union igp_info *igp_info;
1281         u8 frev, crev;
1282         u16 data_offset;
1283
1284         /* sideport is AMD only */
1285         if (rdev->family == CHIP_RS600)
1286                 return false;
1287
1288         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1289                                    &frev, &crev, &data_offset)) {
1290                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1291                                       data_offset);
1292                 switch (crev) {
1293                 case 1:
1294                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1295                                 return true;
1296                         break;
1297                 case 2:
1298                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1299                                 return true;
1300                         break;
1301                 default:
1302                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1303                         break;
1304                 }
1305         }
1306         return false;
1307 }
1308
1309 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1310                                    struct radeon_encoder_int_tmds *tmds)
1311 {
1312         struct drm_device *dev = encoder->base.dev;
1313         struct radeon_device *rdev = dev->dev_private;
1314         struct radeon_mode_info *mode_info = &rdev->mode_info;
1315         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1316         uint16_t data_offset;
1317         struct _ATOM_TMDS_INFO *tmds_info;
1318         uint8_t frev, crev;
1319         uint16_t maxfreq;
1320         int i;
1321
1322         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1323                                    &frev, &crev, &data_offset)) {
1324                 tmds_info =
1325                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1326                                                    data_offset);
1327
1328                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1329                 for (i = 0; i < 4; i++) {
1330                         tmds->tmds_pll[i].freq =
1331                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1332                         tmds->tmds_pll[i].value =
1333                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1334                         tmds->tmds_pll[i].value |=
1335                             (tmds_info->asMiscInfo[i].
1336                              ucPLL_VCO_Gain & 0x3f) << 6;
1337                         tmds->tmds_pll[i].value |=
1338                             (tmds_info->asMiscInfo[i].
1339                              ucPLL_DutyCycle & 0xf) << 12;
1340                         tmds->tmds_pll[i].value |=
1341                             (tmds_info->asMiscInfo[i].
1342                              ucPLL_VoltageSwing & 0xf) << 16;
1343
1344                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1345                                   tmds->tmds_pll[i].freq,
1346                                   tmds->tmds_pll[i].value);
1347
1348                         if (maxfreq == tmds->tmds_pll[i].freq) {
1349                                 tmds->tmds_pll[i].freq = 0xffffffff;
1350                                 break;
1351                         }
1352                 }
1353                 return true;
1354         }
1355         return false;
1356 }
1357
1358 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1359                                       struct radeon_atom_ss *ss,
1360                                       int id)
1361 {
1362         struct radeon_mode_info *mode_info = &rdev->mode_info;
1363         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1364         uint16_t data_offset, size;
1365         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1366         uint8_t frev, crev;
1367         int i, num_indices;
1368
1369         memset(ss, 0, sizeof(struct radeon_atom_ss));
1370         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1371                                    &frev, &crev, &data_offset)) {
1372                 ss_info =
1373                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1374
1375                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1376                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1377
1378                 for (i = 0; i < num_indices; i++) {
1379                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1380                                 ss->percentage =
1381                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1382                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1383                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1384                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1385                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1386                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1387                                 return true;
1388                         }
1389                 }
1390         }
1391         return false;
1392 }
1393
1394 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1395                                                  struct radeon_atom_ss *ss,
1396                                                  int id)
1397 {
1398         struct radeon_mode_info *mode_info = &rdev->mode_info;
1399         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1400         u16 data_offset, size;
1401         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1402         u8 frev, crev;
1403         u16 percentage = 0, rate = 0;
1404
1405         /* get any igp specific overrides */
1406         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1407                                    &frev, &crev, &data_offset)) {
1408                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1409                         (mode_info->atom_context->bios + data_offset);
1410                 switch (id) {
1411                 case ASIC_INTERNAL_SS_ON_TMDS:
1412                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1413                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1414                         break;
1415                 case ASIC_INTERNAL_SS_ON_HDMI:
1416                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1417                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1418                         break;
1419                 case ASIC_INTERNAL_SS_ON_LVDS:
1420                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1421                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1422                         break;
1423                 }
1424                 if (percentage)
1425                         ss->percentage = percentage;
1426                 if (rate)
1427                         ss->rate = rate;
1428         }
1429 }
1430
1431 union asic_ss_info {
1432         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1433         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1434         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1435 };
1436
1437 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1438                                       struct radeon_atom_ss *ss,
1439                                       int id, u32 clock)
1440 {
1441         struct radeon_mode_info *mode_info = &rdev->mode_info;
1442         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1443         uint16_t data_offset, size;
1444         union asic_ss_info *ss_info;
1445         uint8_t frev, crev;
1446         int i, num_indices;
1447
1448         memset(ss, 0, sizeof(struct radeon_atom_ss));
1449         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1450                                    &frev, &crev, &data_offset)) {
1451
1452                 ss_info =
1453                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1454
1455                 switch (frev) {
1456                 case 1:
1457                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1458                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1459
1460                         for (i = 0; i < num_indices; i++) {
1461                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1462                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1463                                         ss->percentage =
1464                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1465                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1466                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1467                                         return true;
1468                                 }
1469                         }
1470                         break;
1471                 case 2:
1472                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1473                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1474                         for (i = 0; i < num_indices; i++) {
1475                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1476                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1477                                         ss->percentage =
1478                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1479                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1480                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1481                                         return true;
1482                                 }
1483                         }
1484                         break;
1485                 case 3:
1486                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1487                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1488                         for (i = 0; i < num_indices; i++) {
1489                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1490                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1491                                         ss->percentage =
1492                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1493                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1494                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1495                                         if (rdev->flags & RADEON_IS_IGP)
1496                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1497                                         return true;
1498                                 }
1499                         }
1500                         break;
1501                 default:
1502                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1503                         break;
1504                 }
1505
1506         }
1507         return false;
1508 }
1509
1510 union lvds_info {
1511         struct _ATOM_LVDS_INFO info;
1512         struct _ATOM_LVDS_INFO_V12 info_12;
1513 };
1514
1515 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1516                                                               radeon_encoder
1517                                                               *encoder)
1518 {
1519         struct drm_device *dev = encoder->base.dev;
1520         struct radeon_device *rdev = dev->dev_private;
1521         struct radeon_mode_info *mode_info = &rdev->mode_info;
1522         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1523         uint16_t data_offset, misc;
1524         union lvds_info *lvds_info;
1525         uint8_t frev, crev;
1526         struct radeon_encoder_atom_dig *lvds = NULL;
1527         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1528
1529         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1530                                    &frev, &crev, &data_offset)) {
1531                 lvds_info =
1532                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1533                 lvds =
1534                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1535
1536                 if (!lvds)
1537                         return NULL;
1538
1539                 lvds->native_mode.clock =
1540                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1541                 lvds->native_mode.hdisplay =
1542                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1543                 lvds->native_mode.vdisplay =
1544                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1545                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1546                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1547                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1548                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1549                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1550                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1551                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1552                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1553                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1554                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1555                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1556                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1557                 lvds->panel_pwr_delay =
1558                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1559                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1560
1561                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1562                 if (misc & ATOM_VSYNC_POLARITY)
1563                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1564                 if (misc & ATOM_HSYNC_POLARITY)
1565                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1566                 if (misc & ATOM_COMPOSITESYNC)
1567                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1568                 if (misc & ATOM_INTERLACE)
1569                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1570                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1571                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1572
1573                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1574                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1575
1576                 /* set crtc values */
1577                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1578
1579                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1580
1581                 encoder->native_mode = lvds->native_mode;
1582
1583                 if (encoder_enum == 2)
1584                         lvds->linkb = true;
1585                 else
1586                         lvds->linkb = false;
1587
1588                 /* parse the lcd record table */
1589                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1590                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1591                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1592                         bool bad_record = false;
1593                         u8 *record;
1594
1595                         if ((frev == 1) && (crev < 2))
1596                                 /* absolute */
1597                                 record = (u8 *)(mode_info->atom_context->bios +
1598                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1599                         else
1600                                 /* relative */
1601                                 record = (u8 *)(mode_info->atom_context->bios +
1602                                                 data_offset +
1603                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1604                         while (*record != ATOM_RECORD_END_TYPE) {
1605                                 switch (*record) {
1606                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1607                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1608                                         break;
1609                                 case LCD_RTS_RECORD_TYPE:
1610                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1611                                         break;
1612                                 case LCD_CAP_RECORD_TYPE:
1613                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1614                                         break;
1615                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1616                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1617                                         if (fake_edid_record->ucFakeEDIDLength) {
1618                                                 struct edid *edid;
1619                                                 int edid_size =
1620                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1621                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1622                                                 if (edid) {
1623                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1624                                                                fake_edid_record->ucFakeEDIDLength);
1625
1626                                                         if (drm_edid_is_valid(edid)) {
1627                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1628                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1629                                                         } else
1630                                                                 kfree(edid);
1631                                                 }
1632                                         }
1633                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1634                                         break;
1635                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1636                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1637                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1638                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1639                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1640                                         break;
1641                                 default:
1642                                         DRM_ERROR("Bad LCD record %d\n", *record);
1643                                         bad_record = true;
1644                                         break;
1645                                 }
1646                                 if (bad_record)
1647                                         break;
1648                         }
1649                 }
1650         }
1651         return lvds;
1652 }
1653
1654 struct radeon_encoder_primary_dac *
1655 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1656 {
1657         struct drm_device *dev = encoder->base.dev;
1658         struct radeon_device *rdev = dev->dev_private;
1659         struct radeon_mode_info *mode_info = &rdev->mode_info;
1660         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1661         uint16_t data_offset;
1662         struct _COMPASSIONATE_DATA *dac_info;
1663         uint8_t frev, crev;
1664         uint8_t bg, dac;
1665         struct radeon_encoder_primary_dac *p_dac = NULL;
1666
1667         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1668                                    &frev, &crev, &data_offset)) {
1669                 dac_info = (struct _COMPASSIONATE_DATA *)
1670                         (mode_info->atom_context->bios + data_offset);
1671
1672                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1673
1674                 if (!p_dac)
1675                         return NULL;
1676
1677                 bg = dac_info->ucDAC1_BG_Adjustment;
1678                 dac = dac_info->ucDAC1_DAC_Adjustment;
1679                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1680
1681         }
1682         return p_dac;
1683 }
1684
1685 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1686                                 struct drm_display_mode *mode)
1687 {
1688         struct radeon_mode_info *mode_info = &rdev->mode_info;
1689         ATOM_ANALOG_TV_INFO *tv_info;
1690         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1691         ATOM_DTD_FORMAT *dtd_timings;
1692         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1693         u8 frev, crev;
1694         u16 data_offset, misc;
1695
1696         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1697                                     &frev, &crev, &data_offset))
1698                 return false;
1699
1700         switch (crev) {
1701         case 1:
1702                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1703                 if (index >= MAX_SUPPORTED_TV_TIMING)
1704                         return false;
1705
1706                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1707                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1708                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1709                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1710                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1711
1712                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1713                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1714                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1715                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1716                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1717
1718                 mode->flags = 0;
1719                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1720                 if (misc & ATOM_VSYNC_POLARITY)
1721                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1722                 if (misc & ATOM_HSYNC_POLARITY)
1723                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1724                 if (misc & ATOM_COMPOSITESYNC)
1725                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1726                 if (misc & ATOM_INTERLACE)
1727                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1728                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1729                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1730
1731                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1732
1733                 if (index == 1) {
1734                         /* PAL timings appear to have wrong values for totals */
1735                         mode->crtc_htotal -= 1;
1736                         mode->crtc_vtotal -= 1;
1737                 }
1738                 break;
1739         case 2:
1740                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1741                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1742                         return false;
1743
1744                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1745                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1746                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1747                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1748                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1749                         le16_to_cpu(dtd_timings->usHSyncOffset);
1750                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1751                         le16_to_cpu(dtd_timings->usHSyncWidth);
1752
1753                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1754                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1755                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1756                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1757                         le16_to_cpu(dtd_timings->usVSyncOffset);
1758                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1759                         le16_to_cpu(dtd_timings->usVSyncWidth);
1760
1761                 mode->flags = 0;
1762                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1763                 if (misc & ATOM_VSYNC_POLARITY)
1764                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1765                 if (misc & ATOM_HSYNC_POLARITY)
1766                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1767                 if (misc & ATOM_COMPOSITESYNC)
1768                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1769                 if (misc & ATOM_INTERLACE)
1770                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1771                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1772                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1773
1774                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1775                 break;
1776         }
1777         return true;
1778 }
1779
1780 enum radeon_tv_std
1781 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1782 {
1783         struct radeon_mode_info *mode_info = &rdev->mode_info;
1784         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1785         uint16_t data_offset;
1786         uint8_t frev, crev;
1787         struct _ATOM_ANALOG_TV_INFO *tv_info;
1788         enum radeon_tv_std tv_std = TV_STD_NTSC;
1789
1790         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1791                                    &frev, &crev, &data_offset)) {
1792
1793                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1794                         (mode_info->atom_context->bios + data_offset);
1795
1796                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1797                 case ATOM_TV_NTSC:
1798                         tv_std = TV_STD_NTSC;
1799                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1800                         break;
1801                 case ATOM_TV_NTSCJ:
1802                         tv_std = TV_STD_NTSC_J;
1803                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1804                         break;
1805                 case ATOM_TV_PAL:
1806                         tv_std = TV_STD_PAL;
1807                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1808                         break;
1809                 case ATOM_TV_PALM:
1810                         tv_std = TV_STD_PAL_M;
1811                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1812                         break;
1813                 case ATOM_TV_PALN:
1814                         tv_std = TV_STD_PAL_N;
1815                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1816                         break;
1817                 case ATOM_TV_PALCN:
1818                         tv_std = TV_STD_PAL_CN;
1819                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1820                         break;
1821                 case ATOM_TV_PAL60:
1822                         tv_std = TV_STD_PAL_60;
1823                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1824                         break;
1825                 case ATOM_TV_SECAM:
1826                         tv_std = TV_STD_SECAM;
1827                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1828                         break;
1829                 default:
1830                         tv_std = TV_STD_NTSC;
1831                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1832                         break;
1833                 }
1834         }
1835         return tv_std;
1836 }
1837
1838 struct radeon_encoder_tv_dac *
1839 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1840 {
1841         struct drm_device *dev = encoder->base.dev;
1842         struct radeon_device *rdev = dev->dev_private;
1843         struct radeon_mode_info *mode_info = &rdev->mode_info;
1844         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1845         uint16_t data_offset;
1846         struct _COMPASSIONATE_DATA *dac_info;
1847         uint8_t frev, crev;
1848         uint8_t bg, dac;
1849         struct radeon_encoder_tv_dac *tv_dac = NULL;
1850
1851         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1852                                    &frev, &crev, &data_offset)) {
1853
1854                 dac_info = (struct _COMPASSIONATE_DATA *)
1855                         (mode_info->atom_context->bios + data_offset);
1856
1857                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1858
1859                 if (!tv_dac)
1860                         return NULL;
1861
1862                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1863                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1864                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1865
1866                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1867                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1868                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1869
1870                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1871                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1872                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1873
1874                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1875         }
1876         return tv_dac;
1877 }
1878
1879 static const char *thermal_controller_names[] = {
1880         "NONE",
1881         "lm63",
1882         "adm1032",
1883         "adm1030",
1884         "max6649",
1885         "lm64",
1886         "f75375",
1887         "asc7xxx",
1888 };
1889
1890 static const char *pp_lib_thermal_controller_names[] = {
1891         "NONE",
1892         "lm63",
1893         "adm1032",
1894         "adm1030",
1895         "max6649",
1896         "lm64",
1897         "f75375",
1898         "RV6xx",
1899         "RV770",
1900         "adt7473",
1901         "NONE",
1902         "External GPIO",
1903         "Evergreen",
1904         "emc2103",
1905         "Sumo",
1906         "Northern Islands",
1907 };
1908
1909 union power_info {
1910         struct _ATOM_POWERPLAY_INFO info;
1911         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1912         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1913         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1914         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1915         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1916 };
1917
1918 union pplib_clock_info {
1919         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1920         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1921         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1922         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1923 };
1924
1925 union pplib_power_state {
1926         struct _ATOM_PPLIB_STATE v1;
1927         struct _ATOM_PPLIB_STATE_V2 v2;
1928 };
1929
1930 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1931                                                  int state_index,
1932                                                  u32 misc, u32 misc2)
1933 {
1934         rdev->pm.power_state[state_index].misc = misc;
1935         rdev->pm.power_state[state_index].misc2 = misc2;
1936         /* order matters! */
1937         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1938                 rdev->pm.power_state[state_index].type =
1939                         POWER_STATE_TYPE_POWERSAVE;
1940         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1941                 rdev->pm.power_state[state_index].type =
1942                         POWER_STATE_TYPE_BATTERY;
1943         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1944                 rdev->pm.power_state[state_index].type =
1945                         POWER_STATE_TYPE_BATTERY;
1946         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1947                 rdev->pm.power_state[state_index].type =
1948                         POWER_STATE_TYPE_BALANCED;
1949         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1950                 rdev->pm.power_state[state_index].type =
1951                         POWER_STATE_TYPE_PERFORMANCE;
1952                 rdev->pm.power_state[state_index].flags &=
1953                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1954         }
1955         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1956                 rdev->pm.power_state[state_index].type =
1957                         POWER_STATE_TYPE_BALANCED;
1958         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1959                 rdev->pm.power_state[state_index].type =
1960                         POWER_STATE_TYPE_DEFAULT;
1961                 rdev->pm.default_power_state_index = state_index;
1962                 rdev->pm.power_state[state_index].default_clock_mode =
1963                         &rdev->pm.power_state[state_index].clock_info[0];
1964         } else if (state_index == 0) {
1965                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1966                         RADEON_PM_MODE_NO_DISPLAY;
1967         }
1968 }
1969
1970 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1971 {
1972         struct radeon_mode_info *mode_info = &rdev->mode_info;
1973         u32 misc, misc2 = 0;
1974         int num_modes = 0, i;
1975         int state_index = 0;
1976         struct radeon_i2c_bus_rec i2c_bus;
1977         union power_info *power_info;
1978         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1979         u16 data_offset;
1980         u8 frev, crev;
1981
1982         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1983                                    &frev, &crev, &data_offset))
1984                 return state_index;
1985         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1986
1987         /* add the i2c bus for thermal/fan chip */
1988         if (power_info->info.ucOverdriveThermalController > 0) {
1989                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1990                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1991                          power_info->info.ucOverdriveControllerAddress >> 1);
1992                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1993                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1994                 if (rdev->pm.i2c_bus) {
1995                         struct i2c_board_info info = { };
1996                         const char *name = thermal_controller_names[power_info->info.
1997                                                                     ucOverdriveThermalController];
1998                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1999                         strlcpy(info.type, name, sizeof(info.type));
2000                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2001                 }
2002         }
2003         num_modes = power_info->info.ucNumOfPowerModeEntries;
2004         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2005                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2006         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2007         if (!rdev->pm.power_state)
2008                 return state_index;
2009         /* last mode is usually default, array is low to high */
2010         for (i = 0; i < num_modes; i++) {
2011                 rdev->pm.power_state[state_index].clock_info =
2012                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2013                 if (!rdev->pm.power_state[state_index].clock_info)
2014                         return state_index;
2015                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2016                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2017                 switch (frev) {
2018                 case 1:
2019                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2020                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2021                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2022                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2023                         /* skip invalid modes */
2024                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2025                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2026                                 continue;
2027                         rdev->pm.power_state[state_index].pcie_lanes =
2028                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2029                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2030                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2031                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2032                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2033                                         VOLTAGE_GPIO;
2034                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2035                                         radeon_lookup_gpio(rdev,
2036                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2037                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2038                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2039                                                 true;
2040                                 else
2041                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2042                                                 false;
2043                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2044                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2045                                         VOLTAGE_VDDC;
2046                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2047                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2048                         }
2049                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2050                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2051                         state_index++;
2052                         break;
2053                 case 2:
2054                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2055                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2056                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2057                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2058                         /* skip invalid modes */
2059                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2060                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2061                                 continue;
2062                         rdev->pm.power_state[state_index].pcie_lanes =
2063                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2064                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2065                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2066                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2067                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2068                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2069                                         VOLTAGE_GPIO;
2070                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2071                                         radeon_lookup_gpio(rdev,
2072                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2073                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2074                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2075                                                 true;
2076                                 else
2077                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2078                                                 false;
2079                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2080                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2081                                         VOLTAGE_VDDC;
2082                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2083                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2084                         }
2085                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2086                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2087                         state_index++;
2088                         break;
2089                 case 3:
2090                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2091                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2092                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2093                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2094                         /* skip invalid modes */
2095                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2096                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2097                                 continue;
2098                         rdev->pm.power_state[state_index].pcie_lanes =
2099                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2100                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2101                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2102                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2103                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2104                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2105                                         VOLTAGE_GPIO;
2106                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2107                                         radeon_lookup_gpio(rdev,
2108                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2109                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2110                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2111                                                 true;
2112                                 else
2113                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2114                                                 false;
2115                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2116                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2117                                         VOLTAGE_VDDC;
2118                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2119                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2120                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2121                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2122                                                 true;
2123                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2124                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2125                                 }
2126                         }
2127                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2128                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2129                         state_index++;
2130                         break;
2131                 }
2132         }
2133         /* last mode is usually default */
2134         if (rdev->pm.default_power_state_index == -1) {
2135                 rdev->pm.power_state[state_index - 1].type =
2136                         POWER_STATE_TYPE_DEFAULT;
2137                 rdev->pm.default_power_state_index = state_index - 1;
2138                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2139                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2140                 rdev->pm.power_state[state_index].flags &=
2141                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2142                 rdev->pm.power_state[state_index].misc = 0;
2143                 rdev->pm.power_state[state_index].misc2 = 0;
2144         }
2145         return state_index;
2146 }
2147
2148 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2149                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2150 {
2151         struct radeon_i2c_bus_rec i2c_bus;
2152
2153         /* add the i2c bus for thermal/fan chip */
2154         if (controller->ucType > 0) {
2155                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2156                         DRM_INFO("Internal thermal controller %s fan control\n",
2157                                  (controller->ucFanParameters &
2158                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2159                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2160                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2161                         DRM_INFO("Internal thermal controller %s fan control\n",
2162                                  (controller->ucFanParameters &
2163                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2164                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2165                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2166                         DRM_INFO("Internal thermal controller %s fan control\n",
2167                                  (controller->ucFanParameters &
2168                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2169                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2170                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2171                         DRM_INFO("Internal thermal controller %s fan control\n",
2172                                  (controller->ucFanParameters &
2173                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2174                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2175                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2176                         DRM_INFO("Internal thermal controller %s fan control\n",
2177                                  (controller->ucFanParameters &
2178                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2180                 } else if ((controller->ucType ==
2181                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2182                            (controller->ucType ==
2183                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2184                            (controller->ucType ==
2185                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2186                         DRM_INFO("Special thermal controller config\n");
2187                 } else {
2188                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2189                                  pp_lib_thermal_controller_names[controller->ucType],
2190                                  controller->ucI2cAddress >> 1,
2191                                  (controller->ucFanParameters &
2192                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2193                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2194                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2195                         if (rdev->pm.i2c_bus) {
2196                                 struct i2c_board_info info = { };
2197                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2198                                 info.addr = controller->ucI2cAddress >> 1;
2199                                 strlcpy(info.type, name, sizeof(info.type));
2200                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2201                         }
2202                 }
2203         }
2204 }
2205
2206 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2207                                                  u16 *vddc, u16 *vddci)
2208 {
2209         struct radeon_mode_info *mode_info = &rdev->mode_info;
2210         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2211         u8 frev, crev;
2212         u16 data_offset;
2213         union firmware_info *firmware_info;
2214
2215         *vddc = 0;
2216         *vddci = 0;
2217
2218         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2219                                    &frev, &crev, &data_offset)) {
2220                 firmware_info =
2221                         (union firmware_info *)(mode_info->atom_context->bios +
2222                                                 data_offset);
2223                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2224                 if ((frev == 2) && (crev >= 2))
2225                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2226         }
2227 }
2228
2229 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2230                                                        int state_index, int mode_index,
2231                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2232 {
2233         int j;
2234         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2235         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2236         u16 vddc, vddci;
2237
2238         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2239
2240         rdev->pm.power_state[state_index].misc = misc;
2241         rdev->pm.power_state[state_index].misc2 = misc2;
2242         rdev->pm.power_state[state_index].pcie_lanes =
2243                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2244                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2245         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2246         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2247                 rdev->pm.power_state[state_index].type =
2248                         POWER_STATE_TYPE_BATTERY;
2249                 break;
2250         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2251                 rdev->pm.power_state[state_index].type =
2252                         POWER_STATE_TYPE_BALANCED;
2253                 break;
2254         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2255                 rdev->pm.power_state[state_index].type =
2256                         POWER_STATE_TYPE_PERFORMANCE;
2257                 break;
2258         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2259                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2260                         rdev->pm.power_state[state_index].type =
2261                                 POWER_STATE_TYPE_PERFORMANCE;
2262                 break;
2263         }
2264         rdev->pm.power_state[state_index].flags = 0;
2265         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2266                 rdev->pm.power_state[state_index].flags |=
2267                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2268         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2269                 rdev->pm.power_state[state_index].type =
2270                         POWER_STATE_TYPE_DEFAULT;
2271                 rdev->pm.default_power_state_index = state_index;
2272                 rdev->pm.power_state[state_index].default_clock_mode =
2273                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2274                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2275                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2276                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2277                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2278                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2279                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2280                 } else {
2281                         /* patch the table values with the default slck/mclk from firmware info */
2282                         for (j = 0; j < mode_index; j++) {
2283                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2284                                         rdev->clock.default_mclk;
2285                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2286                                         rdev->clock.default_sclk;
2287                                 if (vddc)
2288                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2289                                                 vddc;
2290                         }
2291                 }
2292         }
2293 }
2294
2295 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2296                                                    int state_index, int mode_index,
2297                                                    union pplib_clock_info *clock_info)
2298 {
2299         u32 sclk, mclk;
2300
2301         if (rdev->flags & RADEON_IS_IGP) {
2302                 if (rdev->family >= CHIP_PALM) {
2303                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2304                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2305                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2306                 } else {
2307                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2308                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2309                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2310                 }
2311         } else if (ASIC_IS_DCE4(rdev)) {
2312                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2313                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2314                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2315                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2316                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2317                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2318                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2319                         VOLTAGE_SW;
2320                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2321                         le16_to_cpu(clock_info->evergreen.usVDDC);
2322                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2323                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2324         } else {
2325                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2326                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2327                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2328                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2329                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2330                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2331                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2332                         VOLTAGE_SW;
2333                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2334                         le16_to_cpu(clock_info->r600.usVDDC);
2335         }
2336
2337         /* patch up vddc if necessary */
2338         if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2339                 u16 vddc;
2340
2341                 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2342                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2343         }
2344
2345         if (rdev->flags & RADEON_IS_IGP) {
2346                 /* skip invalid modes */
2347                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2348                         return false;
2349         } else {
2350                 /* skip invalid modes */
2351                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2352                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2353                         return false;
2354         }
2355         return true;
2356 }
2357
2358 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2359 {
2360         struct radeon_mode_info *mode_info = &rdev->mode_info;
2361         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2362         union pplib_power_state *power_state;
2363         int i, j;
2364         int state_index = 0, mode_index = 0;
2365         union pplib_clock_info *clock_info;
2366         bool valid;
2367         union power_info *power_info;
2368         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2369         u16 data_offset;
2370         u8 frev, crev;
2371
2372         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2373                                    &frev, &crev, &data_offset))
2374                 return state_index;
2375         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2376
2377         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2378         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2379                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2380         if (!rdev->pm.power_state)
2381                 return state_index;
2382         /* first mode is usually default, followed by low to high */
2383         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2384                 mode_index = 0;
2385                 power_state = (union pplib_power_state *)
2386                         (mode_info->atom_context->bios + data_offset +
2387                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2388                          i * power_info->pplib.ucStateEntrySize);
2389                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2390                         (mode_info->atom_context->bios + data_offset +
2391                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2392                          (power_state->v1.ucNonClockStateIndex *
2393                           power_info->pplib.ucNonClockSize));
2394                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2395                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2396                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2397                                                              GFP_KERNEL);
2398                 if (!rdev->pm.power_state[i].clock_info)
2399                         return state_index;
2400                 if (power_info->pplib.ucStateEntrySize - 1) {
2401                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2402                                 clock_info = (union pplib_clock_info *)
2403                                         (mode_info->atom_context->bios + data_offset +
2404                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2405                                          (power_state->v1.ucClockStateIndices[j] *
2406                                           power_info->pplib.ucClockInfoSize));
2407                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2408                                                                                state_index, mode_index,
2409                                                                                clock_info);
2410                                 if (valid)
2411                                         mode_index++;
2412                         }
2413                 } else {
2414                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2415                                 rdev->clock.default_mclk;
2416                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2417                                 rdev->clock.default_sclk;
2418                         mode_index++;
2419                 }
2420                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2421                 if (mode_index) {
2422                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2423                                                                    non_clock_info);
2424                         state_index++;
2425                 }
2426         }
2427         /* if multiple clock modes, mark the lowest as no display */
2428         for (i = 0; i < state_index; i++) {
2429                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2430                         rdev->pm.power_state[i].clock_info[0].flags |=
2431                                 RADEON_PM_MODE_NO_DISPLAY;
2432         }
2433         /* first mode is usually default */
2434         if (rdev->pm.default_power_state_index == -1) {
2435                 rdev->pm.power_state[0].type =
2436                         POWER_STATE_TYPE_DEFAULT;
2437                 rdev->pm.default_power_state_index = 0;
2438                 rdev->pm.power_state[0].default_clock_mode =
2439                         &rdev->pm.power_state[0].clock_info[0];
2440         }
2441         return state_index;
2442 }
2443
2444 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2445 {
2446         struct radeon_mode_info *mode_info = &rdev->mode_info;
2447         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2448         union pplib_power_state *power_state;
2449         int i, j, non_clock_array_index, clock_array_index;
2450         int state_index = 0, mode_index = 0;
2451         union pplib_clock_info *clock_info;
2452         struct StateArray *state_array;
2453         struct ClockInfoArray *clock_info_array;
2454         struct NonClockInfoArray *non_clock_info_array;
2455         bool valid;
2456         union power_info *power_info;
2457         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2458         u16 data_offset;
2459         u8 frev, crev;
2460
2461         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2462                                    &frev, &crev, &data_offset))
2463                 return state_index;
2464         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2465
2466         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2467         state_array = (struct StateArray *)
2468                 (mode_info->atom_context->bios + data_offset +
2469                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2470         clock_info_array = (struct ClockInfoArray *)
2471                 (mode_info->atom_context->bios + data_offset +
2472                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2473         non_clock_info_array = (struct NonClockInfoArray *)
2474                 (mode_info->atom_context->bios + data_offset +
2475                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2476         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2477                                        state_array->ucNumEntries, GFP_KERNEL);
2478         if (!rdev->pm.power_state)
2479                 return state_index;
2480         for (i = 0; i < state_array->ucNumEntries; i++) {
2481                 mode_index = 0;
2482                 power_state = (union pplib_power_state *)&state_array->states[i];
2483                 /* XXX this might be an inagua bug... */
2484                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2485                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2486                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2487                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2488                                                              (power_state->v2.ucNumDPMLevels ?
2489                                                               power_state->v2.ucNumDPMLevels : 1),
2490                                                              GFP_KERNEL);
2491                 if (!rdev->pm.power_state[i].clock_info)
2492                         return state_index;
2493                 if (power_state->v2.ucNumDPMLevels) {
2494                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2495                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2496                                 /* XXX this might be an inagua bug... */
2497                                 if (clock_array_index >= clock_info_array->ucNumEntries)
2498                                         continue;
2499                                 clock_info = (union pplib_clock_info *)
2500                                         &clock_info_array->clockInfo[clock_array_index];
2501                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2502                                                                                state_index, mode_index,
2503                                                                                clock_info);
2504                                 if (valid)
2505                                         mode_index++;
2506                         }
2507                 } else {
2508                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2509                                 rdev->clock.default_mclk;
2510                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2511                                 rdev->clock.default_sclk;
2512                         mode_index++;
2513                 }
2514                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2515                 if (mode_index) {
2516                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2517                                                                    non_clock_info);
2518                         state_index++;
2519                 }
2520         }
2521         /* if multiple clock modes, mark the lowest as no display */
2522         for (i = 0; i < state_index; i++) {
2523                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2524                         rdev->pm.power_state[i].clock_info[0].flags |=
2525                                 RADEON_PM_MODE_NO_DISPLAY;
2526         }
2527         /* first mode is usually default */
2528         if (rdev->pm.default_power_state_index == -1) {
2529                 rdev->pm.power_state[0].type =
2530                         POWER_STATE_TYPE_DEFAULT;
2531                 rdev->pm.default_power_state_index = 0;
2532                 rdev->pm.power_state[0].default_clock_mode =
2533                         &rdev->pm.power_state[0].clock_info[0];
2534         }
2535         return state_index;
2536 }
2537
2538 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2539 {
2540         struct radeon_mode_info *mode_info = &rdev->mode_info;
2541         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2542         u16 data_offset;
2543         u8 frev, crev;
2544         int state_index = 0;
2545
2546         rdev->pm.default_power_state_index = -1;
2547
2548         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2549                                    &frev, &crev, &data_offset)) {
2550                 switch (frev) {
2551                 case 1:
2552                 case 2:
2553                 case 3:
2554                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2555                         break;
2556                 case 4:
2557                 case 5:
2558                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2559                         break;
2560                 case 6:
2561                         state_index = radeon_atombios_parse_power_table_6(rdev);
2562                         break;
2563                 default:
2564                         break;
2565                 }
2566         } else {
2567                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2568                 if (rdev->pm.power_state) {
2569                         rdev->pm.power_state[0].clock_info =
2570                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2571                         if (rdev->pm.power_state[0].clock_info) {
2572                                 /* add the default mode */
2573                                 rdev->pm.power_state[state_index].type =
2574                                         POWER_STATE_TYPE_DEFAULT;
2575                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2576                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2577                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2578                                 rdev->pm.power_state[state_index].default_clock_mode =
2579                                         &rdev->pm.power_state[state_index].clock_info[0];
2580                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2581                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2582                                 rdev->pm.default_power_state_index = state_index;
2583                                 rdev->pm.power_state[state_index].flags = 0;
2584                                 state_index++;
2585                         }
2586                 }
2587         }
2588
2589         rdev->pm.num_power_states = state_index;
2590
2591         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2592         rdev->pm.current_clock_mode_index = 0;
2593         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2594 }
2595
2596 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2597 {
2598         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2599         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2600
2601         args.ucEnable = enable;
2602
2603         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2604 }
2605
2606 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2607 {
2608         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2609         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2610
2611         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2612         return le32_to_cpu(args.ulReturnEngineClock);
2613 }
2614
2615 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2616 {
2617         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2618         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2619
2620         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2621         return le32_to_cpu(args.ulReturnMemoryClock);
2622 }
2623
2624 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2625                                   uint32_t eng_clock)
2626 {
2627         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2628         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2629
2630         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2631
2632         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2633 }
2634
2635 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2636                                   uint32_t mem_clock)
2637 {
2638         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2639         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2640
2641         if (rdev->flags & RADEON_IS_IGP)
2642                 return;
2643
2644         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2645
2646         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2647 }
2648
2649 union set_voltage {
2650         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2651         struct _SET_VOLTAGE_PARAMETERS v1;
2652         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2653 };
2654
2655 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2656 {
2657         union set_voltage args;
2658         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2659         u8 frev, crev, volt_index = voltage_level;
2660
2661         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2662                 return;
2663
2664         /* 0xff01 is a flag rather then an actual voltage */
2665         if (voltage_level == 0xff01)
2666                 return;
2667
2668         switch (crev) {
2669         case 1:
2670                 args.v1.ucVoltageType = voltage_type;
2671                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2672                 args.v1.ucVoltageIndex = volt_index;
2673                 break;
2674         case 2:
2675                 args.v2.ucVoltageType = voltage_type;
2676                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2677                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2678                 break;
2679         default:
2680                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2681                 return;
2682         }
2683
2684         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2685 }
2686
2687 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2688                              u16 *voltage)
2689 {
2690         union set_voltage args;
2691         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2692         u8 frev, crev;
2693
2694         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2695                 return -EINVAL;
2696
2697         switch (crev) {
2698         case 1:
2699                 return -EINVAL;
2700         case 2:
2701                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2702                 args.v2.ucVoltageMode = 0;
2703                 args.v2.usVoltageLevel = 0;
2704
2705                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2706
2707                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2708                 break;
2709         default:
2710                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2711                 return -EINVAL;
2712         }
2713
2714         return 0;
2715 }
2716
2717 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2718 {
2719         struct radeon_device *rdev = dev->dev_private;
2720         uint32_t bios_2_scratch, bios_6_scratch;
2721
2722         if (rdev->family >= CHIP_R600) {
2723                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2724                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2725         } else {
2726                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2727                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2728         }
2729
2730         /* let the bios control the backlight */
2731         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2732
2733         /* tell the bios not to handle mode switching */
2734         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2735
2736         if (rdev->family >= CHIP_R600) {
2737                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2738                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2739         } else {
2740                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2741                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2742         }
2743
2744 }
2745
2746 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2747 {
2748         uint32_t scratch_reg;
2749         int i;
2750
2751         if (rdev->family >= CHIP_R600)
2752                 scratch_reg = R600_BIOS_0_SCRATCH;
2753         else
2754                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2755
2756         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2757                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2758 }
2759
2760 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2761 {
2762         uint32_t scratch_reg;
2763         int i;
2764
2765         if (rdev->family >= CHIP_R600)
2766                 scratch_reg = R600_BIOS_0_SCRATCH;
2767         else
2768                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2769
2770         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2771                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2772 }
2773
2774 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2775 {
2776         struct drm_device *dev = encoder->dev;
2777         struct radeon_device *rdev = dev->dev_private;
2778         uint32_t bios_6_scratch;
2779
2780         if (rdev->family >= CHIP_R600)
2781                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2782         else
2783                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2784
2785         if (lock) {
2786                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2787                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2788         } else {
2789                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2790                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2791         }
2792
2793         if (rdev->family >= CHIP_R600)
2794                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2795         else
2796                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2797 }
2798
2799 /* at some point we may want to break this out into individual functions */
2800 void
2801 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2802                                        struct drm_encoder *encoder,
2803                                        bool connected)
2804 {
2805         struct drm_device *dev = connector->dev;
2806         struct radeon_device *rdev = dev->dev_private;
2807         struct radeon_connector *radeon_connector =
2808             to_radeon_connector(connector);
2809         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2810         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2811
2812         if (rdev->family >= CHIP_R600) {
2813                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2814                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2815                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2816         } else {
2817                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2818                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2819                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2820         }
2821
2822         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2823             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2824                 if (connected) {
2825                         DRM_DEBUG_KMS("TV1 connected\n");
2826                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2827                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2828                 } else {
2829                         DRM_DEBUG_KMS("TV1 disconnected\n");
2830                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2831                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2832                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2833                 }
2834         }
2835         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2836             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2837                 if (connected) {
2838                         DRM_DEBUG_KMS("CV connected\n");
2839                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2840                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2841                 } else {
2842                         DRM_DEBUG_KMS("CV disconnected\n");
2843                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2844                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2845                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2846                 }
2847         }
2848         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2849             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2850                 if (connected) {
2851                         DRM_DEBUG_KMS("LCD1 connected\n");
2852                         bios_0_scratch |= ATOM_S0_LCD1;
2853                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2854                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2855                 } else {
2856                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2857                         bios_0_scratch &= ~ATOM_S0_LCD1;
2858                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2859                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2860                 }
2861         }
2862         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2863             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2864                 if (connected) {
2865                         DRM_DEBUG_KMS("CRT1 connected\n");
2866                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2867                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2868                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2869                 } else {
2870                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2871                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2872                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2873                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2874                 }
2875         }
2876         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2877             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2878                 if (connected) {
2879                         DRM_DEBUG_KMS("CRT2 connected\n");
2880                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2881                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2882                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2883                 } else {
2884                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2885                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2886                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2887                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2888                 }
2889         }
2890         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2891             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2892                 if (connected) {
2893                         DRM_DEBUG_KMS("DFP1 connected\n");
2894                         bios_0_scratch |= ATOM_S0_DFP1;
2895                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2896                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2897                 } else {
2898                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2899                         bios_0_scratch &= ~ATOM_S0_DFP1;
2900                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2901                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2902                 }
2903         }
2904         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2905             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2906                 if (connected) {
2907                         DRM_DEBUG_KMS("DFP2 connected\n");
2908                         bios_0_scratch |= ATOM_S0_DFP2;
2909                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2910                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2911                 } else {
2912                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2913                         bios_0_scratch &= ~ATOM_S0_DFP2;
2914                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2915                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2916                 }
2917         }
2918         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2919             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2920                 if (connected) {
2921                         DRM_DEBUG_KMS("DFP3 connected\n");
2922                         bios_0_scratch |= ATOM_S0_DFP3;
2923                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2924                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2925                 } else {
2926                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2927                         bios_0_scratch &= ~ATOM_S0_DFP3;
2928                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2929                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2930                 }
2931         }
2932         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2933             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2934                 if (connected) {
2935                         DRM_DEBUG_KMS("DFP4 connected\n");
2936                         bios_0_scratch |= ATOM_S0_DFP4;
2937                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2938                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2939                 } else {
2940                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2941                         bios_0_scratch &= ~ATOM_S0_DFP4;
2942                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2943                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2944                 }
2945         }
2946         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2947             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2948                 if (connected) {
2949                         DRM_DEBUG_KMS("DFP5 connected\n");
2950                         bios_0_scratch |= ATOM_S0_DFP5;
2951                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2952                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2953                 } else {
2954                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2955                         bios_0_scratch &= ~ATOM_S0_DFP5;
2956                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2957                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2958                 }
2959         }
2960
2961         if (rdev->family >= CHIP_R600) {
2962                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2963                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2964                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2965         } else {
2966                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2967                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2968                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2969         }
2970 }
2971
2972 void
2973 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2974 {
2975         struct drm_device *dev = encoder->dev;
2976         struct radeon_device *rdev = dev->dev_private;
2977         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2978         uint32_t bios_3_scratch;
2979
2980         if (rdev->family >= CHIP_R600)
2981                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2982         else
2983                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2984
2985         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2986                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2987                 bios_3_scratch |= (crtc << 18);
2988         }
2989         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2990                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2991                 bios_3_scratch |= (crtc << 24);
2992         }
2993         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2994                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2995                 bios_3_scratch |= (crtc << 16);
2996         }
2997         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2998                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2999                 bios_3_scratch |= (crtc << 20);
3000         }
3001         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3002                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3003                 bios_3_scratch |= (crtc << 17);
3004         }
3005         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3006                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3007                 bios_3_scratch |= (crtc << 19);
3008         }
3009         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3010                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3011                 bios_3_scratch |= (crtc << 23);
3012         }
3013         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3014                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3015                 bios_3_scratch |= (crtc << 25);
3016         }
3017
3018         if (rdev->family >= CHIP_R600)
3019                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3020         else
3021                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3022 }
3023
3024 void
3025 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3026 {
3027         struct drm_device *dev = encoder->dev;
3028         struct radeon_device *rdev = dev->dev_private;
3029         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3030         uint32_t bios_2_scratch;
3031
3032         if (rdev->family >= CHIP_R600)
3033                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3034         else
3035                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3036
3037         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3038                 if (on)
3039                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3040                 else
3041                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3042         }
3043         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3044                 if (on)
3045                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3046                 else
3047                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3048         }
3049         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3050                 if (on)
3051                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3052                 else
3053                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3054         }
3055         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3056                 if (on)
3057                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3058                 else
3059                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3060         }
3061         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3062                 if (on)
3063                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3064                 else
3065                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3066         }
3067         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3068                 if (on)
3069                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3070                 else
3071                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3072         }
3073         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3074                 if (on)
3075                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3076                 else
3077                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3078         }
3079         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3080                 if (on)
3081                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3082                 else
3083                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3084         }
3085         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3086                 if (on)
3087                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3088                 else
3089                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3090         }
3091         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3092                 if (on)
3093                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3094                 else
3095                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3096         }
3097
3098         if (rdev->family >= CHIP_R600)
3099                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3100         else
3101                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3102 }