drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset, size;
  73         int i, num_indices;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  79                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  80
  81                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  82                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  83
  84                 for (i = 0; i < num_indices; i++) {
  85                         gpio = &i2c_info->asGPIO_Info[i];
  86
  87                         if (gpio->sucI2cId.ucAccess == id) {
  88                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  89                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  90                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  91                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  92                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  93                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  94                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  95                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  96                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  97                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  98                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  99                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 100                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 101                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 102                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 103                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 104
 105                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 106                                         i2c.hw_capable = true;
 107                                 else
 108                                         i2c.hw_capable = false;
 109
 110                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 111                                         i2c.mm_i2c = true;
 112                                 else
 113                                         i2c.mm_i2c = false;
 114
 115                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 116
 117                                 i2c.valid = true;
 118                                 break;
 119                         }
 120                 }
 121         }
 122
 123         return i2c;
 124 }
 125
 126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 127                                                         u8 id)
 128 {
 129         struct atom_context *ctx = rdev->mode_info.atom_context;
 130         struct radeon_gpio_rec gpio;
 131         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 132         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 133         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 134         u16 data_offset, size;
 135         int i, num_indices;
 136
 137         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 138         gpio.valid = false;
 139
 140         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 141                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 142
 143                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 144                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 145
 146                 for (i = 0; i < num_indices; i++) {
 147                         pin = &gpio_info->asGPIO_Pin[i];
 148                         if (id == pin->ucGPIO_ID) {
 149                                 gpio.id = pin->ucGPIO_ID;
 150                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 151                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 152                                 gpio.valid = true;
 153                                 break;
 154                         }
 155                 }
 156         }
 157
 158         return gpio;
 159 }
 160
 161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 162                                                             struct radeon_gpio_rec *gpio)
 163 {
 164         struct radeon_hpd hpd;
 165         u32 reg;
 166
 167         if (ASIC_IS_DCE4(rdev))
 168                 reg = EVERGREEN_DC_GPIO_HPD_A;
 169         else
 170                 reg = AVIVO_DC_GPIO_HPD_A;
 171
 172         hpd.gpio = *gpio;
 173         if (gpio->reg == reg) {
 174                 switch(gpio->mask) {
 175                 case (1 << 0):
 176                         hpd.hpd = RADEON_HPD_1;
 177                         break;
 178                 case (1 << 8):
 179                         hpd.hpd = RADEON_HPD_2;
 180                         break;
 181                 case (1 << 16):
 182                         hpd.hpd = RADEON_HPD_3;
 183                         break;
 184                 case (1 << 24):
 185                         hpd.hpd = RADEON_HPD_4;
 186                         break;
 187                 case (1 << 26):
 188                         hpd.hpd = RADEON_HPD_5;
 189                         break;
 190                 case (1 << 28):
 191                         hpd.hpd = RADEON_HPD_6;
 192                         break;
 193                 default:
 194                         hpd.hpd = RADEON_HPD_NONE;
 195                         break;
 196                 }
 197         } else
 198                 hpd.hpd = RADEON_HPD_NONE;
 199         return hpd;
 200 }
 201
 202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 203                                      uint32_t supported_device,
 204                                      int *connector_type,
 205                                      struct radeon_i2c_bus_rec *i2c_bus,
 206                                      uint16_t *line_mux,
 207                                      struct radeon_hpd *hpd)
 208 {
 209
 210         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 211         if ((dev->pdev->device == 0x791e) &&
 212             (dev->pdev->subsystem_vendor == 0x1043) &&
 213             (dev->pdev->subsystem_device == 0x826d)) {
 214                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 215                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 216                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 217         }
 218
 219         /* Asrock RS600 board lists the DVI port as HDMI */
 220         if ((dev->pdev->device == 0x7941) &&
 221             (dev->pdev->subsystem_vendor == 0x1849) &&
 222             (dev->pdev->subsystem_device == 0x7941)) {
 223                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 224                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 225                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 226         }
 227
 228         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 229         if ((dev->pdev->device == 0x7941) &&
 230             (dev->pdev->subsystem_vendor == 0x147b) &&
 231             (dev->pdev->subsystem_device == 0x2412)) {
 232                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 233                         return false;
 234         }
 235
 236         /* Falcon NW laptop lists vga ddc line for LVDS */
 237         if ((dev->pdev->device == 0x5653) &&
 238             (dev->pdev->subsystem_vendor == 0x1462) &&
 239             (dev->pdev->subsystem_device == 0x0291)) {
 240                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 241                         i2c_bus->valid = false;
 242                         *line_mux = 53;
 243                 }
 244         }
 245
 246         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 247         if ((dev->pdev->device == 0x7146) &&
 248             (dev->pdev->subsystem_vendor == 0x17af) &&
 249             (dev->pdev->subsystem_device == 0x2058)) {
 250                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 251                         return false;
 252         }
 253
 254         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 255         if ((dev->pdev->device == 0x7142) &&
 256             (dev->pdev->subsystem_vendor == 0x1458) &&
 257             (dev->pdev->subsystem_device == 0x2134)) {
 258                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 259                         return false;
 260         }
 261
 262
 263         /* Funky macbooks */
 264         if ((dev->pdev->device == 0x71C5) &&
 265             (dev->pdev->subsystem_vendor == 0x106b) &&
 266             (dev->pdev->subsystem_device == 0x0080)) {
 267                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 268                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 269                         return false;
 270                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 271                         *line_mux = 0x90;
 272         }
 273
 274         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 275         if ((dev->pdev->device == 0x9598) &&
 276             (dev->pdev->subsystem_vendor == 0x1043) &&
 277             (dev->pdev->subsystem_device == 0x01da)) {
 278                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 279                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 280                 }
 281         }
 282
 283         /* ASUS HD 3450 board lists the DVI port as HDMI */
 284         if ((dev->pdev->device == 0x95C5) &&
 285             (dev->pdev->subsystem_vendor == 0x1043) &&
 286             (dev->pdev->subsystem_device == 0x01e2)) {
 287                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 288                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 289                 }
 290         }
 291
 292         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 293          * HDMI + VGA reporting as HDMI
 294          */
 295         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 296                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 297                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 298                         *line_mux = 0;
 299                 }
 300         }
 301
 302         /* Acer laptop reports DVI-D as DVI-I */
 303         if ((dev->pdev->device == 0x95c4) &&
 304             (dev->pdev->subsystem_vendor == 0x1025) &&
 305             (dev->pdev->subsystem_device == 0x013c)) {
 306                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 307                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 308                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 309         }
 310
 311         /* XFX Pine Group device rv730 reports no VGA DDC lines
 312          * even though they are wired up to record 0x93
 313          */
 314         if ((dev->pdev->device == 0x9498) &&
 315             (dev->pdev->subsystem_vendor == 0x1682) &&
 316             (dev->pdev->subsystem_device == 0x2452)) {
 317                 struct radeon_device *rdev = dev->dev_private;
 318                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 319         }
 320         return true;
 321 }
 322
 323 const int supported_devices_connector_convert[] = {
 324         DRM_MODE_CONNECTOR_Unknown,
 325         DRM_MODE_CONNECTOR_VGA,
 326         DRM_MODE_CONNECTOR_DVII,
 327         DRM_MODE_CONNECTOR_DVID,
 328         DRM_MODE_CONNECTOR_DVIA,
 329         DRM_MODE_CONNECTOR_SVIDEO,
 330         DRM_MODE_CONNECTOR_Composite,
 331         DRM_MODE_CONNECTOR_LVDS,
 332         DRM_MODE_CONNECTOR_Unknown,
 333         DRM_MODE_CONNECTOR_Unknown,
 334         DRM_MODE_CONNECTOR_HDMIA,
 335         DRM_MODE_CONNECTOR_HDMIB,
 336         DRM_MODE_CONNECTOR_Unknown,
 337         DRM_MODE_CONNECTOR_Unknown,
 338         DRM_MODE_CONNECTOR_9PinDIN,
 339         DRM_MODE_CONNECTOR_DisplayPort
 340 };
 341
 342 const uint16_t supported_devices_connector_object_id_convert[] = {
 343         CONNECTOR_OBJECT_ID_NONE,
 344         CONNECTOR_OBJECT_ID_VGA,
 345         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 346         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 347         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 348         CONNECTOR_OBJECT_ID_COMPOSITE,
 349         CONNECTOR_OBJECT_ID_SVIDEO,
 350         CONNECTOR_OBJECT_ID_LVDS,
 351         CONNECTOR_OBJECT_ID_9PIN_DIN,
 352         CONNECTOR_OBJECT_ID_9PIN_DIN,
 353         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 354         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 355         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 356         CONNECTOR_OBJECT_ID_SVIDEO
 357 };
 358
 359 const int object_connector_convert[] = {
 360         DRM_MODE_CONNECTOR_Unknown,
 361         DRM_MODE_CONNECTOR_DVII,
 362         DRM_MODE_CONNECTOR_DVII,
 363         DRM_MODE_CONNECTOR_DVID,
 364         DRM_MODE_CONNECTOR_DVID,
 365         DRM_MODE_CONNECTOR_VGA,
 366         DRM_MODE_CONNECTOR_Composite,
 367         DRM_MODE_CONNECTOR_SVIDEO,
 368         DRM_MODE_CONNECTOR_Unknown,
 369         DRM_MODE_CONNECTOR_Unknown,
 370         DRM_MODE_CONNECTOR_9PinDIN,
 371         DRM_MODE_CONNECTOR_Unknown,
 372         DRM_MODE_CONNECTOR_HDMIA,
 373         DRM_MODE_CONNECTOR_HDMIB,
 374         DRM_MODE_CONNECTOR_LVDS,
 375         DRM_MODE_CONNECTOR_9PinDIN,
 376         DRM_MODE_CONNECTOR_Unknown,
 377         DRM_MODE_CONNECTOR_Unknown,
 378         DRM_MODE_CONNECTOR_Unknown,
 379         DRM_MODE_CONNECTOR_DisplayPort,
 380         DRM_MODE_CONNECTOR_eDP,
 381         DRM_MODE_CONNECTOR_Unknown
 382 };
 383
 384 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 385 {
 386         struct radeon_device *rdev = dev->dev_private;
 387         struct radeon_mode_info *mode_info = &rdev->mode_info;
 388         struct atom_context *ctx = mode_info->atom_context;
 389         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 390         u16 size, data_offset;
 391         u8 frev, crev;
 392         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 393         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 394         ATOM_OBJECT_HEADER *obj_header;
 395         int i, j, path_size, device_support;
 396         int connector_type;
 397         u16 igp_lane_info, conn_id, connector_object_id;
 398         bool linkb;
 399         struct radeon_i2c_bus_rec ddc_bus;
 400         struct radeon_gpio_rec gpio;
 401         struct radeon_hpd hpd;
 402
 403         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 404                 return false;
 405
 406         if (crev < 2)
 407                 return false;
 408
 409         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 410         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 411             (ctx->bios + data_offset +
 412              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 413         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 414             (ctx->bios + data_offset +
 415              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 416         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 417
 418         path_size = 0;
 419         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 420                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 421                 ATOM_DISPLAY_OBJECT_PATH *path;
 422                 addr += path_size;
 423                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 424                 path_size += le16_to_cpu(path->usSize);
 425                 linkb = false;
 426                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 427                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 428
 429                         con_obj_id =
 430                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 431                             >> OBJECT_ID_SHIFT;
 432                         con_obj_num =
 433                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 434                             >> ENUM_ID_SHIFT;
 435                         con_obj_type =
 436                             (le16_to_cpu(path->usConnObjectId) &
 437                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 438
 439                         /* TODO CV support */
 440                         if (le16_to_cpu(path->usDeviceTag) ==
 441                                 ATOM_DEVICE_CV_SUPPORT)
 442                                 continue;
 443
 444                         /* IGP chips */
 445                         if ((rdev->flags & RADEON_IS_IGP) &&
 446                             (con_obj_id ==
 447                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 448                                 uint16_t igp_offset = 0;
 449                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 450
 451                                 index =
 452                                     GetIndexIntoMasterTable(DATA,
 453                                                             IntegratedSystemInfo);
 454
 455                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 456                                                            &crev, &igp_offset)) {
 457
 458                                         if (crev >= 2) {
 459                                                 igp_obj =
 460                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 461                                                          *) (ctx->bios + igp_offset);
 462
 463                                                 if (igp_obj) {
 464                                                         uint32_t slot_config, ct;
 465
 466                                                         if (con_obj_num == 1)
 467                                                                 slot_config =
 468                                                                         igp_obj->
 469                                                                         ulDDISlot1Config;
 470                                                         else
 471                                                                 slot_config =
 472                                                                         igp_obj->
 473                                                                         ulDDISlot2Config;
 474
 475                                                         ct = (slot_config >> 16) & 0xff;
 476                                                         connector_type =
 477                                                                 object_connector_convert
 478                                                                 [ct];
 479                                                         connector_object_id = ct;
 480                                                         igp_lane_info =
 481                                                                 slot_config & 0xffff;
 482                                                 } else
 483                                                         continue;
 484                                         } else
 485                                                 continue;
 486                                 } else {
 487                                         igp_lane_info = 0;
 488                                         connector_type =
 489                                                 object_connector_convert[con_obj_id];
 490                                         connector_object_id = con_obj_id;
 491                                 }
 492                         } else {
 493                                 igp_lane_info = 0;
 494                                 connector_type =
 495                                     object_connector_convert[con_obj_id];
 496                                 connector_object_id = con_obj_id;
 497                         }
 498
 499                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 500                                 continue;
 501
 502                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 503                              j++) {
 504                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 505
 506                                 enc_obj_id =
 507                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 508                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 509                                 enc_obj_num =
 510                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 511                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 512                                 enc_obj_type =
 513                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 514                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 515
 516                                 /* FIXME: add support for router objects */
 517                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 518                                         if (enc_obj_num == 2)
 519                                                 linkb = true;
 520                                         else
 521                                                 linkb = false;
 522
 523                                         radeon_add_atom_encoder(dev,
 524                                                                 enc_obj_id,
 525                                                                 le16_to_cpu
 526                                                                 (path->
 527                                                                  usDeviceTag));
 528
 529                                 }
 530                         }
 531
 532                         /* look up gpio for ddc, hpd */
 533                         if ((le16_to_cpu(path->usDeviceTag) &
 534                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 535                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 536                                         if (le16_to_cpu(path->usConnObjectId) ==
 537                                             le16_to_cpu(con_obj->asObjects[j].
 538                                                         usObjectID)) {
 539                                                 ATOM_COMMON_RECORD_HEADER
 540                                                     *record =
 541                                                     (ATOM_COMMON_RECORD_HEADER
 542                                                      *)
 543                                                     (ctx->bios + data_offset +
 544                                                      le16_to_cpu(con_obj->
 545                                                                  asObjects[j].
 546                                                                  usRecordOffset));
 547                                                 ATOM_I2C_RECORD *i2c_record;
 548                                                 ATOM_HPD_INT_RECORD *hpd_record;
 549                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 550                                                 hpd.hpd = RADEON_HPD_NONE;
 551
 552                                                 while (record->ucRecordType > 0
 553                                                        && record->
 554                                                        ucRecordType <=
 555                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 556                                                         switch (record->ucRecordType) {
 557                                                         case ATOM_I2C_RECORD_TYPE:
 558                                                                 i2c_record =
 559                                                                     (ATOM_I2C_RECORD *)
 560                                                                         record;
 561                                                                 i2c_config =
 562                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 563                                                                         &i2c_record->sucI2cId;
 564                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 565                                                                                                  i2c_config->
 566                                                                                                  ucAccess);
 567                                                                 break;
 568                                                         case ATOM_HPD_INT_RECORD_TYPE:
 569                                                                 hpd_record =
 570                                                                         (ATOM_HPD_INT_RECORD *)
 571                                                                         record;
 572                                                                 gpio = radeon_lookup_gpio(rdev,
 573                                                                                           hpd_record->ucHPDIntGPIOID);
 574                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 575                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 576                                                                 break;
 577                                                         }
 578                                                         record =
 579                                                             (ATOM_COMMON_RECORD_HEADER
 580                                                              *) ((char *)record
 581                                                                  +
 582                                                                  record->
 583                                                                  ucRecordSize);
 584                                                 }
 585                                                 break;
 586                                         }
 587                                 }
 588                         } else {
 589                                 hpd.hpd = RADEON_HPD_NONE;
 590                                 ddc_bus.valid = false;
 591                         }
 592
 593                         /* needed for aux chan transactions */
 594                         ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
 595
 596                         conn_id = le16_to_cpu(path->usConnObjectId);
 597
 598                         if (!radeon_atom_apply_quirks
 599                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 600                              &ddc_bus, &conn_id, &hpd))
 601                                 continue;
 602
 603                         radeon_add_atom_connector(dev,
 604                                                   conn_id,
 605                                                   le16_to_cpu(path->
 606                                                               usDeviceTag),
 607                                                   connector_type, &ddc_bus,
 608                                                   linkb, igp_lane_info,
 609                                                   connector_object_id,
 610                                                   &hpd);
 611
 612                 }
 613         }
 614
 615         radeon_link_encoder_connector(dev);
 616
 617         return true;
 618 }
 619
 620 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 621                                                  int connector_type,
 622                                                  uint16_t devices)
 623 {
 624         struct radeon_device *rdev = dev->dev_private;
 625
 626         if (rdev->flags & RADEON_IS_IGP) {
 627                 return supported_devices_connector_object_id_convert
 628                         [connector_type];
 629         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 630                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 631                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 632                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 633                 struct atom_context *ctx = mode_info->atom_context;
 634                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 635                 uint16_t size, data_offset;
 636                 uint8_t frev, crev;
 637                 ATOM_XTMDS_INFO *xtmds;
 638
 639                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 640                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 641
 642                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 643                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 644                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 645                                 else
 646                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 647                         } else {
 648                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 649                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 650                                 else
 651                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 652                         }
 653                 } else
 654                         return supported_devices_connector_object_id_convert
 655                                 [connector_type];
 656         } else {
 657                 return supported_devices_connector_object_id_convert
 658                         [connector_type];
 659         }
 660 }
 661
 662 struct bios_connector {
 663         bool valid;
 664         uint16_t line_mux;
 665         uint16_t devices;
 666         int connector_type;
 667         struct radeon_i2c_bus_rec ddc_bus;
 668         struct radeon_hpd hpd;
 669 };
 670
 671 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 672                                                                  drm_device
 673                                                                  *dev)
 674 {
 675         struct radeon_device *rdev = dev->dev_private;
 676         struct radeon_mode_info *mode_info = &rdev->mode_info;
 677         struct atom_context *ctx = mode_info->atom_context;
 678         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 679         uint16_t size, data_offset;
 680         uint8_t frev, crev;
 681         uint16_t device_support;
 682         uint8_t dac;
 683         union atom_supported_devices *supported_devices;
 684         int i, j, max_device;
 685         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 686
 687         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 688                 return false;
 689
 690         supported_devices =
 691             (union atom_supported_devices *)(ctx->bios + data_offset);
 692
 693         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 694
 695         if (frev > 1)
 696                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 697         else
 698                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 699
 700         for (i = 0; i < max_device; i++) {
 701                 ATOM_CONNECTOR_INFO_I2C ci =
 702                     supported_devices->info.asConnInfo[i];
 703
 704                 bios_connectors[i].valid = false;
 705
 706                 if (!(device_support & (1 << i))) {
 707                         continue;
 708                 }
 709
 710                 if (i == ATOM_DEVICE_CV_INDEX) {
 711                         DRM_DEBUG("Skipping Component Video\n");
 712                         continue;
 713                 }
 714
 715                 bios_connectors[i].connector_type =
 716                     supported_devices_connector_convert[ci.sucConnectorInfo.
 717                                                         sbfAccess.
 718                                                         bfConnectorType];
 719
 720                 if (bios_connectors[i].connector_type ==
 721                     DRM_MODE_CONNECTOR_Unknown)
 722                         continue;
 723
 724                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 725
 726                 bios_connectors[i].line_mux =
 727                         ci.sucI2cId.ucAccess;
 728
 729                 /* give tv unique connector ids */
 730                 if (i == ATOM_DEVICE_TV1_INDEX) {
 731                         bios_connectors[i].ddc_bus.valid = false;
 732                         bios_connectors[i].line_mux = 50;
 733                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 734                         bios_connectors[i].ddc_bus.valid = false;
 735                         bios_connectors[i].line_mux = 51;
 736                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 737                         bios_connectors[i].ddc_bus.valid = false;
 738                         bios_connectors[i].line_mux = 52;
 739                 } else
 740                         bios_connectors[i].ddc_bus =
 741                             radeon_lookup_i2c_gpio(rdev,
 742                                                    bios_connectors[i].line_mux);
 743
 744                 if ((crev > 1) && (frev > 1)) {
 745                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 746                         switch (isb) {
 747                         case 0x4:
 748                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 749                                 break;
 750                         case 0xa:
 751                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 752                                 break;
 753                         default:
 754                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 755                                 break;
 756                         }
 757                 } else {
 758                         if (i == ATOM_DEVICE_DFP1_INDEX)
 759                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 760                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 761                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 762                         else
 763                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 764                 }
 765
 766                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 767                  * shared with a DVI port, we'll pick up the DVI connector when we
 768                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 769                  */
 770                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 771                         bios_connectors[i].connector_type =
 772                             DRM_MODE_CONNECTOR_VGA;
 773
 774                 if (!radeon_atom_apply_quirks
 775                     (dev, (1 << i), &bios_connectors[i].connector_type,
 776                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 777                      &bios_connectors[i].hpd))
 778                         continue;
 779
 780                 bios_connectors[i].valid = true;
 781                 bios_connectors[i].devices = (1 << i);
 782
 783                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 784                         radeon_add_atom_encoder(dev,
 785                                                 radeon_get_encoder_id(dev,
 786                                                                       (1 << i),
 787                                                                       dac),
 788                                                 (1 << i));
 789                 else
 790                         radeon_add_legacy_encoder(dev,
 791                                                   radeon_get_encoder_id(dev,
 792                                                                         (1 << i),
 793                                                                         dac),
 794                                                   (1 << i));
 795         }
 796
 797         /* combine shared connectors */
 798         for (i = 0; i < max_device; i++) {
 799                 if (bios_connectors[i].valid) {
 800                         for (j = 0; j < max_device; j++) {
 801                                 if (bios_connectors[j].valid && (i != j)) {
 802                                         if (bios_connectors[i].line_mux ==
 803                                             bios_connectors[j].line_mux) {
 804                                                 /* make sure not to combine LVDS */
 805                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 806                                                         bios_connectors[i].line_mux = 53;
 807                                                         bios_connectors[i].ddc_bus.valid = false;
 808                                                         continue;
 809                                                 }
 810                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 811                                                         bios_connectors[j].line_mux = 53;
 812                                                         bios_connectors[j].ddc_bus.valid = false;
 813                                                         continue;
 814                                                 }
 815                                                 /* combine analog and digital for DVI-I */
 816                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 817                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 818                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 819                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 820                                                         bios_connectors[i].devices |=
 821                                                                 bios_connectors[j].devices;
 822                                                         bios_connectors[i].connector_type =
 823                                                                 DRM_MODE_CONNECTOR_DVII;
 824                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 825                                                                 bios_connectors[i].hpd =
 826                                                                         bios_connectors[j].hpd;
 827                                                         bios_connectors[j].valid = false;
 828                                                 }
 829                                         }
 830                                 }
 831                         }
 832                 }
 833         }
 834
 835         /* add the connectors */
 836         for (i = 0; i < max_device; i++) {
 837                 if (bios_connectors[i].valid) {
 838                         uint16_t connector_object_id =
 839                                 atombios_get_connector_object_id(dev,
 840                                                       bios_connectors[i].connector_type,
 841                                                       bios_connectors[i].devices);
 842                         radeon_add_atom_connector(dev,
 843                                                   bios_connectors[i].line_mux,
 844                                                   bios_connectors[i].devices,
 845                                                   bios_connectors[i].
 846                                                   connector_type,
 847                                                   &bios_connectors[i].ddc_bus,
 848                                                   false, 0,
 849                                                   connector_object_id,
 850                                                   &bios_connectors[i].hpd);
 851                 }
 852         }
 853
 854         radeon_link_encoder_connector(dev);
 855
 856         return true;
 857 }
 858
 859 union firmware_info {
 860         ATOM_FIRMWARE_INFO info;
 861         ATOM_FIRMWARE_INFO_V1_2 info_12;
 862         ATOM_FIRMWARE_INFO_V1_3 info_13;
 863         ATOM_FIRMWARE_INFO_V1_4 info_14;
 864         ATOM_FIRMWARE_INFO_V2_1 info_21;
 865 };
 866
 867 bool radeon_atom_get_clock_info(struct drm_device *dev)
 868 {
 869         struct radeon_device *rdev = dev->dev_private;
 870         struct radeon_mode_info *mode_info = &rdev->mode_info;
 871         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 872         union firmware_info *firmware_info;
 873         uint8_t frev, crev;
 874         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 875         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 876         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 877         struct radeon_pll *spll = &rdev->clock.spll;
 878         struct radeon_pll *mpll = &rdev->clock.mpll;
 879         uint16_t data_offset;
 880
 881         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
 882                                    &frev, &crev, &data_offset)) {
 883                 firmware_info =
 884                         (union firmware_info *)(mode_info->atom_context->bios +
 885                                                 data_offset);
 886                 /* pixel clocks */
 887                 p1pll->reference_freq =
 888                     le16_to_cpu(firmware_info->info.usReferenceClock);
 889                 p1pll->reference_div = 0;
 890
 891                 if (crev < 2)
 892                         p1pll->pll_out_min =
 893                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 894                 else
 895                         p1pll->pll_out_min =
 896                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 897                 p1pll->pll_out_max =
 898                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 899
 900                 if (crev >= 4) {
 901                         p1pll->lcd_pll_out_min =
 902                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 903                         if (p1pll->lcd_pll_out_min == 0)
 904                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 905                         p1pll->lcd_pll_out_max =
 906                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 907                         if (p1pll->lcd_pll_out_max == 0)
 908                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 909                 } else {
 910                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 911                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 912                 }
 913
 914                 if (p1pll->pll_out_min == 0) {
 915                         if (ASIC_IS_AVIVO(rdev))
 916                                 p1pll->pll_out_min = 64800;
 917                         else
 918                                 p1pll->pll_out_min = 20000;
 919                 } else if (p1pll->pll_out_min > 64800) {
 920                         /* Limiting the pll output range is a good thing generally as
 921                          * it limits the number of possible pll combinations for a given
 922                          * frequency presumably to the ones that work best on each card.
 923                          * However, certain duallink DVI monitors seem to like
 924                          * pll combinations that would be limited by this at least on
 925                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 926                          * family.
 927                          */
 928                         if (!radeon_new_pll)
 929                                 p1pll->pll_out_min = 64800;
 930                 }
 931
 932                 p1pll->pll_in_min =
 933                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 934                 p1pll->pll_in_max =
 935                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 936
 937                 *p2pll = *p1pll;
 938
 939                 /* system clock */
 940                 spll->reference_freq =
 941                     le16_to_cpu(firmware_info->info.usReferenceClock);
 942                 spll->reference_div = 0;
 943
 944                 spll->pll_out_min =
 945                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 946                 spll->pll_out_max =
 947                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 948
 949                 /* ??? */
 950                 if (spll->pll_out_min == 0) {
 951                         if (ASIC_IS_AVIVO(rdev))
 952                                 spll->pll_out_min = 64800;
 953                         else
 954                                 spll->pll_out_min = 20000;
 955                 }
 956
 957                 spll->pll_in_min =
 958                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 959                 spll->pll_in_max =
 960                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 961
 962                 /* memory clock */
 963                 mpll->reference_freq =
 964                     le16_to_cpu(firmware_info->info.usReferenceClock);
 965                 mpll->reference_div = 0;
 966
 967                 mpll->pll_out_min =
 968                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 969                 mpll->pll_out_max =
 970                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 971
 972                 /* ??? */
 973                 if (mpll->pll_out_min == 0) {
 974                         if (ASIC_IS_AVIVO(rdev))
 975                                 mpll->pll_out_min = 64800;
 976                         else
 977                                 mpll->pll_out_min = 20000;
 978                 }
 979
 980                 mpll->pll_in_min =
 981                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 982                 mpll->pll_in_max =
 983                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 984
 985                 rdev->clock.default_sclk =
 986                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 987                 rdev->clock.default_mclk =
 988                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 989
 990                 if (ASIC_IS_DCE4(rdev)) {
 991                         rdev->clock.default_dispclk =
 992                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 993                         if (rdev->clock.default_dispclk == 0)
 994                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
 995                         rdev->clock.dp_extclk =
 996                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 997                 }
 998                 *dcpll = *p1pll;
 999
1000                 return true;
1001         }
1002
1003         return false;
1004 }
1005
1006 union igp_info {
1007         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1008         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1009 };
1010
1011 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1012 {
1013         struct radeon_mode_info *mode_info = &rdev->mode_info;
1014         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1015         union igp_info *igp_info;
1016         u8 frev, crev;
1017         u16 data_offset;
1018
1019         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1020                                    &frev, &crev, &data_offset)) {
1021                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1022                                       data_offset);
1023                 switch (crev) {
1024                 case 1:
1025                         if (igp_info->info.ucMemoryType & 0xf0)
1026                                 return true;
1027                         break;
1028                 case 2:
1029                         if (igp_info->info_2.ucMemoryType & 0x0f)
1030                                 return true;
1031                         break;
1032                 default:
1033                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1034                         break;
1035                 }
1036         }
1037         return false;
1038 }
1039
1040 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1041                                    struct radeon_encoder_int_tmds *tmds)
1042 {
1043         struct drm_device *dev = encoder->base.dev;
1044         struct radeon_device *rdev = dev->dev_private;
1045         struct radeon_mode_info *mode_info = &rdev->mode_info;
1046         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1047         uint16_t data_offset;
1048         struct _ATOM_TMDS_INFO *tmds_info;
1049         uint8_t frev, crev;
1050         uint16_t maxfreq;
1051         int i;
1052
1053         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1054                                    &frev, &crev, &data_offset)) {
1055                 tmds_info =
1056                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1057                                                    data_offset);
1058
1059                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1060                 for (i = 0; i < 4; i++) {
1061                         tmds->tmds_pll[i].freq =
1062                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1063                         tmds->tmds_pll[i].value =
1064                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1065                         tmds->tmds_pll[i].value |=
1066                             (tmds_info->asMiscInfo[i].
1067                              ucPLL_VCO_Gain & 0x3f) << 6;
1068                         tmds->tmds_pll[i].value |=
1069                             (tmds_info->asMiscInfo[i].
1070                              ucPLL_DutyCycle & 0xf) << 12;
1071                         tmds->tmds_pll[i].value |=
1072                             (tmds_info->asMiscInfo[i].
1073                              ucPLL_VoltageSwing & 0xf) << 16;
1074
1075                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1076                                   tmds->tmds_pll[i].freq,
1077                                   tmds->tmds_pll[i].value);
1078
1079                         if (maxfreq == tmds->tmds_pll[i].freq) {
1080                                 tmds->tmds_pll[i].freq = 0xffffffff;
1081                                 break;
1082                         }
1083                 }
1084                 return true;
1085         }
1086         return false;
1087 }
1088
1089 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1090                                                           radeon_encoder
1091                                                           *encoder,
1092                                                           int id)
1093 {
1094         struct drm_device *dev = encoder->base.dev;
1095         struct radeon_device *rdev = dev->dev_private;
1096         struct radeon_mode_info *mode_info = &rdev->mode_info;
1097         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1098         uint16_t data_offset;
1099         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1100         uint8_t frev, crev;
1101         struct radeon_atom_ss *ss = NULL;
1102         int i;
1103
1104         if (id > ATOM_MAX_SS_ENTRY)
1105                 return NULL;
1106
1107         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1108                                    &frev, &crev, &data_offset)) {
1109                 ss_info =
1110                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1111
1112                 ss =
1113                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1114
1115                 if (!ss)
1116                         return NULL;
1117
1118                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1119                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1120                                 ss->percentage =
1121                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1122                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1123                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1124                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1125                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1126                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1127                                 break;
1128                         }
1129                 }
1130         }
1131         return ss;
1132 }
1133
1134 union lvds_info {
1135         struct _ATOM_LVDS_INFO info;
1136         struct _ATOM_LVDS_INFO_V12 info_12;
1137 };
1138
1139 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1140                                                               radeon_encoder
1141                                                               *encoder)
1142 {
1143         struct drm_device *dev = encoder->base.dev;
1144         struct radeon_device *rdev = dev->dev_private;
1145         struct radeon_mode_info *mode_info = &rdev->mode_info;
1146         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1147         uint16_t data_offset, misc;
1148         union lvds_info *lvds_info;
1149         uint8_t frev, crev;
1150         struct radeon_encoder_atom_dig *lvds = NULL;
1151
1152         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1153                                    &frev, &crev, &data_offset)) {
1154                 lvds_info =
1155                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1156                 lvds =
1157                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1158
1159                 if (!lvds)
1160                         return NULL;
1161
1162                 lvds->native_mode.clock =
1163                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1164                 lvds->native_mode.hdisplay =
1165                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1166                 lvds->native_mode.vdisplay =
1167                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1168                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1169                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1170                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1171                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1172                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1173                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1174                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1175                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1176                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1177                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1178                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1179                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1180                 lvds->panel_pwr_delay =
1181                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1182                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1183
1184                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1185                 if (misc & ATOM_VSYNC_POLARITY)
1186                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1187                 if (misc & ATOM_HSYNC_POLARITY)
1188                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1189                 if (misc & ATOM_COMPOSITESYNC)
1190                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1191                 if (misc & ATOM_INTERLACE)
1192                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1193                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1194                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1195
1196                 /* set crtc values */
1197                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1198
1199                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1200
1201                 if (ASIC_IS_AVIVO(rdev)) {
1202                         if (radeon_new_pll == 0)
1203                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1204                         else
1205                                 lvds->pll_algo = PLL_ALGO_NEW;
1206                 } else {
1207                         if (radeon_new_pll == 1)
1208                                 lvds->pll_algo = PLL_ALGO_NEW;
1209                         else
1210                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1211                 }
1212
1213                 encoder->native_mode = lvds->native_mode;
1214         }
1215         return lvds;
1216 }
1217
1218 struct radeon_encoder_primary_dac *
1219 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1220 {
1221         struct drm_device *dev = encoder->base.dev;
1222         struct radeon_device *rdev = dev->dev_private;
1223         struct radeon_mode_info *mode_info = &rdev->mode_info;
1224         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1225         uint16_t data_offset;
1226         struct _COMPASSIONATE_DATA *dac_info;
1227         uint8_t frev, crev;
1228         uint8_t bg, dac;
1229         struct radeon_encoder_primary_dac *p_dac = NULL;
1230
1231         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1232                                    &frev, &crev, &data_offset)) {
1233                 dac_info = (struct _COMPASSIONATE_DATA *)
1234                         (mode_info->atom_context->bios + data_offset);
1235
1236                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1237
1238                 if (!p_dac)
1239                         return NULL;
1240
1241                 bg = dac_info->ucDAC1_BG_Adjustment;
1242                 dac = dac_info->ucDAC1_DAC_Adjustment;
1243                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1244
1245         }
1246         return p_dac;
1247 }
1248
1249 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1250                                 struct drm_display_mode *mode)
1251 {
1252         struct radeon_mode_info *mode_info = &rdev->mode_info;
1253         ATOM_ANALOG_TV_INFO *tv_info;
1254         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1255         ATOM_DTD_FORMAT *dtd_timings;
1256         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1257         u8 frev, crev;
1258         u16 data_offset, misc;
1259
1260         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1261                                     &frev, &crev, &data_offset))
1262                 return false;
1263
1264         switch (crev) {
1265         case 1:
1266                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1267                 if (index >= MAX_SUPPORTED_TV_TIMING)
1268                         return false;
1269
1270                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1271                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1272                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1273                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1274                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1275
1276                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1277                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1278                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1279                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1280                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1281
1282                 mode->flags = 0;
1283                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1284                 if (misc & ATOM_VSYNC_POLARITY)
1285                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1286                 if (misc & ATOM_HSYNC_POLARITY)
1287                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1288                 if (misc & ATOM_COMPOSITESYNC)
1289                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1290                 if (misc & ATOM_INTERLACE)
1291                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1292                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1293                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1294
1295                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1296
1297                 if (index == 1) {
1298                         /* PAL timings appear to have wrong values for totals */
1299                         mode->crtc_htotal -= 1;
1300                         mode->crtc_vtotal -= 1;
1301                 }
1302                 break;
1303         case 2:
1304                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1305                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1306                         return false;
1307
1308                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1309                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1310                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1311                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1312                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1313                         le16_to_cpu(dtd_timings->usHSyncOffset);
1314                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1315                         le16_to_cpu(dtd_timings->usHSyncWidth);
1316
1317                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1318                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1319                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1320                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1321                         le16_to_cpu(dtd_timings->usVSyncOffset);
1322                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1323                         le16_to_cpu(dtd_timings->usVSyncWidth);
1324
1325                 mode->flags = 0;
1326                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1327                 if (misc & ATOM_VSYNC_POLARITY)
1328                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1329                 if (misc & ATOM_HSYNC_POLARITY)
1330                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1331                 if (misc & ATOM_COMPOSITESYNC)
1332                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1333                 if (misc & ATOM_INTERLACE)
1334                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1335                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1336                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1337
1338                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1339                 break;
1340         }
1341         return true;
1342 }
1343
1344 enum radeon_tv_std
1345 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1346 {
1347         struct radeon_mode_info *mode_info = &rdev->mode_info;
1348         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1349         uint16_t data_offset;
1350         uint8_t frev, crev;
1351         struct _ATOM_ANALOG_TV_INFO *tv_info;
1352         enum radeon_tv_std tv_std = TV_STD_NTSC;
1353
1354         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1355                                    &frev, &crev, &data_offset)) {
1356
1357                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1358                         (mode_info->atom_context->bios + data_offset);
1359
1360                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1361                 case ATOM_TV_NTSC:
1362                         tv_std = TV_STD_NTSC;
1363                         DRM_INFO("Default TV standard: NTSC\n");
1364                         break;
1365                 case ATOM_TV_NTSCJ:
1366                         tv_std = TV_STD_NTSC_J;
1367                         DRM_INFO("Default TV standard: NTSC-J\n");
1368                         break;
1369                 case ATOM_TV_PAL:
1370                         tv_std = TV_STD_PAL;
1371                         DRM_INFO("Default TV standard: PAL\n");
1372                         break;
1373                 case ATOM_TV_PALM:
1374                         tv_std = TV_STD_PAL_M;
1375                         DRM_INFO("Default TV standard: PAL-M\n");
1376                         break;
1377                 case ATOM_TV_PALN:
1378                         tv_std = TV_STD_PAL_N;
1379                         DRM_INFO("Default TV standard: PAL-N\n");
1380                         break;
1381                 case ATOM_TV_PALCN:
1382                         tv_std = TV_STD_PAL_CN;
1383                         DRM_INFO("Default TV standard: PAL-CN\n");
1384                         break;
1385                 case ATOM_TV_PAL60:
1386                         tv_std = TV_STD_PAL_60;
1387                         DRM_INFO("Default TV standard: PAL-60\n");
1388                         break;
1389                 case ATOM_TV_SECAM:
1390                         tv_std = TV_STD_SECAM;
1391                         DRM_INFO("Default TV standard: SECAM\n");
1392                         break;
1393                 default:
1394                         tv_std = TV_STD_NTSC;
1395                         DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1396                         break;
1397                 }
1398         }
1399         return tv_std;
1400 }
1401
1402 struct radeon_encoder_tv_dac *
1403 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1404 {
1405         struct drm_device *dev = encoder->base.dev;
1406         struct radeon_device *rdev = dev->dev_private;
1407         struct radeon_mode_info *mode_info = &rdev->mode_info;
1408         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1409         uint16_t data_offset;
1410         struct _COMPASSIONATE_DATA *dac_info;
1411         uint8_t frev, crev;
1412         uint8_t bg, dac;
1413         struct radeon_encoder_tv_dac *tv_dac = NULL;
1414
1415         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1416                                    &frev, &crev, &data_offset)) {
1417
1418                 dac_info = (struct _COMPASSIONATE_DATA *)
1419                         (mode_info->atom_context->bios + data_offset);
1420
1421                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1422
1423                 if (!tv_dac)
1424                         return NULL;
1425
1426                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1427                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1428                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1429
1430                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1431                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1432                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1433
1434                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1435                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1436                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1437
1438                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1439         }
1440         return tv_dac;
1441 }
1442
1443 static const char *thermal_controller_names[] = {
1444         "NONE",
1445         "LM63",
1446         "ADM1032",
1447         "ADM1030",
1448         "MUA6649",
1449         "LM64",
1450         "F75375",
1451         "ASC7512",
1452 };
1453
1454 static const char *pp_lib_thermal_controller_names[] = {
1455         "NONE",
1456         "LM63",
1457         "ADM1032",
1458         "ADM1030",
1459         "MUA6649",
1460         "LM64",
1461         "F75375",
1462         "RV6xx",
1463         "RV770",
1464         "ADT7473",
1465 };
1466
1467 union power_info {
1468         struct _ATOM_POWERPLAY_INFO info;
1469         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1470         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1471         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1472 };
1473
1474 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1475 {
1476         struct radeon_mode_info *mode_info = &rdev->mode_info;
1477         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1478         u16 data_offset;
1479         u8 frev, crev;
1480         u32 misc, misc2 = 0, sclk, mclk;
1481         union power_info *power_info;
1482         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1483         struct _ATOM_PPLIB_STATE *power_state;
1484         int num_modes = 0, i, j;
1485         int state_index = 0, mode_index = 0;
1486         struct radeon_i2c_bus_rec i2c_bus;
1487
1488         rdev->pm.default_power_state = NULL;
1489
1490         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1491                                    &frev, &crev, &data_offset)) {
1492                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1493                 if (frev < 4) {
1494                         /* add the i2c bus for thermal/fan chip */
1495                         if (power_info->info.ucOverdriveThermalController > 0) {
1496                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1497                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1498                                          power_info->info.ucOverdriveControllerAddress >> 1);
1499                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1500                                 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1501                         }
1502                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1503                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1504                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1505                         for (i = 0; i < num_modes; i++) {
1506                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1507                                 switch (frev) {
1508                                 case 1:
1509                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1510                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1511                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1512                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1513                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1514                                         /* skip invalid modes */
1515                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1516                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1517                                                 continue;
1518                                         /* skip overclock modes for now */
1519                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1520                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1521                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1522                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1523                                                 continue;
1524                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1525                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1526                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1527                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1528                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1529                                                         VOLTAGE_GPIO;
1530                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1531                                                         radeon_lookup_gpio(rdev,
1532                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1533                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1534                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1535                                                                 true;
1536                                                 else
1537                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1538                                                                 false;
1539                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1540                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1541                                                         VOLTAGE_VDDC;
1542                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1543                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1544                                         }
1545                                         /* order matters! */
1546                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1547                                                 rdev->pm.power_state[state_index].type =
1548                                                         POWER_STATE_TYPE_POWERSAVE;
1549                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1550                                                 rdev->pm.power_state[state_index].type =
1551                                                         POWER_STATE_TYPE_BATTERY;
1552                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1553                                                 rdev->pm.power_state[state_index].type =
1554                                                         POWER_STATE_TYPE_BATTERY;
1555                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1556                                                 rdev->pm.power_state[state_index].type =
1557                                                         POWER_STATE_TYPE_BALANCED;
1558                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1559                                                 rdev->pm.power_state[state_index].type =
1560                                                         POWER_STATE_TYPE_PERFORMANCE;
1561                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1562                                                 rdev->pm.power_state[state_index].type =
1563                                                         POWER_STATE_TYPE_DEFAULT;
1564                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1565                                                 rdev->pm.power_state[state_index].default_clock_mode =
1566                                                         &rdev->pm.power_state[state_index].clock_info[0];
1567                                         }
1568                                         state_index++;
1569                                         break;
1570                                 case 2:
1571                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1572                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1573                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1574                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1575                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1576                                         /* skip invalid modes */
1577                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1578                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1579                                                 continue;
1580                                         /* skip overclock modes for now */
1581                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1582                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1583                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1584                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1585                                                 continue;
1586                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1587                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1588                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1589                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1590                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1591                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1592                                                         VOLTAGE_GPIO;
1593                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1594                                                         radeon_lookup_gpio(rdev,
1595                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1596                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1597                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1598                                                                 true;
1599                                                 else
1600                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1601                                                                 false;
1602                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1603                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1604                                                         VOLTAGE_VDDC;
1605                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1606                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1607                                         }
1608                                         /* order matters! */
1609                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1610                                                 rdev->pm.power_state[state_index].type =
1611                                                         POWER_STATE_TYPE_POWERSAVE;
1612                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1613                                                 rdev->pm.power_state[state_index].type =
1614                                                         POWER_STATE_TYPE_BATTERY;
1615                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1616                                                 rdev->pm.power_state[state_index].type =
1617                                                         POWER_STATE_TYPE_BATTERY;
1618                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1619                                                 rdev->pm.power_state[state_index].type =
1620                                                         POWER_STATE_TYPE_BALANCED;
1621                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1622                                                 rdev->pm.power_state[state_index].type =
1623                                                         POWER_STATE_TYPE_PERFORMANCE;
1624                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1625                                                 rdev->pm.power_state[state_index].type =
1626                                                         POWER_STATE_TYPE_BALANCED;
1627                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1628                                                 rdev->pm.power_state[state_index].type =
1629                                                         POWER_STATE_TYPE_DEFAULT;
1630                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1631                                                 rdev->pm.power_state[state_index].default_clock_mode =
1632                                                         &rdev->pm.power_state[state_index].clock_info[0];
1633                                         }
1634                                         state_index++;
1635                                         break;
1636                                 case 3:
1637                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1638                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1639                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1640                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1641                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1642                                         /* skip invalid modes */
1643                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1644                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1645                                                 continue;
1646                                         /* skip overclock modes for now */
1647                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1648                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1649                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1650                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1651                                                 continue;
1652                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1653                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1654                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1655                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1656                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1657                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1658                                                         VOLTAGE_GPIO;
1659                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1660                                                         radeon_lookup_gpio(rdev,
1661                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1662                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1663                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1664                                                                 true;
1665                                                 else
1666                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1667                                                                 false;
1668                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1669                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1670                                                         VOLTAGE_VDDC;
1671                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1672                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1673                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1674                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1675                                                                 true;
1676                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1677                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1678                                                 }
1679                                         }
1680                                         /* order matters! */
1681                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1682                                                 rdev->pm.power_state[state_index].type =
1683                                                         POWER_STATE_TYPE_POWERSAVE;
1684                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1685                                                 rdev->pm.power_state[state_index].type =
1686                                                         POWER_STATE_TYPE_BATTERY;
1687                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1688                                                 rdev->pm.power_state[state_index].type =
1689                                                         POWER_STATE_TYPE_BATTERY;
1690                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1691                                                 rdev->pm.power_state[state_index].type =
1692                                                         POWER_STATE_TYPE_BALANCED;
1693                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1694                                                 rdev->pm.power_state[state_index].type =
1695                                                         POWER_STATE_TYPE_PERFORMANCE;
1696                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1697                                                 rdev->pm.power_state[state_index].type =
1698                                                         POWER_STATE_TYPE_BALANCED;
1699                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1700                                                 rdev->pm.power_state[state_index].type =
1701                                                         POWER_STATE_TYPE_DEFAULT;
1702                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1703                                                 rdev->pm.power_state[state_index].default_clock_mode =
1704                                                         &rdev->pm.power_state[state_index].clock_info[0];
1705                                         }
1706                                         state_index++;
1707                                         break;
1708                                 }
1709                         }
1710                 } else if (frev == 4) {
1711                         /* add the i2c bus for thermal/fan chip */
1712                         /* no support for internal controller yet */
1713                         if (power_info->info_4.sThermalController.ucType > 0) {
1714                                 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1715                                     (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1716                                         DRM_INFO("Internal thermal controller %s fan control\n",
1717                                                  (power_info->info_4.sThermalController.ucFanParameters &
1718                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1719                                 } else {
1720                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1721                                                  pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1722                                                  power_info->info_4.sThermalController.ucI2cAddress >> 1,
1723                                                  (power_info->info_4.sThermalController.ucFanParameters &
1724                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1725                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1726                                         rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1727                                 }
1728                         }
1729                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1730                                 mode_index = 0;
1731                                 power_state = (struct _ATOM_PPLIB_STATE *)
1732                                         (mode_info->atom_context->bios +
1733                                          data_offset +
1734                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1735                                          i * power_info->info_4.ucStateEntrySize);
1736                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1737                                         (mode_info->atom_context->bios +
1738                                          data_offset +
1739                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1740                                          (power_state->ucNonClockStateIndex *
1741                                           power_info->info_4.ucNonClockSize));
1742                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1743                                         if (rdev->flags & RADEON_IS_IGP) {
1744                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1745                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1746                                                         (mode_info->atom_context->bios +
1747                                                          data_offset +
1748                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1749                                                          (power_state->ucClockStateIndices[j] *
1750                                                           power_info->info_4.ucClockInfoSize));
1751                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1752                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1753                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1754                                                 /* skip invalid modes */
1755                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1756                                                         continue;
1757                                                 /* skip overclock modes for now */
1758                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1759                                                     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1760                                                         continue;
1761                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1762                                                         VOLTAGE_SW;
1763                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1764                                                         clock_info->usVDDC;
1765                                                 mode_index++;
1766                                         } else {
1767                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1768                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1769                                                         (mode_info->atom_context->bios +
1770                                                          data_offset +
1771                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1772                                                          (power_state->ucClockStateIndices[j] *
1773                                                           power_info->info_4.ucClockInfoSize));
1774                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1775                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1776                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1777                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1778                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1779                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1780                                                 /* skip invalid modes */
1781                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1782                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1783                                                         continue;
1784                                                 /* skip overclock modes for now */
1785                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1786                                                      rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1787                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1788                                                      rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1789                                                         continue;
1790                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1791                                                         VOLTAGE_SW;
1792                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1793                                                         clock_info->usVDDC;
1794                                                 mode_index++;
1795                                         }
1796                                 }
1797                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1798                                 if (mode_index) {
1799                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1800                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1801                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1802                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1803                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1804                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1805                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1806                                                 rdev->pm.power_state[state_index].type =
1807                                                         POWER_STATE_TYPE_BATTERY;
1808                                                 break;
1809                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1810                                                 rdev->pm.power_state[state_index].type =
1811                                                         POWER_STATE_TYPE_BALANCED;
1812                                                 break;
1813                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1814                                                 rdev->pm.power_state[state_index].type =
1815                                                         POWER_STATE_TYPE_PERFORMANCE;
1816                                                 break;
1817                                         }
1818                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1819                                                 rdev->pm.power_state[state_index].type =
1820                                                         POWER_STATE_TYPE_DEFAULT;
1821                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1822                                                 rdev->pm.power_state[state_index].default_clock_mode =
1823                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1824                                         }
1825                                         state_index++;
1826                                 }
1827                         }
1828                 }
1829         } else {
1830                 /* XXX figure out some good default low power mode for cards w/out power tables */
1831         }
1832
1833         if (rdev->pm.default_power_state == NULL) {
1834                 /* add the default mode */
1835                 rdev->pm.power_state[state_index].type =
1836                         POWER_STATE_TYPE_DEFAULT;
1837                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1838                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1839                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1840                 rdev->pm.power_state[state_index].default_clock_mode =
1841                         &rdev->pm.power_state[state_index].clock_info[0];
1842                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1843                 if (rdev->asic->get_pcie_lanes)
1844                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1845                 else
1846                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1847                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1848                 state_index++;
1849         }
1850         rdev->pm.num_power_states = state_index;
1851
1852         rdev->pm.current_power_state = rdev->pm.default_power_state;
1853         rdev->pm.current_clock_mode =
1854                 rdev->pm.default_power_state->default_clock_mode;
1855 }
1856
1857 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1858 {
1859         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1860         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1861
1862         args.ucEnable = enable;
1863
1864         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1865 }
1866
1867 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1868 {
1869         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1870         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1871
1872         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1873         return args.ulReturnEngineClock;
1874 }
1875
1876 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1877 {
1878         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1879         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1880
1881         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1882         return args.ulReturnMemoryClock;
1883 }
1884
1885 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1886                                   uint32_t eng_clock)
1887 {
1888         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1889         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1890
1891         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1892
1893         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1894 }
1895
1896 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1897                                   uint32_t mem_clock)
1898 {
1899         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1900         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1901
1902         if (rdev->flags & RADEON_IS_IGP)
1903                 return;
1904
1905         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1906
1907         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1908 }
1909
1910 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1911 {
1912         struct radeon_device *rdev = dev->dev_private;
1913         uint32_t bios_2_scratch, bios_6_scratch;
1914
1915         if (rdev->family >= CHIP_R600) {
1916                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1917                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1918         } else {
1919                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1920                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1921         }
1922
1923         /* let the bios control the backlight */
1924         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1925
1926         /* tell the bios not to handle mode switching */
1927         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1928
1929         if (rdev->family >= CHIP_R600) {
1930                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1931                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1932         } else {
1933                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1934                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1935         }
1936
1937 }
1938
1939 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1940 {
1941         uint32_t scratch_reg;
1942         int i;
1943
1944         if (rdev->family >= CHIP_R600)
1945                 scratch_reg = R600_BIOS_0_SCRATCH;
1946         else
1947                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1948
1949         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1950                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1951 }
1952
1953 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1954 {
1955         uint32_t scratch_reg;
1956         int i;
1957
1958         if (rdev->family >= CHIP_R600)
1959                 scratch_reg = R600_BIOS_0_SCRATCH;
1960         else
1961                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1962
1963         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1964                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1965 }
1966
1967 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1968 {
1969         struct drm_device *dev = encoder->dev;
1970         struct radeon_device *rdev = dev->dev_private;
1971         uint32_t bios_6_scratch;
1972
1973         if (rdev->family >= CHIP_R600)
1974                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1975         else
1976                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1977
1978         if (lock)
1979                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1980         else
1981                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1982
1983         if (rdev->family >= CHIP_R600)
1984                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1985         else
1986                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1987 }
1988
1989 /* at some point we may want to break this out into individual functions */
1990 void
1991 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1992                                        struct drm_encoder *encoder,
1993                                        bool connected)
1994 {
1995         struct drm_device *dev = connector->dev;
1996         struct radeon_device *rdev = dev->dev_private;
1997         struct radeon_connector *radeon_connector =
1998             to_radeon_connector(connector);
1999         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2000         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2001
2002         if (rdev->family >= CHIP_R600) {
2003                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2004                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2005                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2006         } else {
2007                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2008                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2009                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2010         }
2011
2012         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2013             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2014                 if (connected) {
2015                         DRM_DEBUG("TV1 connected\n");
2016                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2017                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2018                 } else {
2019                         DRM_DEBUG("TV1 disconnected\n");
2020                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2021                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2022                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2023                 }
2024         }
2025         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2026             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2027                 if (connected) {
2028                         DRM_DEBUG("CV connected\n");
2029                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2030                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2031                 } else {
2032                         DRM_DEBUG("CV disconnected\n");
2033                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2034                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2035                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2036                 }
2037         }
2038         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2039             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2040                 if (connected) {
2041                         DRM_DEBUG("LCD1 connected\n");
2042                         bios_0_scratch |= ATOM_S0_LCD1;
2043                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2044                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2045                 } else {
2046                         DRM_DEBUG("LCD1 disconnected\n");
2047                         bios_0_scratch &= ~ATOM_S0_LCD1;
2048                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2049                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2050                 }
2051         }
2052         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2053             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2054                 if (connected) {
2055                         DRM_DEBUG("CRT1 connected\n");
2056                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2057                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2058                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2059                 } else {
2060                         DRM_DEBUG("CRT1 disconnected\n");
2061                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2062                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2063                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2064                 }
2065         }
2066         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2067             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2068                 if (connected) {
2069                         DRM_DEBUG("CRT2 connected\n");
2070                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2071                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2072                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2073                 } else {
2074                         DRM_DEBUG("CRT2 disconnected\n");
2075                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2076                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2077                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2078                 }
2079         }
2080         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2081             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2082                 if (connected) {
2083                         DRM_DEBUG("DFP1 connected\n");
2084                         bios_0_scratch |= ATOM_S0_DFP1;
2085                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2086                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2087                 } else {
2088                         DRM_DEBUG("DFP1 disconnected\n");
2089                         bios_0_scratch &= ~ATOM_S0_DFP1;
2090                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2091                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2092                 }
2093         }
2094         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2095             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2096                 if (connected) {
2097                         DRM_DEBUG("DFP2 connected\n");
2098                         bios_0_scratch |= ATOM_S0_DFP2;
2099                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2100                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2101                 } else {
2102                         DRM_DEBUG("DFP2 disconnected\n");
2103                         bios_0_scratch &= ~ATOM_S0_DFP2;
2104                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2105                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2106                 }
2107         }
2108         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2109             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2110                 if (connected) {
2111                         DRM_DEBUG("DFP3 connected\n");
2112                         bios_0_scratch |= ATOM_S0_DFP3;
2113                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2114                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2115                 } else {
2116                         DRM_DEBUG("DFP3 disconnected\n");
2117                         bios_0_scratch &= ~ATOM_S0_DFP3;
2118                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2119                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2120                 }
2121         }
2122         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2123             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2124                 if (connected) {
2125                         DRM_DEBUG("DFP4 connected\n");
2126                         bios_0_scratch |= ATOM_S0_DFP4;
2127                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2128                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2129                 } else {
2130                         DRM_DEBUG("DFP4 disconnected\n");
2131                         bios_0_scratch &= ~ATOM_S0_DFP4;
2132                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2133                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2134                 }
2135         }
2136         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2137             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2138                 if (connected) {
2139                         DRM_DEBUG("DFP5 connected\n");
2140                         bios_0_scratch |= ATOM_S0_DFP5;
2141                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2142                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2143                 } else {
2144                         DRM_DEBUG("DFP5 disconnected\n");
2145                         bios_0_scratch &= ~ATOM_S0_DFP5;
2146                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2147                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2148                 }
2149         }
2150
2151         if (rdev->family >= CHIP_R600) {
2152                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2153                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2154                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2155         } else {
2156                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2157                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2158                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2159         }
2160 }
2161
2162 void
2163 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2164 {
2165         struct drm_device *dev = encoder->dev;
2166         struct radeon_device *rdev = dev->dev_private;
2167         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2168         uint32_t bios_3_scratch;
2169
2170         if (rdev->family >= CHIP_R600)
2171                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2172         else
2173                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2174
2175         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2176                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2177                 bios_3_scratch |= (crtc << 18);
2178         }
2179         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2180                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2181                 bios_3_scratch |= (crtc << 24);
2182         }
2183         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2184                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2185                 bios_3_scratch |= (crtc << 16);
2186         }
2187         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2188                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2189                 bios_3_scratch |= (crtc << 20);
2190         }
2191         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2192                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2193                 bios_3_scratch |= (crtc << 17);
2194         }
2195         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2196                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2197                 bios_3_scratch |= (crtc << 19);
2198         }
2199         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2200                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2201                 bios_3_scratch |= (crtc << 23);
2202         }
2203         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2204                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2205                 bios_3_scratch |= (crtc << 25);
2206         }
2207
2208         if (rdev->family >= CHIP_R600)
2209                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2210         else
2211                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2212 }
2213
2214 void
2215 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2216 {
2217         struct drm_device *dev = encoder->dev;
2218         struct radeon_device *rdev = dev->dev_private;
2219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2220         uint32_t bios_2_scratch;
2221
2222         if (rdev->family >= CHIP_R600)
2223                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2224         else
2225                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2226
2227         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2228                 if (on)
2229                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2230                 else
2231                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2232         }
2233         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2234                 if (on)
2235                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2236                 else
2237                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2238         }
2239         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2240                 if (on)
2241                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2242                 else
2243                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2244         }
2245         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2246                 if (on)
2247                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2248                 else
2249                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2250         }
2251         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2252                 if (on)
2253                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2254                 else
2255                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2256         }
2257         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2258                 if (on)
2259                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2260                 else
2261                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2262         }
2263         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2264                 if (on)
2265                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2266                 else
2267                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2268         }
2269         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2270                 if (on)
2271                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2272                 else
2273                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2274         }
2275         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2276                 if (on)
2277                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2278                 else
2279                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2280         }
2281         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2282                 if (on)
2283                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2284                 else
2285                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2286         }
2287
2288         if (rdev->family >= CHIP_R600)
2289                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2290         else
2291                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2292 }