drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  66                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  67                                           u8 index)
  68 {
  69         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  70         if ((rdev->family == CHIP_R420) ||
  71             (rdev->family == CHIP_R423) ||
  72             (rdev->family == CHIP_RV410)) {
  73                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  74                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  75                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  76                         gpio->ucClkMaskShift = 0x19;
  77                         gpio->ucDataMaskShift = 0x18;
  78                 }
  79         }
  80
  81         /* some evergreen boards have bad data for this entry */
  82         if (ASIC_IS_DCE4(rdev)) {
  83                 if ((index == 7) &&
  84                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  85                     (gpio->sucI2cId.ucAccess == 0)) {
  86                         gpio->sucI2cId.ucAccess = 0x97;
  87                         gpio->ucDataMaskShift = 8;
  88                         gpio->ucDataEnShift = 8;
  89                         gpio->ucDataY_Shift = 8;
  90                         gpio->ucDataA_Shift = 8;
  91                 }
  92         }
  93
  94         /* some DCE3 boards have bad data for this entry */
  95         if (ASIC_IS_DCE3(rdev)) {
  96                 if ((index == 4) &&
  97                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  98                     (gpio->sucI2cId.ucAccess == 0x94))
  99                         gpio->sucI2cId.ucAccess = 0x14;
 100         }
 101 }
 102
 103 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
 104 {
 105         struct radeon_i2c_bus_rec i2c;
 106
 107         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 108
 109         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 110         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 111         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 112         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 113         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 114         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 115         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 116         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 117         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 118         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 119         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 120         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 121         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 122         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 123         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 124         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 125
 126         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 127                 i2c.hw_capable = true;
 128         else
 129                 i2c.hw_capable = false;
 130
 131         if (gpio->sucI2cId.ucAccess == 0xa0)
 132                 i2c.mm_i2c = true;
 133         else
 134                 i2c.mm_i2c = false;
 135
 136         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 137
 138         if (i2c.mask_clk_reg)
 139                 i2c.valid = true;
 140         else
 141                 i2c.valid = false;
 142
 143         return i2c;
 144 }
 145
 146 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 147                                                                uint8_t id)
 148 {
 149         struct atom_context *ctx = rdev->mode_info.atom_context;
 150         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 151         struct radeon_i2c_bus_rec i2c;
 152         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 153         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 154         uint16_t data_offset, size;
 155         int i, num_indices;
 156
 157         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 158         i2c.valid = false;
 159
 160         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 161                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 162
 163                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 164                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 165
 166                 for (i = 0; i < num_indices; i++) {
 167                         gpio = &i2c_info->asGPIO_Info[i];
 168
 169                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 170
 171                         if (gpio->sucI2cId.ucAccess == id) {
 172                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 173                                 break;
 174                         }
 175                 }
 176         }
 177
 178         return i2c;
 179 }
 180
 181 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 182 {
 183         struct atom_context *ctx = rdev->mode_info.atom_context;
 184         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 185         struct radeon_i2c_bus_rec i2c;
 186         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 187         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 188         uint16_t data_offset, size;
 189         int i, num_indices;
 190         char stmp[32];
 191
 192         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 193                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 194
 195                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 196                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 197
 198                 for (i = 0; i < num_indices; i++) {
 199                         gpio = &i2c_info->asGPIO_Info[i];
 200
 201                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 202
 203                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 204
 205                         if (i2c.valid) {
 206                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 207                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 208                         }
 209                 }
 210         }
 211 }
 212
 213 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 214                                                         u8 id)
 215 {
 216         struct atom_context *ctx = rdev->mode_info.atom_context;
 217         struct radeon_gpio_rec gpio;
 218         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 219         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 220         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 221         u16 data_offset, size;
 222         int i, num_indices;
 223
 224         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 225         gpio.valid = false;
 226
 227         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 228                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 229
 230                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 231                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 232
 233                 for (i = 0; i < num_indices; i++) {
 234                         pin = &gpio_info->asGPIO_Pin[i];
 235                         if (id == pin->ucGPIO_ID) {
 236                                 gpio.id = pin->ucGPIO_ID;
 237                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 238                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 239                                 gpio.valid = true;
 240                                 break;
 241                         }
 242                 }
 243         }
 244
 245         return gpio;
 246 }
 247
 248 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 249                                                             struct radeon_gpio_rec *gpio)
 250 {
 251         struct radeon_hpd hpd;
 252         u32 reg;
 253
 254         memset(&hpd, 0, sizeof(struct radeon_hpd));
 255
 256         if (ASIC_IS_DCE4(rdev))
 257                 reg = EVERGREEN_DC_GPIO_HPD_A;
 258         else
 259                 reg = AVIVO_DC_GPIO_HPD_A;
 260
 261         hpd.gpio = *gpio;
 262         if (gpio->reg == reg) {
 263                 switch(gpio->mask) {
 264                 case (1 << 0):
 265                         hpd.hpd = RADEON_HPD_1;
 266                         break;
 267                 case (1 << 8):
 268                         hpd.hpd = RADEON_HPD_2;
 269                         break;
 270                 case (1 << 16):
 271                         hpd.hpd = RADEON_HPD_3;
 272                         break;
 273                 case (1 << 24):
 274                         hpd.hpd = RADEON_HPD_4;
 275                         break;
 276                 case (1 << 26):
 277                         hpd.hpd = RADEON_HPD_5;
 278                         break;
 279                 case (1 << 28):
 280                         hpd.hpd = RADEON_HPD_6;
 281                         break;
 282                 default:
 283                         hpd.hpd = RADEON_HPD_NONE;
 284                         break;
 285                 }
 286         } else
 287                 hpd.hpd = RADEON_HPD_NONE;
 288         return hpd;
 289 }
 290
 291 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 292                                      uint32_t supported_device,
 293                                      int *connector_type,
 294                                      struct radeon_i2c_bus_rec *i2c_bus,
 295                                      uint16_t *line_mux,
 296                                      struct radeon_hpd *hpd)
 297 {
 298
 299         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 300         if ((dev->pdev->device == 0x791e) &&
 301             (dev->pdev->subsystem_vendor == 0x1043) &&
 302             (dev->pdev->subsystem_device == 0x826d)) {
 303                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 304                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 305                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 306         }
 307
 308         /* Asrock RS600 board lists the DVI port as HDMI */
 309         if ((dev->pdev->device == 0x7941) &&
 310             (dev->pdev->subsystem_vendor == 0x1849) &&
 311             (dev->pdev->subsystem_device == 0x7941)) {
 312                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 313                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 314                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 315         }
 316
 317         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 318         if ((dev->pdev->device == 0x796e) &&
 319             (dev->pdev->subsystem_vendor == 0x1462) &&
 320             (dev->pdev->subsystem_device == 0x7302)) {
 321                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 322                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 323                         return false;
 324         }
 325
 326         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 327         if ((dev->pdev->device == 0x7941) &&
 328             (dev->pdev->subsystem_vendor == 0x147b) &&
 329             (dev->pdev->subsystem_device == 0x2412)) {
 330                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 331                         return false;
 332         }
 333
 334         /* Falcon NW laptop lists vga ddc line for LVDS */
 335         if ((dev->pdev->device == 0x5653) &&
 336             (dev->pdev->subsystem_vendor == 0x1462) &&
 337             (dev->pdev->subsystem_device == 0x0291)) {
 338                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 339                         i2c_bus->valid = false;
 340                         *line_mux = 53;
 341                 }
 342         }
 343
 344         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 345         if ((dev->pdev->device == 0x7146) &&
 346             (dev->pdev->subsystem_vendor == 0x17af) &&
 347             (dev->pdev->subsystem_device == 0x2058)) {
 348                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 349                         return false;
 350         }
 351
 352         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 353         if ((dev->pdev->device == 0x7142) &&
 354             (dev->pdev->subsystem_vendor == 0x1458) &&
 355             (dev->pdev->subsystem_device == 0x2134)) {
 356                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 357                         return false;
 358         }
 359
 360
 361         /* Funky macbooks */
 362         if ((dev->pdev->device == 0x71C5) &&
 363             (dev->pdev->subsystem_vendor == 0x106b) &&
 364             (dev->pdev->subsystem_device == 0x0080)) {
 365                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 366                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 367                         return false;
 368                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 369                         *line_mux = 0x90;
 370         }
 371
 372         /* mac rv630, rv730, others */
 373         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 374             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 375                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 376                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 377         }
 378
 379         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 380         if ((dev->pdev->device == 0x9598) &&
 381             (dev->pdev->subsystem_vendor == 0x1043) &&
 382             (dev->pdev->subsystem_device == 0x01da)) {
 383                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 384                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 385                 }
 386         }
 387
 388         /* ASUS HD 3600 board lists the DVI port as HDMI */
 389         if ((dev->pdev->device == 0x9598) &&
 390             (dev->pdev->subsystem_vendor == 0x1043) &&
 391             (dev->pdev->subsystem_device == 0x01e4)) {
 392                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 393                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 394                 }
 395         }
 396
 397         /* ASUS HD 3450 board lists the DVI port as HDMI */
 398         if ((dev->pdev->device == 0x95C5) &&
 399             (dev->pdev->subsystem_vendor == 0x1043) &&
 400             (dev->pdev->subsystem_device == 0x01e2)) {
 401                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 402                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 403                 }
 404         }
 405
 406         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 407          * HDMI + VGA reporting as HDMI
 408          */
 409         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 410                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 411                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 412                         *line_mux = 0;
 413                 }
 414         }
 415
 416         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 417          * on the laptop and a DVI port on the docking station and
 418          * both share the same encoder, hpd pin, and ddc line.
 419          * So while the bios table is technically correct,
 420          * we drop the DVI port here since xrandr has no concept of
 421          * encoders and will try and drive both connectors
 422          * with different crtcs which isn't possible on the hardware
 423          * side and leaves no crtcs for LVDS or VGA.
 424          */
 425         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 426             (dev->pdev->subsystem_vendor == 0x1025) &&
 427             (dev->pdev->subsystem_device == 0x013c)) {
 428                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 429                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 430                         /* actually it's a DVI-D port not DVI-I */
 431                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 432                         return false;
 433                 }
 434         }
 435
 436         /* XFX Pine Group device rv730 reports no VGA DDC lines
 437          * even though they are wired up to record 0x93
 438          */
 439         if ((dev->pdev->device == 0x9498) &&
 440             (dev->pdev->subsystem_vendor == 0x1682) &&
 441             (dev->pdev->subsystem_device == 0x2452) &&
 442             (i2c_bus->valid == false) &&
 443             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 444                 struct radeon_device *rdev = dev->dev_private;
 445                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 446         }
 447
 448         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 449         if (((dev->pdev->device == 0x9802) ||
 450              (dev->pdev->device == 0x9805) ||
 451              (dev->pdev->device == 0x9806)) &&
 452             (dev->pdev->subsystem_vendor == 0x1734) &&
 453             (dev->pdev->subsystem_device == 0x11bd)) {
 454                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 455                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 456                         *line_mux = 0x3103;
 457                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 458                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 459                 }
 460         }
 461
 462         return true;
 463 }
 464
 465 const int supported_devices_connector_convert[] = {
 466         DRM_MODE_CONNECTOR_Unknown,
 467         DRM_MODE_CONNECTOR_VGA,
 468         DRM_MODE_CONNECTOR_DVII,
 469         DRM_MODE_CONNECTOR_DVID,
 470         DRM_MODE_CONNECTOR_DVIA,
 471         DRM_MODE_CONNECTOR_SVIDEO,
 472         DRM_MODE_CONNECTOR_Composite,
 473         DRM_MODE_CONNECTOR_LVDS,
 474         DRM_MODE_CONNECTOR_Unknown,
 475         DRM_MODE_CONNECTOR_Unknown,
 476         DRM_MODE_CONNECTOR_HDMIA,
 477         DRM_MODE_CONNECTOR_HDMIB,
 478         DRM_MODE_CONNECTOR_Unknown,
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_9PinDIN,
 481         DRM_MODE_CONNECTOR_DisplayPort
 482 };
 483
 484 const uint16_t supported_devices_connector_object_id_convert[] = {
 485         CONNECTOR_OBJECT_ID_NONE,
 486         CONNECTOR_OBJECT_ID_VGA,
 487         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 488         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 489         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 490         CONNECTOR_OBJECT_ID_COMPOSITE,
 491         CONNECTOR_OBJECT_ID_SVIDEO,
 492         CONNECTOR_OBJECT_ID_LVDS,
 493         CONNECTOR_OBJECT_ID_9PIN_DIN,
 494         CONNECTOR_OBJECT_ID_9PIN_DIN,
 495         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 496         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 497         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 498         CONNECTOR_OBJECT_ID_SVIDEO
 499 };
 500
 501 const int object_connector_convert[] = {
 502         DRM_MODE_CONNECTOR_Unknown,
 503         DRM_MODE_CONNECTOR_DVII,
 504         DRM_MODE_CONNECTOR_DVII,
 505         DRM_MODE_CONNECTOR_DVID,
 506         DRM_MODE_CONNECTOR_DVID,
 507         DRM_MODE_CONNECTOR_VGA,
 508         DRM_MODE_CONNECTOR_Composite,
 509         DRM_MODE_CONNECTOR_SVIDEO,
 510         DRM_MODE_CONNECTOR_Unknown,
 511         DRM_MODE_CONNECTOR_Unknown,
 512         DRM_MODE_CONNECTOR_9PinDIN,
 513         DRM_MODE_CONNECTOR_Unknown,
 514         DRM_MODE_CONNECTOR_HDMIA,
 515         DRM_MODE_CONNECTOR_HDMIB,
 516         DRM_MODE_CONNECTOR_LVDS,
 517         DRM_MODE_CONNECTOR_9PinDIN,
 518         DRM_MODE_CONNECTOR_Unknown,
 519         DRM_MODE_CONNECTOR_Unknown,
 520         DRM_MODE_CONNECTOR_Unknown,
 521         DRM_MODE_CONNECTOR_DisplayPort,
 522         DRM_MODE_CONNECTOR_eDP,
 523         DRM_MODE_CONNECTOR_Unknown
 524 };
 525
 526 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 527 {
 528         struct radeon_device *rdev = dev->dev_private;
 529         struct radeon_mode_info *mode_info = &rdev->mode_info;
 530         struct atom_context *ctx = mode_info->atom_context;
 531         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 532         u16 size, data_offset;
 533         u8 frev, crev;
 534         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 535         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 536         ATOM_OBJECT_TABLE *router_obj;
 537         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 538         ATOM_OBJECT_HEADER *obj_header;
 539         int i, j, k, path_size, device_support;
 540         int connector_type;
 541         u16 igp_lane_info, conn_id, connector_object_id;
 542         struct radeon_i2c_bus_rec ddc_bus;
 543         struct radeon_router router;
 544         struct radeon_gpio_rec gpio;
 545         struct radeon_hpd hpd;
 546
 547         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 548                 return false;
 549
 550         if (crev < 2)
 551                 return false;
 552
 553         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 554         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 555             (ctx->bios + data_offset +
 556              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 557         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 558             (ctx->bios + data_offset +
 559              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 560         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 561             (ctx->bios + data_offset +
 562              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 563         router_obj = (ATOM_OBJECT_TABLE *)
 564                 (ctx->bios + data_offset +
 565                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 566         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 567
 568         path_size = 0;
 569         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 570                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 571                 ATOM_DISPLAY_OBJECT_PATH *path;
 572                 addr += path_size;
 573                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 574                 path_size += le16_to_cpu(path->usSize);
 575
 576                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 577                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 578
 579                         con_obj_id =
 580                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 581                             >> OBJECT_ID_SHIFT;
 582                         con_obj_num =
 583                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 584                             >> ENUM_ID_SHIFT;
 585                         con_obj_type =
 586                             (le16_to_cpu(path->usConnObjectId) &
 587                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 588
 589                         /* TODO CV support */
 590                         if (le16_to_cpu(path->usDeviceTag) ==
 591                                 ATOM_DEVICE_CV_SUPPORT)
 592                                 continue;
 593
 594                         /* IGP chips */
 595                         if ((rdev->flags & RADEON_IS_IGP) &&
 596                             (con_obj_id ==
 597                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 598                                 uint16_t igp_offset = 0;
 599                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 600
 601                                 index =
 602                                     GetIndexIntoMasterTable(DATA,
 603                                                             IntegratedSystemInfo);
 604
 605                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 606                                                            &crev, &igp_offset)) {
 607
 608                                         if (crev >= 2) {
 609                                                 igp_obj =
 610                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 611                                                          *) (ctx->bios + igp_offset);
 612
 613                                                 if (igp_obj) {
 614                                                         uint32_t slot_config, ct;
 615
 616                                                         if (con_obj_num == 1)
 617                                                                 slot_config =
 618                                                                         igp_obj->
 619                                                                         ulDDISlot1Config;
 620                                                         else
 621                                                                 slot_config =
 622                                                                         igp_obj->
 623                                                                         ulDDISlot2Config;
 624
 625                                                         ct = (slot_config >> 16) & 0xff;
 626                                                         connector_type =
 627                                                                 object_connector_convert
 628                                                                 [ct];
 629                                                         connector_object_id = ct;
 630                                                         igp_lane_info =
 631                                                                 slot_config & 0xffff;
 632                                                 } else
 633                                                         continue;
 634                                         } else
 635                                                 continue;
 636                                 } else {
 637                                         igp_lane_info = 0;
 638                                         connector_type =
 639                                                 object_connector_convert[con_obj_id];
 640                                         connector_object_id = con_obj_id;
 641                                 }
 642                         } else {
 643                                 igp_lane_info = 0;
 644                                 connector_type =
 645                                     object_connector_convert[con_obj_id];
 646                                 connector_object_id = con_obj_id;
 647                         }
 648
 649                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 650                                 continue;
 651
 652                         router.ddc_valid = false;
 653                         router.cd_valid = false;
 654                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 655                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 656
 657                                 grph_obj_id =
 658                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 659                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 660                                 grph_obj_num =
 661                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 662                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 663                                 grph_obj_type =
 664                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 665                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 666
 667                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 668                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 669                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 670                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 671                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 672                                                                 (ctx->bios + data_offset +
 673                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 674                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 675                                                         u16 caps = 0;
 676
 677                                                         while (record->ucRecordSize > 0 &&
 678                                                                record->ucRecordType > 0 &&
 679                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 680                                                                 switch (record->ucRecordType) {
 681                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 682                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 683                                                                                 record;
 684                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 685                                                                         break;
 686                                                                 }
 687                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 688                                                                         ((char *)record + record->ucRecordSize);
 689                                                         }
 690                                                         radeon_add_atom_encoder(dev,
 691                                                                                 encoder_obj,
 692                                                                                 le16_to_cpu
 693                                                                                 (path->
 694                                                                                  usDeviceTag),
 695                                                                                 caps);
 696                                                 }
 697                                         }
 698                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 699                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 700                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 701                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 702                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 703                                                                 (ctx->bios + data_offset +
 704                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 705                                                         ATOM_I2C_RECORD *i2c_record;
 706                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 707                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 708                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 709                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 710                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 711                                                                 (ctx->bios + data_offset +
 712                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 713                                                         u8 *num_dst_objs = (u8 *)
 714                                                                 ((u8 *)router_src_dst_table + 1 +
 715                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 716                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 717                                                         int enum_id;
 718
 719                                                         router.router_id = router_obj_id;
 720                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 721                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 722                                                                     le16_to_cpu(dst_objs[enum_id]))
 723                                                                         break;
 724                                                         }
 725
 726                                                         while (record->ucRecordSize > 0 &&
 727                                                                record->ucRecordType > 0 &&
 728                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 729                                                                 switch (record->ucRecordType) {
 730                                                                 case ATOM_I2C_RECORD_TYPE:
 731                                                                         i2c_record =
 732                                                                                 (ATOM_I2C_RECORD *)
 733                                                                                 record;
 734                                                                         i2c_config =
 735                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 736                                                                                 &i2c_record->sucI2cId;
 737                                                                         router.i2c_info =
 738                                                                                 radeon_lookup_i2c_gpio(rdev,
 739                                                                                                        i2c_config->
 740                                                                                                        ucAccess);
 741                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 742                                                                         break;
 743                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 744                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 745                                                                                 record;
 746                                                                         router.ddc_valid = true;
 747                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 748                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 749                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 750                                                                         break;
 751                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 752                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 753                                                                                 record;
 754                                                                         router.cd_valid = true;
 755                                                                         router.cd_mux_type = cd_path->ucMuxType;
 756                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 757                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 758                                                                         break;
 759                                                                 }
 760                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 761                                                                         ((char *)record + record->ucRecordSize);
 762                                                         }
 763                                                 }
 764                                         }
 765                                 }
 766                         }
 767
 768                         /* look up gpio for ddc, hpd */
 769                         ddc_bus.valid = false;
 770                         hpd.hpd = RADEON_HPD_NONE;
 771                         if ((le16_to_cpu(path->usDeviceTag) &
 772                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 773                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 774                                         if (le16_to_cpu(path->usConnObjectId) ==
 775                                             le16_to_cpu(con_obj->asObjects[j].
 776                                                         usObjectID)) {
 777                                                 ATOM_COMMON_RECORD_HEADER
 778                                                     *record =
 779                                                     (ATOM_COMMON_RECORD_HEADER
 780                                                      *)
 781                                                     (ctx->bios + data_offset +
 782                                                      le16_to_cpu(con_obj->
 783                                                                  asObjects[j].
 784                                                                  usRecordOffset));
 785                                                 ATOM_I2C_RECORD *i2c_record;
 786                                                 ATOM_HPD_INT_RECORD *hpd_record;
 787                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 788
 789                                                 while (record->ucRecordSize > 0 &&
 790                                                        record->ucRecordType > 0 &&
 791                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 792                                                         switch (record->ucRecordType) {
 793                                                         case ATOM_I2C_RECORD_TYPE:
 794                                                                 i2c_record =
 795                                                                     (ATOM_I2C_RECORD *)
 796                                                                         record;
 797                                                                 i2c_config =
 798                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 799                                                                         &i2c_record->sucI2cId;
 800                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 801                                                                                                  i2c_config->
 802                                                                                                  ucAccess);
 803                                                                 break;
 804                                                         case ATOM_HPD_INT_RECORD_TYPE:
 805                                                                 hpd_record =
 806                                                                         (ATOM_HPD_INT_RECORD *)
 807                                                                         record;
 808                                                                 gpio = radeon_lookup_gpio(rdev,
 809                                                                                           hpd_record->ucHPDIntGPIOID);
 810                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 811                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 812                                                                 break;
 813                                                         }
 814                                                         record =
 815                                                             (ATOM_COMMON_RECORD_HEADER
 816                                                              *) ((char *)record
 817                                                                  +
 818                                                                  record->
 819                                                                  ucRecordSize);
 820                                                 }
 821                                                 break;
 822                                         }
 823                                 }
 824                         }
 825
 826                         /* needed for aux chan transactions */
 827                         ddc_bus.hpd = hpd.hpd;
 828
 829                         conn_id = le16_to_cpu(path->usConnObjectId);
 830
 831                         if (!radeon_atom_apply_quirks
 832                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 833                              &ddc_bus, &conn_id, &hpd))
 834                                 continue;
 835
 836                         radeon_add_atom_connector(dev,
 837                                                   conn_id,
 838                                                   le16_to_cpu(path->
 839                                                               usDeviceTag),
 840                                                   connector_type, &ddc_bus,
 841                                                   igp_lane_info,
 842                                                   connector_object_id,
 843                                                   &hpd,
 844                                                   &router);
 845
 846                 }
 847         }
 848
 849         radeon_link_encoder_connector(dev);
 850
 851         return true;
 852 }
 853
 854 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 855                                                  int connector_type,
 856                                                  uint16_t devices)
 857 {
 858         struct radeon_device *rdev = dev->dev_private;
 859
 860         if (rdev->flags & RADEON_IS_IGP) {
 861                 return supported_devices_connector_object_id_convert
 862                         [connector_type];
 863         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 864                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 865                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 866                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 867                 struct atom_context *ctx = mode_info->atom_context;
 868                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 869                 uint16_t size, data_offset;
 870                 uint8_t frev, crev;
 871                 ATOM_XTMDS_INFO *xtmds;
 872
 873                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 874                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 875
 876                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 877                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 878                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 879                                 else
 880                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 881                         } else {
 882                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 883                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 884                                 else
 885                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 886                         }
 887                 } else
 888                         return supported_devices_connector_object_id_convert
 889                                 [connector_type];
 890         } else {
 891                 return supported_devices_connector_object_id_convert
 892                         [connector_type];
 893         }
 894 }
 895
 896 struct bios_connector {
 897         bool valid;
 898         uint16_t line_mux;
 899         uint16_t devices;
 900         int connector_type;
 901         struct radeon_i2c_bus_rec ddc_bus;
 902         struct radeon_hpd hpd;
 903 };
 904
 905 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 906                                                                  drm_device
 907                                                                  *dev)
 908 {
 909         struct radeon_device *rdev = dev->dev_private;
 910         struct radeon_mode_info *mode_info = &rdev->mode_info;
 911         struct atom_context *ctx = mode_info->atom_context;
 912         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 913         uint16_t size, data_offset;
 914         uint8_t frev, crev;
 915         uint16_t device_support;
 916         uint8_t dac;
 917         union atom_supported_devices *supported_devices;
 918         int i, j, max_device;
 919         struct bios_connector *bios_connectors;
 920         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 921         struct radeon_router router;
 922
 923         router.ddc_valid = false;
 924         router.cd_valid = false;
 925
 926         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 927         if (!bios_connectors)
 928                 return false;
 929
 930         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 931                                     &data_offset)) {
 932                 kfree(bios_connectors);
 933                 return false;
 934         }
 935
 936         supported_devices =
 937             (union atom_supported_devices *)(ctx->bios + data_offset);
 938
 939         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 940
 941         if (frev > 1)
 942                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 943         else
 944                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 945
 946         for (i = 0; i < max_device; i++) {
 947                 ATOM_CONNECTOR_INFO_I2C ci =
 948                     supported_devices->info.asConnInfo[i];
 949
 950                 bios_connectors[i].valid = false;
 951
 952                 if (!(device_support & (1 << i))) {
 953                         continue;
 954                 }
 955
 956                 if (i == ATOM_DEVICE_CV_INDEX) {
 957                         DRM_DEBUG_KMS("Skipping Component Video\n");
 958                         continue;
 959                 }
 960
 961                 bios_connectors[i].connector_type =
 962                     supported_devices_connector_convert[ci.sucConnectorInfo.
 963                                                         sbfAccess.
 964                                                         bfConnectorType];
 965
 966                 if (bios_connectors[i].connector_type ==
 967                     DRM_MODE_CONNECTOR_Unknown)
 968                         continue;
 969
 970                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 971
 972                 bios_connectors[i].line_mux =
 973                         ci.sucI2cId.ucAccess;
 974
 975                 /* give tv unique connector ids */
 976                 if (i == ATOM_DEVICE_TV1_INDEX) {
 977                         bios_connectors[i].ddc_bus.valid = false;
 978                         bios_connectors[i].line_mux = 50;
 979                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 980                         bios_connectors[i].ddc_bus.valid = false;
 981                         bios_connectors[i].line_mux = 51;
 982                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 983                         bios_connectors[i].ddc_bus.valid = false;
 984                         bios_connectors[i].line_mux = 52;
 985                 } else
 986                         bios_connectors[i].ddc_bus =
 987                             radeon_lookup_i2c_gpio(rdev,
 988                                                    bios_connectors[i].line_mux);
 989
 990                 if ((crev > 1) && (frev > 1)) {
 991                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 992                         switch (isb) {
 993                         case 0x4:
 994                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 995                                 break;
 996                         case 0xa:
 997                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 998                                 break;
 999                         default:
1000                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1001                                 break;
1002                         }
1003                 } else {
1004                         if (i == ATOM_DEVICE_DFP1_INDEX)
1005                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1006                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1007                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1008                         else
1009                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1010                 }
1011
1012                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1013                  * shared with a DVI port, we'll pick up the DVI connector when we
1014                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1015                  */
1016                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1017                         bios_connectors[i].connector_type =
1018                             DRM_MODE_CONNECTOR_VGA;
1019
1020                 if (!radeon_atom_apply_quirks
1021                     (dev, (1 << i), &bios_connectors[i].connector_type,
1022                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1023                      &bios_connectors[i].hpd))
1024                         continue;
1025
1026                 bios_connectors[i].valid = true;
1027                 bios_connectors[i].devices = (1 << i);
1028
1029                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1030                         radeon_add_atom_encoder(dev,
1031                                                 radeon_get_encoder_enum(dev,
1032                                                                       (1 << i),
1033                                                                       dac),
1034                                                 (1 << i),
1035                                                 0);
1036                 else
1037                         radeon_add_legacy_encoder(dev,
1038                                                   radeon_get_encoder_enum(dev,
1039                                                                         (1 << i),
1040                                                                         dac),
1041                                                   (1 << i));
1042         }
1043
1044         /* combine shared connectors */
1045         for (i = 0; i < max_device; i++) {
1046                 if (bios_connectors[i].valid) {
1047                         for (j = 0; j < max_device; j++) {
1048                                 if (bios_connectors[j].valid && (i != j)) {
1049                                         if (bios_connectors[i].line_mux ==
1050                                             bios_connectors[j].line_mux) {
1051                                                 /* make sure not to combine LVDS */
1052                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1053                                                         bios_connectors[i].line_mux = 53;
1054                                                         bios_connectors[i].ddc_bus.valid = false;
1055                                                         continue;
1056                                                 }
1057                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1058                                                         bios_connectors[j].line_mux = 53;
1059                                                         bios_connectors[j].ddc_bus.valid = false;
1060                                                         continue;
1061                                                 }
1062                                                 /* combine analog and digital for DVI-I */
1063                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1065                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1066                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1067                                                         bios_connectors[i].devices |=
1068                                                                 bios_connectors[j].devices;
1069                                                         bios_connectors[i].connector_type =
1070                                                                 DRM_MODE_CONNECTOR_DVII;
1071                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1072                                                                 bios_connectors[i].hpd =
1073                                                                         bios_connectors[j].hpd;
1074                                                         bios_connectors[j].valid = false;
1075                                                 }
1076                                         }
1077                                 }
1078                         }
1079                 }
1080         }
1081
1082         /* add the connectors */
1083         for (i = 0; i < max_device; i++) {
1084                 if (bios_connectors[i].valid) {
1085                         uint16_t connector_object_id =
1086                                 atombios_get_connector_object_id(dev,
1087                                                       bios_connectors[i].connector_type,
1088                                                       bios_connectors[i].devices);
1089                         radeon_add_atom_connector(dev,
1090                                                   bios_connectors[i].line_mux,
1091                                                   bios_connectors[i].devices,
1092                                                   bios_connectors[i].
1093                                                   connector_type,
1094                                                   &bios_connectors[i].ddc_bus,
1095                                                   0,
1096                                                   connector_object_id,
1097                                                   &bios_connectors[i].hpd,
1098                                                   &router);
1099                 }
1100         }
1101
1102         radeon_link_encoder_connector(dev);
1103
1104         kfree(bios_connectors);
1105         return true;
1106 }
1107
1108 union firmware_info {
1109         ATOM_FIRMWARE_INFO info;
1110         ATOM_FIRMWARE_INFO_V1_2 info_12;
1111         ATOM_FIRMWARE_INFO_V1_3 info_13;
1112         ATOM_FIRMWARE_INFO_V1_4 info_14;
1113         ATOM_FIRMWARE_INFO_V2_1 info_21;
1114         ATOM_FIRMWARE_INFO_V2_2 info_22;
1115 };
1116
1117 bool radeon_atom_get_clock_info(struct drm_device *dev)
1118 {
1119         struct radeon_device *rdev = dev->dev_private;
1120         struct radeon_mode_info *mode_info = &rdev->mode_info;
1121         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1122         union firmware_info *firmware_info;
1123         uint8_t frev, crev;
1124         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1125         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1126         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1127         struct radeon_pll *spll = &rdev->clock.spll;
1128         struct radeon_pll *mpll = &rdev->clock.mpll;
1129         uint16_t data_offset;
1130
1131         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1132                                    &frev, &crev, &data_offset)) {
1133                 firmware_info =
1134                         (union firmware_info *)(mode_info->atom_context->bios +
1135                                                 data_offset);
1136                 /* pixel clocks */
1137                 p1pll->reference_freq =
1138                     le16_to_cpu(firmware_info->info.usReferenceClock);
1139                 p1pll->reference_div = 0;
1140
1141                 if (crev < 2)
1142                         p1pll->pll_out_min =
1143                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1144                 else
1145                         p1pll->pll_out_min =
1146                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1147                 p1pll->pll_out_max =
1148                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1149
1150                 if (crev >= 4) {
1151                         p1pll->lcd_pll_out_min =
1152                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1153                         if (p1pll->lcd_pll_out_min == 0)
1154                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1155                         p1pll->lcd_pll_out_max =
1156                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1157                         if (p1pll->lcd_pll_out_max == 0)
1158                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1159                 } else {
1160                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1161                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1162                 }
1163
1164                 if (p1pll->pll_out_min == 0) {
1165                         if (ASIC_IS_AVIVO(rdev))
1166                                 p1pll->pll_out_min = 64800;
1167                         else
1168                                 p1pll->pll_out_min = 20000;
1169                 }
1170
1171                 p1pll->pll_in_min =
1172                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1173                 p1pll->pll_in_max =
1174                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1175
1176                 *p2pll = *p1pll;
1177
1178                 /* system clock */
1179                 if (ASIC_IS_DCE4(rdev))
1180                         spll->reference_freq =
1181                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1182                 else
1183                         spll->reference_freq =
1184                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1185                 spll->reference_div = 0;
1186
1187                 spll->pll_out_min =
1188                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1189                 spll->pll_out_max =
1190                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1191
1192                 /* ??? */
1193                 if (spll->pll_out_min == 0) {
1194                         if (ASIC_IS_AVIVO(rdev))
1195                                 spll->pll_out_min = 64800;
1196                         else
1197                                 spll->pll_out_min = 20000;
1198                 }
1199
1200                 spll->pll_in_min =
1201                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1202                 spll->pll_in_max =
1203                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1204
1205                 /* memory clock */
1206                 if (ASIC_IS_DCE4(rdev))
1207                         mpll->reference_freq =
1208                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1209                 else
1210                         mpll->reference_freq =
1211                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1212                 mpll->reference_div = 0;
1213
1214                 mpll->pll_out_min =
1215                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1216                 mpll->pll_out_max =
1217                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1218
1219                 /* ??? */
1220                 if (mpll->pll_out_min == 0) {
1221                         if (ASIC_IS_AVIVO(rdev))
1222                                 mpll->pll_out_min = 64800;
1223                         else
1224                                 mpll->pll_out_min = 20000;
1225                 }
1226
1227                 mpll->pll_in_min =
1228                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1229                 mpll->pll_in_max =
1230                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1231
1232                 rdev->clock.default_sclk =
1233                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1234                 rdev->clock.default_mclk =
1235                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1236
1237                 if (ASIC_IS_DCE4(rdev)) {
1238                         rdev->clock.default_dispclk =
1239                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1240                         if (rdev->clock.default_dispclk == 0) {
1241                                 if (ASIC_IS_DCE5(rdev))
1242                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1243                                 else
1244                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1245                         }
1246                         rdev->clock.dp_extclk =
1247                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1248                 }
1249                 *dcpll = *p1pll;
1250
1251                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1252                 if (rdev->clock.max_pixel_clock == 0)
1253                         rdev->clock.max_pixel_clock = 40000;
1254
1255                 return true;
1256         }
1257
1258         return false;
1259 }
1260
1261 union igp_info {
1262         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1263         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1264 };
1265
1266 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1267 {
1268         struct radeon_mode_info *mode_info = &rdev->mode_info;
1269         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1270         union igp_info *igp_info;
1271         u8 frev, crev;
1272         u16 data_offset;
1273
1274         /* sideport is AMD only */
1275         if (rdev->family == CHIP_RS600)
1276                 return false;
1277
1278         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1279                                    &frev, &crev, &data_offset)) {
1280                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1281                                       data_offset);
1282                 switch (crev) {
1283                 case 1:
1284                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1285                                 return true;
1286                         break;
1287                 case 2:
1288                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1289                                 return true;
1290                         break;
1291                 default:
1292                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1293                         break;
1294                 }
1295         }
1296         return false;
1297 }
1298
1299 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1300                                    struct radeon_encoder_int_tmds *tmds)
1301 {
1302         struct drm_device *dev = encoder->base.dev;
1303         struct radeon_device *rdev = dev->dev_private;
1304         struct radeon_mode_info *mode_info = &rdev->mode_info;
1305         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1306         uint16_t data_offset;
1307         struct _ATOM_TMDS_INFO *tmds_info;
1308         uint8_t frev, crev;
1309         uint16_t maxfreq;
1310         int i;
1311
1312         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1313                                    &frev, &crev, &data_offset)) {
1314                 tmds_info =
1315                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1316                                                    data_offset);
1317
1318                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1319                 for (i = 0; i < 4; i++) {
1320                         tmds->tmds_pll[i].freq =
1321                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1322                         tmds->tmds_pll[i].value =
1323                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1324                         tmds->tmds_pll[i].value |=
1325                             (tmds_info->asMiscInfo[i].
1326                              ucPLL_VCO_Gain & 0x3f) << 6;
1327                         tmds->tmds_pll[i].value |=
1328                             (tmds_info->asMiscInfo[i].
1329                              ucPLL_DutyCycle & 0xf) << 12;
1330                         tmds->tmds_pll[i].value |=
1331                             (tmds_info->asMiscInfo[i].
1332                              ucPLL_VoltageSwing & 0xf) << 16;
1333
1334                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1335                                   tmds->tmds_pll[i].freq,
1336                                   tmds->tmds_pll[i].value);
1337
1338                         if (maxfreq == tmds->tmds_pll[i].freq) {
1339                                 tmds->tmds_pll[i].freq = 0xffffffff;
1340                                 break;
1341                         }
1342                 }
1343                 return true;
1344         }
1345         return false;
1346 }
1347
1348 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1349                                       struct radeon_atom_ss *ss,
1350                                       int id)
1351 {
1352         struct radeon_mode_info *mode_info = &rdev->mode_info;
1353         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1354         uint16_t data_offset, size;
1355         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1356         uint8_t frev, crev;
1357         int i, num_indices;
1358
1359         memset(ss, 0, sizeof(struct radeon_atom_ss));
1360         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1361                                    &frev, &crev, &data_offset)) {
1362                 ss_info =
1363                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1364
1365                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1366                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1367
1368                 for (i = 0; i < num_indices; i++) {
1369                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1370                                 ss->percentage =
1371                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1372                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1373                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1374                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1375                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1376                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1377                                 return true;
1378                         }
1379                 }
1380         }
1381         return false;
1382 }
1383
1384 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1385                                                  struct radeon_atom_ss *ss,
1386                                                  int id)
1387 {
1388         struct radeon_mode_info *mode_info = &rdev->mode_info;
1389         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1390         u16 data_offset, size;
1391         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1392         u8 frev, crev;
1393         u16 percentage = 0, rate = 0;
1394
1395         /* get any igp specific overrides */
1396         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1397                                    &frev, &crev, &data_offset)) {
1398                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1399                         (mode_info->atom_context->bios + data_offset);
1400                 switch (id) {
1401                 case ASIC_INTERNAL_SS_ON_TMDS:
1402                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1403                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1404                         break;
1405                 case ASIC_INTERNAL_SS_ON_HDMI:
1406                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1407                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1408                         break;
1409                 case ASIC_INTERNAL_SS_ON_LVDS:
1410                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1411                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1412                         break;
1413                 }
1414                 if (percentage)
1415                         ss->percentage = percentage;
1416                 if (rate)
1417                         ss->rate = rate;
1418         }
1419 }
1420
1421 union asic_ss_info {
1422         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1423         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1424         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1425 };
1426
1427 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1428                                       struct radeon_atom_ss *ss,
1429                                       int id, u32 clock)
1430 {
1431         struct radeon_mode_info *mode_info = &rdev->mode_info;
1432         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1433         uint16_t data_offset, size;
1434         union asic_ss_info *ss_info;
1435         uint8_t frev, crev;
1436         int i, num_indices;
1437
1438         memset(ss, 0, sizeof(struct radeon_atom_ss));
1439         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1440                                    &frev, &crev, &data_offset)) {
1441
1442                 ss_info =
1443                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1444
1445                 switch (frev) {
1446                 case 1:
1447                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1448                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1449
1450                         for (i = 0; i < num_indices; i++) {
1451                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1452                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1453                                         ss->percentage =
1454                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1455                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1456                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1457                                         return true;
1458                                 }
1459                         }
1460                         break;
1461                 case 2:
1462                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1463                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1464                         for (i = 0; i < num_indices; i++) {
1465                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1466                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1467                                         ss->percentage =
1468                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1469                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1470                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1471                                         return true;
1472                                 }
1473                         }
1474                         break;
1475                 case 3:
1476                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1477                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1478                         for (i = 0; i < num_indices; i++) {
1479                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1480                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1481                                         ss->percentage =
1482                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1483                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1484                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1485                                         if (rdev->flags & RADEON_IS_IGP)
1486                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1487                                         return true;
1488                                 }
1489                         }
1490                         break;
1491                 default:
1492                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1493                         break;
1494                 }
1495
1496         }
1497         return false;
1498 }
1499
1500 union lvds_info {
1501         struct _ATOM_LVDS_INFO info;
1502         struct _ATOM_LVDS_INFO_V12 info_12;
1503 };
1504
1505 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1506                                                               radeon_encoder
1507                                                               *encoder)
1508 {
1509         struct drm_device *dev = encoder->base.dev;
1510         struct radeon_device *rdev = dev->dev_private;
1511         struct radeon_mode_info *mode_info = &rdev->mode_info;
1512         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1513         uint16_t data_offset, misc;
1514         union lvds_info *lvds_info;
1515         uint8_t frev, crev;
1516         struct radeon_encoder_atom_dig *lvds = NULL;
1517         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1518
1519         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1520                                    &frev, &crev, &data_offset)) {
1521                 lvds_info =
1522                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1523                 lvds =
1524                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1525
1526                 if (!lvds)
1527                         return NULL;
1528
1529                 lvds->native_mode.clock =
1530                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1531                 lvds->native_mode.hdisplay =
1532                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1533                 lvds->native_mode.vdisplay =
1534                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1535                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1536                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1537                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1538                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1539                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1540                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1541                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1542                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1543                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1544                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1545                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1546                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1547                 lvds->panel_pwr_delay =
1548                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1549                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1550
1551                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1552                 if (misc & ATOM_VSYNC_POLARITY)
1553                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1554                 if (misc & ATOM_HSYNC_POLARITY)
1555                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1556                 if (misc & ATOM_COMPOSITESYNC)
1557                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1558                 if (misc & ATOM_INTERLACE)
1559                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1560                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1561                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1562
1563                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1564                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1565
1566                 /* set crtc values */
1567                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1568
1569                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1570
1571                 encoder->native_mode = lvds->native_mode;
1572
1573                 if (encoder_enum == 2)
1574                         lvds->linkb = true;
1575                 else
1576                         lvds->linkb = false;
1577
1578                 /* parse the lcd record table */
1579                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1580                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1581                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1582                         bool bad_record = false;
1583                         u8 *record;
1584
1585                         if ((frev == 1) && (crev < 2))
1586                                 /* absolute */
1587                                 record = (u8 *)(mode_info->atom_context->bios +
1588                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1589                         else
1590                                 /* relative */
1591                                 record = (u8 *)(mode_info->atom_context->bios +
1592                                                 data_offset +
1593                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1594                         while (*record != ATOM_RECORD_END_TYPE) {
1595                                 switch (*record) {
1596                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1597                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1598                                         break;
1599                                 case LCD_RTS_RECORD_TYPE:
1600                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1601                                         break;
1602                                 case LCD_CAP_RECORD_TYPE:
1603                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1604                                         break;
1605                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1606                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1607                                         if (fake_edid_record->ucFakeEDIDLength) {
1608                                                 struct edid *edid;
1609                                                 int edid_size =
1610                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1611                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1612                                                 if (edid) {
1613                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1614                                                                fake_edid_record->ucFakeEDIDLength);
1615
1616                                                         if (drm_edid_is_valid(edid)) {
1617                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1618                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1619                                                         } else
1620                                                                 kfree(edid);
1621                                                 }
1622                                         }
1623                                         record += fake_edid_record->ucFakeEDIDLength ?
1624                                                 fake_edid_record->ucFakeEDIDLength + 2 :
1625                                                 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1626                                         break;
1627                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1628                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1629                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1630                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1631                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1632                                         break;
1633                                 default:
1634                                         DRM_ERROR("Bad LCD record %d\n", *record);
1635                                         bad_record = true;
1636                                         break;
1637                                 }
1638                                 if (bad_record)
1639                                         break;
1640                         }
1641                 }
1642         }
1643         return lvds;
1644 }
1645
1646 struct radeon_encoder_primary_dac *
1647 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1648 {
1649         struct drm_device *dev = encoder->base.dev;
1650         struct radeon_device *rdev = dev->dev_private;
1651         struct radeon_mode_info *mode_info = &rdev->mode_info;
1652         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1653         uint16_t data_offset;
1654         struct _COMPASSIONATE_DATA *dac_info;
1655         uint8_t frev, crev;
1656         uint8_t bg, dac;
1657         struct radeon_encoder_primary_dac *p_dac = NULL;
1658
1659         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1660                                    &frev, &crev, &data_offset)) {
1661                 dac_info = (struct _COMPASSIONATE_DATA *)
1662                         (mode_info->atom_context->bios + data_offset);
1663
1664                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1665
1666                 if (!p_dac)
1667                         return NULL;
1668
1669                 bg = dac_info->ucDAC1_BG_Adjustment;
1670                 dac = dac_info->ucDAC1_DAC_Adjustment;
1671                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1672
1673         }
1674         return p_dac;
1675 }
1676
1677 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1678                                 struct drm_display_mode *mode)
1679 {
1680         struct radeon_mode_info *mode_info = &rdev->mode_info;
1681         ATOM_ANALOG_TV_INFO *tv_info;
1682         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1683         ATOM_DTD_FORMAT *dtd_timings;
1684         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1685         u8 frev, crev;
1686         u16 data_offset, misc;
1687
1688         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1689                                     &frev, &crev, &data_offset))
1690                 return false;
1691
1692         switch (crev) {
1693         case 1:
1694                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1695                 if (index >= MAX_SUPPORTED_TV_TIMING)
1696                         return false;
1697
1698                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1699                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1700                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1701                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1702                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1703
1704                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1705                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1706                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1707                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1708                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1709
1710                 mode->flags = 0;
1711                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1712                 if (misc & ATOM_VSYNC_POLARITY)
1713                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1714                 if (misc & ATOM_HSYNC_POLARITY)
1715                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1716                 if (misc & ATOM_COMPOSITESYNC)
1717                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1718                 if (misc & ATOM_INTERLACE)
1719                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1720                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1721                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1722
1723                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1724
1725                 if (index == 1) {
1726                         /* PAL timings appear to have wrong values for totals */
1727                         mode->crtc_htotal -= 1;
1728                         mode->crtc_vtotal -= 1;
1729                 }
1730                 break;
1731         case 2:
1732                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1733                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1734                         return false;
1735
1736                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1737                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1738                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1739                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1740                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1741                         le16_to_cpu(dtd_timings->usHSyncOffset);
1742                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1743                         le16_to_cpu(dtd_timings->usHSyncWidth);
1744
1745                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1746                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1747                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1748                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1749                         le16_to_cpu(dtd_timings->usVSyncOffset);
1750                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1751                         le16_to_cpu(dtd_timings->usVSyncWidth);
1752
1753                 mode->flags = 0;
1754                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1755                 if (misc & ATOM_VSYNC_POLARITY)
1756                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1757                 if (misc & ATOM_HSYNC_POLARITY)
1758                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1759                 if (misc & ATOM_COMPOSITESYNC)
1760                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1761                 if (misc & ATOM_INTERLACE)
1762                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1763                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1764                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1765
1766                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1767                 break;
1768         }
1769         return true;
1770 }
1771
1772 enum radeon_tv_std
1773 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1774 {
1775         struct radeon_mode_info *mode_info = &rdev->mode_info;
1776         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1777         uint16_t data_offset;
1778         uint8_t frev, crev;
1779         struct _ATOM_ANALOG_TV_INFO *tv_info;
1780         enum radeon_tv_std tv_std = TV_STD_NTSC;
1781
1782         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1783                                    &frev, &crev, &data_offset)) {
1784
1785                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1786                         (mode_info->atom_context->bios + data_offset);
1787
1788                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1789                 case ATOM_TV_NTSC:
1790                         tv_std = TV_STD_NTSC;
1791                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1792                         break;
1793                 case ATOM_TV_NTSCJ:
1794                         tv_std = TV_STD_NTSC_J;
1795                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1796                         break;
1797                 case ATOM_TV_PAL:
1798                         tv_std = TV_STD_PAL;
1799                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1800                         break;
1801                 case ATOM_TV_PALM:
1802                         tv_std = TV_STD_PAL_M;
1803                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1804                         break;
1805                 case ATOM_TV_PALN:
1806                         tv_std = TV_STD_PAL_N;
1807                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1808                         break;
1809                 case ATOM_TV_PALCN:
1810                         tv_std = TV_STD_PAL_CN;
1811                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1812                         break;
1813                 case ATOM_TV_PAL60:
1814                         tv_std = TV_STD_PAL_60;
1815                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1816                         break;
1817                 case ATOM_TV_SECAM:
1818                         tv_std = TV_STD_SECAM;
1819                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1820                         break;
1821                 default:
1822                         tv_std = TV_STD_NTSC;
1823                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1824                         break;
1825                 }
1826         }
1827         return tv_std;
1828 }
1829
1830 struct radeon_encoder_tv_dac *
1831 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1832 {
1833         struct drm_device *dev = encoder->base.dev;
1834         struct radeon_device *rdev = dev->dev_private;
1835         struct radeon_mode_info *mode_info = &rdev->mode_info;
1836         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1837         uint16_t data_offset;
1838         struct _COMPASSIONATE_DATA *dac_info;
1839         uint8_t frev, crev;
1840         uint8_t bg, dac;
1841         struct radeon_encoder_tv_dac *tv_dac = NULL;
1842
1843         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1844                                    &frev, &crev, &data_offset)) {
1845
1846                 dac_info = (struct _COMPASSIONATE_DATA *)
1847                         (mode_info->atom_context->bios + data_offset);
1848
1849                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1850
1851                 if (!tv_dac)
1852                         return NULL;
1853
1854                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1855                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1856                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1859                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1860                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1861
1862                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1863                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1864                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1865
1866                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1867         }
1868         return tv_dac;
1869 }
1870
1871 static const char *thermal_controller_names[] = {
1872         "NONE",
1873         "lm63",
1874         "adm1032",
1875         "adm1030",
1876         "max6649",
1877         "lm63", /* lm64 */
1878         "f75375",
1879         "asc7xxx",
1880 };
1881
1882 static const char *pp_lib_thermal_controller_names[] = {
1883         "NONE",
1884         "lm63",
1885         "adm1032",
1886         "adm1030",
1887         "max6649",
1888         "lm63", /* lm64 */
1889         "f75375",
1890         "RV6xx",
1891         "RV770",
1892         "adt7473",
1893         "NONE",
1894         "External GPIO",
1895         "Evergreen",
1896         "emc2103",
1897         "Sumo",
1898         "Northern Islands",
1899 };
1900
1901 union power_info {
1902         struct _ATOM_POWERPLAY_INFO info;
1903         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1904         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1905         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1906         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1907         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1908 };
1909
1910 union pplib_clock_info {
1911         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1912         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1913         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1914         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1915 };
1916
1917 union pplib_power_state {
1918         struct _ATOM_PPLIB_STATE v1;
1919         struct _ATOM_PPLIB_STATE_V2 v2;
1920 };
1921
1922 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1923                                                  int state_index,
1924                                                  u32 misc, u32 misc2)
1925 {
1926         rdev->pm.power_state[state_index].misc = misc;
1927         rdev->pm.power_state[state_index].misc2 = misc2;
1928         /* order matters! */
1929         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1930                 rdev->pm.power_state[state_index].type =
1931                         POWER_STATE_TYPE_POWERSAVE;
1932         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1933                 rdev->pm.power_state[state_index].type =
1934                         POWER_STATE_TYPE_BATTERY;
1935         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1936                 rdev->pm.power_state[state_index].type =
1937                         POWER_STATE_TYPE_BATTERY;
1938         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1939                 rdev->pm.power_state[state_index].type =
1940                         POWER_STATE_TYPE_BALANCED;
1941         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1942                 rdev->pm.power_state[state_index].type =
1943                         POWER_STATE_TYPE_PERFORMANCE;
1944                 rdev->pm.power_state[state_index].flags &=
1945                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1946         }
1947         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1948                 rdev->pm.power_state[state_index].type =
1949                         POWER_STATE_TYPE_BALANCED;
1950         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1951                 rdev->pm.power_state[state_index].type =
1952                         POWER_STATE_TYPE_DEFAULT;
1953                 rdev->pm.default_power_state_index = state_index;
1954                 rdev->pm.power_state[state_index].default_clock_mode =
1955                         &rdev->pm.power_state[state_index].clock_info[0];
1956         } else if (state_index == 0) {
1957                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1958                         RADEON_PM_MODE_NO_DISPLAY;
1959         }
1960 }
1961
1962 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1963 {
1964         struct radeon_mode_info *mode_info = &rdev->mode_info;
1965         u32 misc, misc2 = 0;
1966         int num_modes = 0, i;
1967         int state_index = 0;
1968         struct radeon_i2c_bus_rec i2c_bus;
1969         union power_info *power_info;
1970         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1971         u16 data_offset;
1972         u8 frev, crev;
1973
1974         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1975                                    &frev, &crev, &data_offset))
1976                 return state_index;
1977         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1978
1979         /* add the i2c bus for thermal/fan chip */
1980         if (power_info->info.ucOverdriveThermalController > 0) {
1981                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1982                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1983                          power_info->info.ucOverdriveControllerAddress >> 1);
1984                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1985                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1986                 if (rdev->pm.i2c_bus) {
1987                         struct i2c_board_info info = { };
1988                         const char *name = thermal_controller_names[power_info->info.
1989                                                                     ucOverdriveThermalController];
1990                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1991                         strlcpy(info.type, name, sizeof(info.type));
1992                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1993                 }
1994         }
1995         num_modes = power_info->info.ucNumOfPowerModeEntries;
1996         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1997                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1998         if (num_modes == 0)
1999                 return state_index;
2000         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2001         if (!rdev->pm.power_state)
2002                 return state_index;
2003         /* last mode is usually default, array is low to high */
2004         for (i = 0; i < num_modes; i++) {
2005                 rdev->pm.power_state[state_index].clock_info =
2006                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2007                 if (!rdev->pm.power_state[state_index].clock_info)
2008                         return state_index;
2009                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2010                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2011                 switch (frev) {
2012                 case 1:
2013                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2014                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2015                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2016                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2017                         /* skip invalid modes */
2018                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2019                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2020                                 continue;
2021                         rdev->pm.power_state[state_index].pcie_lanes =
2022                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2023                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2024                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2025                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2026                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2027                                         VOLTAGE_GPIO;
2028                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2029                                         radeon_lookup_gpio(rdev,
2030                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2031                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2032                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2033                                                 true;
2034                                 else
2035                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2036                                                 false;
2037                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2038                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2039                                         VOLTAGE_VDDC;
2040                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2041                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2042                         }
2043                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2044                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2045                         state_index++;
2046                         break;
2047                 case 2:
2048                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2049                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2050                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2051                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2052                         /* skip invalid modes */
2053                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2054                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2055                                 continue;
2056                         rdev->pm.power_state[state_index].pcie_lanes =
2057                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2058                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2059                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2060                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2061                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2062                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2063                                         VOLTAGE_GPIO;
2064                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2065                                         radeon_lookup_gpio(rdev,
2066                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2067                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2068                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2069                                                 true;
2070                                 else
2071                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2072                                                 false;
2073                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2074                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2075                                         VOLTAGE_VDDC;
2076                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2077                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2078                         }
2079                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2080                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2081                         state_index++;
2082                         break;
2083                 case 3:
2084                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2085                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2086                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2087                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2088                         /* skip invalid modes */
2089                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2090                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2091                                 continue;
2092                         rdev->pm.power_state[state_index].pcie_lanes =
2093                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2094                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2095                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2096                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2097                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2098                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2099                                         VOLTAGE_GPIO;
2100                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2101                                         radeon_lookup_gpio(rdev,
2102                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2103                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2104                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2105                                                 true;
2106                                 else
2107                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2108                                                 false;
2109                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2110                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2111                                         VOLTAGE_VDDC;
2112                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2113                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2114                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2115                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2116                                                 true;
2117                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2118                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2119                                 }
2120                         }
2121                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2122                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2123                         state_index++;
2124                         break;
2125                 }
2126         }
2127         /* last mode is usually default */
2128         if (rdev->pm.default_power_state_index == -1) {
2129                 rdev->pm.power_state[state_index - 1].type =
2130                         POWER_STATE_TYPE_DEFAULT;
2131                 rdev->pm.default_power_state_index = state_index - 1;
2132                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2133                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2134                 rdev->pm.power_state[state_index].flags &=
2135                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2136                 rdev->pm.power_state[state_index].misc = 0;
2137                 rdev->pm.power_state[state_index].misc2 = 0;
2138         }
2139         return state_index;
2140 }
2141
2142 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2143                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2144 {
2145         struct radeon_i2c_bus_rec i2c_bus;
2146
2147         /* add the i2c bus for thermal/fan chip */
2148         if (controller->ucType > 0) {
2149                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2150                         DRM_INFO("Internal thermal controller %s fan control\n",
2151                                  (controller->ucFanParameters &
2152                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2153                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2154                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2155                         DRM_INFO("Internal thermal controller %s fan control\n",
2156                                  (controller->ucFanParameters &
2157                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2158                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2159                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2160                         DRM_INFO("Internal thermal controller %s fan control\n",
2161                                  (controller->ucFanParameters &
2162                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2163                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2164                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2165                         DRM_INFO("Internal thermal controller %s fan control\n",
2166                                  (controller->ucFanParameters &
2167                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2168                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2169                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2170                         DRM_INFO("Internal thermal controller %s fan control\n",
2171                                  (controller->ucFanParameters &
2172                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2173                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2174                 } else if ((controller->ucType ==
2175                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2176                            (controller->ucType ==
2177                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2178                            (controller->ucType ==
2179                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2180                         DRM_INFO("Special thermal controller config\n");
2181                 } else {
2182                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2183                                  pp_lib_thermal_controller_names[controller->ucType],
2184                                  controller->ucI2cAddress >> 1,
2185                                  (controller->ucFanParameters &
2186                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2187                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2188                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2189                         if (rdev->pm.i2c_bus) {
2190                                 struct i2c_board_info info = { };
2191                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2192                                 info.addr = controller->ucI2cAddress >> 1;
2193                                 strlcpy(info.type, name, sizeof(info.type));
2194                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2195                         }
2196                 }
2197         }
2198 }
2199
2200 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2201                                                  u16 *vddc, u16 *vddci)
2202 {
2203         struct radeon_mode_info *mode_info = &rdev->mode_info;
2204         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2205         u8 frev, crev;
2206         u16 data_offset;
2207         union firmware_info *firmware_info;
2208
2209         *vddc = 0;
2210         *vddci = 0;
2211
2212         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2213                                    &frev, &crev, &data_offset)) {
2214                 firmware_info =
2215                         (union firmware_info *)(mode_info->atom_context->bios +
2216                                                 data_offset);
2217                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2218                 if ((frev == 2) && (crev >= 2))
2219                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2220         }
2221 }
2222
2223 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2224                                                        int state_index, int mode_index,
2225                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2226 {
2227         int j;
2228         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2229         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2230         u16 vddc, vddci;
2231
2232         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2233
2234         rdev->pm.power_state[state_index].misc = misc;
2235         rdev->pm.power_state[state_index].misc2 = misc2;
2236         rdev->pm.power_state[state_index].pcie_lanes =
2237                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2238                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2239         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2240         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2241                 rdev->pm.power_state[state_index].type =
2242                         POWER_STATE_TYPE_BATTERY;
2243                 break;
2244         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2245                 rdev->pm.power_state[state_index].type =
2246                         POWER_STATE_TYPE_BALANCED;
2247                 break;
2248         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2249                 rdev->pm.power_state[state_index].type =
2250                         POWER_STATE_TYPE_PERFORMANCE;
2251                 break;
2252         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2253                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2254                         rdev->pm.power_state[state_index].type =
2255                                 POWER_STATE_TYPE_PERFORMANCE;
2256                 break;
2257         }
2258         rdev->pm.power_state[state_index].flags = 0;
2259         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2260                 rdev->pm.power_state[state_index].flags |=
2261                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2262         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2263                 rdev->pm.power_state[state_index].type =
2264                         POWER_STATE_TYPE_DEFAULT;
2265                 rdev->pm.default_power_state_index = state_index;
2266                 rdev->pm.power_state[state_index].default_clock_mode =
2267                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2268                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2269                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2270                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2271                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2272                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2273                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2274                 } else {
2275                         /* patch the table values with the default slck/mclk from firmware info */
2276                         for (j = 0; j < mode_index; j++) {
2277                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2278                                         rdev->clock.default_mclk;
2279                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2280                                         rdev->clock.default_sclk;
2281                                 if (vddc)
2282                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2283                                                 vddc;
2284                         }
2285                 }
2286         }
2287 }
2288
2289 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2290                                                    int state_index, int mode_index,
2291                                                    union pplib_clock_info *clock_info)
2292 {
2293         u32 sclk, mclk;
2294
2295         if (rdev->flags & RADEON_IS_IGP) {
2296                 if (rdev->family >= CHIP_PALM) {
2297                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2298                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2299                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2300                 } else {
2301                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2302                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2303                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2304                 }
2305         } else if (ASIC_IS_DCE4(rdev)) {
2306                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2307                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2308                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2309                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2310                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2311                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2312                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2313                         VOLTAGE_SW;
2314                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2315                         le16_to_cpu(clock_info->evergreen.usVDDC);
2316                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2317                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2318         } else {
2319                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2320                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2321                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2322                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2323                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2324                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2325                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2326                         VOLTAGE_SW;
2327                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2328                         le16_to_cpu(clock_info->r600.usVDDC);
2329         }
2330
2331         /* patch up vddc if necessary */
2332         if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2333                 u16 vddc;
2334
2335                 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2336                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2337         }
2338
2339         if (rdev->flags & RADEON_IS_IGP) {
2340                 /* skip invalid modes */
2341                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2342                         return false;
2343         } else {
2344                 /* skip invalid modes */
2345                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2346                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2347                         return false;
2348         }
2349         return true;
2350 }
2351
2352 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2353 {
2354         struct radeon_mode_info *mode_info = &rdev->mode_info;
2355         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2356         union pplib_power_state *power_state;
2357         int i, j;
2358         int state_index = 0, mode_index = 0;
2359         union pplib_clock_info *clock_info;
2360         bool valid;
2361         union power_info *power_info;
2362         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2363         u16 data_offset;
2364         u8 frev, crev;
2365
2366         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2367                                    &frev, &crev, &data_offset))
2368                 return state_index;
2369         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2370
2371         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2372         if (power_info->pplib.ucNumStates == 0)
2373                 return state_index;
2374         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2375                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2376         if (!rdev->pm.power_state)
2377                 return state_index;
2378         /* first mode is usually default, followed by low to high */
2379         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2380                 mode_index = 0;
2381                 power_state = (union pplib_power_state *)
2382                         (mode_info->atom_context->bios + data_offset +
2383                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2384                          i * power_info->pplib.ucStateEntrySize);
2385                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2386                         (mode_info->atom_context->bios + data_offset +
2387                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2388                          (power_state->v1.ucNonClockStateIndex *
2389                           power_info->pplib.ucNonClockSize));
2390                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2391                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2392                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2393                                                              GFP_KERNEL);
2394                 if (!rdev->pm.power_state[i].clock_info)
2395                         return state_index;
2396                 if (power_info->pplib.ucStateEntrySize - 1) {
2397                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2398                                 clock_info = (union pplib_clock_info *)
2399                                         (mode_info->atom_context->bios + data_offset +
2400                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2401                                          (power_state->v1.ucClockStateIndices[j] *
2402                                           power_info->pplib.ucClockInfoSize));
2403                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2404                                                                                state_index, mode_index,
2405                                                                                clock_info);
2406                                 if (valid)
2407                                         mode_index++;
2408                         }
2409                 } else {
2410                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2411                                 rdev->clock.default_mclk;
2412                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2413                                 rdev->clock.default_sclk;
2414                         mode_index++;
2415                 }
2416                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2417                 if (mode_index) {
2418                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2419                                                                    non_clock_info);
2420                         state_index++;
2421                 }
2422         }
2423         /* if multiple clock modes, mark the lowest as no display */
2424         for (i = 0; i < state_index; i++) {
2425                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2426                         rdev->pm.power_state[i].clock_info[0].flags |=
2427                                 RADEON_PM_MODE_NO_DISPLAY;
2428         }
2429         /* first mode is usually default */
2430         if (rdev->pm.default_power_state_index == -1) {
2431                 rdev->pm.power_state[0].type =
2432                         POWER_STATE_TYPE_DEFAULT;
2433                 rdev->pm.default_power_state_index = 0;
2434                 rdev->pm.power_state[0].default_clock_mode =
2435                         &rdev->pm.power_state[0].clock_info[0];
2436         }
2437         return state_index;
2438 }
2439
2440 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2441 {
2442         struct radeon_mode_info *mode_info = &rdev->mode_info;
2443         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2444         union pplib_power_state *power_state;
2445         int i, j, non_clock_array_index, clock_array_index;
2446         int state_index = 0, mode_index = 0;
2447         union pplib_clock_info *clock_info;
2448         struct StateArray *state_array;
2449         struct ClockInfoArray *clock_info_array;
2450         struct NonClockInfoArray *non_clock_info_array;
2451         bool valid;
2452         union power_info *power_info;
2453         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2454         u16 data_offset;
2455         u8 frev, crev;
2456         u8 *power_state_offset;
2457
2458         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2459                                    &frev, &crev, &data_offset))
2460                 return state_index;
2461         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2462
2463         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2464         state_array = (struct StateArray *)
2465                 (mode_info->atom_context->bios + data_offset +
2466                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2467         clock_info_array = (struct ClockInfoArray *)
2468                 (mode_info->atom_context->bios + data_offset +
2469                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2470         non_clock_info_array = (struct NonClockInfoArray *)
2471                 (mode_info->atom_context->bios + data_offset +
2472                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2473         if (state_array->ucNumEntries == 0)
2474                 return state_index;
2475         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2476                                        state_array->ucNumEntries, GFP_KERNEL);
2477         if (!rdev->pm.power_state)
2478                 return state_index;
2479         power_state_offset = (u8 *)state_array->states;
2480         for (i = 0; i < state_array->ucNumEntries; i++) {
2481                 mode_index = 0;
2482                 power_state = (union pplib_power_state *)power_state_offset;
2483                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2484                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2485                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2486                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2487                                                              (power_state->v2.ucNumDPMLevels ?
2488                                                               power_state->v2.ucNumDPMLevels : 1),
2489                                                              GFP_KERNEL);
2490                 if (!rdev->pm.power_state[i].clock_info)
2491                         return state_index;
2492                 if (power_state->v2.ucNumDPMLevels) {
2493                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2494                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2495                                 clock_info = (union pplib_clock_info *)
2496                                         &clock_info_array->clockInfo[clock_array_index];
2497                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2498                                                                                state_index, mode_index,
2499                                                                                clock_info);
2500                                 if (valid)
2501                                         mode_index++;
2502                         }
2503                 } else {
2504                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2505                                 rdev->clock.default_mclk;
2506                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2507                                 rdev->clock.default_sclk;
2508                         mode_index++;
2509                 }
2510                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2511                 if (mode_index) {
2512                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2513                                                                    non_clock_info);
2514                         state_index++;
2515                 }
2516                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2517         }
2518         /* if multiple clock modes, mark the lowest as no display */
2519         for (i = 0; i < state_index; i++) {
2520                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2521                         rdev->pm.power_state[i].clock_info[0].flags |=
2522                                 RADEON_PM_MODE_NO_DISPLAY;
2523         }
2524         /* first mode is usually default */
2525         if (rdev->pm.default_power_state_index == -1) {
2526                 rdev->pm.power_state[0].type =
2527                         POWER_STATE_TYPE_DEFAULT;
2528                 rdev->pm.default_power_state_index = 0;
2529                 rdev->pm.power_state[0].default_clock_mode =
2530                         &rdev->pm.power_state[0].clock_info[0];
2531         }
2532         return state_index;
2533 }
2534
2535 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2536 {
2537         struct radeon_mode_info *mode_info = &rdev->mode_info;
2538         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2539         u16 data_offset;
2540         u8 frev, crev;
2541         int state_index = 0;
2542
2543         rdev->pm.default_power_state_index = -1;
2544
2545         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2546                                    &frev, &crev, &data_offset)) {
2547                 switch (frev) {
2548                 case 1:
2549                 case 2:
2550                 case 3:
2551                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2552                         break;
2553                 case 4:
2554                 case 5:
2555                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2556                         break;
2557                 case 6:
2558                         state_index = radeon_atombios_parse_power_table_6(rdev);
2559                         break;
2560                 default:
2561                         break;
2562                 }
2563         }
2564
2565         if (state_index == 0) {
2566                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2567                 if (rdev->pm.power_state) {
2568                         rdev->pm.power_state[0].clock_info =
2569                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2570                         if (rdev->pm.power_state[0].clock_info) {
2571                                 /* add the default mode */
2572                                 rdev->pm.power_state[state_index].type =
2573                                         POWER_STATE_TYPE_DEFAULT;
2574                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2575                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2576                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2577                                 rdev->pm.power_state[state_index].default_clock_mode =
2578                                         &rdev->pm.power_state[state_index].clock_info[0];
2579                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2580                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2581                                 rdev->pm.default_power_state_index = state_index;
2582                                 rdev->pm.power_state[state_index].flags = 0;
2583                                 state_index++;
2584                         }
2585                 }
2586         }
2587
2588         rdev->pm.num_power_states = state_index;
2589
2590         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2591         rdev->pm.current_clock_mode_index = 0;
2592         if (rdev->pm.default_power_state_index >= 0)
2593                 rdev->pm.current_vddc =
2594                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2595         else
2596                 rdev->pm.current_vddc = 0;
2597 }
2598
2599 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2600 {
2601         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2602         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2603
2604         args.ucEnable = enable;
2605
2606         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2607 }
2608
2609 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2610 {
2611         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2612         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2613
2614         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2615         return le32_to_cpu(args.ulReturnEngineClock);
2616 }
2617
2618 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2619 {
2620         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2621         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2622
2623         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2624         return le32_to_cpu(args.ulReturnMemoryClock);
2625 }
2626
2627 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2628                                   uint32_t eng_clock)
2629 {
2630         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2631         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2632
2633         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2634
2635         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2636 }
2637
2638 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2639                                   uint32_t mem_clock)
2640 {
2641         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2642         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2643
2644         if (rdev->flags & RADEON_IS_IGP)
2645                 return;
2646
2647         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2648
2649         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2650 }
2651
2652 union set_voltage {
2653         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2654         struct _SET_VOLTAGE_PARAMETERS v1;
2655         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2656 };
2657
2658 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2659 {
2660         union set_voltage args;
2661         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2662         u8 frev, crev, volt_index = voltage_level;
2663
2664         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2665                 return;
2666
2667         /* 0xff01 is a flag rather then an actual voltage */
2668         if (voltage_level == 0xff01)
2669                 return;
2670
2671         switch (crev) {
2672         case 1:
2673                 args.v1.ucVoltageType = voltage_type;
2674                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2675                 args.v1.ucVoltageIndex = volt_index;
2676                 break;
2677         case 2:
2678                 args.v2.ucVoltageType = voltage_type;
2679                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2680                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2681                 break;
2682         default:
2683                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2684                 return;
2685         }
2686
2687         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2688 }
2689
2690 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2691                              u16 *voltage)
2692 {
2693         union set_voltage args;
2694         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2695         u8 frev, crev;
2696
2697         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2698                 return -EINVAL;
2699
2700         switch (crev) {
2701         case 1:
2702                 return -EINVAL;
2703         case 2:
2704                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2705                 args.v2.ucVoltageMode = 0;
2706                 args.v2.usVoltageLevel = 0;
2707
2708                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2709
2710                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2711                 break;
2712         default:
2713                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2714                 return -EINVAL;
2715         }
2716
2717         return 0;
2718 }
2719
2720 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2721 {
2722         struct radeon_device *rdev = dev->dev_private;
2723         uint32_t bios_2_scratch, bios_6_scratch;
2724
2725         if (rdev->family >= CHIP_R600) {
2726                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2727                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2728         } else {
2729                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2730                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2731         }
2732
2733         /* let the bios control the backlight */
2734         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2735
2736         /* tell the bios not to handle mode switching */
2737         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2738
2739         /* clear the vbios dpms state */
2740         if (ASIC_IS_DCE4(rdev))
2741                 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
2742
2743         if (rdev->family >= CHIP_R600) {
2744                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2745                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2746         } else {
2747                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2748                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2749         }
2750
2751 }
2752
2753 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2754 {
2755         uint32_t scratch_reg;
2756         int i;
2757
2758         if (rdev->family >= CHIP_R600)
2759                 scratch_reg = R600_BIOS_0_SCRATCH;
2760         else
2761                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2762
2763         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2764                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2765 }
2766
2767 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2768 {
2769         uint32_t scratch_reg;
2770         int i;
2771
2772         if (rdev->family >= CHIP_R600)
2773                 scratch_reg = R600_BIOS_0_SCRATCH;
2774         else
2775                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2776
2777         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2778                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2779 }
2780
2781 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2782 {
2783         struct drm_device *dev = encoder->dev;
2784         struct radeon_device *rdev = dev->dev_private;
2785         uint32_t bios_6_scratch;
2786
2787         if (rdev->family >= CHIP_R600)
2788                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2789         else
2790                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2791
2792         if (lock) {
2793                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2794                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2795         } else {
2796                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2797                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2798         }
2799
2800         if (rdev->family >= CHIP_R600)
2801                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2802         else
2803                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2804 }
2805
2806 /* at some point we may want to break this out into individual functions */
2807 void
2808 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2809                                        struct drm_encoder *encoder,
2810                                        bool connected)
2811 {
2812         struct drm_device *dev = connector->dev;
2813         struct radeon_device *rdev = dev->dev_private;
2814         struct radeon_connector *radeon_connector =
2815             to_radeon_connector(connector);
2816         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2817         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2818
2819         if (rdev->family >= CHIP_R600) {
2820                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2821                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2822                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2823         } else {
2824                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2825                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2826                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2827         }
2828
2829         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2830             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2831                 if (connected) {
2832                         DRM_DEBUG_KMS("TV1 connected\n");
2833                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2834                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2835                 } else {
2836                         DRM_DEBUG_KMS("TV1 disconnected\n");
2837                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2838                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2839                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2840                 }
2841         }
2842         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2843             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2844                 if (connected) {
2845                         DRM_DEBUG_KMS("CV connected\n");
2846                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2847                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2848                 } else {
2849                         DRM_DEBUG_KMS("CV disconnected\n");
2850                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2851                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2852                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2853                 }
2854         }
2855         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2856             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2857                 if (connected) {
2858                         DRM_DEBUG_KMS("LCD1 connected\n");
2859                         bios_0_scratch |= ATOM_S0_LCD1;
2860                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2861                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2862                 } else {
2863                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2864                         bios_0_scratch &= ~ATOM_S0_LCD1;
2865                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2866                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2867                 }
2868         }
2869         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2870             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2871                 if (connected) {
2872                         DRM_DEBUG_KMS("CRT1 connected\n");
2873                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2874                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2875                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2876                 } else {
2877                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2878                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2879                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2880                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2881                 }
2882         }
2883         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2884             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2885                 if (connected) {
2886                         DRM_DEBUG_KMS("CRT2 connected\n");
2887                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2888                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2889                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2890                 } else {
2891                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2892                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2893                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2894                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2895                 }
2896         }
2897         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2898             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2899                 if (connected) {
2900                         DRM_DEBUG_KMS("DFP1 connected\n");
2901                         bios_0_scratch |= ATOM_S0_DFP1;
2902                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2903                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2904                 } else {
2905                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2906                         bios_0_scratch &= ~ATOM_S0_DFP1;
2907                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2908                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2909                 }
2910         }
2911         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2912             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2913                 if (connected) {
2914                         DRM_DEBUG_KMS("DFP2 connected\n");
2915                         bios_0_scratch |= ATOM_S0_DFP2;
2916                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2917                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2918                 } else {
2919                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2920                         bios_0_scratch &= ~ATOM_S0_DFP2;
2921                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2922                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2923                 }
2924         }
2925         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2926             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2927                 if (connected) {
2928                         DRM_DEBUG_KMS("DFP3 connected\n");
2929                         bios_0_scratch |= ATOM_S0_DFP3;
2930                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2931                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2932                 } else {
2933                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2934                         bios_0_scratch &= ~ATOM_S0_DFP3;
2935                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2936                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2937                 }
2938         }
2939         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2940             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2941                 if (connected) {
2942                         DRM_DEBUG_KMS("DFP4 connected\n");
2943                         bios_0_scratch |= ATOM_S0_DFP4;
2944                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2945                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2946                 } else {
2947                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2948                         bios_0_scratch &= ~ATOM_S0_DFP4;
2949                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2950                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2951                 }
2952         }
2953         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2954             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2955                 if (connected) {
2956                         DRM_DEBUG_KMS("DFP5 connected\n");
2957                         bios_0_scratch |= ATOM_S0_DFP5;
2958                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2959                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2960                 } else {
2961                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2962                         bios_0_scratch &= ~ATOM_S0_DFP5;
2963                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2964                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2965                 }
2966         }
2967
2968         if (rdev->family >= CHIP_R600) {
2969                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2970                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2971                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2972         } else {
2973                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2974                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2975                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2976         }
2977 }
2978
2979 void
2980 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2981 {
2982         struct drm_device *dev = encoder->dev;
2983         struct radeon_device *rdev = dev->dev_private;
2984         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2985         uint32_t bios_3_scratch;
2986
2987         if (rdev->family >= CHIP_R600)
2988                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2989         else
2990                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2991
2992         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2993                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2994                 bios_3_scratch |= (crtc << 18);
2995         }
2996         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2997                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2998                 bios_3_scratch |= (crtc << 24);
2999         }
3000         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3001                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3002                 bios_3_scratch |= (crtc << 16);
3003         }
3004         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3005                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3006                 bios_3_scratch |= (crtc << 20);
3007         }
3008         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3009                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3010                 bios_3_scratch |= (crtc << 17);
3011         }
3012         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3013                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3014                 bios_3_scratch |= (crtc << 19);
3015         }
3016         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3017                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3018                 bios_3_scratch |= (crtc << 23);
3019         }
3020         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3021                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3022                 bios_3_scratch |= (crtc << 25);
3023         }
3024
3025         if (rdev->family >= CHIP_R600)
3026                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3027         else
3028                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3029 }
3030
3031 void
3032 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3033 {
3034         struct drm_device *dev = encoder->dev;
3035         struct radeon_device *rdev = dev->dev_private;
3036         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3037         uint32_t bios_2_scratch;
3038
3039         if (rdev->family >= CHIP_R600)
3040                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3041         else
3042                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3043
3044         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3045                 if (on)
3046                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3047                 else
3048                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3049         }
3050         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3051                 if (on)
3052                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3053                 else
3054                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3055         }
3056         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3057                 if (on)
3058                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3059                 else
3060                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3061         }
3062         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3063                 if (on)
3064                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3065                 else
3066                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3067         }
3068         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3069                 if (on)
3070                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3071                 else
3072                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3073         }
3074         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3075                 if (on)
3076                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3077                 else
3078                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3079         }
3080         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3081                 if (on)
3082                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3083                 else
3084                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3085         }
3086         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3087                 if (on)
3088                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3089                 else
3090                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3091         }
3092         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3093                 if (on)
3094                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3095                 else
3096                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3097         }
3098         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3099                 if (on)
3100                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3101                 else
3102                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3103         }
3104
3105         if (rdev->family >= CHIP_R600)
3106                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3107         else
3108                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3109 }