drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73         int i;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  79
  80         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82
  83         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  84                 gpio = &i2c_info->asGPIO_Info[i];
  85
  86                 if (gpio->sucI2cId.ucAccess == id) {
  87                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  88                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  89                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  90                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  91                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  92                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  93                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  94                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  95                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  96                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  97                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  98                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  99                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 100                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 101                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 102                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 103
 104                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 105                                 i2c.hw_capable = true;
 106                         else
 107                                 i2c.hw_capable = false;
 108
 109                         if (gpio->sucI2cId.ucAccess == 0xa0)
 110                                 i2c.mm_i2c = true;
 111                         else
 112                                 i2c.mm_i2c = false;
 113
 114                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 115
 116                         i2c.valid = true;
 117                 }
 118         }
 119
 120         return i2c;
 121 }
 122
 123 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 124                                                         u8 id)
 125 {
 126         struct atom_context *ctx = rdev->mode_info.atom_context;
 127         struct radeon_gpio_rec gpio;
 128         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 129         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 130         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 131         u16 data_offset, size;
 132         int i, num_indices;
 133
 134         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 135         gpio.valid = false;
 136
 137         atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
 138
 139         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 140
 141         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 142
 143         for (i = 0; i < num_indices; i++) {
 144                 pin = &gpio_info->asGPIO_Pin[i];
 145                 if (id == pin->ucGPIO_ID) {
 146                         gpio.id = pin->ucGPIO_ID;
 147                         gpio.reg = pin->usGpioPin_AIndex * 4;
 148                         gpio.mask = (1 << pin->ucGpioPinBitShift);
 149                         gpio.valid = true;
 150                         break;
 151                 }
 152         }
 153
 154         return gpio;
 155 }
 156
 157 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 158                                                             struct radeon_gpio_rec *gpio)
 159 {
 160         struct radeon_hpd hpd;
 161         hpd.gpio = *gpio;
 162         if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
 163                 switch(gpio->mask) {
 164                 case (1 << 0):
 165                         hpd.hpd = RADEON_HPD_1;
 166                         break;
 167                 case (1 << 8):
 168                         hpd.hpd = RADEON_HPD_2;
 169                         break;
 170                 case (1 << 16):
 171                         hpd.hpd = RADEON_HPD_3;
 172                         break;
 173                 case (1 << 24):
 174                         hpd.hpd = RADEON_HPD_4;
 175                         break;
 176                 case (1 << 26):
 177                         hpd.hpd = RADEON_HPD_5;
 178                         break;
 179                 case (1 << 28):
 180                         hpd.hpd = RADEON_HPD_6;
 181                         break;
 182                 default:
 183                         hpd.hpd = RADEON_HPD_NONE;
 184                         break;
 185                 }
 186         } else
 187                 hpd.hpd = RADEON_HPD_NONE;
 188         return hpd;
 189 }
 190
 191 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 192                                      uint32_t supported_device,
 193                                      int *connector_type,
 194                                      struct radeon_i2c_bus_rec *i2c_bus,
 195                                      uint16_t *line_mux,
 196                                      struct radeon_hpd *hpd)
 197 {
 198
 199         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 200         if ((dev->pdev->device == 0x791e) &&
 201             (dev->pdev->subsystem_vendor == 0x1043) &&
 202             (dev->pdev->subsystem_device == 0x826d)) {
 203                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 204                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 205                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 206         }
 207
 208         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 209         if ((dev->pdev->device == 0x7941) &&
 210             (dev->pdev->subsystem_vendor == 0x147b) &&
 211             (dev->pdev->subsystem_device == 0x2412)) {
 212                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 213                         return false;
 214         }
 215
 216         /* Falcon NW laptop lists vga ddc line for LVDS */
 217         if ((dev->pdev->device == 0x5653) &&
 218             (dev->pdev->subsystem_vendor == 0x1462) &&
 219             (dev->pdev->subsystem_device == 0x0291)) {
 220                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 221                         i2c_bus->valid = false;
 222                         *line_mux = 53;
 223                 }
 224         }
 225
 226         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 227         if ((dev->pdev->device == 0x7146) &&
 228             (dev->pdev->subsystem_vendor == 0x17af) &&
 229             (dev->pdev->subsystem_device == 0x2058)) {
 230                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 231                         return false;
 232         }
 233
 234         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 235         if ((dev->pdev->device == 0x7142) &&
 236             (dev->pdev->subsystem_vendor == 0x1458) &&
 237             (dev->pdev->subsystem_device == 0x2134)) {
 238                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 239                         return false;
 240         }
 241
 242
 243         /* Funky macbooks */
 244         if ((dev->pdev->device == 0x71C5) &&
 245             (dev->pdev->subsystem_vendor == 0x106b) &&
 246             (dev->pdev->subsystem_device == 0x0080)) {
 247                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 248                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 249                         return false;
 250         }
 251
 252         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 253         if ((dev->pdev->device == 0x9598) &&
 254             (dev->pdev->subsystem_vendor == 0x1043) &&
 255             (dev->pdev->subsystem_device == 0x01da)) {
 256                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 257                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 258                 }
 259         }
 260
 261         /* ASUS HD 3450 board lists the DVI port as HDMI */
 262         if ((dev->pdev->device == 0x95C5) &&
 263             (dev->pdev->subsystem_vendor == 0x1043) &&
 264             (dev->pdev->subsystem_device == 0x01e2)) {
 265                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 266                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 267                 }
 268         }
 269
 270         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 271          * HDMI + VGA reporting as HDMI
 272          */
 273         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 274                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 275                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 276                         *line_mux = 0;
 277                 }
 278         }
 279
 280         /* Acer laptop reports DVI-D as DVI-I */
 281         if ((dev->pdev->device == 0x95c4) &&
 282             (dev->pdev->subsystem_vendor == 0x1025) &&
 283             (dev->pdev->subsystem_device == 0x013c)) {
 284                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 285                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 286                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 287         }
 288
 289         return true;
 290 }
 291
 292 const int supported_devices_connector_convert[] = {
 293         DRM_MODE_CONNECTOR_Unknown,
 294         DRM_MODE_CONNECTOR_VGA,
 295         DRM_MODE_CONNECTOR_DVII,
 296         DRM_MODE_CONNECTOR_DVID,
 297         DRM_MODE_CONNECTOR_DVIA,
 298         DRM_MODE_CONNECTOR_SVIDEO,
 299         DRM_MODE_CONNECTOR_Composite,
 300         DRM_MODE_CONNECTOR_LVDS,
 301         DRM_MODE_CONNECTOR_Unknown,
 302         DRM_MODE_CONNECTOR_Unknown,
 303         DRM_MODE_CONNECTOR_HDMIA,
 304         DRM_MODE_CONNECTOR_HDMIB,
 305         DRM_MODE_CONNECTOR_Unknown,
 306         DRM_MODE_CONNECTOR_Unknown,
 307         DRM_MODE_CONNECTOR_9PinDIN,
 308         DRM_MODE_CONNECTOR_DisplayPort
 309 };
 310
 311 const uint16_t supported_devices_connector_object_id_convert[] = {
 312         CONNECTOR_OBJECT_ID_NONE,
 313         CONNECTOR_OBJECT_ID_VGA,
 314         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 315         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 316         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 317         CONNECTOR_OBJECT_ID_COMPOSITE,
 318         CONNECTOR_OBJECT_ID_SVIDEO,
 319         CONNECTOR_OBJECT_ID_LVDS,
 320         CONNECTOR_OBJECT_ID_9PIN_DIN,
 321         CONNECTOR_OBJECT_ID_9PIN_DIN,
 322         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 323         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 324         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 325         CONNECTOR_OBJECT_ID_SVIDEO
 326 };
 327
 328 const int object_connector_convert[] = {
 329         DRM_MODE_CONNECTOR_Unknown,
 330         DRM_MODE_CONNECTOR_DVII,
 331         DRM_MODE_CONNECTOR_DVII,
 332         DRM_MODE_CONNECTOR_DVID,
 333         DRM_MODE_CONNECTOR_DVID,
 334         DRM_MODE_CONNECTOR_VGA,
 335         DRM_MODE_CONNECTOR_Composite,
 336         DRM_MODE_CONNECTOR_SVIDEO,
 337         DRM_MODE_CONNECTOR_Unknown,
 338         DRM_MODE_CONNECTOR_Unknown,
 339         DRM_MODE_CONNECTOR_9PinDIN,
 340         DRM_MODE_CONNECTOR_Unknown,
 341         DRM_MODE_CONNECTOR_HDMIA,
 342         DRM_MODE_CONNECTOR_HDMIB,
 343         DRM_MODE_CONNECTOR_LVDS,
 344         DRM_MODE_CONNECTOR_9PinDIN,
 345         DRM_MODE_CONNECTOR_Unknown,
 346         DRM_MODE_CONNECTOR_Unknown,
 347         DRM_MODE_CONNECTOR_Unknown,
 348         DRM_MODE_CONNECTOR_DisplayPort
 349 };
 350
 351 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 352 {
 353         struct radeon_device *rdev = dev->dev_private;
 354         struct radeon_mode_info *mode_info = &rdev->mode_info;
 355         struct atom_context *ctx = mode_info->atom_context;
 356         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 357         u16 size, data_offset;
 358         u8 frev, crev;
 359         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 360         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 361         ATOM_OBJECT_HEADER *obj_header;
 362         int i, j, path_size, device_support;
 363         int connector_type;
 364         u16 igp_lane_info, conn_id, connector_object_id;
 365         bool linkb;
 366         struct radeon_i2c_bus_rec ddc_bus;
 367         struct radeon_gpio_rec gpio;
 368         struct radeon_hpd hpd;
 369
 370         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 371
 372         if (data_offset == 0)
 373                 return false;
 374
 375         if (crev < 2)
 376                 return false;
 377
 378         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 379         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 380             (ctx->bios + data_offset +
 381              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 382         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 383             (ctx->bios + data_offset +
 384              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 385         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 386
 387         path_size = 0;
 388         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 389                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 390                 ATOM_DISPLAY_OBJECT_PATH *path;
 391                 addr += path_size;
 392                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 393                 path_size += le16_to_cpu(path->usSize);
 394                 linkb = false;
 395                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 396                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 397
 398                         con_obj_id =
 399                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 400                             >> OBJECT_ID_SHIFT;
 401                         con_obj_num =
 402                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 403                             >> ENUM_ID_SHIFT;
 404                         con_obj_type =
 405                             (le16_to_cpu(path->usConnObjectId) &
 406                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 407
 408                         /* TODO CV support */
 409                         if (le16_to_cpu(path->usDeviceTag) ==
 410                                 ATOM_DEVICE_CV_SUPPORT)
 411                                 continue;
 412
 413                         /* IGP chips */
 414                         if ((rdev->flags & RADEON_IS_IGP) &&
 415                             (con_obj_id ==
 416                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 417                                 uint16_t igp_offset = 0;
 418                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 419
 420                                 index =
 421                                     GetIndexIntoMasterTable(DATA,
 422                                                             IntegratedSystemInfo);
 423
 424                                 atom_parse_data_header(ctx, index, &size, &frev,
 425                                                        &crev, &igp_offset);
 426
 427                                 if (crev >= 2) {
 428                                         igp_obj =
 429                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 430                                              *) (ctx->bios + igp_offset);
 431
 432                                         if (igp_obj) {
 433                                                 uint32_t slot_config, ct;
 434
 435                                                 if (con_obj_num == 1)
 436                                                         slot_config =
 437                                                             igp_obj->
 438                                                             ulDDISlot1Config;
 439                                                 else
 440                                                         slot_config =
 441                                                             igp_obj->
 442                                                             ulDDISlot2Config;
 443
 444                                                 ct = (slot_config >> 16) & 0xff;
 445                                                 connector_type =
 446                                                     object_connector_convert
 447                                                     [ct];
 448                                                 connector_object_id = ct;
 449                                                 igp_lane_info =
 450                                                     slot_config & 0xffff;
 451                                         } else
 452                                                 continue;
 453                                 } else
 454                                         continue;
 455                         } else {
 456                                 igp_lane_info = 0;
 457                                 connector_type =
 458                                     object_connector_convert[con_obj_id];
 459                                 connector_object_id = con_obj_id;
 460                         }
 461
 462                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 463                                 continue;
 464
 465                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 466                              j++) {
 467                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 468
 469                                 enc_obj_id =
 470                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 471                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 472                                 enc_obj_num =
 473                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 474                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 475                                 enc_obj_type =
 476                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 477                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 478
 479                                 /* FIXME: add support for router objects */
 480                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 481                                         if (enc_obj_num == 2)
 482                                                 linkb = true;
 483                                         else
 484                                                 linkb = false;
 485
 486                                         radeon_add_atom_encoder(dev,
 487                                                                 enc_obj_id,
 488                                                                 le16_to_cpu
 489                                                                 (path->
 490                                                                  usDeviceTag));
 491
 492                                 }
 493                         }
 494
 495                         /* look up gpio for ddc, hpd */
 496                         if ((le16_to_cpu(path->usDeviceTag) &
 497                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 498                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 499                                         if (le16_to_cpu(path->usConnObjectId) ==
 500                                             le16_to_cpu(con_obj->asObjects[j].
 501                                                         usObjectID)) {
 502                                                 ATOM_COMMON_RECORD_HEADER
 503                                                     *record =
 504                                                     (ATOM_COMMON_RECORD_HEADER
 505                                                      *)
 506                                                     (ctx->bios + data_offset +
 507                                                      le16_to_cpu(con_obj->
 508                                                                  asObjects[j].
 509                                                                  usRecordOffset));
 510                                                 ATOM_I2C_RECORD *i2c_record;
 511                                                 ATOM_HPD_INT_RECORD *hpd_record;
 512                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 513                                                 hpd.hpd = RADEON_HPD_NONE;
 514
 515                                                 while (record->ucRecordType > 0
 516                                                        && record->
 517                                                        ucRecordType <=
 518                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 519                                                         switch (record->ucRecordType) {
 520                                                         case ATOM_I2C_RECORD_TYPE:
 521                                                                 i2c_record =
 522                                                                     (ATOM_I2C_RECORD *)
 523                                                                         record;
 524                                                                 i2c_config =
 525                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 526                                                                         &i2c_record->sucI2cId;
 527                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 528                                                                                                  i2c_config->
 529                                                                                                  ucAccess);
 530                                                                 break;
 531                                                         case ATOM_HPD_INT_RECORD_TYPE:
 532                                                                 hpd_record =
 533                                                                         (ATOM_HPD_INT_RECORD *)
 534                                                                         record;
 535                                                                 gpio = radeon_lookup_gpio(rdev,
 536                                                                                           hpd_record->ucHPDIntGPIOID);
 537                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 538                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 539                                                                 break;
 540                                                         }
 541                                                         record =
 542                                                             (ATOM_COMMON_RECORD_HEADER
 543                                                              *) ((char *)record
 544                                                                  +
 545                                                                  record->
 546                                                                  ucRecordSize);
 547                                                 }
 548                                                 break;
 549                                         }
 550                                 }
 551                         } else {
 552                                 hpd.hpd = RADEON_HPD_NONE;
 553                                 ddc_bus.valid = false;
 554                         }
 555
 556                         conn_id = le16_to_cpu(path->usConnObjectId);
 557
 558                         if (!radeon_atom_apply_quirks
 559                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 560                              &ddc_bus, &conn_id, &hpd))
 561                                 continue;
 562
 563                         radeon_add_atom_connector(dev,
 564                                                   conn_id,
 565                                                   le16_to_cpu(path->
 566                                                               usDeviceTag),
 567                                                   connector_type, &ddc_bus,
 568                                                   linkb, igp_lane_info,
 569                                                   connector_object_id,
 570                                                   &hpd);
 571
 572                 }
 573         }
 574
 575         radeon_link_encoder_connector(dev);
 576
 577         return true;
 578 }
 579
 580 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 581                                                  int connector_type,
 582                                                  uint16_t devices)
 583 {
 584         struct radeon_device *rdev = dev->dev_private;
 585
 586         if (rdev->flags & RADEON_IS_IGP) {
 587                 return supported_devices_connector_object_id_convert
 588                         [connector_type];
 589         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 590                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 591                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 592                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 593                 struct atom_context *ctx = mode_info->atom_context;
 594                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 595                 uint16_t size, data_offset;
 596                 uint8_t frev, crev;
 597                 ATOM_XTMDS_INFO *xtmds;
 598
 599                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 600                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 601
 602                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 603                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 604                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 605                         else
 606                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 607                 } else {
 608                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 609                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 610                         else
 611                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 612                 }
 613         } else {
 614                 return supported_devices_connector_object_id_convert
 615                         [connector_type];
 616         }
 617 }
 618
 619 struct bios_connector {
 620         bool valid;
 621         uint16_t line_mux;
 622         uint16_t devices;
 623         int connector_type;
 624         struct radeon_i2c_bus_rec ddc_bus;
 625         struct radeon_hpd hpd;
 626 };
 627
 628 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 629                                                                  drm_device
 630                                                                  *dev)
 631 {
 632         struct radeon_device *rdev = dev->dev_private;
 633         struct radeon_mode_info *mode_info = &rdev->mode_info;
 634         struct atom_context *ctx = mode_info->atom_context;
 635         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 636         uint16_t size, data_offset;
 637         uint8_t frev, crev;
 638         uint16_t device_support;
 639         uint8_t dac;
 640         union atom_supported_devices *supported_devices;
 641         int i, j, max_device;
 642         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 643
 644         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 645
 646         supported_devices =
 647             (union atom_supported_devices *)(ctx->bios + data_offset);
 648
 649         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 650
 651         if (frev > 1)
 652                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 653         else
 654                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 655
 656         for (i = 0; i < max_device; i++) {
 657                 ATOM_CONNECTOR_INFO_I2C ci =
 658                     supported_devices->info.asConnInfo[i];
 659
 660                 bios_connectors[i].valid = false;
 661
 662                 if (!(device_support & (1 << i))) {
 663                         continue;
 664                 }
 665
 666                 if (i == ATOM_DEVICE_CV_INDEX) {
 667                         DRM_DEBUG("Skipping Component Video\n");
 668                         continue;
 669                 }
 670
 671                 bios_connectors[i].connector_type =
 672                     supported_devices_connector_convert[ci.sucConnectorInfo.
 673                                                         sbfAccess.
 674                                                         bfConnectorType];
 675
 676                 if (bios_connectors[i].connector_type ==
 677                     DRM_MODE_CONNECTOR_Unknown)
 678                         continue;
 679
 680                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 681
 682                 bios_connectors[i].line_mux =
 683                         ci.sucI2cId.ucAccess;
 684
 685                 /* give tv unique connector ids */
 686                 if (i == ATOM_DEVICE_TV1_INDEX) {
 687                         bios_connectors[i].ddc_bus.valid = false;
 688                         bios_connectors[i].line_mux = 50;
 689                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 690                         bios_connectors[i].ddc_bus.valid = false;
 691                         bios_connectors[i].line_mux = 51;
 692                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 693                         bios_connectors[i].ddc_bus.valid = false;
 694                         bios_connectors[i].line_mux = 52;
 695                 } else
 696                         bios_connectors[i].ddc_bus =
 697                             radeon_lookup_i2c_gpio(rdev,
 698                                                    bios_connectors[i].line_mux);
 699
 700                 if ((crev > 1) && (frev > 1)) {
 701                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 702                         switch (isb) {
 703                         case 0x4:
 704                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 705                                 break;
 706                         case 0xa:
 707                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 708                                 break;
 709                         default:
 710                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 711                                 break;
 712                         }
 713                 } else {
 714                         if (i == ATOM_DEVICE_DFP1_INDEX)
 715                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 716                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 717                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 718                         else
 719                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 720                 }
 721
 722                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 723                  * shared with a DVI port, we'll pick up the DVI connector when we
 724                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 725                  */
 726                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 727                         bios_connectors[i].connector_type =
 728                             DRM_MODE_CONNECTOR_VGA;
 729
 730                 if (!radeon_atom_apply_quirks
 731                     (dev, (1 << i), &bios_connectors[i].connector_type,
 732                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 733                      &bios_connectors[i].hpd))
 734                         continue;
 735
 736                 bios_connectors[i].valid = true;
 737                 bios_connectors[i].devices = (1 << i);
 738
 739                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 740                         radeon_add_atom_encoder(dev,
 741                                                 radeon_get_encoder_id(dev,
 742                                                                       (1 << i),
 743                                                                       dac),
 744                                                 (1 << i));
 745                 else
 746                         radeon_add_legacy_encoder(dev,
 747                                                   radeon_get_encoder_id(dev,
 748                                                                         (1 << i),
 749                                                                         dac),
 750                                                   (1 << i));
 751         }
 752
 753         /* combine shared connectors */
 754         for (i = 0; i < max_device; i++) {
 755                 if (bios_connectors[i].valid) {
 756                         for (j = 0; j < max_device; j++) {
 757                                 if (bios_connectors[j].valid && (i != j)) {
 758                                         if (bios_connectors[i].line_mux ==
 759                                             bios_connectors[j].line_mux) {
 760                                                 /* make sure not to combine LVDS */
 761                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 762                                                         bios_connectors[i].line_mux = 53;
 763                                                         bios_connectors[i].ddc_bus.valid = false;
 764                                                         continue;
 765                                                 }
 766                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 767                                                         bios_connectors[j].line_mux = 53;
 768                                                         bios_connectors[j].ddc_bus.valid = false;
 769                                                         continue;
 770                                                 }
 771                                                 /* combine analog and digital for DVI-I */
 772                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 773                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 774                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 775                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 776                                                         bios_connectors[i].devices |=
 777                                                                 bios_connectors[j].devices;
 778                                                         bios_connectors[i].connector_type =
 779                                                                 DRM_MODE_CONNECTOR_DVII;
 780                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 781                                                                 bios_connectors[i].hpd =
 782                                                                         bios_connectors[j].hpd;
 783                                                         bios_connectors[j].valid = false;
 784                                                 }
 785                                         }
 786                                 }
 787                         }
 788                 }
 789         }
 790
 791         /* add the connectors */
 792         for (i = 0; i < max_device; i++) {
 793                 if (bios_connectors[i].valid) {
 794                         uint16_t connector_object_id =
 795                                 atombios_get_connector_object_id(dev,
 796                                                       bios_connectors[i].connector_type,
 797                                                       bios_connectors[i].devices);
 798                         radeon_add_atom_connector(dev,
 799                                                   bios_connectors[i].line_mux,
 800                                                   bios_connectors[i].devices,
 801                                                   bios_connectors[i].
 802                                                   connector_type,
 803                                                   &bios_connectors[i].ddc_bus,
 804                                                   false, 0,
 805                                                   connector_object_id,
 806                                                   &bios_connectors[i].hpd);
 807                 }
 808         }
 809
 810         radeon_link_encoder_connector(dev);
 811
 812         return true;
 813 }
 814
 815 union firmware_info {
 816         ATOM_FIRMWARE_INFO info;
 817         ATOM_FIRMWARE_INFO_V1_2 info_12;
 818         ATOM_FIRMWARE_INFO_V1_3 info_13;
 819         ATOM_FIRMWARE_INFO_V1_4 info_14;
 820 };
 821
 822 bool radeon_atom_get_clock_info(struct drm_device *dev)
 823 {
 824         struct radeon_device *rdev = dev->dev_private;
 825         struct radeon_mode_info *mode_info = &rdev->mode_info;
 826         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 827         union firmware_info *firmware_info;
 828         uint8_t frev, crev;
 829         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 830         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 831         struct radeon_pll *spll = &rdev->clock.spll;
 832         struct radeon_pll *mpll = &rdev->clock.mpll;
 833         uint16_t data_offset;
 834
 835         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 836                                &crev, &data_offset);
 837
 838         firmware_info =
 839             (union firmware_info *)(mode_info->atom_context->bios +
 840                                     data_offset);
 841
 842         if (firmware_info) {
 843                 /* pixel clocks */
 844                 p1pll->reference_freq =
 845                     le16_to_cpu(firmware_info->info.usReferenceClock);
 846                 p1pll->reference_div = 0;
 847
 848                 if (crev < 2)
 849                         p1pll->pll_out_min =
 850                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 851                 else
 852                         p1pll->pll_out_min =
 853                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 854                 p1pll->pll_out_max =
 855                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 856
 857                 if (p1pll->pll_out_min == 0) {
 858                         if (ASIC_IS_AVIVO(rdev))
 859                                 p1pll->pll_out_min = 64800;
 860                         else
 861                                 p1pll->pll_out_min = 20000;
 862                 } else if (p1pll->pll_out_min > 64800) {
 863                         /* Limiting the pll output range is a good thing generally as
 864                          * it limits the number of possible pll combinations for a given
 865                          * frequency presumably to the ones that work best on each card.
 866                          * However, certain duallink DVI monitors seem to like
 867                          * pll combinations that would be limited by this at least on
 868                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 869                          * family.
 870                          */
 871                         if (!radeon_new_pll)
 872                                 p1pll->pll_out_min = 64800;
 873                 }
 874
 875                 p1pll->pll_in_min =
 876                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 877                 p1pll->pll_in_max =
 878                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 879
 880                 *p2pll = *p1pll;
 881
 882                 /* system clock */
 883                 spll->reference_freq =
 884                     le16_to_cpu(firmware_info->info.usReferenceClock);
 885                 spll->reference_div = 0;
 886
 887                 spll->pll_out_min =
 888                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 889                 spll->pll_out_max =
 890                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 891
 892                 /* ??? */
 893                 if (spll->pll_out_min == 0) {
 894                         if (ASIC_IS_AVIVO(rdev))
 895                                 spll->pll_out_min = 64800;
 896                         else
 897                                 spll->pll_out_min = 20000;
 898                 }
 899
 900                 spll->pll_in_min =
 901                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 902                 spll->pll_in_max =
 903                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 904
 905                 /* memory clock */
 906                 mpll->reference_freq =
 907                     le16_to_cpu(firmware_info->info.usReferenceClock);
 908                 mpll->reference_div = 0;
 909
 910                 mpll->pll_out_min =
 911                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 912                 mpll->pll_out_max =
 913                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 914
 915                 /* ??? */
 916                 if (mpll->pll_out_min == 0) {
 917                         if (ASIC_IS_AVIVO(rdev))
 918                                 mpll->pll_out_min = 64800;
 919                         else
 920                                 mpll->pll_out_min = 20000;
 921                 }
 922
 923                 mpll->pll_in_min =
 924                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 925                 mpll->pll_in_max =
 926                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 927
 928                 rdev->clock.default_sclk =
 929                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 930                 rdev->clock.default_mclk =
 931                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 932
 933                 return true;
 934         }
 935         return false;
 936 }
 937
 938 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 939                                    struct radeon_encoder_int_tmds *tmds)
 940 {
 941         struct drm_device *dev = encoder->base.dev;
 942         struct radeon_device *rdev = dev->dev_private;
 943         struct radeon_mode_info *mode_info = &rdev->mode_info;
 944         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
 945         uint16_t data_offset;
 946         struct _ATOM_TMDS_INFO *tmds_info;
 947         uint8_t frev, crev;
 948         uint16_t maxfreq;
 949         int i;
 950
 951         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 952                                &crev, &data_offset);
 953
 954         tmds_info =
 955             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
 956                                        data_offset);
 957
 958         if (tmds_info) {
 959                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
 960                 for (i = 0; i < 4; i++) {
 961                         tmds->tmds_pll[i].freq =
 962                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
 963                         tmds->tmds_pll[i].value =
 964                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
 965                         tmds->tmds_pll[i].value |=
 966                             (tmds_info->asMiscInfo[i].
 967                              ucPLL_VCO_Gain & 0x3f) << 6;
 968                         tmds->tmds_pll[i].value |=
 969                             (tmds_info->asMiscInfo[i].
 970                              ucPLL_DutyCycle & 0xf) << 12;
 971                         tmds->tmds_pll[i].value |=
 972                             (tmds_info->asMiscInfo[i].
 973                              ucPLL_VoltageSwing & 0xf) << 16;
 974
 975                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
 976                                   tmds->tmds_pll[i].freq,
 977                                   tmds->tmds_pll[i].value);
 978
 979                         if (maxfreq == tmds->tmds_pll[i].freq) {
 980                                 tmds->tmds_pll[i].freq = 0xffffffff;
 981                                 break;
 982                         }
 983                 }
 984                 return true;
 985         }
 986         return false;
 987 }
 988
 989 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
 990                                                           radeon_encoder
 991                                                           *encoder,
 992                                                           int id)
 993 {
 994         struct drm_device *dev = encoder->base.dev;
 995         struct radeon_device *rdev = dev->dev_private;
 996         struct radeon_mode_info *mode_info = &rdev->mode_info;
 997         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
 998         uint16_t data_offset;
 999         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1000         uint8_t frev, crev;
1001         struct radeon_atom_ss *ss = NULL;
1002         int i;
1003
1004         if (id > ATOM_MAX_SS_ENTRY)
1005                 return NULL;
1006
1007         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1008                                &crev, &data_offset);
1009
1010         ss_info =
1011             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1012
1013         if (ss_info) {
1014                 ss =
1015                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1016
1017                 if (!ss)
1018                         return NULL;
1019
1020                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1021                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1022                                 ss->percentage =
1023                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1024                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1025                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1026                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1027                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1028                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1029                         }
1030                 }
1031         }
1032         return ss;
1033 }
1034
1035 union lvds_info {
1036         struct _ATOM_LVDS_INFO info;
1037         struct _ATOM_LVDS_INFO_V12 info_12;
1038 };
1039
1040 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1041                                                               radeon_encoder
1042                                                               *encoder)
1043 {
1044         struct drm_device *dev = encoder->base.dev;
1045         struct radeon_device *rdev = dev->dev_private;
1046         struct radeon_mode_info *mode_info = &rdev->mode_info;
1047         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1048         uint16_t data_offset, misc;
1049         union lvds_info *lvds_info;
1050         uint8_t frev, crev;
1051         struct radeon_encoder_atom_dig *lvds = NULL;
1052
1053         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1054                                &crev, &data_offset);
1055
1056         lvds_info =
1057             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1058
1059         if (lvds_info) {
1060                 lvds =
1061                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1062
1063                 if (!lvds)
1064                         return NULL;
1065
1066                 lvds->native_mode.clock =
1067                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1068                 lvds->native_mode.hdisplay =
1069                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1070                 lvds->native_mode.vdisplay =
1071                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1072                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1073                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1074                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1075                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1076                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1077                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1078                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1079                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1080                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1081                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1082                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1083                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1084                 lvds->panel_pwr_delay =
1085                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1086                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1087
1088                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1089                 if (misc & ATOM_VSYNC_POLARITY)
1090                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1091                 if (misc & ATOM_HSYNC_POLARITY)
1092                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1093                 if (misc & ATOM_COMPOSITESYNC)
1094                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1095                 if (misc & ATOM_INTERLACE)
1096                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1097                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1098                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1099
1100                 /* set crtc values */
1101                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1102
1103                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1104
1105                 encoder->native_mode = lvds->native_mode;
1106         }
1107         return lvds;
1108 }
1109
1110 struct radeon_encoder_primary_dac *
1111 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1112 {
1113         struct drm_device *dev = encoder->base.dev;
1114         struct radeon_device *rdev = dev->dev_private;
1115         struct radeon_mode_info *mode_info = &rdev->mode_info;
1116         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1117         uint16_t data_offset;
1118         struct _COMPASSIONATE_DATA *dac_info;
1119         uint8_t frev, crev;
1120         uint8_t bg, dac;
1121         struct radeon_encoder_primary_dac *p_dac = NULL;
1122
1123         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1124
1125         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1126
1127         if (dac_info) {
1128                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1129
1130                 if (!p_dac)
1131                         return NULL;
1132
1133                 bg = dac_info->ucDAC1_BG_Adjustment;
1134                 dac = dac_info->ucDAC1_DAC_Adjustment;
1135                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1136
1137         }
1138         return p_dac;
1139 }
1140
1141 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1142                                 struct drm_display_mode *mode)
1143 {
1144         struct radeon_mode_info *mode_info = &rdev->mode_info;
1145         ATOM_ANALOG_TV_INFO *tv_info;
1146         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1147         ATOM_DTD_FORMAT *dtd_timings;
1148         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1149         u8 frev, crev;
1150         u16 data_offset, misc;
1151
1152         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1153
1154         switch (crev) {
1155         case 1:
1156                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1157                 if (index > MAX_SUPPORTED_TV_TIMING)
1158                         return false;
1159
1160                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1161                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1162                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1163                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1164                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1165
1166                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1167                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1168                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1169                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1170                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1171
1172                 mode->flags = 0;
1173                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1174                 if (misc & ATOM_VSYNC_POLARITY)
1175                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1176                 if (misc & ATOM_HSYNC_POLARITY)
1177                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1178                 if (misc & ATOM_COMPOSITESYNC)
1179                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1180                 if (misc & ATOM_INTERLACE)
1181                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1182                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1183                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1184
1185                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1186
1187                 if (index == 1) {
1188                         /* PAL timings appear to have wrong values for totals */
1189                         mode->crtc_htotal -= 1;
1190                         mode->crtc_vtotal -= 1;
1191                 }
1192                 break;
1193         case 2:
1194                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1195                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1196                         return false;
1197
1198                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1199                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1200                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1201                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1202                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1203                         le16_to_cpu(dtd_timings->usHSyncOffset);
1204                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1205                         le16_to_cpu(dtd_timings->usHSyncWidth);
1206
1207                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1208                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1209                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1210                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1211                         le16_to_cpu(dtd_timings->usVSyncOffset);
1212                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1213                         le16_to_cpu(dtd_timings->usVSyncWidth);
1214
1215                 mode->flags = 0;
1216                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1217                 if (misc & ATOM_VSYNC_POLARITY)
1218                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1219                 if (misc & ATOM_HSYNC_POLARITY)
1220                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1221                 if (misc & ATOM_COMPOSITESYNC)
1222                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1223                 if (misc & ATOM_INTERLACE)
1224                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1225                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1226                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1227
1228                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1229                 break;
1230         }
1231         return true;
1232 }
1233
1234 enum radeon_tv_std
1235 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1236 {
1237         struct radeon_mode_info *mode_info = &rdev->mode_info;
1238         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1239         uint16_t data_offset;
1240         uint8_t frev, crev;
1241         struct _ATOM_ANALOG_TV_INFO *tv_info;
1242         enum radeon_tv_std tv_std = TV_STD_NTSC;
1243
1244         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1245
1246         tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1247
1248         switch (tv_info->ucTV_BootUpDefaultStandard) {
1249         case ATOM_TV_NTSC:
1250                 tv_std = TV_STD_NTSC;
1251                 DRM_INFO("Default TV standard: NTSC\n");
1252                 break;
1253         case ATOM_TV_NTSCJ:
1254                 tv_std = TV_STD_NTSC_J;
1255                 DRM_INFO("Default TV standard: NTSC-J\n");
1256                 break;
1257         case ATOM_TV_PAL:
1258                 tv_std = TV_STD_PAL;
1259                 DRM_INFO("Default TV standard: PAL\n");
1260                 break;
1261         case ATOM_TV_PALM:
1262                 tv_std = TV_STD_PAL_M;
1263                 DRM_INFO("Default TV standard: PAL-M\n");
1264                 break;
1265         case ATOM_TV_PALN:
1266                 tv_std = TV_STD_PAL_N;
1267                 DRM_INFO("Default TV standard: PAL-N\n");
1268                 break;
1269         case ATOM_TV_PALCN:
1270                 tv_std = TV_STD_PAL_CN;
1271                 DRM_INFO("Default TV standard: PAL-CN\n");
1272                 break;
1273         case ATOM_TV_PAL60:
1274                 tv_std = TV_STD_PAL_60;
1275                 DRM_INFO("Default TV standard: PAL-60\n");
1276                 break;
1277         case ATOM_TV_SECAM:
1278                 tv_std = TV_STD_SECAM;
1279                 DRM_INFO("Default TV standard: SECAM\n");
1280                 break;
1281         default:
1282                 tv_std = TV_STD_NTSC;
1283                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1284                 break;
1285         }
1286         return tv_std;
1287 }
1288
1289 struct radeon_encoder_tv_dac *
1290 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1291 {
1292         struct drm_device *dev = encoder->base.dev;
1293         struct radeon_device *rdev = dev->dev_private;
1294         struct radeon_mode_info *mode_info = &rdev->mode_info;
1295         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1296         uint16_t data_offset;
1297         struct _COMPASSIONATE_DATA *dac_info;
1298         uint8_t frev, crev;
1299         uint8_t bg, dac;
1300         struct radeon_encoder_tv_dac *tv_dac = NULL;
1301
1302         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1303
1304         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1305
1306         if (dac_info) {
1307                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1308
1309                 if (!tv_dac)
1310                         return NULL;
1311
1312                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1313                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1314                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1315
1316                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1317                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1318                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1319
1320                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1321                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1322                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1323
1324                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1325         }
1326         return tv_dac;
1327 }
1328
1329 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1330 {
1331         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1332         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1333
1334         args.ucEnable = enable;
1335
1336         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1337 }
1338
1339 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1340 {
1341         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1342         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1343
1344         args.ucEnable = enable;
1345
1346         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1347 }
1348
1349 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1350 {
1351         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1352         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1353
1354         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1355         return args.ulReturnEngineClock;
1356 }
1357
1358 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1359 {
1360         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1361         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1362
1363         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1364         return args.ulReturnMemoryClock;
1365 }
1366
1367 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1368                                   uint32_t eng_clock)
1369 {
1370         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1371         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1372
1373         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1374
1375         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1376 }
1377
1378 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1379                                   uint32_t mem_clock)
1380 {
1381         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1382         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1383
1384         if (rdev->flags & RADEON_IS_IGP)
1385                 return;
1386
1387         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1388
1389         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1390 }
1391
1392 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1393 {
1394         struct radeon_device *rdev = dev->dev_private;
1395         uint32_t bios_2_scratch, bios_6_scratch;
1396
1397         if (rdev->family >= CHIP_R600) {
1398                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1399                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1400         } else {
1401                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1402                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1403         }
1404
1405         /* let the bios control the backlight */
1406         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1407
1408         /* tell the bios not to handle mode switching */
1409         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1410
1411         if (rdev->family >= CHIP_R600) {
1412                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1413                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1414         } else {
1415                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1416                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1417         }
1418
1419 }
1420
1421 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1422 {
1423         uint32_t scratch_reg;
1424         int i;
1425
1426         if (rdev->family >= CHIP_R600)
1427                 scratch_reg = R600_BIOS_0_SCRATCH;
1428         else
1429                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1430
1431         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1432                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1433 }
1434
1435 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1436 {
1437         uint32_t scratch_reg;
1438         int i;
1439
1440         if (rdev->family >= CHIP_R600)
1441                 scratch_reg = R600_BIOS_0_SCRATCH;
1442         else
1443                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1444
1445         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1446                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1447 }
1448
1449 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1450 {
1451         struct drm_device *dev = encoder->dev;
1452         struct radeon_device *rdev = dev->dev_private;
1453         uint32_t bios_6_scratch;
1454
1455         if (rdev->family >= CHIP_R600)
1456                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1457         else
1458                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1459
1460         if (lock)
1461                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1462         else
1463                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1464
1465         if (rdev->family >= CHIP_R600)
1466                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1467         else
1468                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1469 }
1470
1471 /* at some point we may want to break this out into individual functions */
1472 void
1473 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1474                                        struct drm_encoder *encoder,
1475                                        bool connected)
1476 {
1477         struct drm_device *dev = connector->dev;
1478         struct radeon_device *rdev = dev->dev_private;
1479         struct radeon_connector *radeon_connector =
1480             to_radeon_connector(connector);
1481         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1482         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1483
1484         if (rdev->family >= CHIP_R600) {
1485                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1486                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1487                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1488         } else {
1489                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1490                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1491                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1492         }
1493
1494         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1495             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1496                 if (connected) {
1497                         DRM_DEBUG("TV1 connected\n");
1498                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1499                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1500                 } else {
1501                         DRM_DEBUG("TV1 disconnected\n");
1502                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1503                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1504                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1505                 }
1506         }
1507         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1508             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1509                 if (connected) {
1510                         DRM_DEBUG("CV connected\n");
1511                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1512                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1513                 } else {
1514                         DRM_DEBUG("CV disconnected\n");
1515                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1516                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1517                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1518                 }
1519         }
1520         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1521             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1522                 if (connected) {
1523                         DRM_DEBUG("LCD1 connected\n");
1524                         bios_0_scratch |= ATOM_S0_LCD1;
1525                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1526                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1527                 } else {
1528                         DRM_DEBUG("LCD1 disconnected\n");
1529                         bios_0_scratch &= ~ATOM_S0_LCD1;
1530                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1531                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1532                 }
1533         }
1534         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1535             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1536                 if (connected) {
1537                         DRM_DEBUG("CRT1 connected\n");
1538                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1539                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1540                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1541                 } else {
1542                         DRM_DEBUG("CRT1 disconnected\n");
1543                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1544                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1545                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1546                 }
1547         }
1548         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1549             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1550                 if (connected) {
1551                         DRM_DEBUG("CRT2 connected\n");
1552                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1553                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1554                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1555                 } else {
1556                         DRM_DEBUG("CRT2 disconnected\n");
1557                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1558                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1559                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1560                 }
1561         }
1562         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1563             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1564                 if (connected) {
1565                         DRM_DEBUG("DFP1 connected\n");
1566                         bios_0_scratch |= ATOM_S0_DFP1;
1567                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1568                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1569                 } else {
1570                         DRM_DEBUG("DFP1 disconnected\n");
1571                         bios_0_scratch &= ~ATOM_S0_DFP1;
1572                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1573                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1574                 }
1575         }
1576         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1577             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1578                 if (connected) {
1579                         DRM_DEBUG("DFP2 connected\n");
1580                         bios_0_scratch |= ATOM_S0_DFP2;
1581                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1582                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1583                 } else {
1584                         DRM_DEBUG("DFP2 disconnected\n");
1585                         bios_0_scratch &= ~ATOM_S0_DFP2;
1586                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1587                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1588                 }
1589         }
1590         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1591             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1592                 if (connected) {
1593                         DRM_DEBUG("DFP3 connected\n");
1594                         bios_0_scratch |= ATOM_S0_DFP3;
1595                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1596                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1597                 } else {
1598                         DRM_DEBUG("DFP3 disconnected\n");
1599                         bios_0_scratch &= ~ATOM_S0_DFP3;
1600                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1601                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1602                 }
1603         }
1604         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1605             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1606                 if (connected) {
1607                         DRM_DEBUG("DFP4 connected\n");
1608                         bios_0_scratch |= ATOM_S0_DFP4;
1609                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1610                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1611                 } else {
1612                         DRM_DEBUG("DFP4 disconnected\n");
1613                         bios_0_scratch &= ~ATOM_S0_DFP4;
1614                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1615                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1616                 }
1617         }
1618         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1619             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1620                 if (connected) {
1621                         DRM_DEBUG("DFP5 connected\n");
1622                         bios_0_scratch |= ATOM_S0_DFP5;
1623                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1624                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1625                 } else {
1626                         DRM_DEBUG("DFP5 disconnected\n");
1627                         bios_0_scratch &= ~ATOM_S0_DFP5;
1628                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1629                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1630                 }
1631         }
1632
1633         if (rdev->family >= CHIP_R600) {
1634                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1635                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1636                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1637         } else {
1638                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1639                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1640                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1641         }
1642 }
1643
1644 void
1645 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1646 {
1647         struct drm_device *dev = encoder->dev;
1648         struct radeon_device *rdev = dev->dev_private;
1649         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1650         uint32_t bios_3_scratch;
1651
1652         if (rdev->family >= CHIP_R600)
1653                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1654         else
1655                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1656
1657         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1658                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1659                 bios_3_scratch |= (crtc << 18);
1660         }
1661         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1662                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1663                 bios_3_scratch |= (crtc << 24);
1664         }
1665         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1666                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1667                 bios_3_scratch |= (crtc << 16);
1668         }
1669         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1670                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1671                 bios_3_scratch |= (crtc << 20);
1672         }
1673         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1674                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1675                 bios_3_scratch |= (crtc << 17);
1676         }
1677         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1678                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1679                 bios_3_scratch |= (crtc << 19);
1680         }
1681         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1682                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1683                 bios_3_scratch |= (crtc << 23);
1684         }
1685         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1686                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1687                 bios_3_scratch |= (crtc << 25);
1688         }
1689
1690         if (rdev->family >= CHIP_R600)
1691                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1692         else
1693                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1694 }
1695
1696 void
1697 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1698 {
1699         struct drm_device *dev = encoder->dev;
1700         struct radeon_device *rdev = dev->dev_private;
1701         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1702         uint32_t bios_2_scratch;
1703
1704         if (rdev->family >= CHIP_R600)
1705                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1706         else
1707                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1708
1709         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1710                 if (on)
1711                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1712                 else
1713                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1714         }
1715         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1716                 if (on)
1717                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1718                 else
1719                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1720         }
1721         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1722                 if (on)
1723                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1724                 else
1725                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1726         }
1727         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1728                 if (on)
1729                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1730                 else
1731                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1732         }
1733         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1734                 if (on)
1735                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1736                 else
1737                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1738         }
1739         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1740                 if (on)
1741                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1742                 else
1743                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1744         }
1745         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1746                 if (on)
1747                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1748                 else
1749                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1750         }
1751         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1752                 if (on)
1753                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1754                 else
1755                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1756         }
1757         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1758                 if (on)
1759                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1760                 else
1761                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1762         }
1763         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1764                 if (on)
1765                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1766                 else
1767                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1768         }
1769
1770         if (rdev->family >= CHIP_R600)
1771                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1772         else
1773                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1774 }