drivers/gpu/drm/radeon/r600_cs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "radeon.h"
  31 #include "r600d.h"
  32 #include "r600_reg_safe.h"
  33
  34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  35                                         struct radeon_cs_reloc **cs_reloc);
  36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  37                                         struct radeon_cs_reloc **cs_reloc);
  38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  41
  42
  43 struct r600_cs_track {
  44         /* configuration we miror so that we use same code btw kms/ums */
  45         u32                     group_size;
  46         u32                     nbanks;
  47         u32                     npipes;
  48         /* value we track */
  49         u32                     sq_config;
  50         u32                     nsamples;
  51         u32                     cb_color_base_last[8];
  52         struct radeon_bo        *cb_color_bo[8];
  53         u64                     cb_color_bo_mc[8];
  54         u32                     cb_color_bo_offset[8];
  55         struct radeon_bo        *cb_color_frag_bo[8];
  56         struct radeon_bo        *cb_color_tile_bo[8];
  57         u32                     cb_color_info[8];
  58         u32                     cb_color_size_idx[8];
  59         u32                     cb_target_mask;
  60         u32                     cb_shader_mask;
  61         u32                     cb_color_size[8];
  62         u32                     vgt_strmout_en;
  63         u32                     vgt_strmout_buffer_en;
  64         u32                     db_depth_control;
  65         u32                     db_depth_info;
  66         u32                     db_depth_size_idx;
  67         u32                     db_depth_view;
  68         u32                     db_depth_size;
  69         u32                     db_offset;
  70         struct radeon_bo        *db_bo;
  71         u64                     db_bo_mc;
  72 };
  73
  74 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc }
  75 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc }
  76 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0 }
  77 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc }
  78 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0 }
  79 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc }
  80 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0 }
  81 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16, vc }
  82
  83 struct gpu_formats {
  84         unsigned blockwidth;
  85         unsigned blockheight;
  86         unsigned blocksize;
  87         unsigned valid_color;
  88 };
  89
  90 static const struct gpu_formats color_formats_table[] = {
  91         /* 8 bit */
  92         FMT_8_BIT(V_038004_COLOR_8, 1),
  93         FMT_8_BIT(V_038004_COLOR_4_4, 1),
  94         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
  95         FMT_8_BIT(V_038004_FMT_1, 0),
  96
  97         /* 16-bit */
  98         FMT_16_BIT(V_038004_COLOR_16, 1),
  99         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
 100         FMT_16_BIT(V_038004_COLOR_8_8, 1),
 101         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
 102         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
 103         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
 104         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
 105         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
 106
 107         /* 24-bit */
 108         FMT_24_BIT(V_038004_FMT_8_8_8),
 109
 110         /* 32-bit */
 111         FMT_32_BIT(V_038004_COLOR_32, 1),
 112         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
 113         FMT_32_BIT(V_038004_COLOR_16_16, 1),
 114         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
 115         FMT_32_BIT(V_038004_COLOR_8_24, 1),
 116         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
 117         FMT_32_BIT(V_038004_COLOR_24_8, 1),
 118         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
 119         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
 120         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
 121         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
 122         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
 123         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
 124         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
 125         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
 126         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
 127         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
 128         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
 129
 130         /* 48-bit */
 131         FMT_48_BIT(V_038004_FMT_16_16_16),
 132         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
 133
 134         /* 64-bit */
 135         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
 136         FMT_64_BIT(V_038004_COLOR_32_32, 1),
 137         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
 138         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
 139         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
 140
 141         FMT_96_BIT(V_038004_FMT_32_32_32),
 142         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
 143
 144         /* 128-bit */
 145         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
 146         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
 147
 148         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
 149         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
 150
 151         /* block compressed formats */
 152         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
 153         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
 154         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
 155         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
 156         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
 157
 158 };
 159
 160 static inline bool fmt_is_valid_color(u32 format)
 161 {
 162         if (format >= ARRAY_SIZE(color_formats_table))
 163                 return false;
 164
 165         if (color_formats_table[format].valid_color)
 166                 return true;
 167
 168         return false;
 169 }
 170
 171 static inline bool fmt_is_valid_texture(u32 format)
 172 {
 173         if (format >= ARRAY_SIZE(color_formats_table))
 174                 return false;
 175
 176         if (color_formats_table[format].blockwidth > 0)
 177                 return true;
 178
 179         return false;
 180 }
 181
 182 static inline int fmt_get_blocksize(u32 format)
 183 {
 184         if (format >= ARRAY_SIZE(color_formats_table))
 185                 return 0;
 186
 187         return color_formats_table[format].blocksize;
 188 }
 189
 190 static inline int fmt_get_nblocksx(u32 format, u32 w)
 191 {
 192         unsigned bw;
 193
 194         if (format >= ARRAY_SIZE(color_formats_table))
 195                 return 0;
 196
 197         bw = color_formats_table[format].blockwidth;
 198         if (bw == 0)
 199                 return 0;
 200
 201         return (w + bw - 1) / bw;
 202 }
 203
 204 static inline int fmt_get_nblocksy(u32 format, u32 h)
 205 {
 206         unsigned bh;
 207
 208         if (format >= ARRAY_SIZE(color_formats_table))
 209                 return 0;
 210
 211         bh = color_formats_table[format].blockheight;
 212         if (bh == 0)
 213                 return 0;
 214
 215         return (h + bh - 1) / bh;
 216 }
 217
 218 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
 219 {
 220         unsigned res;
 221
 222         if (format >= ARRAY_SIZE(color_formats_table))
 223                 goto fail;
 224
 225         res = color_formats_table[format].blocksize;
 226         if (res == 0)
 227                 goto fail;
 228
 229         *bpe = res;
 230         return 0;
 231
 232 fail:
 233         *bpe = 16;
 234         return -EINVAL;
 235 }
 236
 237 struct array_mode_checker {
 238         int array_mode;
 239         u32 group_size;
 240         u32 nbanks;
 241         u32 npipes;
 242         u32 nsamples;
 243         u32 blocksize;
 244 };
 245
 246 /* returns alignment in pixels for pitch/height/depth and bytes for base */
 247 static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
 248                                                 u32 *pitch_align,
 249                                                 u32 *height_align,
 250                                                 u32 *depth_align,
 251                                                 u64 *base_align)
 252 {
 253         u32 tile_width = 8;
 254         u32 tile_height = 8;
 255         u32 macro_tile_width = values->nbanks;
 256         u32 macro_tile_height = values->npipes;
 257         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
 258         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
 259
 260         switch (values->array_mode) {
 261         case ARRAY_LINEAR_GENERAL:
 262                 /* technically tile_width/_height for pitch/height */
 263                 *pitch_align = 1; /* tile_width */
 264                 *height_align = 1; /* tile_height */
 265                 *depth_align = 1;
 266                 *base_align = 1;
 267                 break;
 268         case ARRAY_LINEAR_ALIGNED:
 269                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
 270                 *height_align = tile_height;
 271                 *depth_align = 1;
 272                 *base_align = values->group_size;
 273                 break;
 274         case ARRAY_1D_TILED_THIN1:
 275                 *pitch_align = max((u32)tile_width,
 276                                    (u32)(values->group_size /
 277                                          (tile_height * values->blocksize * values->nsamples)));
 278                 *height_align = tile_height;
 279                 *depth_align = 1;
 280                 *base_align = values->group_size;
 281                 break;
 282         case ARRAY_2D_TILED_THIN1:
 283                 *pitch_align = max((u32)macro_tile_width,
 284                                   (u32)(((values->group_size / tile_height) /
 285                                          (values->blocksize * values->nsamples)) *
 286                                         values->nbanks)) * tile_width;
 287                 *height_align = macro_tile_height * tile_height;
 288                 *depth_align = 1;
 289                 *base_align = max(macro_tile_bytes,
 290                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
 291                 break;
 292         default:
 293                 return -EINVAL;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static void r600_cs_track_init(struct r600_cs_track *track)
 300 {
 301         int i;
 302
 303         /* assume DX9 mode */
 304         track->sq_config = DX9_CONSTS;
 305         for (i = 0; i < 8; i++) {
 306                 track->cb_color_base_last[i] = 0;
 307                 track->cb_color_size[i] = 0;
 308                 track->cb_color_size_idx[i] = 0;
 309                 track->cb_color_info[i] = 0;
 310                 track->cb_color_bo[i] = NULL;
 311                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 312                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
 313         }
 314         track->cb_target_mask = 0xFFFFFFFF;
 315         track->cb_shader_mask = 0xFFFFFFFF;
 316         track->db_bo = NULL;
 317         track->db_bo_mc = 0xFFFFFFFF;
 318         /* assume the biggest format and that htile is enabled */
 319         track->db_depth_info = 7 | (1 << 25);
 320         track->db_depth_view = 0xFFFFC000;
 321         track->db_depth_size = 0xFFFFFFFF;
 322         track->db_depth_size_idx = 0;
 323         track->db_depth_control = 0xFFFFFFFF;
 324 }
 325
 326 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 327 {
 328         struct r600_cs_track *track = p->track;
 329         u32 slice_tile_max, size, tmp;
 330         u32 height, height_align, pitch, pitch_align, depth_align;
 331         u64 base_offset, base_align;
 332         struct array_mode_checker array_check;
 333         volatile u32 *ib = p->ib->ptr;
 334         unsigned array_mode;
 335         u32 format;
 336         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
 337                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
 338                 return -EINVAL;
 339         }
 340         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
 341         format = G_0280A0_FORMAT(track->cb_color_info[i]);
 342         if (!fmt_is_valid_color(format)) {
 343                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
 344                          __func__, __LINE__, format,
 345                         i, track->cb_color_info[i]);
 346                 return -EINVAL;
 347         }
 348         /* pitch in pixels */
 349         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
 350         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
 351         slice_tile_max *= 64;
 352         height = slice_tile_max / pitch;
 353         if (height > 8192)
 354                 height = 8192;
 355         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
 356
 357         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
 358         array_check.array_mode = array_mode;
 359         array_check.group_size = track->group_size;
 360         array_check.nbanks = track->nbanks;
 361         array_check.npipes = track->npipes;
 362         array_check.nsamples = track->nsamples;
 363         array_check.blocksize = fmt_get_blocksize(format);
 364         if (r600_get_array_mode_alignment(&array_check,
 365                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 366                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 367                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 368                          track->cb_color_info[i]);
 369                 return -EINVAL;
 370         }
 371         switch (array_mode) {
 372         case V_0280A0_ARRAY_LINEAR_GENERAL:
 373                 break;
 374         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 375                 break;
 376         case V_0280A0_ARRAY_1D_TILED_THIN1:
 377                 /* avoid breaking userspace */
 378                 if (height > 7)
 379                         height &= ~0x7;
 380                 break;
 381         case V_0280A0_ARRAY_2D_TILED_THIN1:
 382                 break;
 383         default:
 384                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 385                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 386                         track->cb_color_info[i]);
 387                 return -EINVAL;
 388         }
 389
 390         if (!IS_ALIGNED(pitch, pitch_align)) {
 391                 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
 392                          __func__, __LINE__, pitch, pitch_align, array_mode);
 393                 return -EINVAL;
 394         }
 395         if (!IS_ALIGNED(height, height_align)) {
 396                 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
 397                          __func__, __LINE__, height, height_align, array_mode);
 398                 return -EINVAL;
 399         }
 400         if (!IS_ALIGNED(base_offset, base_align)) {
 401                 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
 402                          base_offset, base_align, array_mode);
 403                 return -EINVAL;
 404         }
 405
 406         /* check offset */
 407         tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format);
 408         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 409                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
 410                         /* the initial DDX does bad things with the CB size occasionally */
 411                         /* it rounds up height too far for slice tile max but the BO is smaller */
 412                         /* r600c,g also seem to flush at bad times in some apps resulting in
 413                          * bogus values here. So for linear just allow anything to avoid breaking
 414                          * broken userspace.
 415                          */
 416                 } else {
 417                         dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i,
 418                                  array_mode,
 419                                  track->cb_color_bo_offset[i], tmp,
 420                                  radeon_bo_size(track->cb_color_bo[i]));
 421                         return -EINVAL;
 422                 }
 423         }
 424         /* limit max tile */
 425         tmp = (height * pitch) >> 6;
 426         if (tmp < slice_tile_max)
 427                 slice_tile_max = tmp;
 428         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
 429                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
 430         ib[track->cb_color_size_idx[i]] = tmp;
 431         return 0;
 432 }
 433
 434 static int r600_cs_track_check(struct radeon_cs_parser *p)
 435 {
 436         struct r600_cs_track *track = p->track;
 437         u32 tmp;
 438         int r, i;
 439         volatile u32 *ib = p->ib->ptr;
 440
 441         /* on legacy kernel we don't perform advanced check */
 442         if (p->rdev == NULL)
 443                 return 0;
 444         /* we don't support out buffer yet */
 445         if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
 446                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
 447                 return -EINVAL;
 448         }
 449         /* check that we have a cb for each enabled target, we don't check
 450          * shader_mask because it seems mesa isn't always setting it :(
 451          */
 452         tmp = track->cb_target_mask;
 453         for (i = 0; i < 8; i++) {
 454                 if ((tmp >> (i * 4)) & 0xF) {
 455                         /* at least one component is enabled */
 456                         if (track->cb_color_bo[i] == NULL) {
 457                                 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 458                                         __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 459                                 return -EINVAL;
 460                         }
 461                         /* perform rewrite of CB_COLOR[0-7]_SIZE */
 462                         r = r600_cs_track_validate_cb(p, i);
 463                         if (r)
 464                                 return r;
 465                 }
 466         }
 467         /* Check depth buffer */
 468         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
 469                 G_028800_Z_ENABLE(track->db_depth_control)) {
 470                 u32 nviews, bpe, ntiles, size, slice_tile_max;
 471                 u32 height, height_align, pitch, pitch_align, depth_align;
 472                 u64 base_offset, base_align;
 473                 struct array_mode_checker array_check;
 474                 int array_mode;
 475
 476                 if (track->db_bo == NULL) {
 477                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
 478                         return -EINVAL;
 479                 }
 480                 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
 481                         dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
 482                         return -EINVAL;
 483                 }
 484                 switch (G_028010_FORMAT(track->db_depth_info)) {
 485                 case V_028010_DEPTH_16:
 486                         bpe = 2;
 487                         break;
 488                 case V_028010_DEPTH_X8_24:
 489                 case V_028010_DEPTH_8_24:
 490                 case V_028010_DEPTH_X8_24_FLOAT:
 491                 case V_028010_DEPTH_8_24_FLOAT:
 492                 case V_028010_DEPTH_32_FLOAT:
 493                         bpe = 4;
 494                         break;
 495                 case V_028010_DEPTH_X24_8_32_FLOAT:
 496                         bpe = 8;
 497                         break;
 498                 default:
 499                         dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
 500                         return -EINVAL;
 501                 }
 502                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 503                         if (!track->db_depth_size_idx) {
 504                                 dev_warn(p->dev, "z/stencil buffer size not set\n");
 505                                 return -EINVAL;
 506                         }
 507                         tmp = radeon_bo_size(track->db_bo) - track->db_offset;
 508                         tmp = (tmp / bpe) >> 6;
 509                         if (!tmp) {
 510                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
 511                                                 track->db_depth_size, bpe, track->db_offset,
 512                                                 radeon_bo_size(track->db_bo));
 513                                 return -EINVAL;
 514                         }
 515                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
 516                 } else {
 517                         size = radeon_bo_size(track->db_bo);
 518                         /* pitch in pixels */
 519                         pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
 520                         slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 521                         slice_tile_max *= 64;
 522                         height = slice_tile_max / pitch;
 523                         if (height > 8192)
 524                                 height = 8192;
 525                         base_offset = track->db_bo_mc + track->db_offset;
 526                         array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
 527                         array_check.array_mode = array_mode;
 528                         array_check.group_size = track->group_size;
 529                         array_check.nbanks = track->nbanks;
 530                         array_check.npipes = track->npipes;
 531                         array_check.nsamples = track->nsamples;
 532                         array_check.blocksize = bpe;
 533                         if (r600_get_array_mode_alignment(&array_check,
 534                                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 535                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 536                                          G_028010_ARRAY_MODE(track->db_depth_info),
 537                                          track->db_depth_info);
 538                                 return -EINVAL;
 539                         }
 540                         switch (array_mode) {
 541                         case V_028010_ARRAY_1D_TILED_THIN1:
 542                                 /* don't break userspace */
 543                                 height &= ~0x7;
 544                                 break;
 545                         case V_028010_ARRAY_2D_TILED_THIN1:
 546                                 break;
 547                         default:
 548                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 549                                          G_028010_ARRAY_MODE(track->db_depth_info),
 550                                          track->db_depth_info);
 551                                 return -EINVAL;
 552                         }
 553
 554                         if (!IS_ALIGNED(pitch, pitch_align)) {
 555                                 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
 556                                          __func__, __LINE__, pitch, pitch_align, array_mode);
 557                                 return -EINVAL;
 558                         }
 559                         if (!IS_ALIGNED(height, height_align)) {
 560                                 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
 561                                          __func__, __LINE__, height, height_align, array_mode);
 562                                 return -EINVAL;
 563                         }
 564                         if (!IS_ALIGNED(base_offset, base_align)) {
 565                                 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
 566                                          base_offset, base_align, array_mode);
 567                                 return -EINVAL;
 568                         }
 569
 570                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 571                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
 572                         tmp = ntiles * bpe * 64 * nviews;
 573                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
 574                                 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
 575                                          array_mode,
 576                                          track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
 577                                          radeon_bo_size(track->db_bo));
 578                                 return -EINVAL;
 579                         }
 580                 }
 581         }
 582         return 0;
 583 }
 584
 585 /**
 586  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
 587  * @parser:     parser structure holding parsing context.
 588  * @pkt:        where to store packet informations
 589  *
 590  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 591  * if packet is bigger than remaining ib size. or if packets is unknown.
 592  **/
 593 int r600_cs_packet_parse(struct radeon_cs_parser *p,
 594                         struct radeon_cs_packet *pkt,
 595                         unsigned idx)
 596 {
 597         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 598         uint32_t header;
 599
 600         if (idx >= ib_chunk->length_dw) {
 601                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 602                           idx, ib_chunk->length_dw);
 603                 return -EINVAL;
 604         }
 605         header = radeon_get_ib_value(p, idx);
 606         pkt->idx = idx;
 607         pkt->type = CP_PACKET_GET_TYPE(header);
 608         pkt->count = CP_PACKET_GET_COUNT(header);
 609         pkt->one_reg_wr = 0;
 610         switch (pkt->type) {
 611         case PACKET_TYPE0:
 612                 pkt->reg = CP_PACKET0_GET_REG(header);
 613                 break;
 614         case PACKET_TYPE3:
 615                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 616                 break;
 617         case PACKET_TYPE2:
 618                 pkt->count = -1;
 619                 break;
 620         default:
 621                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 622                 return -EINVAL;
 623         }
 624         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 625                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 626                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 627                 return -EINVAL;
 628         }
 629         return 0;
 630 }
 631
 632 /**
 633  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
 634  * @parser:             parser structure holding parsing context.
 635  * @data:               pointer to relocation data
 636  * @offset_start:       starting offset
 637  * @offset_mask:        offset mask (to align start offset on)
 638  * @reloc:              reloc informations
 639  *
 640  * Check next packet is relocation packet3, do bo validation and compute
 641  * GPU offset using the provided start.
 642  **/
 643 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
 644                                         struct radeon_cs_reloc **cs_reloc)
 645 {
 646         struct radeon_cs_chunk *relocs_chunk;
 647         struct radeon_cs_packet p3reloc;
 648         unsigned idx;
 649         int r;
 650
 651         if (p->chunk_relocs_idx == -1) {
 652                 DRM_ERROR("No relocation chunk !\n");
 653                 return -EINVAL;
 654         }
 655         *cs_reloc = NULL;
 656         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 657         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 658         if (r) {
 659                 return r;
 660         }
 661         p->idx += p3reloc.count + 2;
 662         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 663                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 664                           p3reloc.idx);
 665                 return -EINVAL;
 666         }
 667         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 668         if (idx >= relocs_chunk->length_dw) {
 669                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 670                           idx, relocs_chunk->length_dw);
 671                 return -EINVAL;
 672         }
 673         /* FIXME: we assume reloc size is 4 dwords */
 674         *cs_reloc = p->relocs_ptr[(idx / 4)];
 675         return 0;
 676 }
 677
 678 /**
 679  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
 680  * @parser:             parser structure holding parsing context.
 681  * @data:               pointer to relocation data
 682  * @offset_start:       starting offset
 683  * @offset_mask:        offset mask (to align start offset on)
 684  * @reloc:              reloc informations
 685  *
 686  * Check next packet is relocation packet3, do bo validation and compute
 687  * GPU offset using the provided start.
 688  **/
 689 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 690                                         struct radeon_cs_reloc **cs_reloc)
 691 {
 692         struct radeon_cs_chunk *relocs_chunk;
 693         struct radeon_cs_packet p3reloc;
 694         unsigned idx;
 695         int r;
 696
 697         if (p->chunk_relocs_idx == -1) {
 698                 DRM_ERROR("No relocation chunk !\n");
 699                 return -EINVAL;
 700         }
 701         *cs_reloc = NULL;
 702         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 703         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 704         if (r) {
 705                 return r;
 706         }
 707         p->idx += p3reloc.count + 2;
 708         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 709                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 710                           p3reloc.idx);
 711                 return -EINVAL;
 712         }
 713         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 714         if (idx >= relocs_chunk->length_dw) {
 715                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 716                           idx, relocs_chunk->length_dw);
 717                 return -EINVAL;
 718         }
 719         *cs_reloc = p->relocs;
 720         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
 721         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 722         return 0;
 723 }
 724
 725 /**
 726  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
 727  * @parser:             parser structure holding parsing context.
 728  *
 729  * Check next packet is relocation packet3, do bo validation and compute
 730  * GPU offset using the provided start.
 731  **/
 732 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 733 {
 734         struct radeon_cs_packet p3reloc;
 735         int r;
 736
 737         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 738         if (r) {
 739                 return 0;
 740         }
 741         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 742                 return 0;
 743         }
 744         return 1;
 745 }
 746
 747 /**
 748  * r600_cs_packet_next_vline() - parse userspace VLINE packet
 749  * @parser:             parser structure holding parsing context.
 750  *
 751  * Userspace sends a special sequence for VLINE waits.
 752  * PACKET0 - VLINE_START_END + value
 753  * PACKET3 - WAIT_REG_MEM poll vline status reg
 754  * RELOC (P3) - crtc_id in reloc.
 755  *
 756  * This function parses this and relocates the VLINE START END
 757  * and WAIT_REG_MEM packets to the correct crtc.
 758  * It also detects a switched off crtc and nulls out the
 759  * wait in that case.
 760  */
 761 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 762 {
 763         struct drm_mode_object *obj;
 764         struct drm_crtc *crtc;
 765         struct radeon_crtc *radeon_crtc;
 766         struct radeon_cs_packet p3reloc, wait_reg_mem;
 767         int crtc_id;
 768         int r;
 769         uint32_t header, h_idx, reg, wait_reg_mem_info;
 770         volatile uint32_t *ib;
 771
 772         ib = p->ib->ptr;
 773
 774         /* parse the WAIT_REG_MEM */
 775         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
 776         if (r)
 777                 return r;
 778
 779         /* check its a WAIT_REG_MEM */
 780         if (wait_reg_mem.type != PACKET_TYPE3 ||
 781             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 782                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 783                 return -EINVAL;
 784         }
 785
 786         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 787         /* bit 4 is reg (0) or mem (1) */
 788         if (wait_reg_mem_info & 0x10) {
 789                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 790                 return -EINVAL;
 791         }
 792         /* waiting for value to be equal */
 793         if ((wait_reg_mem_info & 0x7) != 0x3) {
 794                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
 795                 return -EINVAL;
 796         }
 797         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
 798                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
 799                 return -EINVAL;
 800         }
 801
 802         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
 803                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
 804                 return -EINVAL;
 805         }
 806
 807         /* jump over the NOP */
 808         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
 809         if (r)
 810                 return r;
 811
 812         h_idx = p->idx - 2;
 813         p->idx += wait_reg_mem.count + 2;
 814         p->idx += p3reloc.count + 2;
 815
 816         header = radeon_get_ib_value(p, h_idx);
 817         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
 818         reg = CP_PACKET0_GET_REG(header);
 819
 820         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 821         if (!obj) {
 822                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 823                 return -EINVAL;
 824         }
 825         crtc = obj_to_crtc(obj);
 826         radeon_crtc = to_radeon_crtc(crtc);
 827         crtc_id = radeon_crtc->crtc_id;
 828
 829         if (!crtc->enabled) {
 830                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
 831                 ib[h_idx + 2] = PACKET2(0);
 832                 ib[h_idx + 3] = PACKET2(0);
 833                 ib[h_idx + 4] = PACKET2(0);
 834                 ib[h_idx + 5] = PACKET2(0);
 835                 ib[h_idx + 6] = PACKET2(0);
 836                 ib[h_idx + 7] = PACKET2(0);
 837                 ib[h_idx + 8] = PACKET2(0);
 838         } else if (crtc_id == 1) {
 839                 switch (reg) {
 840                 case AVIVO_D1MODE_VLINE_START_END:
 841                         header &= ~R600_CP_PACKET0_REG_MASK;
 842                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 843                         break;
 844                 default:
 845                         DRM_ERROR("unknown crtc reloc\n");
 846                         return -EINVAL;
 847                 }
 848                 ib[h_idx] = header;
 849                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int r600_packet0_check(struct radeon_cs_parser *p,
 856                                 struct radeon_cs_packet *pkt,
 857                                 unsigned idx, unsigned reg)
 858 {
 859         int r;
 860
 861         switch (reg) {
 862         case AVIVO_D1MODE_VLINE_START_END:
 863                 r = r600_cs_packet_parse_vline(p);
 864                 if (r) {
 865                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 866                                         idx, reg);
 867                         return r;
 868                 }
 869                 break;
 870         default:
 871                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
 872                        reg, idx);
 873                 return -EINVAL;
 874         }
 875         return 0;
 876 }
 877
 878 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
 879                                 struct radeon_cs_packet *pkt)
 880 {
 881         unsigned reg, i;
 882         unsigned idx;
 883         int r;
 884
 885         idx = pkt->idx + 1;
 886         reg = pkt->reg;
 887         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 888                 r = r600_packet0_check(p, pkt, idx, reg);
 889                 if (r) {
 890                         return r;
 891                 }
 892         }
 893         return 0;
 894 }
 895
 896 /**
 897  * r600_cs_check_reg() - check if register is authorized or not
 898  * @parser: parser structure holding parsing context
 899  * @reg: register we are testing
 900  * @idx: index into the cs buffer
 901  *
 902  * This function will test against r600_reg_safe_bm and return 0
 903  * if register is safe. If register is not flag as safe this function
 904  * will test it against a list of register needind special handling.
 905  */
 906 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 907 {
 908         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
 909         struct radeon_cs_reloc *reloc;
 910         u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
 911         u32 m, i, tmp, *ib;
 912         int r;
 913
 914         i = (reg >> 7);
 915         if (i > last_reg) {
 916                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
 917                 return -EINVAL;
 918         }
 919         m = 1 << ((reg >> 2) & 31);
 920         if (!(r600_reg_safe_bm[i] & m))
 921                 return 0;
 922         ib = p->ib->ptr;
 923         switch (reg) {
 924         /* force following reg to 0 in an attempt to disable out buffer
 925          * which will need us to better understand how it works to perform
 926          * security check on it (Jerome)
 927          */
 928         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
 929         case R_008C44_SQ_ESGS_RING_SIZE:
 930         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
 931         case R_008C54_SQ_ESTMP_RING_SIZE:
 932         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
 933         case R_008C74_SQ_FBUF_RING_SIZE:
 934         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
 935         case R_008C5C_SQ_GSTMP_RING_SIZE:
 936         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
 937         case R_008C4C_SQ_GSVS_RING_SIZE:
 938         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
 939         case R_008C6C_SQ_PSTMP_RING_SIZE:
 940         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
 941         case R_008C7C_SQ_REDUC_RING_SIZE:
 942         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
 943         case R_008C64_SQ_VSTMP_RING_SIZE:
 944         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
 945                 /* get value to populate the IB don't remove */
 946                 tmp =radeon_get_ib_value(p, idx);
 947                 ib[idx] = 0;
 948                 break;
 949         case SQ_CONFIG:
 950                 track->sq_config = radeon_get_ib_value(p, idx);
 951                 break;
 952         case R_028800_DB_DEPTH_CONTROL:
 953                 track->db_depth_control = radeon_get_ib_value(p, idx);
 954                 break;
 955         case R_028010_DB_DEPTH_INFO:
 956                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
 957                         r = r600_cs_packet_next_reloc(p, &reloc);
 958                         if (r) {
 959                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
 960                                          "0x%04X\n", reg);
 961                                 return -EINVAL;
 962                         }
 963                         track->db_depth_info = radeon_get_ib_value(p, idx);
 964                         ib[idx] &= C_028010_ARRAY_MODE;
 965                         track->db_depth_info &= C_028010_ARRAY_MODE;
 966                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 967                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
 968                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
 969                         } else {
 970                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
 971                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
 972                         }
 973                 } else
 974                         track->db_depth_info = radeon_get_ib_value(p, idx);
 975                 break;
 976         case R_028004_DB_DEPTH_VIEW:
 977                 track->db_depth_view = radeon_get_ib_value(p, idx);
 978                 break;
 979         case R_028000_DB_DEPTH_SIZE:
 980                 track->db_depth_size = radeon_get_ib_value(p, idx);
 981                 track->db_depth_size_idx = idx;
 982                 break;
 983         case R_028AB0_VGT_STRMOUT_EN:
 984                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
 985                 break;
 986         case R_028B20_VGT_STRMOUT_BUFFER_EN:
 987                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
 988                 break;
 989         case R_028238_CB_TARGET_MASK:
 990                 track->cb_target_mask = radeon_get_ib_value(p, idx);
 991                 break;
 992         case R_02823C_CB_SHADER_MASK:
 993                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
 994                 break;
 995         case R_028C04_PA_SC_AA_CONFIG:
 996                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
 997                 track->nsamples = 1 << tmp;
 998                 break;
 999         case R_0280A0_CB_COLOR0_INFO:
1000         case R_0280A4_CB_COLOR1_INFO:
1001         case R_0280A8_CB_COLOR2_INFO:
1002         case R_0280AC_CB_COLOR3_INFO:
1003         case R_0280B0_CB_COLOR4_INFO:
1004         case R_0280B4_CB_COLOR5_INFO:
1005         case R_0280B8_CB_COLOR6_INFO:
1006         case R_0280BC_CB_COLOR7_INFO:
1007                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
1008                         r = r600_cs_packet_next_reloc(p, &reloc);
1009                         if (r) {
1010                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1011                                 return -EINVAL;
1012                         }
1013                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1014                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1015                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1016                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1017                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1018                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1019                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1020                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1021                         }
1022                 } else {
1023                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1024                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1025                 }
1026                 break;
1027         case R_028060_CB_COLOR0_SIZE:
1028         case R_028064_CB_COLOR1_SIZE:
1029         case R_028068_CB_COLOR2_SIZE:
1030         case R_02806C_CB_COLOR3_SIZE:
1031         case R_028070_CB_COLOR4_SIZE:
1032         case R_028074_CB_COLOR5_SIZE:
1033         case R_028078_CB_COLOR6_SIZE:
1034         case R_02807C_CB_COLOR7_SIZE:
1035                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1036                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1037                 track->cb_color_size_idx[tmp] = idx;
1038                 break;
1039                 /* This register were added late, there is userspace
1040                  * which does provide relocation for those but set
1041                  * 0 offset. In order to avoid breaking old userspace
1042                  * we detect this and set address to point to last
1043                  * CB_COLOR0_BASE, note that if userspace doesn't set
1044                  * CB_COLOR0_BASE before this register we will report
1045                  * error. Old userspace always set CB_COLOR0_BASE
1046                  * before any of this.
1047                  */
1048         case R_0280E0_CB_COLOR0_FRAG:
1049         case R_0280E4_CB_COLOR1_FRAG:
1050         case R_0280E8_CB_COLOR2_FRAG:
1051         case R_0280EC_CB_COLOR3_FRAG:
1052         case R_0280F0_CB_COLOR4_FRAG:
1053         case R_0280F4_CB_COLOR5_FRAG:
1054         case R_0280F8_CB_COLOR6_FRAG:
1055         case R_0280FC_CB_COLOR7_FRAG:
1056                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1057                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1058                         if (!track->cb_color_base_last[tmp]) {
1059                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1060                                 return -EINVAL;
1061                         }
1062                         ib[idx] = track->cb_color_base_last[tmp];
1063                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1064                 } else {
1065                         r = r600_cs_packet_next_reloc(p, &reloc);
1066                         if (r) {
1067                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1068                                 return -EINVAL;
1069                         }
1070                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1071                         track->cb_color_frag_bo[tmp] = reloc->robj;
1072                 }
1073                 break;
1074         case R_0280C0_CB_COLOR0_TILE:
1075         case R_0280C4_CB_COLOR1_TILE:
1076         case R_0280C8_CB_COLOR2_TILE:
1077         case R_0280CC_CB_COLOR3_TILE:
1078         case R_0280D0_CB_COLOR4_TILE:
1079         case R_0280D4_CB_COLOR5_TILE:
1080         case R_0280D8_CB_COLOR6_TILE:
1081         case R_0280DC_CB_COLOR7_TILE:
1082                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1083                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1084                         if (!track->cb_color_base_last[tmp]) {
1085                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1086                                 return -EINVAL;
1087                         }
1088                         ib[idx] = track->cb_color_base_last[tmp];
1089                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1090                 } else {
1091                         r = r600_cs_packet_next_reloc(p, &reloc);
1092                         if (r) {
1093                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1094                                 return -EINVAL;
1095                         }
1096                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1097                         track->cb_color_tile_bo[tmp] = reloc->robj;
1098                 }
1099                 break;
1100         case CB_COLOR0_BASE:
1101         case CB_COLOR1_BASE:
1102         case CB_COLOR2_BASE:
1103         case CB_COLOR3_BASE:
1104         case CB_COLOR4_BASE:
1105         case CB_COLOR5_BASE:
1106         case CB_COLOR6_BASE:
1107         case CB_COLOR7_BASE:
1108                 r = r600_cs_packet_next_reloc(p, &reloc);
1109                 if (r) {
1110                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1111                                         "0x%04X\n", reg);
1112                         return -EINVAL;
1113                 }
1114                 tmp = (reg - CB_COLOR0_BASE) / 4;
1115                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1116                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1117                 track->cb_color_base_last[tmp] = ib[idx];
1118                 track->cb_color_bo[tmp] = reloc->robj;
1119                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1120                 break;
1121         case DB_DEPTH_BASE:
1122                 r = r600_cs_packet_next_reloc(p, &reloc);
1123                 if (r) {
1124                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1125                                         "0x%04X\n", reg);
1126                         return -EINVAL;
1127                 }
1128                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1129                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1130                 track->db_bo = reloc->robj;
1131                 track->db_bo_mc = reloc->lobj.gpu_offset;
1132                 break;
1133         case DB_HTILE_DATA_BASE:
1134         case SQ_PGM_START_FS:
1135         case SQ_PGM_START_ES:
1136         case SQ_PGM_START_VS:
1137         case SQ_PGM_START_GS:
1138         case SQ_PGM_START_PS:
1139         case SQ_ALU_CONST_CACHE_GS_0:
1140         case SQ_ALU_CONST_CACHE_GS_1:
1141         case SQ_ALU_CONST_CACHE_GS_2:
1142         case SQ_ALU_CONST_CACHE_GS_3:
1143         case SQ_ALU_CONST_CACHE_GS_4:
1144         case SQ_ALU_CONST_CACHE_GS_5:
1145         case SQ_ALU_CONST_CACHE_GS_6:
1146         case SQ_ALU_CONST_CACHE_GS_7:
1147         case SQ_ALU_CONST_CACHE_GS_8:
1148         case SQ_ALU_CONST_CACHE_GS_9:
1149         case SQ_ALU_CONST_CACHE_GS_10:
1150         case SQ_ALU_CONST_CACHE_GS_11:
1151         case SQ_ALU_CONST_CACHE_GS_12:
1152         case SQ_ALU_CONST_CACHE_GS_13:
1153         case SQ_ALU_CONST_CACHE_GS_14:
1154         case SQ_ALU_CONST_CACHE_GS_15:
1155         case SQ_ALU_CONST_CACHE_PS_0:
1156         case SQ_ALU_CONST_CACHE_PS_1:
1157         case SQ_ALU_CONST_CACHE_PS_2:
1158         case SQ_ALU_CONST_CACHE_PS_3:
1159         case SQ_ALU_CONST_CACHE_PS_4:
1160         case SQ_ALU_CONST_CACHE_PS_5:
1161         case SQ_ALU_CONST_CACHE_PS_6:
1162         case SQ_ALU_CONST_CACHE_PS_7:
1163         case SQ_ALU_CONST_CACHE_PS_8:
1164         case SQ_ALU_CONST_CACHE_PS_9:
1165         case SQ_ALU_CONST_CACHE_PS_10:
1166         case SQ_ALU_CONST_CACHE_PS_11:
1167         case SQ_ALU_CONST_CACHE_PS_12:
1168         case SQ_ALU_CONST_CACHE_PS_13:
1169         case SQ_ALU_CONST_CACHE_PS_14:
1170         case SQ_ALU_CONST_CACHE_PS_15:
1171         case SQ_ALU_CONST_CACHE_VS_0:
1172         case SQ_ALU_CONST_CACHE_VS_1:
1173         case SQ_ALU_CONST_CACHE_VS_2:
1174         case SQ_ALU_CONST_CACHE_VS_3:
1175         case SQ_ALU_CONST_CACHE_VS_4:
1176         case SQ_ALU_CONST_CACHE_VS_5:
1177         case SQ_ALU_CONST_CACHE_VS_6:
1178         case SQ_ALU_CONST_CACHE_VS_7:
1179         case SQ_ALU_CONST_CACHE_VS_8:
1180         case SQ_ALU_CONST_CACHE_VS_9:
1181         case SQ_ALU_CONST_CACHE_VS_10:
1182         case SQ_ALU_CONST_CACHE_VS_11:
1183         case SQ_ALU_CONST_CACHE_VS_12:
1184         case SQ_ALU_CONST_CACHE_VS_13:
1185         case SQ_ALU_CONST_CACHE_VS_14:
1186         case SQ_ALU_CONST_CACHE_VS_15:
1187                 r = r600_cs_packet_next_reloc(p, &reloc);
1188                 if (r) {
1189                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1190                                         "0x%04X\n", reg);
1191                         return -EINVAL;
1192                 }
1193                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1194                 break;
1195         default:
1196                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1197                 return -EINVAL;
1198         }
1199         return 0;
1200 }
1201
1202 static inline unsigned mip_minify(unsigned size, unsigned level)
1203 {
1204         unsigned val;
1205
1206         val = max(1U, size >> level);
1207         if (level > 0)
1208                 val = roundup_pow_of_two(val);
1209         return val;
1210 }
1211
1212 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1213                               unsigned w0, unsigned h0, unsigned d0, unsigned format,
1214                               unsigned block_align, unsigned height_align, unsigned base_align,
1215                               unsigned *l0_size, unsigned *mipmap_size)
1216 {
1217         unsigned offset, i, level;
1218         unsigned width, height, depth, size;
1219         unsigned blocksize;
1220         unsigned nbx, nby;
1221         unsigned nlevels = llevel - blevel + 1;
1222
1223         *l0_size = -1;
1224         blocksize = fmt_get_blocksize(format);
1225
1226         w0 = mip_minify(w0, 0);
1227         h0 = mip_minify(h0, 0);
1228         d0 = mip_minify(d0, 0);
1229         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1230                 width = mip_minify(w0, i);
1231                 nbx = fmt_get_nblocksx(format, width);
1232
1233                 nbx = round_up(nbx, block_align);
1234
1235                 height = mip_minify(h0, i);
1236                 nby = fmt_get_nblocksy(format, height);
1237                 nby = round_up(nby, height_align);
1238
1239                 depth = mip_minify(d0, i);
1240
1241                 size = nbx * nby * blocksize;
1242                 if (nfaces)
1243                         size *= nfaces;
1244                 else
1245                         size *= depth;
1246
1247                 if (i == 0)
1248                         *l0_size = size;
1249
1250                 if (i == 0 || i == 1)
1251                         offset = round_up(offset, base_align);
1252
1253                 offset += size;
1254         }
1255         *mipmap_size = offset;
1256         if (llevel == 0)
1257                 *mipmap_size = *l0_size;
1258         if (!blevel)
1259                 *mipmap_size -= *l0_size;
1260 }
1261
1262 /**
1263  * r600_check_texture_resource() - check if register is authorized or not
1264  * @p: parser structure holding parsing context
1265  * @idx: index into the cs buffer
1266  * @texture: texture's bo structure
1267  * @mipmap: mipmap's bo structure
1268  *
1269  * This function will check that the resource has valid field and that
1270  * the texture and mipmap bo object are big enough to cover this resource.
1271  */
1272 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1273                                               struct radeon_bo *texture,
1274                                               struct radeon_bo *mipmap,
1275                                               u64 base_offset,
1276                                               u64 mip_offset,
1277                                               u32 tiling_flags)
1278 {
1279         struct r600_cs_track *track = p->track;
1280         u32 nfaces, llevel, blevel, w0, h0, d0;
1281         u32 word0, word1, l0_size, mipmap_size, word2, word3;
1282         u32 height_align, pitch, pitch_align, depth_align;
1283         u32 array, barray, larray;
1284         u64 base_align;
1285         struct array_mode_checker array_check;
1286         u32 format;
1287
1288         /* on legacy kernel we don't perform advanced check */
1289         if (p->rdev == NULL)
1290                 return 0;
1291
1292         /* convert to bytes */
1293         base_offset <<= 8;
1294         mip_offset <<= 8;
1295
1296         word0 = radeon_get_ib_value(p, idx + 0);
1297         if (tiling_flags & RADEON_TILING_MACRO)
1298                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1299         else if (tiling_flags & RADEON_TILING_MICRO)
1300                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1301         word1 = radeon_get_ib_value(p, idx + 1);
1302         w0 = G_038000_TEX_WIDTH(word0) + 1;
1303         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1304         d0 = G_038004_TEX_DEPTH(word1);
1305         nfaces = 1;
1306         switch (G_038000_DIM(word0)) {
1307         case V_038000_SQ_TEX_DIM_1D:
1308         case V_038000_SQ_TEX_DIM_2D:
1309         case V_038000_SQ_TEX_DIM_3D:
1310                 break;
1311         case V_038000_SQ_TEX_DIM_CUBEMAP:
1312                 if (p->family >= CHIP_RV770)
1313                         nfaces = 8;
1314                 else
1315                         nfaces = 6;
1316                 break;
1317         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1318         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1319                 array = 1;
1320                 break;
1321         case V_038000_SQ_TEX_DIM_2D_MSAA:
1322         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1323         default:
1324                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1325                 return -EINVAL;
1326         }
1327         format = G_038004_DATA_FORMAT(word1);
1328         if (!fmt_is_valid_texture(format)) {
1329                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1330                          __func__, __LINE__, format);
1331                 return -EINVAL;
1332         }
1333
1334         /* pitch in texels */
1335         pitch = (G_038000_PITCH(word0) + 1) * 8;
1336         array_check.array_mode = G_038000_TILE_MODE(word0);
1337         array_check.group_size = track->group_size;
1338         array_check.nbanks = track->nbanks;
1339         array_check.npipes = track->npipes;
1340         array_check.nsamples = 1;
1341         array_check.blocksize = fmt_get_blocksize(format);
1342         if (r600_get_array_mode_alignment(&array_check,
1343                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1344                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1345                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1346                 return -EINVAL;
1347         }
1348
1349         /* XXX check height as well... */
1350
1351         if (!IS_ALIGNED(pitch, pitch_align)) {
1352                 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1353                          __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1354                 return -EINVAL;
1355         }
1356         if (!IS_ALIGNED(base_offset, base_align)) {
1357                 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1358                          __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1359                 return -EINVAL;
1360         }
1361         if (!IS_ALIGNED(mip_offset, base_align)) {
1362                 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1363                          __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1364                 return -EINVAL;
1365         }
1366
1367         word2 = radeon_get_ib_value(p, idx + 2) << 8;
1368         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1369
1370         word0 = radeon_get_ib_value(p, idx + 4);
1371         word1 = radeon_get_ib_value(p, idx + 5);
1372         blevel = G_038010_BASE_LEVEL(word0);
1373         llevel = G_038014_LAST_LEVEL(word1);
1374         if (array == 1) {
1375                 barray = G_038014_BASE_ARRAY(word1);
1376                 larray = G_038014_LAST_ARRAY(word1);
1377
1378                 nfaces = larray - barray + 1;
1379         }
1380         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1381                           pitch_align, height_align, base_align,
1382                           &l0_size, &mipmap_size);
1383         /* using get ib will give us the offset into the texture bo */
1384         if ((l0_size + word2) > radeon_bo_size(texture)) {
1385                 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1386                         w0, h0, format, word2, l0_size, radeon_bo_size(texture));
1387                 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1388                 return -EINVAL;
1389         }
1390         /* using get ib will give us the offset into the mipmap bo */
1391         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1392         if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1393                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1394                   w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1395         }
1396         return 0;
1397 }
1398
1399 static int r600_packet3_check(struct radeon_cs_parser *p,
1400                                 struct radeon_cs_packet *pkt)
1401 {
1402         struct radeon_cs_reloc *reloc;
1403         struct r600_cs_track *track;
1404         volatile u32 *ib;
1405         unsigned idx;
1406         unsigned i;
1407         unsigned start_reg, end_reg, reg;
1408         int r;
1409         u32 idx_value;
1410
1411         track = (struct r600_cs_track *)p->track;
1412         ib = p->ib->ptr;
1413         idx = pkt->idx + 1;
1414         idx_value = radeon_get_ib_value(p, idx);
1415
1416         switch (pkt->opcode) {
1417         case PACKET3_SET_PREDICATION:
1418         {
1419                 int pred_op;
1420                 int tmp;
1421                 if (pkt->count != 1) {
1422                         DRM_ERROR("bad SET PREDICATION\n");
1423                         return -EINVAL;
1424                 }
1425
1426                 tmp = radeon_get_ib_value(p, idx + 1);
1427                 pred_op = (tmp >> 16) & 0x7;
1428
1429                 /* for the clear predicate operation */
1430                 if (pred_op == 0)
1431                         return 0;
1432
1433                 if (pred_op > 2) {
1434                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1435                         return -EINVAL;
1436                 }
1437
1438                 r = r600_cs_packet_next_reloc(p, &reloc);
1439                 if (r) {
1440                         DRM_ERROR("bad SET PREDICATION\n");
1441                         return -EINVAL;
1442                 }
1443
1444                 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1445                 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1446         }
1447         break;
1448
1449         case PACKET3_START_3D_CMDBUF:
1450                 if (p->family >= CHIP_RV770 || pkt->count) {
1451                         DRM_ERROR("bad START_3D\n");
1452                         return -EINVAL;
1453                 }
1454                 break;
1455         case PACKET3_CONTEXT_CONTROL:
1456                 if (pkt->count != 1) {
1457                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1458                         return -EINVAL;
1459                 }
1460                 break;
1461         case PACKET3_INDEX_TYPE:
1462         case PACKET3_NUM_INSTANCES:
1463                 if (pkt->count) {
1464                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1465                         return -EINVAL;
1466                 }
1467                 break;
1468         case PACKET3_DRAW_INDEX:
1469                 if (pkt->count != 3) {
1470                         DRM_ERROR("bad DRAW_INDEX\n");
1471                         return -EINVAL;
1472                 }
1473                 r = r600_cs_packet_next_reloc(p, &reloc);
1474                 if (r) {
1475                         DRM_ERROR("bad DRAW_INDEX\n");
1476                         return -EINVAL;
1477                 }
1478                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1479                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1480                 r = r600_cs_track_check(p);
1481                 if (r) {
1482                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1483                         return r;
1484                 }
1485                 break;
1486         case PACKET3_DRAW_INDEX_AUTO:
1487                 if (pkt->count != 1) {
1488                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1489                         return -EINVAL;
1490                 }
1491                 r = r600_cs_track_check(p);
1492                 if (r) {
1493                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1494                         return r;
1495                 }
1496                 break;
1497         case PACKET3_DRAW_INDEX_IMMD_BE:
1498         case PACKET3_DRAW_INDEX_IMMD:
1499                 if (pkt->count < 2) {
1500                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1501                         return -EINVAL;
1502                 }
1503                 r = r600_cs_track_check(p);
1504                 if (r) {
1505                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1506                         return r;
1507                 }
1508                 break;
1509         case PACKET3_WAIT_REG_MEM:
1510                 if (pkt->count != 5) {
1511                         DRM_ERROR("bad WAIT_REG_MEM\n");
1512                         return -EINVAL;
1513                 }
1514                 /* bit 4 is reg (0) or mem (1) */
1515                 if (idx_value & 0x10) {
1516                         r = r600_cs_packet_next_reloc(p, &reloc);
1517                         if (r) {
1518                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1519                                 return -EINVAL;
1520                         }
1521                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1522                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1523                 }
1524                 break;
1525         case PACKET3_SURFACE_SYNC:
1526                 if (pkt->count != 3) {
1527                         DRM_ERROR("bad SURFACE_SYNC\n");
1528                         return -EINVAL;
1529                 }
1530                 /* 0xffffffff/0x0 is flush all cache flag */
1531                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1532                     radeon_get_ib_value(p, idx + 2) != 0) {
1533                         r = r600_cs_packet_next_reloc(p, &reloc);
1534                         if (r) {
1535                                 DRM_ERROR("bad SURFACE_SYNC\n");
1536                                 return -EINVAL;
1537                         }
1538                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1539                 }
1540                 break;
1541         case PACKET3_EVENT_WRITE:
1542                 if (pkt->count != 2 && pkt->count != 0) {
1543                         DRM_ERROR("bad EVENT_WRITE\n");
1544                         return -EINVAL;
1545                 }
1546                 if (pkt->count) {
1547                         r = r600_cs_packet_next_reloc(p, &reloc);
1548                         if (r) {
1549                                 DRM_ERROR("bad EVENT_WRITE\n");
1550                                 return -EINVAL;
1551                         }
1552                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1553                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1554                 }
1555                 break;
1556         case PACKET3_EVENT_WRITE_EOP:
1557                 if (pkt->count != 4) {
1558                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1559                         return -EINVAL;
1560                 }
1561                 r = r600_cs_packet_next_reloc(p, &reloc);
1562                 if (r) {
1563                         DRM_ERROR("bad EVENT_WRITE\n");
1564                         return -EINVAL;
1565                 }
1566                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1567                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1568                 break;
1569         case PACKET3_SET_CONFIG_REG:
1570                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1571                 end_reg = 4 * pkt->count + start_reg - 4;
1572                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1573                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1574                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1575                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1576                         return -EINVAL;
1577                 }
1578                 for (i = 0; i < pkt->count; i++) {
1579                         reg = start_reg + (4 * i);
1580                         r = r600_cs_check_reg(p, reg, idx+1+i);
1581                         if (r)
1582                                 return r;
1583                 }
1584                 break;
1585         case PACKET3_SET_CONTEXT_REG:
1586                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1587                 end_reg = 4 * pkt->count + start_reg - 4;
1588                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1589                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1590                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1591                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1592                         return -EINVAL;
1593                 }
1594                 for (i = 0; i < pkt->count; i++) {
1595                         reg = start_reg + (4 * i);
1596                         r = r600_cs_check_reg(p, reg, idx+1+i);
1597                         if (r)
1598                                 return r;
1599                 }
1600                 break;
1601         case PACKET3_SET_RESOURCE:
1602                 if (pkt->count % 7) {
1603                         DRM_ERROR("bad SET_RESOURCE\n");
1604                         return -EINVAL;
1605                 }
1606                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1607                 end_reg = 4 * pkt->count + start_reg - 4;
1608                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1609                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1610                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1611                         DRM_ERROR("bad SET_RESOURCE\n");
1612                         return -EINVAL;
1613                 }
1614                 for (i = 0; i < (pkt->count / 7); i++) {
1615                         struct radeon_bo *texture, *mipmap;
1616                         u32 size, offset, base_offset, mip_offset;
1617
1618                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1619                         case SQ_TEX_VTX_VALID_TEXTURE:
1620                                 /* tex base */
1621                                 r = r600_cs_packet_next_reloc(p, &reloc);
1622                                 if (r) {
1623                                         DRM_ERROR("bad SET_RESOURCE\n");
1624                                         return -EINVAL;
1625                                 }
1626                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1627                                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1628                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1629                                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1630                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1631                                 texture = reloc->robj;
1632                                 /* tex mip base */
1633                                 r = r600_cs_packet_next_reloc(p, &reloc);
1634                                 if (r) {
1635                                         DRM_ERROR("bad SET_RESOURCE\n");
1636                                         return -EINVAL;
1637                                 }
1638                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1639                                 mipmap = reloc->robj;
1640                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1641                                                                 texture, mipmap,
1642                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1643                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1644                                                                 reloc->lobj.tiling_flags);
1645                                 if (r)
1646                                         return r;
1647                                 ib[idx+1+(i*7)+2] += base_offset;
1648                                 ib[idx+1+(i*7)+3] += mip_offset;
1649                                 break;
1650                         case SQ_TEX_VTX_VALID_BUFFER:
1651                                 /* vtx base */
1652                                 r = r600_cs_packet_next_reloc(p, &reloc);
1653                                 if (r) {
1654                                         DRM_ERROR("bad SET_RESOURCE\n");
1655                                         return -EINVAL;
1656                                 }
1657                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1658                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1659                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1660                                         /* force size to size of the buffer */
1661                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1662                                                  size + offset, radeon_bo_size(reloc->robj));
1663                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1664                                 }
1665                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1666                                 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1667                                 break;
1668                         case SQ_TEX_VTX_INVALID_TEXTURE:
1669                         case SQ_TEX_VTX_INVALID_BUFFER:
1670                         default:
1671                                 DRM_ERROR("bad SET_RESOURCE\n");
1672                                 return -EINVAL;
1673                         }
1674                 }
1675                 break;
1676         case PACKET3_SET_ALU_CONST:
1677                 if (track->sq_config & DX9_CONSTS) {
1678                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1679                         end_reg = 4 * pkt->count + start_reg - 4;
1680                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1681                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1682                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1683                                 DRM_ERROR("bad SET_ALU_CONST\n");
1684                                 return -EINVAL;
1685                         }
1686                 }
1687                 break;
1688         case PACKET3_SET_BOOL_CONST:
1689                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1690                 end_reg = 4 * pkt->count + start_reg - 4;
1691                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1692                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1693                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1694                         DRM_ERROR("bad SET_BOOL_CONST\n");
1695                         return -EINVAL;
1696                 }
1697                 break;
1698         case PACKET3_SET_LOOP_CONST:
1699                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1700                 end_reg = 4 * pkt->count + start_reg - 4;
1701                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1702                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1703                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1704                         DRM_ERROR("bad SET_LOOP_CONST\n");
1705                         return -EINVAL;
1706                 }
1707                 break;
1708         case PACKET3_SET_CTL_CONST:
1709                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1710                 end_reg = 4 * pkt->count + start_reg - 4;
1711                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1712                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1713                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1714                         DRM_ERROR("bad SET_CTL_CONST\n");
1715                         return -EINVAL;
1716                 }
1717                 break;
1718         case PACKET3_SET_SAMPLER:
1719                 if (pkt->count % 3) {
1720                         DRM_ERROR("bad SET_SAMPLER\n");
1721                         return -EINVAL;
1722                 }
1723                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1724                 end_reg = 4 * pkt->count + start_reg - 4;
1725                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1726                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1727                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1728                         DRM_ERROR("bad SET_SAMPLER\n");
1729                         return -EINVAL;
1730                 }
1731                 break;
1732         case PACKET3_SURFACE_BASE_UPDATE:
1733                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1734                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1735                         return -EINVAL;
1736                 }
1737                 if (pkt->count) {
1738                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1739                         return -EINVAL;
1740                 }
1741                 break;
1742         case PACKET3_NOP:
1743                 break;
1744         default:
1745                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1746                 return -EINVAL;
1747         }
1748         return 0;
1749 }
1750
1751 int r600_cs_parse(struct radeon_cs_parser *p)
1752 {
1753         struct radeon_cs_packet pkt;
1754         struct r600_cs_track *track;
1755         int r;
1756
1757         if (p->track == NULL) {
1758                 /* initialize tracker, we are in kms */
1759                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1760                 if (track == NULL)
1761                         return -ENOMEM;
1762                 r600_cs_track_init(track);
1763                 if (p->rdev->family < CHIP_RV770) {
1764                         track->npipes = p->rdev->config.r600.tiling_npipes;
1765                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
1766                         track->group_size = p->rdev->config.r600.tiling_group_size;
1767                 } else if (p->rdev->family <= CHIP_RV740) {
1768                         track->npipes = p->rdev->config.rv770.tiling_npipes;
1769                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1770                         track->group_size = p->rdev->config.rv770.tiling_group_size;
1771                 }
1772                 p->track = track;
1773         }
1774         do {
1775                 r = r600_cs_packet_parse(p, &pkt, p->idx);
1776                 if (r) {
1777                         kfree(p->track);
1778                         p->track = NULL;
1779                         return r;
1780                 }
1781                 p->idx += pkt.count + 2;
1782                 switch (pkt.type) {
1783                 case PACKET_TYPE0:
1784                         r = r600_cs_parse_packet0(p, &pkt);
1785                         break;
1786                 case PACKET_TYPE2:
1787                         break;
1788                 case PACKET_TYPE3:
1789                         r = r600_packet3_check(p, &pkt);
1790                         break;
1791                 default:
1792                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1793                         kfree(p->track);
1794                         p->track = NULL;
1795                         return -EINVAL;
1796                 }
1797                 if (r) {
1798                         kfree(p->track);
1799                         p->track = NULL;
1800                         return r;
1801                 }
1802         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1803 #if 0
1804         for (r = 0; r < p->ib->length_dw; r++) {
1805                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1806                 mdelay(1);
1807         }
1808 #endif
1809         kfree(p->track);
1810         p->track = NULL;
1811         return 0;
1812 }
1813
1814 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1815 {
1816         if (p->chunk_relocs_idx == -1) {
1817                 return 0;
1818         }
1819         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1820         if (p->relocs == NULL) {
1821                 return -ENOMEM;
1822         }
1823         return 0;
1824 }
1825
1826 /**
1827  * cs_parser_fini() - clean parser states
1828  * @parser:     parser structure holding parsing context.
1829  * @error:      error number
1830  *
1831  * If error is set than unvalidate buffer, otherwise just free memory
1832  * used by parsing context.
1833  **/
1834 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1835 {
1836         unsigned i;
1837
1838         kfree(parser->relocs);
1839         for (i = 0; i < parser->nchunks; i++) {
1840                 kfree(parser->chunks[i].kdata);
1841                 kfree(parser->chunks[i].kpage[0]);
1842                 kfree(parser->chunks[i].kpage[1]);
1843         }
1844         kfree(parser->chunks);
1845         kfree(parser->chunks_array);
1846 }
1847
1848 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1849                         unsigned family, u32 *ib, int *l)
1850 {
1851         struct radeon_cs_parser parser;
1852         struct radeon_cs_chunk *ib_chunk;
1853         struct radeon_ib fake_ib;
1854         struct r600_cs_track *track;
1855         int r;
1856
1857         /* initialize tracker */
1858         track = kzalloc(sizeof(*track), GFP_KERNEL);
1859         if (track == NULL)
1860                 return -ENOMEM;
1861         r600_cs_track_init(track);
1862         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1863         /* initialize parser */
1864         memset(&parser, 0, sizeof(struct radeon_cs_parser));
1865         parser.filp = filp;
1866         parser.dev = &dev->pdev->dev;
1867         parser.rdev = NULL;
1868         parser.family = family;
1869         parser.ib = &fake_ib;
1870         parser.track = track;
1871         fake_ib.ptr = ib;
1872         r = radeon_cs_parser_init(&parser, data);
1873         if (r) {
1874                 DRM_ERROR("Failed to initialize parser !\n");
1875                 r600_cs_parser_fini(&parser, r);
1876                 return r;
1877         }
1878         r = r600_cs_parser_relocs_legacy(&parser);
1879         if (r) {
1880                 DRM_ERROR("Failed to parse relocation !\n");
1881                 r600_cs_parser_fini(&parser, r);
1882                 return r;
1883         }
1884         /* Copy the packet into the IB, the parser will read from the
1885          * input memory (cached) and write to the IB (which can be
1886          * uncached). */
1887         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1888         parser.ib->length_dw = ib_chunk->length_dw;
1889         *l = parser.ib->length_dw;
1890         r = r600_cs_parse(&parser);
1891         if (r) {
1892                 DRM_ERROR("Invalid command stream !\n");
1893                 r600_cs_parser_fini(&parser, r);
1894                 return r;
1895         }
1896         r = radeon_cs_finish_pages(&parser);
1897         if (r) {
1898                 DRM_ERROR("Invalid command stream !\n");
1899                 r600_cs_parser_fini(&parser, r);
1900                 return r;
1901         }
1902         r600_cs_parser_fini(&parser, r);
1903         return r;
1904 }
1905
1906 void r600_cs_legacy_init(void)
1907 {
1908         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1909 }