Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes
[pandora-kernel.git] / drivers / gpu / drm / radeon / r600_blit_kms.c
1 #include "drmP.h"
2 #include "drm.h"
3 #include "radeon_drm.h"
4 #include "radeon.h"
5
6 #include "r600d.h"
7 #include "r600_blit_shaders.h"
8
9 #define DI_PT_RECTLIST        0x11
10 #define DI_INDEX_SIZE_16_BIT  0x0
11 #define DI_SRC_SEL_AUTO_INDEX 0x2
12
13 #define FMT_8                 0x1
14 #define FMT_5_6_5             0x8
15 #define FMT_8_8_8_8           0x1a
16 #define COLOR_8               0x1
17 #define COLOR_5_6_5           0x8
18 #define COLOR_8_8_8_8         0x1a
19
20 /* emits 21 on rv770+, 23 on r600 */
21 static void
22 set_render_target(struct radeon_device *rdev, int format,
23                   int w, int h, u64 gpu_addr)
24 {
25         u32 cb_color_info;
26         int pitch, slice;
27
28         h = ALIGN(h, 8);
29         if (h < 8)
30                 h = 8;
31
32         cb_color_info = ((format << 2) | (1 << 27));
33         pitch = (w / 8) - 1;
34         slice = ((w * h) / 64) - 1;
35
36         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
37         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
38         radeon_ring_write(rdev, gpu_addr >> 8);
39
40         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
41                 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
42                 radeon_ring_write(rdev, 2 << 0);
43         }
44
45         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
46         radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
47         radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
48
49         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
50         radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
51         radeon_ring_write(rdev, 0);
52
53         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
54         radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
55         radeon_ring_write(rdev, cb_color_info);
56
57         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58         radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59         radeon_ring_write(rdev, 0);
60
61         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
62         radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
63         radeon_ring_write(rdev, 0);
64
65         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
66         radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
67         radeon_ring_write(rdev, 0);
68 }
69
70 /* emits 5dw */
71 static void
72 cp_set_surface_sync(struct radeon_device *rdev,
73                     u32 sync_type, u32 size,
74                     u64 mc_addr)
75 {
76         u32 cp_coher_size;
77
78         if (size == 0xffffffff)
79                 cp_coher_size = 0xffffffff;
80         else
81                 cp_coher_size = ((size + 255) >> 8);
82
83         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
84         radeon_ring_write(rdev, sync_type);
85         radeon_ring_write(rdev, cp_coher_size);
86         radeon_ring_write(rdev, mc_addr >> 8);
87         radeon_ring_write(rdev, 10); /* poll interval */
88 }
89
90 /* emits 21dw + 1 surface sync = 26dw */
91 static void
92 set_shaders(struct radeon_device *rdev)
93 {
94         u64 gpu_addr;
95         u32 sq_pgm_resources;
96
97         /* setup shader regs */
98         sq_pgm_resources = (1 << 0);
99
100         /* VS */
101         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
102         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
103         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
104         radeon_ring_write(rdev, gpu_addr >> 8);
105
106         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
107         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
108         radeon_ring_write(rdev, sq_pgm_resources);
109
110         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
111         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
112         radeon_ring_write(rdev, 0);
113
114         /* PS */
115         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
116         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
117         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
118         radeon_ring_write(rdev, gpu_addr >> 8);
119
120         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
121         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
122         radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
123
124         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
125         radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
126         radeon_ring_write(rdev, 2);
127
128         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
129         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
130         radeon_ring_write(rdev, 0);
131
132         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
133         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
134 }
135
136 /* emits 9 + 1 sync (5) = 14*/
137 static void
138 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
139 {
140         u32 sq_vtx_constant_word2;
141
142         sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
143
144         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
145         radeon_ring_write(rdev, 0x460);
146         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
147         radeon_ring_write(rdev, 48 - 1);
148         radeon_ring_write(rdev, sq_vtx_constant_word2);
149         radeon_ring_write(rdev, 1 << 0);
150         radeon_ring_write(rdev, 0);
151         radeon_ring_write(rdev, 0);
152         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
153
154         if ((rdev->family == CHIP_RV610) ||
155             (rdev->family == CHIP_RV620) ||
156             (rdev->family == CHIP_RS780) ||
157             (rdev->family == CHIP_RS880) ||
158             (rdev->family == CHIP_RV710))
159                 cp_set_surface_sync(rdev,
160                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
161         else
162                 cp_set_surface_sync(rdev,
163                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
164 }
165
166 /* emits 9 */
167 static void
168 set_tex_resource(struct radeon_device *rdev,
169                  int format, int w, int h, int pitch,
170                  u64 gpu_addr)
171 {
172         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
173
174         if (h < 1)
175                 h = 1;
176
177         sq_tex_resource_word0 = (1 << 0);
178         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
179                                   ((w - 1) << 19));
180
181         sq_tex_resource_word1 = (format << 26);
182         sq_tex_resource_word1 |= ((h - 1) << 0);
183
184         sq_tex_resource_word4 = ((1 << 14) |
185                                  (0 << 16) |
186                                  (1 << 19) |
187                                  (2 << 22) |
188                                  (3 << 25));
189
190         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
191         radeon_ring_write(rdev, 0);
192         radeon_ring_write(rdev, sq_tex_resource_word0);
193         radeon_ring_write(rdev, sq_tex_resource_word1);
194         radeon_ring_write(rdev, gpu_addr >> 8);
195         radeon_ring_write(rdev, gpu_addr >> 8);
196         radeon_ring_write(rdev, sq_tex_resource_word4);
197         radeon_ring_write(rdev, 0);
198         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
199 }
200
201 /* emits 12 */
202 static void
203 set_scissors(struct radeon_device *rdev, int x1, int y1,
204              int x2, int y2)
205 {
206         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
207         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
208         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
209         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
210
211         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
212         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
213         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
214         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
215
216         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
217         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
218         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
219         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
220 }
221
222 /* emits 10 */
223 static void
224 draw_auto(struct radeon_device *rdev)
225 {
226         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
227         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
228         radeon_ring_write(rdev, DI_PT_RECTLIST);
229
230         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
231         radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
232
233         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
234         radeon_ring_write(rdev, 1);
235
236         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
237         radeon_ring_write(rdev, 3);
238         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
239
240 }
241
242 /* emits 14 */
243 static void
244 set_default_state(struct radeon_device *rdev)
245 {
246         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
247         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
248         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
249         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
250         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
251         u64 gpu_addr;
252         int dwords;
253
254         switch (rdev->family) {
255         case CHIP_R600:
256                 num_ps_gprs = 192;
257                 num_vs_gprs = 56;
258                 num_temp_gprs = 4;
259                 num_gs_gprs = 0;
260                 num_es_gprs = 0;
261                 num_ps_threads = 136;
262                 num_vs_threads = 48;
263                 num_gs_threads = 4;
264                 num_es_threads = 4;
265                 num_ps_stack_entries = 128;
266                 num_vs_stack_entries = 128;
267                 num_gs_stack_entries = 0;
268                 num_es_stack_entries = 0;
269                 break;
270         case CHIP_RV630:
271         case CHIP_RV635:
272                 num_ps_gprs = 84;
273                 num_vs_gprs = 36;
274                 num_temp_gprs = 4;
275                 num_gs_gprs = 0;
276                 num_es_gprs = 0;
277                 num_ps_threads = 144;
278                 num_vs_threads = 40;
279                 num_gs_threads = 4;
280                 num_es_threads = 4;
281                 num_ps_stack_entries = 40;
282                 num_vs_stack_entries = 40;
283                 num_gs_stack_entries = 32;
284                 num_es_stack_entries = 16;
285                 break;
286         case CHIP_RV610:
287         case CHIP_RV620:
288         case CHIP_RS780:
289         case CHIP_RS880:
290         default:
291                 num_ps_gprs = 84;
292                 num_vs_gprs = 36;
293                 num_temp_gprs = 4;
294                 num_gs_gprs = 0;
295                 num_es_gprs = 0;
296                 num_ps_threads = 136;
297                 num_vs_threads = 48;
298                 num_gs_threads = 4;
299                 num_es_threads = 4;
300                 num_ps_stack_entries = 40;
301                 num_vs_stack_entries = 40;
302                 num_gs_stack_entries = 32;
303                 num_es_stack_entries = 16;
304                 break;
305         case CHIP_RV670:
306                 num_ps_gprs = 144;
307                 num_vs_gprs = 40;
308                 num_temp_gprs = 4;
309                 num_gs_gprs = 0;
310                 num_es_gprs = 0;
311                 num_ps_threads = 136;
312                 num_vs_threads = 48;
313                 num_gs_threads = 4;
314                 num_es_threads = 4;
315                 num_ps_stack_entries = 40;
316                 num_vs_stack_entries = 40;
317                 num_gs_stack_entries = 32;
318                 num_es_stack_entries = 16;
319                 break;
320         case CHIP_RV770:
321                 num_ps_gprs = 192;
322                 num_vs_gprs = 56;
323                 num_temp_gprs = 4;
324                 num_gs_gprs = 0;
325                 num_es_gprs = 0;
326                 num_ps_threads = 188;
327                 num_vs_threads = 60;
328                 num_gs_threads = 0;
329                 num_es_threads = 0;
330                 num_ps_stack_entries = 256;
331                 num_vs_stack_entries = 256;
332                 num_gs_stack_entries = 0;
333                 num_es_stack_entries = 0;
334                 break;
335         case CHIP_RV730:
336         case CHIP_RV740:
337                 num_ps_gprs = 84;
338                 num_vs_gprs = 36;
339                 num_temp_gprs = 4;
340                 num_gs_gprs = 0;
341                 num_es_gprs = 0;
342                 num_ps_threads = 188;
343                 num_vs_threads = 60;
344                 num_gs_threads = 0;
345                 num_es_threads = 0;
346                 num_ps_stack_entries = 128;
347                 num_vs_stack_entries = 128;
348                 num_gs_stack_entries = 0;
349                 num_es_stack_entries = 0;
350                 break;
351         case CHIP_RV710:
352                 num_ps_gprs = 192;
353                 num_vs_gprs = 56;
354                 num_temp_gprs = 4;
355                 num_gs_gprs = 0;
356                 num_es_gprs = 0;
357                 num_ps_threads = 144;
358                 num_vs_threads = 48;
359                 num_gs_threads = 0;
360                 num_es_threads = 0;
361                 num_ps_stack_entries = 128;
362                 num_vs_stack_entries = 128;
363                 num_gs_stack_entries = 0;
364                 num_es_stack_entries = 0;
365                 break;
366         }
367
368         if ((rdev->family == CHIP_RV610) ||
369             (rdev->family == CHIP_RV620) ||
370             (rdev->family == CHIP_RS780) ||
371             (rdev->family == CHIP_RS880) ||
372             (rdev->family == CHIP_RV710))
373                 sq_config = 0;
374         else
375                 sq_config = VC_ENABLE;
376
377         sq_config |= (DX9_CONSTS |
378                       ALU_INST_PREFER_VECTOR |
379                       PS_PRIO(0) |
380                       VS_PRIO(1) |
381                       GS_PRIO(2) |
382                       ES_PRIO(3));
383
384         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
385                                   NUM_VS_GPRS(num_vs_gprs) |
386                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
387         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
388                                   NUM_ES_GPRS(num_es_gprs));
389         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
390                                    NUM_VS_THREADS(num_vs_threads) |
391                                    NUM_GS_THREADS(num_gs_threads) |
392                                    NUM_ES_THREADS(num_es_threads));
393         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
394                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
395         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
396                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
397
398         /* emit an IB pointing at default state */
399         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
400         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
401         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
402         radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
403         radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
404         radeon_ring_write(rdev, dwords);
405
406         /* SQ config */
407         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
408         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
409         radeon_ring_write(rdev, sq_config);
410         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
411         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
412         radeon_ring_write(rdev, sq_thread_resource_mgmt);
413         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
414         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
415 }
416
417 static inline uint32_t i2f(uint32_t input)
418 {
419         u32 result, i, exponent, fraction;
420
421         if ((input & 0x3fff) == 0)
422                 result = 0; /* 0 is a special case */
423         else {
424                 exponent = 140; /* exponent biased by 127; */
425                 fraction = (input & 0x3fff) << 10; /* cheat and only
426                                                       handle numbers below 2^^15 */
427                 for (i = 0; i < 14; i++) {
428                         if (fraction & 0x800000)
429                                 break;
430                         else {
431                                 fraction = fraction << 1; /* keep
432                                                              shifting left until top bit = 1 */
433                                 exponent = exponent - 1;
434                         }
435                 }
436                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
437                                                                     off top bit; assumed 1 */
438         }
439         return result;
440 }
441
442 int r600_blit_init(struct radeon_device *rdev)
443 {
444         u32 obj_size;
445         int r, dwords;
446         void *ptr;
447         u32 packet2s[16];
448         int num_packet2s = 0;
449
450         /* don't reinitialize blit */
451         if (rdev->r600_blit.shader_obj)
452                 return 0;
453         mutex_init(&rdev->r600_blit.mutex);
454         rdev->r600_blit.state_offset = 0;
455
456         if (rdev->family >= CHIP_RV770)
457                 rdev->r600_blit.state_len = r7xx_default_size;
458         else
459                 rdev->r600_blit.state_len = r6xx_default_size;
460
461         dwords = rdev->r600_blit.state_len;
462         while (dwords & 0xf) {
463                 packet2s[num_packet2s++] = PACKET2(0);
464                 dwords++;
465         }
466
467         obj_size = dwords * 4;
468         obj_size = ALIGN(obj_size, 256);
469
470         rdev->r600_blit.vs_offset = obj_size;
471         obj_size += r6xx_vs_size * 4;
472         obj_size = ALIGN(obj_size, 256);
473
474         rdev->r600_blit.ps_offset = obj_size;
475         obj_size += r6xx_ps_size * 4;
476         obj_size = ALIGN(obj_size, 256);
477
478         r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM,
479                                 &rdev->r600_blit.shader_obj);
480         if (r) {
481                 DRM_ERROR("r600 failed to allocate shader\n");
482                 return r;
483         }
484
485         DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
486                   obj_size,
487                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
488
489         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
490         if (unlikely(r != 0))
491                 return r;
492         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
493         if (r) {
494                 DRM_ERROR("failed to map blit object %d\n", r);
495                 return r;
496         }
497         if (rdev->family >= CHIP_RV770)
498                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
499                             r7xx_default_state, rdev->r600_blit.state_len * 4);
500         else
501                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
502                             r6xx_default_state, rdev->r600_blit.state_len * 4);
503         if (num_packet2s)
504                 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
505                             packet2s, num_packet2s * 4);
506         memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
507         memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
508         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
509         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
510         return 0;
511 }
512
513 void r600_blit_fini(struct radeon_device *rdev)
514 {
515         int r;
516
517         if (rdev->r600_blit.shader_obj == NULL)
518                 return;
519         /* If we can't reserve the bo, unref should be enough to destroy
520          * it when it becomes idle.
521          */
522         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
523         if (!r) {
524                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
525                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
526         }
527         radeon_bo_unref(&rdev->r600_blit.shader_obj);
528 }
529
530 int r600_vb_ib_get(struct radeon_device *rdev)
531 {
532         int r;
533         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
534         if (r) {
535                 DRM_ERROR("failed to get IB for vertex buffer\n");
536                 return r;
537         }
538
539         rdev->r600_blit.vb_total = 64*1024;
540         rdev->r600_blit.vb_used = 0;
541         return 0;
542 }
543
544 void r600_vb_ib_put(struct radeon_device *rdev)
545 {
546         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
547         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
548 }
549
550 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
551 {
552         int r;
553         int ring_size, line_size;
554         int max_size;
555         /* loops of emits 64 + fence emit possible */
556         int dwords_per_loop = 76, num_loops;
557
558         r = r600_vb_ib_get(rdev);
559         if (r)
560                 return r;
561
562         /* set_render_target emits 2 extra dwords on rv6xx */
563         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
564                 dwords_per_loop += 2;
565
566         /* 8 bpp vs 32 bpp for xfer unit */
567         if (size_bytes & 3)
568                 line_size = 8192;
569         else
570                 line_size = 8192*4;
571
572         max_size = 8192 * line_size;
573
574         /* major loops cover the max size transfer */
575         num_loops = ((size_bytes + max_size) / max_size);
576         /* minor loops cover the extra non aligned bits */
577         num_loops += ((size_bytes % line_size) ? 1 : 0);
578         /* calculate number of loops correctly */
579         ring_size = num_loops * dwords_per_loop;
580         /* set default  + shaders */
581         ring_size += 40; /* shaders + def state */
582         ring_size += 10; /* fence emit for VB IB */
583         ring_size += 5; /* done copy */
584         ring_size += 10; /* fence emit for done copy */
585         r = radeon_ring_lock(rdev, ring_size);
586         if (r)
587                 return r;
588
589         set_default_state(rdev); /* 14 */
590         set_shaders(rdev); /* 26 */
591         return 0;
592 }
593
594 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
595 {
596         int r;
597
598         if (rdev->r600_blit.vb_ib)
599                 r600_vb_ib_put(rdev);
600
601         if (fence)
602                 r = radeon_fence_emit(rdev, fence);
603
604         radeon_ring_unlock_commit(rdev);
605 }
606
607 void r600_kms_blit_copy(struct radeon_device *rdev,
608                         u64 src_gpu_addr, u64 dst_gpu_addr,
609                         int size_bytes)
610 {
611         int max_bytes;
612         u64 vb_gpu_addr;
613         u32 *vb;
614
615         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
616                   size_bytes, rdev->r600_blit.vb_used);
617         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
618         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
619                 max_bytes = 8192;
620
621                 while (size_bytes) {
622                         int cur_size = size_bytes;
623                         int src_x = src_gpu_addr & 255;
624                         int dst_x = dst_gpu_addr & 255;
625                         int h = 1;
626                         src_gpu_addr = src_gpu_addr & ~255;
627                         dst_gpu_addr = dst_gpu_addr & ~255;
628
629                         if (!src_x && !dst_x) {
630                                 h = (cur_size / max_bytes);
631                                 if (h > 8192)
632                                         h = 8192;
633                                 if (h == 0)
634                                         h = 1;
635                                 else
636                                         cur_size = max_bytes;
637                         } else {
638                                 if (cur_size > max_bytes)
639                                         cur_size = max_bytes;
640                                 if (cur_size > (max_bytes - dst_x))
641                                         cur_size = (max_bytes - dst_x);
642                                 if (cur_size > (max_bytes - src_x))
643                                         cur_size = (max_bytes - src_x);
644                         }
645
646                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
647                                 WARN_ON(1);
648
649 #if 0
650                                 r600_vb_ib_put(rdev);
651
652                                 r600_nomm_put_vb(dev);
653                                 r600_nomm_get_vb(dev);
654                                 if (!dev_priv->blit_vb)
655                                         return;
656                                 set_shaders(dev);
657                                 vb = r600_nomm_get_vb_ptr(dev);
658 #endif
659                         }
660
661                         vb[0] = i2f(dst_x);
662                         vb[1] = 0;
663                         vb[2] = i2f(src_x);
664                         vb[3] = 0;
665
666                         vb[4] = i2f(dst_x);
667                         vb[5] = i2f(h);
668                         vb[6] = i2f(src_x);
669                         vb[7] = i2f(h);
670
671                         vb[8] = i2f(dst_x + cur_size);
672                         vb[9] = i2f(h);
673                         vb[10] = i2f(src_x + cur_size);
674                         vb[11] = i2f(h);
675
676                         /* src 9 */
677                         set_tex_resource(rdev, FMT_8,
678                                          src_x + cur_size, h, src_x + cur_size,
679                                          src_gpu_addr);
680
681                         /* 5 */
682                         cp_set_surface_sync(rdev,
683                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
684
685                         /* dst 23 */
686                         set_render_target(rdev, COLOR_8,
687                                           dst_x + cur_size, h,
688                                           dst_gpu_addr);
689
690                         /* scissors 12 */
691                         set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
692
693                         /* 14 */
694                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
695                         set_vtx_resource(rdev, vb_gpu_addr);
696
697                         /* draw 10 */
698                         draw_auto(rdev);
699
700                         /* 5 */
701                         cp_set_surface_sync(rdev,
702                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
703                                             cur_size * h, dst_gpu_addr);
704
705                         vb += 12;
706                         rdev->r600_blit.vb_used += 12 * 4;
707
708                         src_gpu_addr += cur_size * h;
709                         dst_gpu_addr += cur_size * h;
710                         size_bytes -= cur_size * h;
711                 }
712         } else {
713                 max_bytes = 8192 * 4;
714
715                 while (size_bytes) {
716                         int cur_size = size_bytes;
717                         int src_x = (src_gpu_addr & 255);
718                         int dst_x = (dst_gpu_addr & 255);
719                         int h = 1;
720                         src_gpu_addr = src_gpu_addr & ~255;
721                         dst_gpu_addr = dst_gpu_addr & ~255;
722
723                         if (!src_x && !dst_x) {
724                                 h = (cur_size / max_bytes);
725                                 if (h > 8192)
726                                         h = 8192;
727                                 if (h == 0)
728                                         h = 1;
729                                 else
730                                         cur_size = max_bytes;
731                         } else {
732                                 if (cur_size > max_bytes)
733                                         cur_size = max_bytes;
734                                 if (cur_size > (max_bytes - dst_x))
735                                         cur_size = (max_bytes - dst_x);
736                                 if (cur_size > (max_bytes - src_x))
737                                         cur_size = (max_bytes - src_x);
738                         }
739
740                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
741                                 WARN_ON(1);
742                         }
743 #if 0
744                         if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) {
745                                 r600_nomm_put_vb(dev);
746                                 r600_nomm_get_vb(dev);
747                                 if (!rdev->blit_vb)
748                                         return;
749
750                                 set_shaders(dev);
751                                 vb = r600_nomm_get_vb_ptr(dev);
752                         }
753 #endif
754
755                         vb[0] = i2f(dst_x / 4);
756                         vb[1] = 0;
757                         vb[2] = i2f(src_x / 4);
758                         vb[3] = 0;
759
760                         vb[4] = i2f(dst_x / 4);
761                         vb[5] = i2f(h);
762                         vb[6] = i2f(src_x / 4);
763                         vb[7] = i2f(h);
764
765                         vb[8] = i2f((dst_x + cur_size) / 4);
766                         vb[9] = i2f(h);
767                         vb[10] = i2f((src_x + cur_size) / 4);
768                         vb[11] = i2f(h);
769
770                         /* src 9 */
771                         set_tex_resource(rdev, FMT_8_8_8_8,
772                                          (src_x + cur_size) / 4,
773                                          h, (src_x + cur_size) / 4,
774                                          src_gpu_addr);
775                         /* 5 */
776                         cp_set_surface_sync(rdev,
777                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
778
779                         /* dst 23 */
780                         set_render_target(rdev, COLOR_8_8_8_8,
781                                           (dst_x + cur_size) / 4, h,
782                                           dst_gpu_addr);
783
784                         /* scissors 12  */
785                         set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
786
787                         /* Vertex buffer setup 14 */
788                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
789                         set_vtx_resource(rdev, vb_gpu_addr);
790
791                         /* draw 10 */
792                         draw_auto(rdev);
793
794                         /* 5 */
795                         cp_set_surface_sync(rdev,
796                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
797                                             cur_size * h, dst_gpu_addr);
798
799                         /* 78 ring dwords per loop */
800                         vb += 12;
801                         rdev->r600_blit.vb_used += 12 * 4;
802
803                         src_gpu_addr += cur_size * h;
804                         dst_gpu_addr += cur_size * h;
805                         size_bytes -= cur_size * h;
806                 }
807         }
808 }
809