drivers/gpu/drm/radeon/r600_blit_kms.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  * Copyright 2009 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "drmP.h"
  27 #include "drm.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30
  31 #include "r600d.h"
  32 #include "r600_blit_shaders.h"
  33
  34 #define DI_PT_RECTLIST        0x11
  35 #define DI_INDEX_SIZE_16_BIT  0x0
  36 #define DI_SRC_SEL_AUTO_INDEX 0x2
  37
  38 #define FMT_8                 0x1
  39 #define FMT_5_6_5             0x8
  40 #define FMT_8_8_8_8           0x1a
  41 #define COLOR_8               0x1
  42 #define COLOR_5_6_5           0x8
  43 #define COLOR_8_8_8_8         0x1a
  44
  45 /* emits 21 on rv770+, 23 on r600 */
  46 static void
  47 set_render_target(struct radeon_device *rdev, int format,
  48                   int w, int h, u64 gpu_addr)
  49 {
  50         u32 cb_color_info;
  51         int pitch, slice;
  52
  53         h = ALIGN(h, 8);
  54         if (h < 8)
  55                 h = 8;
  56
  57         cb_color_info = ((format << 2) | (1 << 27));
  58         pitch = (w / 8) - 1;
  59         slice = ((w * h) / 64) - 1;
  60
  61         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  62         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  63         radeon_ring_write(rdev, gpu_addr >> 8);
  64
  65         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
  66                 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
  67                 radeon_ring_write(rdev, 2 << 0);
  68         }
  69
  70         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  71         radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  72         radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
  73
  74         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  75         radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  76         radeon_ring_write(rdev, 0);
  77
  78         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  79         radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  80         radeon_ring_write(rdev, cb_color_info);
  81
  82         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  83         radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  84         radeon_ring_write(rdev, 0);
  85
  86         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  87         radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  88         radeon_ring_write(rdev, 0);
  89
  90         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  91         radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  92         radeon_ring_write(rdev, 0);
  93 }
  94
  95 /* emits 5dw */
  96 static void
  97 cp_set_surface_sync(struct radeon_device *rdev,
  98                     u32 sync_type, u32 size,
  99                     u64 mc_addr)
 100 {
 101         u32 cp_coher_size;
 102
 103         if (size == 0xffffffff)
 104                 cp_coher_size = 0xffffffff;
 105         else
 106                 cp_coher_size = ((size + 255) >> 8);
 107
 108         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
 109         radeon_ring_write(rdev, sync_type);
 110         radeon_ring_write(rdev, cp_coher_size);
 111         radeon_ring_write(rdev, mc_addr >> 8);
 112         radeon_ring_write(rdev, 10); /* poll interval */
 113 }
 114
 115 /* emits 21dw + 1 surface sync = 26dw */
 116 static void
 117 set_shaders(struct radeon_device *rdev)
 118 {
 119         u64 gpu_addr;
 120         u32 sq_pgm_resources;
 121
 122         /* setup shader regs */
 123         sq_pgm_resources = (1 << 0);
 124
 125         /* VS */
 126         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 127         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 128         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 129         radeon_ring_write(rdev, gpu_addr >> 8);
 130
 131         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 132         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 133         radeon_ring_write(rdev, sq_pgm_resources);
 134
 135         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 136         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 137         radeon_ring_write(rdev, 0);
 138
 139         /* PS */
 140         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 141         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 142         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 143         radeon_ring_write(rdev, gpu_addr >> 8);
 144
 145         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 146         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 147         radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
 148
 149         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 150         radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 151         radeon_ring_write(rdev, 2);
 152
 153         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 154         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 155         radeon_ring_write(rdev, 0);
 156
 157         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 158         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 159 }
 160
 161 /* emits 9 + 1 sync (5) = 14*/
 162 static void
 163 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 164 {
 165         u32 sq_vtx_constant_word2;
 166
 167         sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
 168
 169         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 170         radeon_ring_write(rdev, 0x460);
 171         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 172         radeon_ring_write(rdev, 48 - 1);
 173         radeon_ring_write(rdev, sq_vtx_constant_word2);
 174         radeon_ring_write(rdev, 1 << 0);
 175         radeon_ring_write(rdev, 0);
 176         radeon_ring_write(rdev, 0);
 177         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 178
 179         if ((rdev->family == CHIP_RV610) ||
 180             (rdev->family == CHIP_RV620) ||
 181             (rdev->family == CHIP_RS780) ||
 182             (rdev->family == CHIP_RS880) ||
 183             (rdev->family == CHIP_RV710))
 184                 cp_set_surface_sync(rdev,
 185                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 186         else
 187                 cp_set_surface_sync(rdev,
 188                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 189 }
 190
 191 /* emits 9 */
 192 static void
 193 set_tex_resource(struct radeon_device *rdev,
 194                  int format, int w, int h, int pitch,
 195                  u64 gpu_addr)
 196 {
 197         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 198
 199         if (h < 1)
 200                 h = 1;
 201
 202         sq_tex_resource_word0 = (1 << 0);
 203         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
 204                                   ((w - 1) << 19));
 205
 206         sq_tex_resource_word1 = (format << 26);
 207         sq_tex_resource_word1 |= ((h - 1) << 0);
 208
 209         sq_tex_resource_word4 = ((1 << 14) |
 210                                  (0 << 16) |
 211                                  (1 << 19) |
 212                                  (2 << 22) |
 213                                  (3 << 25));
 214
 215         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 216         radeon_ring_write(rdev, 0);
 217         radeon_ring_write(rdev, sq_tex_resource_word0);
 218         radeon_ring_write(rdev, sq_tex_resource_word1);
 219         radeon_ring_write(rdev, gpu_addr >> 8);
 220         radeon_ring_write(rdev, gpu_addr >> 8);
 221         radeon_ring_write(rdev, sq_tex_resource_word4);
 222         radeon_ring_write(rdev, 0);
 223         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
 224 }
 225
 226 /* emits 12 */
 227 static void
 228 set_scissors(struct radeon_device *rdev, int x1, int y1,
 229              int x2, int y2)
 230 {
 231         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 232         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 233         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 234         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 235
 236         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 237         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 238         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 239         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 240
 241         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 242         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 243         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 244         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 245 }
 246
 247 /* emits 10 */
 248 static void
 249 draw_auto(struct radeon_device *rdev)
 250 {
 251         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 252         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 253         radeon_ring_write(rdev, DI_PT_RECTLIST);
 254
 255         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 256         radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
 257
 258         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 259         radeon_ring_write(rdev, 1);
 260
 261         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 262         radeon_ring_write(rdev, 3);
 263         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 264
 265 }
 266
 267 /* emits 14 */
 268 static void
 269 set_default_state(struct radeon_device *rdev)
 270 {
 271         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 272         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 273         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 274         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 275         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 276         u64 gpu_addr;
 277         int dwords;
 278
 279         switch (rdev->family) {
 280         case CHIP_R600:
 281                 num_ps_gprs = 192;
 282                 num_vs_gprs = 56;
 283                 num_temp_gprs = 4;
 284                 num_gs_gprs = 0;
 285                 num_es_gprs = 0;
 286                 num_ps_threads = 136;
 287                 num_vs_threads = 48;
 288                 num_gs_threads = 4;
 289                 num_es_threads = 4;
 290                 num_ps_stack_entries = 128;
 291                 num_vs_stack_entries = 128;
 292                 num_gs_stack_entries = 0;
 293                 num_es_stack_entries = 0;
 294                 break;
 295         case CHIP_RV630:
 296         case CHIP_RV635:
 297                 num_ps_gprs = 84;
 298                 num_vs_gprs = 36;
 299                 num_temp_gprs = 4;
 300                 num_gs_gprs = 0;
 301                 num_es_gprs = 0;
 302                 num_ps_threads = 144;
 303                 num_vs_threads = 40;
 304                 num_gs_threads = 4;
 305                 num_es_threads = 4;
 306                 num_ps_stack_entries = 40;
 307                 num_vs_stack_entries = 40;
 308                 num_gs_stack_entries = 32;
 309                 num_es_stack_entries = 16;
 310                 break;
 311         case CHIP_RV610:
 312         case CHIP_RV620:
 313         case CHIP_RS780:
 314         case CHIP_RS880:
 315         default:
 316                 num_ps_gprs = 84;
 317                 num_vs_gprs = 36;
 318                 num_temp_gprs = 4;
 319                 num_gs_gprs = 0;
 320                 num_es_gprs = 0;
 321                 num_ps_threads = 136;
 322                 num_vs_threads = 48;
 323                 num_gs_threads = 4;
 324                 num_es_threads = 4;
 325                 num_ps_stack_entries = 40;
 326                 num_vs_stack_entries = 40;
 327                 num_gs_stack_entries = 32;
 328                 num_es_stack_entries = 16;
 329                 break;
 330         case CHIP_RV670:
 331                 num_ps_gprs = 144;
 332                 num_vs_gprs = 40;
 333                 num_temp_gprs = 4;
 334                 num_gs_gprs = 0;
 335                 num_es_gprs = 0;
 336                 num_ps_threads = 136;
 337                 num_vs_threads = 48;
 338                 num_gs_threads = 4;
 339                 num_es_threads = 4;
 340                 num_ps_stack_entries = 40;
 341                 num_vs_stack_entries = 40;
 342                 num_gs_stack_entries = 32;
 343                 num_es_stack_entries = 16;
 344                 break;
 345         case CHIP_RV770:
 346                 num_ps_gprs = 192;
 347                 num_vs_gprs = 56;
 348                 num_temp_gprs = 4;
 349                 num_gs_gprs = 0;
 350                 num_es_gprs = 0;
 351                 num_ps_threads = 188;
 352                 num_vs_threads = 60;
 353                 num_gs_threads = 0;
 354                 num_es_threads = 0;
 355                 num_ps_stack_entries = 256;
 356                 num_vs_stack_entries = 256;
 357                 num_gs_stack_entries = 0;
 358                 num_es_stack_entries = 0;
 359                 break;
 360         case CHIP_RV730:
 361         case CHIP_RV740:
 362                 num_ps_gprs = 84;
 363                 num_vs_gprs = 36;
 364                 num_temp_gprs = 4;
 365                 num_gs_gprs = 0;
 366                 num_es_gprs = 0;
 367                 num_ps_threads = 188;
 368                 num_vs_threads = 60;
 369                 num_gs_threads = 0;
 370                 num_es_threads = 0;
 371                 num_ps_stack_entries = 128;
 372                 num_vs_stack_entries = 128;
 373                 num_gs_stack_entries = 0;
 374                 num_es_stack_entries = 0;
 375                 break;
 376         case CHIP_RV710:
 377                 num_ps_gprs = 192;
 378                 num_vs_gprs = 56;
 379                 num_temp_gprs = 4;
 380                 num_gs_gprs = 0;
 381                 num_es_gprs = 0;
 382                 num_ps_threads = 144;
 383                 num_vs_threads = 48;
 384                 num_gs_threads = 0;
 385                 num_es_threads = 0;
 386                 num_ps_stack_entries = 128;
 387                 num_vs_stack_entries = 128;
 388                 num_gs_stack_entries = 0;
 389                 num_es_stack_entries = 0;
 390                 break;
 391         }
 392
 393         if ((rdev->family == CHIP_RV610) ||
 394             (rdev->family == CHIP_RV620) ||
 395             (rdev->family == CHIP_RS780) ||
 396             (rdev->family == CHIP_RS880) ||
 397             (rdev->family == CHIP_RV710))
 398                 sq_config = 0;
 399         else
 400                 sq_config = VC_ENABLE;
 401
 402         sq_config |= (DX9_CONSTS |
 403                       ALU_INST_PREFER_VECTOR |
 404                       PS_PRIO(0) |
 405                       VS_PRIO(1) |
 406                       GS_PRIO(2) |
 407                       ES_PRIO(3));
 408
 409         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 410                                   NUM_VS_GPRS(num_vs_gprs) |
 411                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 412         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 413                                   NUM_ES_GPRS(num_es_gprs));
 414         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 415                                    NUM_VS_THREADS(num_vs_threads) |
 416                                    NUM_GS_THREADS(num_gs_threads) |
 417                                    NUM_ES_THREADS(num_es_threads));
 418         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 419                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 420         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 421                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 422
 423         /* emit an IB pointing at default state */
 424         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 425         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 426         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 427         radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
 428         radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
 429         radeon_ring_write(rdev, dwords);
 430
 431         /* SQ config */
 432         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
 433         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 434         radeon_ring_write(rdev, sq_config);
 435         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 436         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 437         radeon_ring_write(rdev, sq_thread_resource_mgmt);
 438         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 439         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 440 }
 441
 442 static inline uint32_t i2f(uint32_t input)
 443 {
 444         u32 result, i, exponent, fraction;
 445
 446         if ((input & 0x3fff) == 0)
 447                 result = 0; /* 0 is a special case */
 448         else {
 449                 exponent = 140; /* exponent biased by 127; */
 450                 fraction = (input & 0x3fff) << 10; /* cheat and only
 451                                                       handle numbers below 2^^15 */
 452                 for (i = 0; i < 14; i++) {
 453                         if (fraction & 0x800000)
 454                                 break;
 455                         else {
 456                                 fraction = fraction << 1; /* keep
 457                                                              shifting left until top bit = 1 */
 458                                 exponent = exponent - 1;
 459                         }
 460                 }
 461                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 462                                                                     off top bit; assumed 1 */
 463         }
 464         return result;
 465 }
 466
 467 int r600_blit_init(struct radeon_device *rdev)
 468 {
 469         u32 obj_size;
 470         int r, dwords;
 471         void *ptr;
 472         u32 packet2s[16];
 473         int num_packet2s = 0;
 474
 475         /* pin copy shader into vram if already initialized */
 476         if (rdev->r600_blit.shader_obj)
 477                 goto done;
 478
 479         mutex_init(&rdev->r600_blit.mutex);
 480         rdev->r600_blit.state_offset = 0;
 481
 482         if (rdev->family >= CHIP_RV770)
 483                 rdev->r600_blit.state_len = r7xx_default_size;
 484         else
 485                 rdev->r600_blit.state_len = r6xx_default_size;
 486
 487         dwords = rdev->r600_blit.state_len;
 488         while (dwords & 0xf) {
 489                 packet2s[num_packet2s++] = PACKET2(0);
 490                 dwords++;
 491         }
 492
 493         obj_size = dwords * 4;
 494         obj_size = ALIGN(obj_size, 256);
 495
 496         rdev->r600_blit.vs_offset = obj_size;
 497         obj_size += r6xx_vs_size * 4;
 498         obj_size = ALIGN(obj_size, 256);
 499
 500         rdev->r600_blit.ps_offset = obj_size;
 501         obj_size += r6xx_ps_size * 4;
 502         obj_size = ALIGN(obj_size, 256);
 503
 504         r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM,
 505                                 &rdev->r600_blit.shader_obj);
 506         if (r) {
 507                 DRM_ERROR("r600 failed to allocate shader\n");
 508                 return r;
 509         }
 510
 511         DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
 512                   obj_size,
 513                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 514
 515         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 516         if (unlikely(r != 0))
 517                 return r;
 518         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 519         if (r) {
 520                 DRM_ERROR("failed to map blit object %d\n", r);
 521                 return r;
 522         }
 523         if (rdev->family >= CHIP_RV770)
 524                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 525                             r7xx_default_state, rdev->r600_blit.state_len * 4);
 526         else
 527                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 528                             r6xx_default_state, rdev->r600_blit.state_len * 4);
 529         if (num_packet2s)
 530                 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 531                             packet2s, num_packet2s * 4);
 532         memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
 533         memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
 534         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 535         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 536
 537 done:
 538         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 539         if (unlikely(r != 0))
 540                 return r;
 541         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 542                           &rdev->r600_blit.shader_gpu_addr);
 543         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 544         if (r) {
 545                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 546                 return r;
 547         }
 548         rdev->mc.active_vram_size = rdev->mc.real_vram_size;
 549         return 0;
 550 }
 551
 552 void r600_blit_fini(struct radeon_device *rdev)
 553 {
 554         int r;
 555
 556         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 557         if (rdev->r600_blit.shader_obj == NULL)
 558                 return;
 559         /* If we can't reserve the bo, unref should be enough to destroy
 560          * it when it becomes idle.
 561          */
 562         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 563         if (!r) {
 564                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 565                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 566         }
 567         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 568 }
 569
 570 static int r600_vb_ib_get(struct radeon_device *rdev)
 571 {
 572         int r;
 573         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 574         if (r) {
 575                 DRM_ERROR("failed to get IB for vertex buffer\n");
 576                 return r;
 577         }
 578
 579         rdev->r600_blit.vb_total = 64*1024;
 580         rdev->r600_blit.vb_used = 0;
 581         return 0;
 582 }
 583
 584 static void r600_vb_ib_put(struct radeon_device *rdev)
 585 {
 586         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 587         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 588 }
 589
 590 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 591 {
 592         int r;
 593         int ring_size, line_size;
 594         int max_size;
 595         /* loops of emits 64 + fence emit possible */
 596         int dwords_per_loop = 76, num_loops;
 597
 598         r = r600_vb_ib_get(rdev);
 599         if (r)
 600                 return r;
 601
 602         /* set_render_target emits 2 extra dwords on rv6xx */
 603         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
 604                 dwords_per_loop += 2;
 605
 606         /* 8 bpp vs 32 bpp for xfer unit */
 607         if (size_bytes & 3)
 608                 line_size = 8192;
 609         else
 610                 line_size = 8192*4;
 611
 612         max_size = 8192 * line_size;
 613
 614         /* major loops cover the max size transfer */
 615         num_loops = ((size_bytes + max_size) / max_size);
 616         /* minor loops cover the extra non aligned bits */
 617         num_loops += ((size_bytes % line_size) ? 1 : 0);
 618         /* calculate number of loops correctly */
 619         ring_size = num_loops * dwords_per_loop;
 620         /* set default  + shaders */
 621         ring_size += 40; /* shaders + def state */
 622         ring_size += 10; /* fence emit for VB IB */
 623         ring_size += 5; /* done copy */
 624         ring_size += 10; /* fence emit for done copy */
 625         r = radeon_ring_lock(rdev, ring_size);
 626         if (r)
 627                 return r;
 628
 629         set_default_state(rdev); /* 14 */
 630         set_shaders(rdev); /* 26 */
 631         return 0;
 632 }
 633
 634 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 635 {
 636         int r;
 637
 638         if (rdev->r600_blit.vb_ib)
 639                 r600_vb_ib_put(rdev);
 640
 641         if (fence)
 642                 r = radeon_fence_emit(rdev, fence);
 643
 644         radeon_ring_unlock_commit(rdev);
 645 }
 646
 647 void r600_kms_blit_copy(struct radeon_device *rdev,
 648                         u64 src_gpu_addr, u64 dst_gpu_addr,
 649                         int size_bytes)
 650 {
 651         int max_bytes;
 652         u64 vb_gpu_addr;
 653         u32 *vb;
 654
 655         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
 656                   size_bytes, rdev->r600_blit.vb_used);
 657         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 658         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
 659                 max_bytes = 8192;
 660
 661                 while (size_bytes) {
 662                         int cur_size = size_bytes;
 663                         int src_x = src_gpu_addr & 255;
 664                         int dst_x = dst_gpu_addr & 255;
 665                         int h = 1;
 666                         src_gpu_addr = src_gpu_addr & ~255ULL;
 667                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 668
 669                         if (!src_x && !dst_x) {
 670                                 h = (cur_size / max_bytes);
 671                                 if (h > 8192)
 672                                         h = 8192;
 673                                 if (h == 0)
 674                                         h = 1;
 675                                 else
 676                                         cur_size = max_bytes;
 677                         } else {
 678                                 if (cur_size > max_bytes)
 679                                         cur_size = max_bytes;
 680                                 if (cur_size > (max_bytes - dst_x))
 681                                         cur_size = (max_bytes - dst_x);
 682                                 if (cur_size > (max_bytes - src_x))
 683                                         cur_size = (max_bytes - src_x);
 684                         }
 685
 686                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 687                                 WARN_ON(1);
 688                         }
 689
 690                         vb[0] = i2f(dst_x);
 691                         vb[1] = 0;
 692                         vb[2] = i2f(src_x);
 693                         vb[3] = 0;
 694
 695                         vb[4] = i2f(dst_x);
 696                         vb[5] = i2f(h);
 697                         vb[6] = i2f(src_x);
 698                         vb[7] = i2f(h);
 699
 700                         vb[8] = i2f(dst_x + cur_size);
 701                         vb[9] = i2f(h);
 702                         vb[10] = i2f(src_x + cur_size);
 703                         vb[11] = i2f(h);
 704
 705                         /* src 9 */
 706                         set_tex_resource(rdev, FMT_8,
 707                                          src_x + cur_size, h, src_x + cur_size,
 708                                          src_gpu_addr);
 709
 710                         /* 5 */
 711                         cp_set_surface_sync(rdev,
 712                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 713
 714                         /* dst 23 */
 715                         set_render_target(rdev, COLOR_8,
 716                                           dst_x + cur_size, h,
 717                                           dst_gpu_addr);
 718
 719                         /* scissors 12 */
 720                         set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
 721
 722                         /* 14 */
 723                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 724                         set_vtx_resource(rdev, vb_gpu_addr);
 725
 726                         /* draw 10 */
 727                         draw_auto(rdev);
 728
 729                         /* 5 */
 730                         cp_set_surface_sync(rdev,
 731                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 732                                             cur_size * h, dst_gpu_addr);
 733
 734                         vb += 12;
 735                         rdev->r600_blit.vb_used += 12 * 4;
 736
 737                         src_gpu_addr += cur_size * h;
 738                         dst_gpu_addr += cur_size * h;
 739                         size_bytes -= cur_size * h;
 740                 }
 741         } else {
 742                 max_bytes = 8192 * 4;
 743
 744                 while (size_bytes) {
 745                         int cur_size = size_bytes;
 746                         int src_x = (src_gpu_addr & 255);
 747                         int dst_x = (dst_gpu_addr & 255);
 748                         int h = 1;
 749                         src_gpu_addr = src_gpu_addr & ~255ULL;
 750                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 751
 752                         if (!src_x && !dst_x) {
 753                                 h = (cur_size / max_bytes);
 754                                 if (h > 8192)
 755                                         h = 8192;
 756                                 if (h == 0)
 757                                         h = 1;
 758                                 else
 759                                         cur_size = max_bytes;
 760                         } else {
 761                                 if (cur_size > max_bytes)
 762                                         cur_size = max_bytes;
 763                                 if (cur_size > (max_bytes - dst_x))
 764                                         cur_size = (max_bytes - dst_x);
 765                                 if (cur_size > (max_bytes - src_x))
 766                                         cur_size = (max_bytes - src_x);
 767                         }
 768
 769                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 770                                 WARN_ON(1);
 771                         }
 772
 773                         vb[0] = i2f(dst_x / 4);
 774                         vb[1] = 0;
 775                         vb[2] = i2f(src_x / 4);
 776                         vb[3] = 0;
 777
 778                         vb[4] = i2f(dst_x / 4);
 779                         vb[5] = i2f(h);
 780                         vb[6] = i2f(src_x / 4);
 781                         vb[7] = i2f(h);
 782
 783                         vb[8] = i2f((dst_x + cur_size) / 4);
 784                         vb[9] = i2f(h);
 785                         vb[10] = i2f((src_x + cur_size) / 4);
 786                         vb[11] = i2f(h);
 787
 788                         /* src 9 */
 789                         set_tex_resource(rdev, FMT_8_8_8_8,
 790                                          (src_x + cur_size) / 4,
 791                                          h, (src_x + cur_size) / 4,
 792                                          src_gpu_addr);
 793                         /* 5 */
 794                         cp_set_surface_sync(rdev,
 795                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 796
 797                         /* dst 23 */
 798                         set_render_target(rdev, COLOR_8_8_8_8,
 799                                           (dst_x + cur_size) / 4, h,
 800                                           dst_gpu_addr);
 801
 802                         /* scissors 12  */
 803                         set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 804
 805                         /* Vertex buffer setup 14 */
 806                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 807                         set_vtx_resource(rdev, vb_gpu_addr);
 808
 809                         /* draw 10 */
 810                         draw_auto(rdev);
 811
 812                         /* 5 */
 813                         cp_set_surface_sync(rdev,
 814                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 815                                             cur_size * h, dst_gpu_addr);
 816
 817                         /* 78 ring dwords per loop */
 818                         vb += 12;
 819                         rdev->r600_blit.vb_used += 12 * 4;
 820
 821                         src_gpu_addr += cur_size * h;
 822                         dst_gpu_addr += cur_size * h;
 823                         size_bytes -= cur_size * h;
 824                 }
 825         }
 826 }
 827