drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define RLC_UCODE_SIZE 768
  42 #define R700_PFP_UCODE_SIZE 848
  43 #define R700_PM4_UCODE_SIZE 1360
  44 #define R700_RLC_UCODE_SIZE 1024
  45
  46 /* Firmware Names */
  47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  48 MODULE_FIRMWARE("radeon/R600_me.bin");
  49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV610_me.bin");
  51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV630_me.bin");
  53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV620_me.bin");
  55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV635_me.bin");
  57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV670_me.bin");
  59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RS780_me.bin");
  61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV770_me.bin");
  63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV730_me.bin");
  65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV710_me.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69
  70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  71
  72 /* r600,rv610,rv630,rv620,rv635,rv670 */
  73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  74 void r600_gpu_init(struct radeon_device *rdev);
  75 void r600_fini(struct radeon_device *rdev);
  76
  77 /* hpd for digital panel detect/disconnect */
  78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  79 {
  80         bool connected = false;
  81
  82         if (ASIC_IS_DCE3(rdev)) {
  83                 switch (hpd) {
  84                 case RADEON_HPD_1:
  85                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  86                                 connected = true;
  87                         break;
  88                 case RADEON_HPD_2:
  89                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  90                                 connected = true;
  91                         break;
  92                 case RADEON_HPD_3:
  93                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  94                                 connected = true;
  95                         break;
  96                 case RADEON_HPD_4:
  97                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  98                                 connected = true;
  99                         break;
 100                         /* DCE 3.2 */
 101                 case RADEON_HPD_5:
 102                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 103                                 connected = true;
 104                         break;
 105                 case RADEON_HPD_6:
 106                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 107                                 connected = true;
 108                         break;
 109                 default:
 110                         break;
 111                 }
 112         } else {
 113                 switch (hpd) {
 114                 case RADEON_HPD_1:
 115                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 116                                 connected = true;
 117                         break;
 118                 case RADEON_HPD_2:
 119                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 120                                 connected = true;
 121                         break;
 122                 case RADEON_HPD_3:
 123                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 124                                 connected = true;
 125                         break;
 126                 default:
 127                         break;
 128                 }
 129         }
 130         return connected;
 131 }
 132
 133 void r600_hpd_set_polarity(struct radeon_device *rdev,
 134                            enum radeon_hpd_id hpd)
 135 {
 136         u32 tmp;
 137         bool connected = r600_hpd_sense(rdev, hpd);
 138
 139         if (ASIC_IS_DCE3(rdev)) {
 140                 switch (hpd) {
 141                 case RADEON_HPD_1:
 142                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 143                         if (connected)
 144                                 tmp &= ~DC_HPDx_INT_POLARITY;
 145                         else
 146                                 tmp |= DC_HPDx_INT_POLARITY;
 147                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 148                         break;
 149                 case RADEON_HPD_2:
 150                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 151                         if (connected)
 152                                 tmp &= ~DC_HPDx_INT_POLARITY;
 153                         else
 154                                 tmp |= DC_HPDx_INT_POLARITY;
 155                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 156                         break;
 157                 case RADEON_HPD_3:
 158                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 159                         if (connected)
 160                                 tmp &= ~DC_HPDx_INT_POLARITY;
 161                         else
 162                                 tmp |= DC_HPDx_INT_POLARITY;
 163                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 164                         break;
 165                 case RADEON_HPD_4:
 166                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 167                         if (connected)
 168                                 tmp &= ~DC_HPDx_INT_POLARITY;
 169                         else
 170                                 tmp |= DC_HPDx_INT_POLARITY;
 171                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 172                         break;
 173                 case RADEON_HPD_5:
 174                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 175                         if (connected)
 176                                 tmp &= ~DC_HPDx_INT_POLARITY;
 177                         else
 178                                 tmp |= DC_HPDx_INT_POLARITY;
 179                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 180                         break;
 181                         /* DCE 3.2 */
 182                 case RADEON_HPD_6:
 183                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 184                         if (connected)
 185                                 tmp &= ~DC_HPDx_INT_POLARITY;
 186                         else
 187                                 tmp |= DC_HPDx_INT_POLARITY;
 188                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 189                         break;
 190                 default:
 191                         break;
 192                 }
 193         } else {
 194                 switch (hpd) {
 195                 case RADEON_HPD_1:
 196                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 197                         if (connected)
 198                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 199                         else
 200                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 201                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 202                         break;
 203                 case RADEON_HPD_2:
 204                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 205                         if (connected)
 206                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 207                         else
 208                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 209                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 210                         break;
 211                 case RADEON_HPD_3:
 212                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 213                         if (connected)
 214                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 215                         else
 216                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 217                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 218                         break;
 219                 default:
 220                         break;
 221                 }
 222         }
 223 }
 224
 225 void r600_hpd_init(struct radeon_device *rdev)
 226 {
 227         struct drm_device *dev = rdev->ddev;
 228         struct drm_connector *connector;
 229
 230         if (ASIC_IS_DCE3(rdev)) {
 231                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 232                 if (ASIC_IS_DCE32(rdev))
 233                         tmp |= DC_HPDx_EN;
 234
 235                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 236                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 237                         switch (radeon_connector->hpd.hpd) {
 238                         case RADEON_HPD_1:
 239                                 WREG32(DC_HPD1_CONTROL, tmp);
 240                                 rdev->irq.hpd[0] = true;
 241                                 break;
 242                         case RADEON_HPD_2:
 243                                 WREG32(DC_HPD2_CONTROL, tmp);
 244                                 rdev->irq.hpd[1] = true;
 245                                 break;
 246                         case RADEON_HPD_3:
 247                                 WREG32(DC_HPD3_CONTROL, tmp);
 248                                 rdev->irq.hpd[2] = true;
 249                                 break;
 250                         case RADEON_HPD_4:
 251                                 WREG32(DC_HPD4_CONTROL, tmp);
 252                                 rdev->irq.hpd[3] = true;
 253                                 break;
 254                                 /* DCE 3.2 */
 255                         case RADEON_HPD_5:
 256                                 WREG32(DC_HPD5_CONTROL, tmp);
 257                                 rdev->irq.hpd[4] = true;
 258                                 break;
 259                         case RADEON_HPD_6:
 260                                 WREG32(DC_HPD6_CONTROL, tmp);
 261                                 rdev->irq.hpd[5] = true;
 262                                 break;
 263                         default:
 264                                 break;
 265                         }
 266                 }
 267         } else {
 268                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 269                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 270                         switch (radeon_connector->hpd.hpd) {
 271                         case RADEON_HPD_1:
 272                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 273                                 rdev->irq.hpd[0] = true;
 274                                 break;
 275                         case RADEON_HPD_2:
 276                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 277                                 rdev->irq.hpd[1] = true;
 278                                 break;
 279                         case RADEON_HPD_3:
 280                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 281                                 rdev->irq.hpd[2] = true;
 282                                 break;
 283                         default:
 284                                 break;
 285                         }
 286                 }
 287         }
 288         r600_irq_set(rdev);
 289 }
 290
 291 void r600_hpd_fini(struct radeon_device *rdev)
 292 {
 293         struct drm_device *dev = rdev->ddev;
 294         struct drm_connector *connector;
 295
 296         if (ASIC_IS_DCE3(rdev)) {
 297                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 298                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 299                         switch (radeon_connector->hpd.hpd) {
 300                         case RADEON_HPD_1:
 301                                 WREG32(DC_HPD1_CONTROL, 0);
 302                                 rdev->irq.hpd[0] = false;
 303                                 break;
 304                         case RADEON_HPD_2:
 305                                 WREG32(DC_HPD2_CONTROL, 0);
 306                                 rdev->irq.hpd[1] = false;
 307                                 break;
 308                         case RADEON_HPD_3:
 309                                 WREG32(DC_HPD3_CONTROL, 0);
 310                                 rdev->irq.hpd[2] = false;
 311                                 break;
 312                         case RADEON_HPD_4:
 313                                 WREG32(DC_HPD4_CONTROL, 0);
 314                                 rdev->irq.hpd[3] = false;
 315                                 break;
 316                                 /* DCE 3.2 */
 317                         case RADEON_HPD_5:
 318                                 WREG32(DC_HPD5_CONTROL, 0);
 319                                 rdev->irq.hpd[4] = false;
 320                                 break;
 321                         case RADEON_HPD_6:
 322                                 WREG32(DC_HPD6_CONTROL, 0);
 323                                 rdev->irq.hpd[5] = false;
 324                                 break;
 325                         default:
 326                                 break;
 327                         }
 328                 }
 329         } else {
 330                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 331                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 332                         switch (radeon_connector->hpd.hpd) {
 333                         case RADEON_HPD_1:
 334                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 335                                 rdev->irq.hpd[0] = false;
 336                                 break;
 337                         case RADEON_HPD_2:
 338                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 339                                 rdev->irq.hpd[1] = false;
 340                                 break;
 341                         case RADEON_HPD_3:
 342                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 343                                 rdev->irq.hpd[2] = false;
 344                                 break;
 345                         default:
 346                                 break;
 347                         }
 348                 }
 349         }
 350 }
 351
 352 /*
 353  * R600 PCIE GART
 354  */
 355 int r600_gart_clear_page(struct radeon_device *rdev, int i)
 356 {
 357         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 358         u64 pte;
 359
 360         if (i < 0 || i > rdev->gart.num_gpu_pages)
 361                 return -EINVAL;
 362         pte = 0;
 363         writeq(pte, ((void __iomem *)ptr) + (i * 8));
 364         return 0;
 365 }
 366
 367 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 368 {
 369         unsigned i;
 370         u32 tmp;
 371
 372         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 373         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 374         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 375         for (i = 0; i < rdev->usec_timeout; i++) {
 376                 /* read MC_STATUS */
 377                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 378                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 379                 if (tmp == 2) {
 380                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 381                         return;
 382                 }
 383                 if (tmp) {
 384                         return;
 385                 }
 386                 udelay(1);
 387         }
 388 }
 389
 390 int r600_pcie_gart_init(struct radeon_device *rdev)
 391 {
 392         int r;
 393
 394         if (rdev->gart.table.vram.robj) {
 395                 WARN(1, "R600 PCIE GART already initialized.\n");
 396                 return 0;
 397         }
 398         /* Initialize common gart structure */
 399         r = radeon_gart_init(rdev);
 400         if (r)
 401                 return r;
 402         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 403         return radeon_gart_table_vram_alloc(rdev);
 404 }
 405
 406 int r600_pcie_gart_enable(struct radeon_device *rdev)
 407 {
 408         u32 tmp;
 409         int r, i;
 410
 411         if (rdev->gart.table.vram.robj == NULL) {
 412                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 413                 return -EINVAL;
 414         }
 415         r = radeon_gart_table_vram_pin(rdev);
 416         if (r)
 417                 return r;
 418
 419         /* Setup L2 cache */
 420         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 421                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 422                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 423         WREG32(VM_L2_CNTL2, 0);
 424         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 425         /* Setup TLB control */
 426         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 427                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 428                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 429                 ENABLE_WAIT_L2_QUERY;
 430         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 431         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 432         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 433         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 434         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 435         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 436         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 437         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 438         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 439         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 440         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 441         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 442         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 443         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 444         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 445         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 446         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 447         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 448                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 449         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 450                         (u32)(rdev->dummy_page.addr >> 12));
 451         for (i = 1; i < 7; i++)
 452                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 453
 454         r600_pcie_gart_tlb_flush(rdev);
 455         rdev->gart.ready = true;
 456         return 0;
 457 }
 458
 459 void r600_pcie_gart_disable(struct radeon_device *rdev)
 460 {
 461         u32 tmp;
 462         int i, r;
 463
 464         /* Disable all tables */
 465         for (i = 0; i < 7; i++)
 466                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 467
 468         /* Disable L2 cache */
 469         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 470                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 471         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 472         /* Setup L1 TLB control */
 473         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 474                 ENABLE_WAIT_L2_QUERY;
 475         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 476         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 477         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 478         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 479         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 480         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 481         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 482         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 483         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 484         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 485         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 486         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 487         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 488         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 489         if (rdev->gart.table.vram.robj) {
 490                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 491                 if (likely(r == 0)) {
 492                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 493                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 494                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 495                 }
 496         }
 497 }
 498
 499 void r600_pcie_gart_fini(struct radeon_device *rdev)
 500 {
 501         r600_pcie_gart_disable(rdev);
 502         radeon_gart_table_vram_free(rdev);
 503         radeon_gart_fini(rdev);
 504 }
 505
 506 void r600_agp_enable(struct radeon_device *rdev)
 507 {
 508         u32 tmp;
 509         int i;
 510
 511         /* Setup L2 cache */
 512         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 513                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 514                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 515         WREG32(VM_L2_CNTL2, 0);
 516         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 517         /* Setup TLB control */
 518         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 519                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 520                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 521                 ENABLE_WAIT_L2_QUERY;
 522         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 523         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 524         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 525         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 526         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 527         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 528         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 529         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 530         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 531         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 532         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 533         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 534         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 535         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 536         for (i = 0; i < 7; i++)
 537                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 538 }
 539
 540 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 541 {
 542         unsigned i;
 543         u32 tmp;
 544
 545         for (i = 0; i < rdev->usec_timeout; i++) {
 546                 /* read MC_STATUS */
 547                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 548                 if (!tmp)
 549                         return 0;
 550                 udelay(1);
 551         }
 552         return -1;
 553 }
 554
 555 static void r600_mc_program(struct radeon_device *rdev)
 556 {
 557         struct rv515_mc_save save;
 558         u32 tmp;
 559         int i, j;
 560
 561         /* Initialize HDP */
 562         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 563                 WREG32((0x2c14 + j), 0x00000000);
 564                 WREG32((0x2c18 + j), 0x00000000);
 565                 WREG32((0x2c1c + j), 0x00000000);
 566                 WREG32((0x2c20 + j), 0x00000000);
 567                 WREG32((0x2c24 + j), 0x00000000);
 568         }
 569         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 570
 571         rv515_mc_stop(rdev, &save);
 572         if (r600_mc_wait_for_idle(rdev)) {
 573                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 574         }
 575         /* Lockout access through VGA aperture (doesn't exist before R600) */
 576         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 577         /* Update configuration */
 578         if (rdev->flags & RADEON_IS_AGP) {
 579                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 580                         /* VRAM before AGP */
 581                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 582                                 rdev->mc.vram_start >> 12);
 583                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 584                                 rdev->mc.gtt_end >> 12);
 585                 } else {
 586                         /* VRAM after AGP */
 587                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 588                                 rdev->mc.gtt_start >> 12);
 589                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 590                                 rdev->mc.vram_end >> 12);
 591                 }
 592         } else {
 593                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 594                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 595         }
 596         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 597         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 598         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 599         WREG32(MC_VM_FB_LOCATION, tmp);
 600         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 601         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 602         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 603         if (rdev->flags & RADEON_IS_AGP) {
 604                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 605                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 606                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 607         } else {
 608                 WREG32(MC_VM_AGP_BASE, 0);
 609                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 610                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 611         }
 612         if (r600_mc_wait_for_idle(rdev)) {
 613                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 614         }
 615         rv515_mc_resume(rdev, &save);
 616         /* we need to own VRAM, so turn off the VGA renderer here
 617          * to stop it overwriting our objects */
 618         rv515_vga_render_disable(rdev);
 619 }
 620
 621 int r600_mc_init(struct radeon_device *rdev)
 622 {
 623         fixed20_12 a;
 624         u32 tmp;
 625         int chansize, numchan;
 626         int r;
 627
 628         /* Get VRAM informations */
 629         rdev->mc.vram_is_ddr = true;
 630         tmp = RREG32(RAMCFG);
 631         if (tmp & CHANSIZE_OVERRIDE) {
 632                 chansize = 16;
 633         } else if (tmp & CHANSIZE_MASK) {
 634                 chansize = 64;
 635         } else {
 636                 chansize = 32;
 637         }
 638         tmp = RREG32(CHMAP);
 639         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 640         case 0:
 641         default:
 642                 numchan = 1;
 643                 break;
 644         case 1:
 645                 numchan = 2;
 646                 break;
 647         case 2:
 648                 numchan = 4;
 649                 break;
 650         case 3:
 651                 numchan = 8;
 652                 break;
 653         }
 654         rdev->mc.vram_width = numchan * chansize;
 655         /* Could aper size report 0 ? */
 656         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 657         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 658         /* Setup GPU memory space */
 659         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 660         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 661
 662         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 663                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 664
 665         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 666                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 667
 668         if (rdev->flags & RADEON_IS_AGP) {
 669                 r = radeon_agp_init(rdev);
 670                 if (r)
 671                         return r;
 672                 /* gtt_size is setup by radeon_agp_init */
 673                 rdev->mc.gtt_location = rdev->mc.agp_base;
 674                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 675                 /* Try to put vram before or after AGP because we
 676                  * we want SYSTEM_APERTURE to cover both VRAM and
 677                  * AGP so that GPU can catch out of VRAM/AGP access
 678                  */
 679                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 680                         /* Enought place before */
 681                         rdev->mc.vram_location = rdev->mc.gtt_location -
 682                                                         rdev->mc.mc_vram_size;
 683                 } else if (tmp > rdev->mc.mc_vram_size) {
 684                         /* Enought place after */
 685                         rdev->mc.vram_location = rdev->mc.gtt_location +
 686                                                         rdev->mc.gtt_size;
 687                 } else {
 688                         /* Try to setup VRAM then AGP might not
 689                          * not work on some card
 690                          */
 691                         rdev->mc.vram_location = 0x00000000UL;
 692                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 693                 }
 694         } else {
 695                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 696                 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 697                                                         0xFFFF) << 24;
 698                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 699                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 700                         /* Enough place after vram */
 701                         rdev->mc.gtt_location = tmp;
 702                 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 703                         /* Enough place before vram */
 704                         rdev->mc.gtt_location = 0;
 705                 } else {
 706                         /* Not enough place after or before shrink
 707                          * gart size
 708                          */
 709                         if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 710                                 rdev->mc.gtt_location = 0;
 711                                 rdev->mc.gtt_size = rdev->mc.vram_location;
 712                         } else {
 713                                 rdev->mc.gtt_location = tmp;
 714                                 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 715                         }
 716                 }
 717                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 718         }
 719         rdev->mc.vram_start = rdev->mc.vram_location;
 720         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 721         rdev->mc.gtt_start = rdev->mc.gtt_location;
 722         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 723         /* FIXME: we should enforce default clock in case GPU is not in
 724          * default setup
 725          */
 726         a.full = rfixed_const(100);
 727         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 728         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 729
 730         if (rdev->flags & RADEON_IS_IGP)
 731                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 732
 733         return 0;
 734 }
 735
 736 /* We doesn't check that the GPU really needs a reset we simply do the
 737  * reset, it's up to the caller to determine if the GPU needs one. We
 738  * might add an helper function to check that.
 739  */
 740 int r600_gpu_soft_reset(struct radeon_device *rdev)
 741 {
 742         struct rv515_mc_save save;
 743         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 744                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 745                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 746                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 747                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 748                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 749                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 750                                 S_008010_GUI_ACTIVE(1);
 751         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 752                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 753                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 754                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 755                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 756                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 757                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 758                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 759         u32 srbm_reset = 0;
 760         u32 tmp;
 761
 762         dev_info(rdev->dev, "GPU softreset \n");
 763         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 764                 RREG32(R_008010_GRBM_STATUS));
 765         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 766                 RREG32(R_008014_GRBM_STATUS2));
 767         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 768                 RREG32(R_000E50_SRBM_STATUS));
 769         rv515_mc_stop(rdev, &save);
 770         if (r600_mc_wait_for_idle(rdev)) {
 771                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 772         }
 773         /* Disable CP parsing/prefetching */
 774         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 775         /* Check if any of the rendering block is busy and reset it */
 776         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 777             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 778                 tmp = S_008020_SOFT_RESET_CR(1) |
 779                         S_008020_SOFT_RESET_DB(1) |
 780                         S_008020_SOFT_RESET_CB(1) |
 781                         S_008020_SOFT_RESET_PA(1) |
 782                         S_008020_SOFT_RESET_SC(1) |
 783                         S_008020_SOFT_RESET_SMX(1) |
 784                         S_008020_SOFT_RESET_SPI(1) |
 785                         S_008020_SOFT_RESET_SX(1) |
 786                         S_008020_SOFT_RESET_SH(1) |
 787                         S_008020_SOFT_RESET_TC(1) |
 788                         S_008020_SOFT_RESET_TA(1) |
 789                         S_008020_SOFT_RESET_VC(1) |
 790                         S_008020_SOFT_RESET_VGT(1);
 791                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 792                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 793                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 794                 udelay(50);
 795                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 796                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 797         }
 798         /* Reset CP (we always reset CP) */
 799         tmp = S_008020_SOFT_RESET_CP(1);
 800         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 801         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 802         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 803         udelay(50);
 804         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 805         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 806         /* Reset others GPU block if necessary */
 807         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 808                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 809         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 810                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 811         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 812                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 813         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 814                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 815         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 816                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 817         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 818                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 819         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 820                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 821         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 822                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 823         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 824                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 825         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 826                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 827         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 828                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 829         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 830                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 831         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 832         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 833         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 834         udelay(50);
 835         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 836         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 837         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 838         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 839         udelay(50);
 840         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 841         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 842         /* Wait a little for things to settle down */
 843         udelay(50);
 844         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 845                 RREG32(R_008010_GRBM_STATUS));
 846         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 847                 RREG32(R_008014_GRBM_STATUS2));
 848         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 849                 RREG32(R_000E50_SRBM_STATUS));
 850         /* After reset we need to reinit the asic as GPU often endup in an
 851          * incoherent state.
 852          */
 853         atom_asic_init(rdev->mode_info.atom_context);
 854         rv515_mc_resume(rdev, &save);
 855         return 0;
 856 }
 857
 858 int r600_gpu_reset(struct radeon_device *rdev)
 859 {
 860         return r600_gpu_soft_reset(rdev);
 861 }
 862
 863 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 864                                              u32 num_backends,
 865                                              u32 backend_disable_mask)
 866 {
 867         u32 backend_map = 0;
 868         u32 enabled_backends_mask;
 869         u32 enabled_backends_count;
 870         u32 cur_pipe;
 871         u32 swizzle_pipe[R6XX_MAX_PIPES];
 872         u32 cur_backend;
 873         u32 i;
 874
 875         if (num_tile_pipes > R6XX_MAX_PIPES)
 876                 num_tile_pipes = R6XX_MAX_PIPES;
 877         if (num_tile_pipes < 1)
 878                 num_tile_pipes = 1;
 879         if (num_backends > R6XX_MAX_BACKENDS)
 880                 num_backends = R6XX_MAX_BACKENDS;
 881         if (num_backends < 1)
 882                 num_backends = 1;
 883
 884         enabled_backends_mask = 0;
 885         enabled_backends_count = 0;
 886         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 887                 if (((backend_disable_mask >> i) & 1) == 0) {
 888                         enabled_backends_mask |= (1 << i);
 889                         ++enabled_backends_count;
 890                 }
 891                 if (enabled_backends_count == num_backends)
 892                         break;
 893         }
 894
 895         if (enabled_backends_count == 0) {
 896                 enabled_backends_mask = 1;
 897                 enabled_backends_count = 1;
 898         }
 899
 900         if (enabled_backends_count != num_backends)
 901                 num_backends = enabled_backends_count;
 902
 903         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 904         switch (num_tile_pipes) {
 905         case 1:
 906                 swizzle_pipe[0] = 0;
 907                 break;
 908         case 2:
 909                 swizzle_pipe[0] = 0;
 910                 swizzle_pipe[1] = 1;
 911                 break;
 912         case 3:
 913                 swizzle_pipe[0] = 0;
 914                 swizzle_pipe[1] = 1;
 915                 swizzle_pipe[2] = 2;
 916                 break;
 917         case 4:
 918                 swizzle_pipe[0] = 0;
 919                 swizzle_pipe[1] = 1;
 920                 swizzle_pipe[2] = 2;
 921                 swizzle_pipe[3] = 3;
 922                 break;
 923         case 5:
 924                 swizzle_pipe[0] = 0;
 925                 swizzle_pipe[1] = 1;
 926                 swizzle_pipe[2] = 2;
 927                 swizzle_pipe[3] = 3;
 928                 swizzle_pipe[4] = 4;
 929                 break;
 930         case 6:
 931                 swizzle_pipe[0] = 0;
 932                 swizzle_pipe[1] = 2;
 933                 swizzle_pipe[2] = 4;
 934                 swizzle_pipe[3] = 5;
 935                 swizzle_pipe[4] = 1;
 936                 swizzle_pipe[5] = 3;
 937                 break;
 938         case 7:
 939                 swizzle_pipe[0] = 0;
 940                 swizzle_pipe[1] = 2;
 941                 swizzle_pipe[2] = 4;
 942                 swizzle_pipe[3] = 6;
 943                 swizzle_pipe[4] = 1;
 944                 swizzle_pipe[5] = 3;
 945                 swizzle_pipe[6] = 5;
 946                 break;
 947         case 8:
 948                 swizzle_pipe[0] = 0;
 949                 swizzle_pipe[1] = 2;
 950                 swizzle_pipe[2] = 4;
 951                 swizzle_pipe[3] = 6;
 952                 swizzle_pipe[4] = 1;
 953                 swizzle_pipe[5] = 3;
 954                 swizzle_pipe[6] = 5;
 955                 swizzle_pipe[7] = 7;
 956                 break;
 957         }
 958
 959         cur_backend = 0;
 960         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 961                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 962                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 963
 964                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 965
 966                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 967         }
 968
 969         return backend_map;
 970 }
 971
 972 int r600_count_pipe_bits(uint32_t val)
 973 {
 974         int i, ret = 0;
 975
 976         for (i = 0; i < 32; i++) {
 977                 ret += val & 1;
 978                 val >>= 1;
 979         }
 980         return ret;
 981 }
 982
 983 void r600_gpu_init(struct radeon_device *rdev)
 984 {
 985         u32 tiling_config;
 986         u32 ramcfg;
 987         u32 tmp;
 988         int i, j;
 989         u32 sq_config;
 990         u32 sq_gpr_resource_mgmt_1 = 0;
 991         u32 sq_gpr_resource_mgmt_2 = 0;
 992         u32 sq_thread_resource_mgmt = 0;
 993         u32 sq_stack_resource_mgmt_1 = 0;
 994         u32 sq_stack_resource_mgmt_2 = 0;
 995
 996         /* FIXME: implement */
 997         switch (rdev->family) {
 998         case CHIP_R600:
 999                 rdev->config.r600.max_pipes = 4;
1000                 rdev->config.r600.max_tile_pipes = 8;
1001                 rdev->config.r600.max_simds = 4;
1002                 rdev->config.r600.max_backends = 4;
1003                 rdev->config.r600.max_gprs = 256;
1004                 rdev->config.r600.max_threads = 192;
1005                 rdev->config.r600.max_stack_entries = 256;
1006                 rdev->config.r600.max_hw_contexts = 8;
1007                 rdev->config.r600.max_gs_threads = 16;
1008                 rdev->config.r600.sx_max_export_size = 128;
1009                 rdev->config.r600.sx_max_export_pos_size = 16;
1010                 rdev->config.r600.sx_max_export_smx_size = 128;
1011                 rdev->config.r600.sq_num_cf_insts = 2;
1012                 break;
1013         case CHIP_RV630:
1014         case CHIP_RV635:
1015                 rdev->config.r600.max_pipes = 2;
1016                 rdev->config.r600.max_tile_pipes = 2;
1017                 rdev->config.r600.max_simds = 3;
1018                 rdev->config.r600.max_backends = 1;
1019                 rdev->config.r600.max_gprs = 128;
1020                 rdev->config.r600.max_threads = 192;
1021                 rdev->config.r600.max_stack_entries = 128;
1022                 rdev->config.r600.max_hw_contexts = 8;
1023                 rdev->config.r600.max_gs_threads = 4;
1024                 rdev->config.r600.sx_max_export_size = 128;
1025                 rdev->config.r600.sx_max_export_pos_size = 16;
1026                 rdev->config.r600.sx_max_export_smx_size = 128;
1027                 rdev->config.r600.sq_num_cf_insts = 2;
1028                 break;
1029         case CHIP_RV610:
1030         case CHIP_RV620:
1031         case CHIP_RS780:
1032         case CHIP_RS880:
1033                 rdev->config.r600.max_pipes = 1;
1034                 rdev->config.r600.max_tile_pipes = 1;
1035                 rdev->config.r600.max_simds = 2;
1036                 rdev->config.r600.max_backends = 1;
1037                 rdev->config.r600.max_gprs = 128;
1038                 rdev->config.r600.max_threads = 192;
1039                 rdev->config.r600.max_stack_entries = 128;
1040                 rdev->config.r600.max_hw_contexts = 4;
1041                 rdev->config.r600.max_gs_threads = 4;
1042                 rdev->config.r600.sx_max_export_size = 128;
1043                 rdev->config.r600.sx_max_export_pos_size = 16;
1044                 rdev->config.r600.sx_max_export_smx_size = 128;
1045                 rdev->config.r600.sq_num_cf_insts = 1;
1046                 break;
1047         case CHIP_RV670:
1048                 rdev->config.r600.max_pipes = 4;
1049                 rdev->config.r600.max_tile_pipes = 4;
1050                 rdev->config.r600.max_simds = 4;
1051                 rdev->config.r600.max_backends = 4;
1052                 rdev->config.r600.max_gprs = 192;
1053                 rdev->config.r600.max_threads = 192;
1054                 rdev->config.r600.max_stack_entries = 256;
1055                 rdev->config.r600.max_hw_contexts = 8;
1056                 rdev->config.r600.max_gs_threads = 16;
1057                 rdev->config.r600.sx_max_export_size = 128;
1058                 rdev->config.r600.sx_max_export_pos_size = 16;
1059                 rdev->config.r600.sx_max_export_smx_size = 128;
1060                 rdev->config.r600.sq_num_cf_insts = 2;
1061                 break;
1062         default:
1063                 break;
1064         }
1065
1066         /* Initialize HDP */
1067         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1068                 WREG32((0x2c14 + j), 0x00000000);
1069                 WREG32((0x2c18 + j), 0x00000000);
1070                 WREG32((0x2c1c + j), 0x00000000);
1071                 WREG32((0x2c20 + j), 0x00000000);
1072                 WREG32((0x2c24 + j), 0x00000000);
1073         }
1074
1075         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1076
1077         /* Setup tiling */
1078         tiling_config = 0;
1079         ramcfg = RREG32(RAMCFG);
1080         switch (rdev->config.r600.max_tile_pipes) {
1081         case 1:
1082                 tiling_config |= PIPE_TILING(0);
1083                 break;
1084         case 2:
1085                 tiling_config |= PIPE_TILING(1);
1086                 break;
1087         case 4:
1088                 tiling_config |= PIPE_TILING(2);
1089                 break;
1090         case 8:
1091                 tiling_config |= PIPE_TILING(3);
1092                 break;
1093         default:
1094                 break;
1095         }
1096         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1097         tiling_config |= GROUP_SIZE(0);
1098         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1099         if (tmp > 3) {
1100                 tiling_config |= ROW_TILING(3);
1101                 tiling_config |= SAMPLE_SPLIT(3);
1102         } else {
1103                 tiling_config |= ROW_TILING(tmp);
1104                 tiling_config |= SAMPLE_SPLIT(tmp);
1105         }
1106         tiling_config |= BANK_SWAPS(1);
1107         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1108                                                 rdev->config.r600.max_backends,
1109                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
1110         tiling_config |= BACKEND_MAP(tmp);
1111         WREG32(GB_TILING_CONFIG, tiling_config);
1112         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1113         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1114
1115         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1116         WREG32(CC_RB_BACKEND_DISABLE, tmp);
1117
1118         /* Setup pipes */
1119         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1120         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1121         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1122         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1123
1124         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1125         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1126         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1127
1128         /* Setup some CP states */
1129         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1130         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1131
1132         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1133                              SYNC_WALKER | SYNC_ALIGNER));
1134         /* Setup various GPU states */
1135         if (rdev->family == CHIP_RV670)
1136                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1137
1138         tmp = RREG32(SX_DEBUG_1);
1139         tmp |= SMX_EVENT_RELEASE;
1140         if ((rdev->family > CHIP_R600))
1141                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1142         WREG32(SX_DEBUG_1, tmp);
1143
1144         if (((rdev->family) == CHIP_R600) ||
1145             ((rdev->family) == CHIP_RV630) ||
1146             ((rdev->family) == CHIP_RV610) ||
1147             ((rdev->family) == CHIP_RV620) ||
1148             ((rdev->family) == CHIP_RS780) ||
1149             ((rdev->family) == CHIP_RS880)) {
1150                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1151         } else {
1152                 WREG32(DB_DEBUG, 0);
1153         }
1154         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1155                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1156
1157         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1158         WREG32(VGT_NUM_INSTANCES, 0);
1159
1160         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1161         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1162
1163         tmp = RREG32(SQ_MS_FIFO_SIZES);
1164         if (((rdev->family) == CHIP_RV610) ||
1165             ((rdev->family) == CHIP_RV620) ||
1166             ((rdev->family) == CHIP_RS780) ||
1167             ((rdev->family) == CHIP_RS880)) {
1168                 tmp = (CACHE_FIFO_SIZE(0xa) |
1169                        FETCH_FIFO_HIWATER(0xa) |
1170                        DONE_FIFO_HIWATER(0xe0) |
1171                        ALU_UPDATE_FIFO_HIWATER(0x8));
1172         } else if (((rdev->family) == CHIP_R600) ||
1173                    ((rdev->family) == CHIP_RV630)) {
1174                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1175                 tmp |= DONE_FIFO_HIWATER(0x4);
1176         }
1177         WREG32(SQ_MS_FIFO_SIZES, tmp);
1178
1179         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1180          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1181          */
1182         sq_config = RREG32(SQ_CONFIG);
1183         sq_config &= ~(PS_PRIO(3) |
1184                        VS_PRIO(3) |
1185                        GS_PRIO(3) |
1186                        ES_PRIO(3));
1187         sq_config |= (DX9_CONSTS |
1188                       VC_ENABLE |
1189                       PS_PRIO(0) |
1190                       VS_PRIO(1) |
1191                       GS_PRIO(2) |
1192                       ES_PRIO(3));
1193
1194         if ((rdev->family) == CHIP_R600) {
1195                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1196                                           NUM_VS_GPRS(124) |
1197                                           NUM_CLAUSE_TEMP_GPRS(4));
1198                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1199                                           NUM_ES_GPRS(0));
1200                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1201                                            NUM_VS_THREADS(48) |
1202                                            NUM_GS_THREADS(4) |
1203                                            NUM_ES_THREADS(4));
1204                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1205                                             NUM_VS_STACK_ENTRIES(128));
1206                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1207                                             NUM_ES_STACK_ENTRIES(0));
1208         } else if (((rdev->family) == CHIP_RV610) ||
1209                    ((rdev->family) == CHIP_RV620) ||
1210                    ((rdev->family) == CHIP_RS780) ||
1211                    ((rdev->family) == CHIP_RS880)) {
1212                 /* no vertex cache */
1213                 sq_config &= ~VC_ENABLE;
1214
1215                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1216                                           NUM_VS_GPRS(44) |
1217                                           NUM_CLAUSE_TEMP_GPRS(2));
1218                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1219                                           NUM_ES_GPRS(17));
1220                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1221                                            NUM_VS_THREADS(78) |
1222                                            NUM_GS_THREADS(4) |
1223                                            NUM_ES_THREADS(31));
1224                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1225                                             NUM_VS_STACK_ENTRIES(40));
1226                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1227                                             NUM_ES_STACK_ENTRIES(16));
1228         } else if (((rdev->family) == CHIP_RV630) ||
1229                    ((rdev->family) == CHIP_RV635)) {
1230                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1231                                           NUM_VS_GPRS(44) |
1232                                           NUM_CLAUSE_TEMP_GPRS(2));
1233                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1234                                           NUM_ES_GPRS(18));
1235                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1236                                            NUM_VS_THREADS(78) |
1237                                            NUM_GS_THREADS(4) |
1238                                            NUM_ES_THREADS(31));
1239                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1240                                             NUM_VS_STACK_ENTRIES(40));
1241                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1242                                             NUM_ES_STACK_ENTRIES(16));
1243         } else if ((rdev->family) == CHIP_RV670) {
1244                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1245                                           NUM_VS_GPRS(44) |
1246                                           NUM_CLAUSE_TEMP_GPRS(2));
1247                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1248                                           NUM_ES_GPRS(17));
1249                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1250                                            NUM_VS_THREADS(78) |
1251                                            NUM_GS_THREADS(4) |
1252                                            NUM_ES_THREADS(31));
1253                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1254                                             NUM_VS_STACK_ENTRIES(64));
1255                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1256                                             NUM_ES_STACK_ENTRIES(64));
1257         }
1258
1259         WREG32(SQ_CONFIG, sq_config);
1260         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1261         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1262         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1263         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1264         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1265
1266         if (((rdev->family) == CHIP_RV610) ||
1267             ((rdev->family) == CHIP_RV620) ||
1268             ((rdev->family) == CHIP_RS780) ||
1269             ((rdev->family) == CHIP_RS880)) {
1270                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1271         } else {
1272                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1273         }
1274
1275         /* More default values. 2D/3D driver should adjust as needed */
1276         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1277                                          S1_X(0x4) | S1_Y(0xc)));
1278         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1279                                          S1_X(0x2) | S1_Y(0x2) |
1280                                          S2_X(0xa) | S2_Y(0x6) |
1281                                          S3_X(0x6) | S3_Y(0xa)));
1282         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1283                                              S1_X(0x4) | S1_Y(0xc) |
1284                                              S2_X(0x1) | S2_Y(0x6) |
1285                                              S3_X(0xa) | S3_Y(0xe)));
1286         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1287                                              S5_X(0x0) | S5_Y(0x0) |
1288                                              S6_X(0xb) | S6_Y(0x4) |
1289                                              S7_X(0x7) | S7_Y(0x8)));
1290
1291         WREG32(VGT_STRMOUT_EN, 0);
1292         tmp = rdev->config.r600.max_pipes * 16;
1293         switch (rdev->family) {
1294         case CHIP_RV610:
1295         case CHIP_RV620:
1296         case CHIP_RS780:
1297         case CHIP_RS880:
1298                 tmp += 32;
1299                 break;
1300         case CHIP_RV670:
1301                 tmp += 128;
1302                 break;
1303         default:
1304                 break;
1305         }
1306         if (tmp > 256) {
1307                 tmp = 256;
1308         }
1309         WREG32(VGT_ES_PER_GS, 128);
1310         WREG32(VGT_GS_PER_ES, tmp);
1311         WREG32(VGT_GS_PER_VS, 2);
1312         WREG32(VGT_GS_VERTEX_REUSE, 16);
1313
1314         /* more default values. 2D/3D driver should adjust as needed */
1315         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1316         WREG32(VGT_STRMOUT_EN, 0);
1317         WREG32(SX_MISC, 0);
1318         WREG32(PA_SC_MODE_CNTL, 0);
1319         WREG32(PA_SC_AA_CONFIG, 0);
1320         WREG32(PA_SC_LINE_STIPPLE, 0);
1321         WREG32(SPI_INPUT_Z, 0);
1322         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1323         WREG32(CB_COLOR7_FRAG, 0);
1324
1325         /* Clear render buffer base addresses */
1326         WREG32(CB_COLOR0_BASE, 0);
1327         WREG32(CB_COLOR1_BASE, 0);
1328         WREG32(CB_COLOR2_BASE, 0);
1329         WREG32(CB_COLOR3_BASE, 0);
1330         WREG32(CB_COLOR4_BASE, 0);
1331         WREG32(CB_COLOR5_BASE, 0);
1332         WREG32(CB_COLOR6_BASE, 0);
1333         WREG32(CB_COLOR7_BASE, 0);
1334         WREG32(CB_COLOR7_FRAG, 0);
1335
1336         switch (rdev->family) {
1337         case CHIP_RV610:
1338         case CHIP_RV620:
1339         case CHIP_RS780:
1340         case CHIP_RS880:
1341                 tmp = TC_L2_SIZE(8);
1342                 break;
1343         case CHIP_RV630:
1344         case CHIP_RV635:
1345                 tmp = TC_L2_SIZE(4);
1346                 break;
1347         case CHIP_R600:
1348                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1349                 break;
1350         default:
1351                 tmp = TC_L2_SIZE(0);
1352                 break;
1353         }
1354         WREG32(TC_CNTL, tmp);
1355
1356         tmp = RREG32(HDP_HOST_PATH_CNTL);
1357         WREG32(HDP_HOST_PATH_CNTL, tmp);
1358
1359         tmp = RREG32(ARB_POP);
1360         tmp |= ENABLE_TC128;
1361         WREG32(ARB_POP, tmp);
1362
1363         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1364         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1365                                NUM_CLIP_SEQ(3)));
1366         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1367 }
1368
1369
1370 /*
1371  * Indirect registers accessor
1372  */
1373 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1374 {
1375         u32 r;
1376
1377         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1378         (void)RREG32(PCIE_PORT_INDEX);
1379         r = RREG32(PCIE_PORT_DATA);
1380         return r;
1381 }
1382
1383 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1384 {
1385         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1386         (void)RREG32(PCIE_PORT_INDEX);
1387         WREG32(PCIE_PORT_DATA, (v));
1388         (void)RREG32(PCIE_PORT_DATA);
1389 }
1390
1391 void r600_hdp_flush(struct radeon_device *rdev)
1392 {
1393         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1394 }
1395
1396 /*
1397  * CP & Ring
1398  */
1399 void r600_cp_stop(struct radeon_device *rdev)
1400 {
1401         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1402 }
1403
1404 int r600_init_microcode(struct radeon_device *rdev)
1405 {
1406         struct platform_device *pdev;
1407         const char *chip_name;
1408         const char *rlc_chip_name;
1409         size_t pfp_req_size, me_req_size, rlc_req_size;
1410         char fw_name[30];
1411         int err;
1412
1413         DRM_DEBUG("\n");
1414
1415         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1416         err = IS_ERR(pdev);
1417         if (err) {
1418                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1419                 return -EINVAL;
1420         }
1421
1422         switch (rdev->family) {
1423         case CHIP_R600:
1424                 chip_name = "R600";
1425                 rlc_chip_name = "R600";
1426                 break;
1427         case CHIP_RV610:
1428                 chip_name = "RV610";
1429                 rlc_chip_name = "R600";
1430                 break;
1431         case CHIP_RV630:
1432                 chip_name = "RV630";
1433                 rlc_chip_name = "R600";
1434                 break;
1435         case CHIP_RV620:
1436                 chip_name = "RV620";
1437                 rlc_chip_name = "R600";
1438                 break;
1439         case CHIP_RV635:
1440                 chip_name = "RV635";
1441                 rlc_chip_name = "R600";
1442                 break;
1443         case CHIP_RV670:
1444                 chip_name = "RV670";
1445                 rlc_chip_name = "R600";
1446                 break;
1447         case CHIP_RS780:
1448         case CHIP_RS880:
1449                 chip_name = "RS780";
1450                 rlc_chip_name = "R600";
1451                 break;
1452         case CHIP_RV770:
1453                 chip_name = "RV770";
1454                 rlc_chip_name = "R700";
1455                 break;
1456         case CHIP_RV730:
1457         case CHIP_RV740:
1458                 chip_name = "RV730";
1459                 rlc_chip_name = "R700";
1460                 break;
1461         case CHIP_RV710:
1462                 chip_name = "RV710";
1463                 rlc_chip_name = "R700";
1464                 break;
1465         default: BUG();
1466         }
1467
1468         if (rdev->family >= CHIP_RV770) {
1469                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1470                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1471                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1472         } else {
1473                 pfp_req_size = PFP_UCODE_SIZE * 4;
1474                 me_req_size = PM4_UCODE_SIZE * 12;
1475                 rlc_req_size = RLC_UCODE_SIZE * 4;
1476         }
1477
1478         DRM_INFO("Loading %s Microcode\n", chip_name);
1479
1480         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1481         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1482         if (err)
1483                 goto out;
1484         if (rdev->pfp_fw->size != pfp_req_size) {
1485                 printk(KERN_ERR
1486                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1487                        rdev->pfp_fw->size, fw_name);
1488                 err = -EINVAL;
1489                 goto out;
1490         }
1491
1492         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1493         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1494         if (err)
1495                 goto out;
1496         if (rdev->me_fw->size != me_req_size) {
1497                 printk(KERN_ERR
1498                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1499                        rdev->me_fw->size, fw_name);
1500                 err = -EINVAL;
1501         }
1502
1503         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1504         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1505         if (err)
1506                 goto out;
1507         if (rdev->rlc_fw->size != rlc_req_size) {
1508                 printk(KERN_ERR
1509                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1510                        rdev->rlc_fw->size, fw_name);
1511                 err = -EINVAL;
1512         }
1513
1514 out:
1515         platform_device_unregister(pdev);
1516
1517         if (err) {
1518                 if (err != -EINVAL)
1519                         printk(KERN_ERR
1520                                "r600_cp: Failed to load firmware \"%s\"\n",
1521                                fw_name);
1522                 release_firmware(rdev->pfp_fw);
1523                 rdev->pfp_fw = NULL;
1524                 release_firmware(rdev->me_fw);
1525                 rdev->me_fw = NULL;
1526                 release_firmware(rdev->rlc_fw);
1527                 rdev->rlc_fw = NULL;
1528         }
1529         return err;
1530 }
1531
1532 static int r600_cp_load_microcode(struct radeon_device *rdev)
1533 {
1534         const __be32 *fw_data;
1535         int i;
1536
1537         if (!rdev->me_fw || !rdev->pfp_fw)
1538                 return -EINVAL;
1539
1540         r600_cp_stop(rdev);
1541
1542         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1543
1544         /* Reset cp */
1545         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1546         RREG32(GRBM_SOFT_RESET);
1547         mdelay(15);
1548         WREG32(GRBM_SOFT_RESET, 0);
1549
1550         WREG32(CP_ME_RAM_WADDR, 0);
1551
1552         fw_data = (const __be32 *)rdev->me_fw->data;
1553         WREG32(CP_ME_RAM_WADDR, 0);
1554         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1555                 WREG32(CP_ME_RAM_DATA,
1556                        be32_to_cpup(fw_data++));
1557
1558         fw_data = (const __be32 *)rdev->pfp_fw->data;
1559         WREG32(CP_PFP_UCODE_ADDR, 0);
1560         for (i = 0; i < PFP_UCODE_SIZE; i++)
1561                 WREG32(CP_PFP_UCODE_DATA,
1562                        be32_to_cpup(fw_data++));
1563
1564         WREG32(CP_PFP_UCODE_ADDR, 0);
1565         WREG32(CP_ME_RAM_WADDR, 0);
1566         WREG32(CP_ME_RAM_RADDR, 0);
1567         return 0;
1568 }
1569
1570 int r600_cp_start(struct radeon_device *rdev)
1571 {
1572         int r;
1573         uint32_t cp_me;
1574
1575         r = radeon_ring_lock(rdev, 7);
1576         if (r) {
1577                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1578                 return r;
1579         }
1580         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1581         radeon_ring_write(rdev, 0x1);
1582         if (rdev->family < CHIP_RV770) {
1583                 radeon_ring_write(rdev, 0x3);
1584                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1585         } else {
1586                 radeon_ring_write(rdev, 0x0);
1587                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1588         }
1589         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1590         radeon_ring_write(rdev, 0);
1591         radeon_ring_write(rdev, 0);
1592         radeon_ring_unlock_commit(rdev);
1593
1594         cp_me = 0xff;
1595         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1596         return 0;
1597 }
1598
1599 int r600_cp_resume(struct radeon_device *rdev)
1600 {
1601         u32 tmp;
1602         u32 rb_bufsz;
1603         int r;
1604
1605         /* Reset cp */
1606         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1607         RREG32(GRBM_SOFT_RESET);
1608         mdelay(15);
1609         WREG32(GRBM_SOFT_RESET, 0);
1610
1611         /* Set ring buffer size */
1612         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1613         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1614 #ifdef __BIG_ENDIAN
1615         tmp |= BUF_SWAP_32BIT;
1616 #endif
1617         WREG32(CP_RB_CNTL, tmp);
1618         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1619
1620         /* Set the write pointer delay */
1621         WREG32(CP_RB_WPTR_DELAY, 0);
1622
1623         /* Initialize the ring buffer's read and write pointers */
1624         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1625         WREG32(CP_RB_RPTR_WR, 0);
1626         WREG32(CP_RB_WPTR, 0);
1627         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1628         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1629         mdelay(1);
1630         WREG32(CP_RB_CNTL, tmp);
1631
1632         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1633         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1634
1635         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1636         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1637
1638         r600_cp_start(rdev);
1639         rdev->cp.ready = true;
1640         r = radeon_ring_test(rdev);
1641         if (r) {
1642                 rdev->cp.ready = false;
1643                 return r;
1644         }
1645         return 0;
1646 }
1647
1648 void r600_cp_commit(struct radeon_device *rdev)
1649 {
1650         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1651         (void)RREG32(CP_RB_WPTR);
1652 }
1653
1654 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1655 {
1656         u32 rb_bufsz;
1657
1658         /* Align ring size */
1659         rb_bufsz = drm_order(ring_size / 8);
1660         ring_size = (1 << (rb_bufsz + 1)) * 4;
1661         rdev->cp.ring_size = ring_size;
1662         rdev->cp.align_mask = 16 - 1;
1663 }
1664
1665
1666 /*
1667  * GPU scratch registers helpers function.
1668  */
1669 void r600_scratch_init(struct radeon_device *rdev)
1670 {
1671         int i;
1672
1673         rdev->scratch.num_reg = 7;
1674         for (i = 0; i < rdev->scratch.num_reg; i++) {
1675                 rdev->scratch.free[i] = true;
1676                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1677         }
1678 }
1679
1680 int r600_ring_test(struct radeon_device *rdev)
1681 {
1682         uint32_t scratch;
1683         uint32_t tmp = 0;
1684         unsigned i;
1685         int r;
1686
1687         r = radeon_scratch_get(rdev, &scratch);
1688         if (r) {
1689                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1690                 return r;
1691         }
1692         WREG32(scratch, 0xCAFEDEAD);
1693         r = radeon_ring_lock(rdev, 3);
1694         if (r) {
1695                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1696                 radeon_scratch_free(rdev, scratch);
1697                 return r;
1698         }
1699         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1700         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1701         radeon_ring_write(rdev, 0xDEADBEEF);
1702         radeon_ring_unlock_commit(rdev);
1703         for (i = 0; i < rdev->usec_timeout; i++) {
1704                 tmp = RREG32(scratch);
1705                 if (tmp == 0xDEADBEEF)
1706                         break;
1707                 DRM_UDELAY(1);
1708         }
1709         if (i < rdev->usec_timeout) {
1710                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1711         } else {
1712                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1713                           scratch, tmp);
1714                 r = -EINVAL;
1715         }
1716         radeon_scratch_free(rdev, scratch);
1717         return r;
1718 }
1719
1720 void r600_wb_disable(struct radeon_device *rdev)
1721 {
1722         int r;
1723
1724         WREG32(SCRATCH_UMSK, 0);
1725         if (rdev->wb.wb_obj) {
1726                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1727                 if (unlikely(r != 0))
1728                         return;
1729                 radeon_bo_kunmap(rdev->wb.wb_obj);
1730                 radeon_bo_unpin(rdev->wb.wb_obj);
1731                 radeon_bo_unreserve(rdev->wb.wb_obj);
1732         }
1733 }
1734
1735 void r600_wb_fini(struct radeon_device *rdev)
1736 {
1737         r600_wb_disable(rdev);
1738         if (rdev->wb.wb_obj) {
1739                 radeon_bo_unref(&rdev->wb.wb_obj);
1740                 rdev->wb.wb = NULL;
1741                 rdev->wb.wb_obj = NULL;
1742         }
1743 }
1744
1745 int r600_wb_enable(struct radeon_device *rdev)
1746 {
1747         int r;
1748
1749         if (rdev->wb.wb_obj == NULL) {
1750                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1751                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1752                 if (r) {
1753                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1754                         return r;
1755                 }
1756                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1757                 if (unlikely(r != 0)) {
1758                         r600_wb_fini(rdev);
1759                         return r;
1760                 }
1761                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1762                                 &rdev->wb.gpu_addr);
1763                 if (r) {
1764                         radeon_bo_unreserve(rdev->wb.wb_obj);
1765                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1766                         r600_wb_fini(rdev);
1767                         return r;
1768                 }
1769                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1770                 radeon_bo_unreserve(rdev->wb.wb_obj);
1771                 if (r) {
1772                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1773                         r600_wb_fini(rdev);
1774                         return r;
1775                 }
1776         }
1777         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1778         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1779         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1780         WREG32(SCRATCH_UMSK, 0xff);
1781         return 0;
1782 }
1783
1784 void r600_fence_ring_emit(struct radeon_device *rdev,
1785                           struct radeon_fence *fence)
1786 {
1787         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1788         /* Emit fence sequence & fire IRQ */
1789         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1790         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1791         radeon_ring_write(rdev, fence->seq);
1792         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1793         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1794         radeon_ring_write(rdev, RB_INT_STAT);
1795 }
1796
1797 int r600_copy_dma(struct radeon_device *rdev,
1798                   uint64_t src_offset,
1799                   uint64_t dst_offset,
1800                   unsigned num_pages,
1801                   struct radeon_fence *fence)
1802 {
1803         /* FIXME: implement */
1804         return 0;
1805 }
1806
1807 int r600_copy_blit(struct radeon_device *rdev,
1808                    uint64_t src_offset, uint64_t dst_offset,
1809                    unsigned num_pages, struct radeon_fence *fence)
1810 {
1811         r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1812         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1813         r600_blit_done_copy(rdev, fence);
1814         return 0;
1815 }
1816
1817 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1818                          uint32_t tiling_flags, uint32_t pitch,
1819                          uint32_t offset, uint32_t obj_size)
1820 {
1821         /* FIXME: implement */
1822         return 0;
1823 }
1824
1825 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1826 {
1827         /* FIXME: implement */
1828 }
1829
1830
1831 bool r600_card_posted(struct radeon_device *rdev)
1832 {
1833         uint32_t reg;
1834
1835         /* first check CRTCs */
1836         reg = RREG32(D1CRTC_CONTROL) |
1837                 RREG32(D2CRTC_CONTROL);
1838         if (reg & CRTC_EN)
1839                 return true;
1840
1841         /* then check MEM_SIZE, in case the crtcs are off */
1842         if (RREG32(CONFIG_MEMSIZE))
1843                 return true;
1844
1845         return false;
1846 }
1847
1848 int r600_startup(struct radeon_device *rdev)
1849 {
1850         int r;
1851
1852         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1853                 r = r600_init_microcode(rdev);
1854                 if (r) {
1855                         DRM_ERROR("Failed to load firmware!\n");
1856                         return r;
1857                 }
1858         }
1859
1860         r600_mc_program(rdev);
1861         if (rdev->flags & RADEON_IS_AGP) {
1862                 r600_agp_enable(rdev);
1863         } else {
1864                 r = r600_pcie_gart_enable(rdev);
1865                 if (r)
1866                         return r;
1867         }
1868         r600_gpu_init(rdev);
1869
1870         if (!rdev->r600_blit.shader_obj) {
1871                 r = r600_blit_init(rdev);
1872                 if (r) {
1873                         DRM_ERROR("radeon: failed blitter (%d).\n", r);
1874                         return r;
1875                 }
1876         }
1877
1878         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1879         if (unlikely(r != 0))
1880                 return r;
1881         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1882                         &rdev->r600_blit.shader_gpu_addr);
1883         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1884         if (r) {
1885                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1886                 return r;
1887         }
1888
1889         /* Enable IRQ */
1890         r = r600_irq_init(rdev);
1891         if (r) {
1892                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1893                 radeon_irq_kms_fini(rdev);
1894                 return r;
1895         }
1896         r600_irq_set(rdev);
1897
1898         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1899         if (r)
1900                 return r;
1901         r = r600_cp_load_microcode(rdev);
1902         if (r)
1903                 return r;
1904         r = r600_cp_resume(rdev);
1905         if (r)
1906                 return r;
1907         /* write back buffer are not vital so don't worry about failure */
1908         r600_wb_enable(rdev);
1909         return 0;
1910 }
1911
1912 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1913 {
1914         uint32_t temp;
1915
1916         temp = RREG32(CONFIG_CNTL);
1917         if (state == false) {
1918                 temp &= ~(1<<0);
1919                 temp |= (1<<1);
1920         } else {
1921                 temp &= ~(1<<1);
1922         }
1923         WREG32(CONFIG_CNTL, temp);
1924 }
1925
1926 int r600_resume(struct radeon_device *rdev)
1927 {
1928         int r;
1929
1930         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1931          * posting will perform necessary task to bring back GPU into good
1932          * shape.
1933          */
1934         /* post card */
1935         atom_asic_init(rdev->mode_info.atom_context);
1936         /* Initialize clocks */
1937         r = radeon_clocks_init(rdev);
1938         if (r) {
1939                 return r;
1940         }
1941
1942         r = r600_startup(rdev);
1943         if (r) {
1944                 DRM_ERROR("r600 startup failed on resume\n");
1945                 return r;
1946         }
1947
1948         r = r600_ib_test(rdev);
1949         if (r) {
1950                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1951                 return r;
1952         }
1953         return r;
1954 }
1955
1956 int r600_suspend(struct radeon_device *rdev)
1957 {
1958         int r;
1959
1960         /* FIXME: we should wait for ring to be empty */
1961         r600_cp_stop(rdev);
1962         rdev->cp.ready = false;
1963         r600_wb_disable(rdev);
1964         r600_pcie_gart_disable(rdev);
1965         /* unpin shaders bo */
1966         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1967         if (unlikely(r != 0))
1968                 return r;
1969         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1970         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1971         return 0;
1972 }
1973
1974 /* Plan is to move initialization in that function and use
1975  * helper function so that radeon_device_init pretty much
1976  * do nothing more than calling asic specific function. This
1977  * should also allow to remove a bunch of callback function
1978  * like vram_info.
1979  */
1980 int r600_init(struct radeon_device *rdev)
1981 {
1982         int r;
1983
1984         r = radeon_dummy_page_init(rdev);
1985         if (r)
1986                 return r;
1987         if (r600_debugfs_mc_info_init(rdev)) {
1988                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1989         }
1990         /* This don't do much */
1991         r = radeon_gem_init(rdev);
1992         if (r)
1993                 return r;
1994         /* Read BIOS */
1995         if (!radeon_get_bios(rdev)) {
1996                 if (ASIC_IS_AVIVO(rdev))
1997                         return -EINVAL;
1998         }
1999         /* Must be an ATOMBIOS */
2000         if (!rdev->is_atom_bios) {
2001                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2002                 return -EINVAL;
2003         }
2004         r = radeon_atombios_init(rdev);
2005         if (r)
2006                 return r;
2007         /* Post card if necessary */
2008         if (!r600_card_posted(rdev)) {
2009                 if (!rdev->bios) {
2010                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2011                         return -EINVAL;
2012                 }
2013                 DRM_INFO("GPU not posted. posting now...\n");
2014                 atom_asic_init(rdev->mode_info.atom_context);
2015         }
2016         /* Initialize scratch registers */
2017         r600_scratch_init(rdev);
2018         /* Initialize surface registers */
2019         radeon_surface_init(rdev);
2020         /* Initialize clocks */
2021         radeon_get_clock_info(rdev->ddev);
2022         r = radeon_clocks_init(rdev);
2023         if (r)
2024                 return r;
2025         /* Initialize power management */
2026         radeon_pm_init(rdev);
2027         /* Fence driver */
2028         r = radeon_fence_driver_init(rdev);
2029         if (r)
2030                 return r;
2031         r = r600_mc_init(rdev);
2032         if (r)
2033                 return r;
2034         /* Memory manager */
2035         r = radeon_bo_init(rdev);
2036         if (r)
2037                 return r;
2038
2039         r = radeon_irq_kms_init(rdev);
2040         if (r)
2041                 return r;
2042
2043         rdev->cp.ring_obj = NULL;
2044         r600_ring_init(rdev, 1024 * 1024);
2045
2046         rdev->ih.ring_obj = NULL;
2047         r600_ih_ring_init(rdev, 64 * 1024);
2048
2049         r = r600_pcie_gart_init(rdev);
2050         if (r)
2051                 return r;
2052
2053         rdev->accel_working = true;
2054         r = r600_startup(rdev);
2055         if (r) {
2056                 r600_suspend(rdev);
2057                 r600_wb_fini(rdev);
2058                 radeon_ring_fini(rdev);
2059                 r600_pcie_gart_fini(rdev);
2060                 rdev->accel_working = false;
2061         }
2062         if (rdev->accel_working) {
2063                 r = radeon_ib_pool_init(rdev);
2064                 if (r) {
2065                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2066                         rdev->accel_working = false;
2067                 }
2068                 r = r600_ib_test(rdev);
2069                 if (r) {
2070                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2071                         rdev->accel_working = false;
2072                 }
2073         }
2074
2075         r = r600_audio_init(rdev);
2076         if (r)
2077                 return r; /* TODO error handling */
2078         return 0;
2079 }
2080
2081 void r600_fini(struct radeon_device *rdev)
2082 {
2083         /* Suspend operations */
2084         r600_suspend(rdev);
2085
2086         r600_audio_fini(rdev);
2087         r600_blit_fini(rdev);
2088         r600_irq_fini(rdev);
2089         radeon_irq_kms_fini(rdev);
2090         radeon_ring_fini(rdev);
2091         r600_wb_fini(rdev);
2092         r600_pcie_gart_fini(rdev);
2093         radeon_gem_fini(rdev);
2094         radeon_fence_driver_fini(rdev);
2095         radeon_clocks_fini(rdev);
2096         if (rdev->flags & RADEON_IS_AGP)
2097                 radeon_agp_fini(rdev);
2098         radeon_bo_fini(rdev);
2099         radeon_atombios_fini(rdev);
2100         kfree(rdev->bios);
2101         rdev->bios = NULL;
2102         radeon_dummy_page_fini(rdev);
2103 }
2104
2105
2106 /*
2107  * CS stuff
2108  */
2109 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2110 {
2111         /* FIXME: implement */
2112         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2113         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2114         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2115         radeon_ring_write(rdev, ib->length_dw);
2116 }
2117
2118 int r600_ib_test(struct radeon_device *rdev)
2119 {
2120         struct radeon_ib *ib;
2121         uint32_t scratch;
2122         uint32_t tmp = 0;
2123         unsigned i;
2124         int r;
2125
2126         r = radeon_scratch_get(rdev, &scratch);
2127         if (r) {
2128                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2129                 return r;
2130         }
2131         WREG32(scratch, 0xCAFEDEAD);
2132         r = radeon_ib_get(rdev, &ib);
2133         if (r) {
2134                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2135                 return r;
2136         }
2137         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2138         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2139         ib->ptr[2] = 0xDEADBEEF;
2140         ib->ptr[3] = PACKET2(0);
2141         ib->ptr[4] = PACKET2(0);
2142         ib->ptr[5] = PACKET2(0);
2143         ib->ptr[6] = PACKET2(0);
2144         ib->ptr[7] = PACKET2(0);
2145         ib->ptr[8] = PACKET2(0);
2146         ib->ptr[9] = PACKET2(0);
2147         ib->ptr[10] = PACKET2(0);
2148         ib->ptr[11] = PACKET2(0);
2149         ib->ptr[12] = PACKET2(0);
2150         ib->ptr[13] = PACKET2(0);
2151         ib->ptr[14] = PACKET2(0);
2152         ib->ptr[15] = PACKET2(0);
2153         ib->length_dw = 16;
2154         r = radeon_ib_schedule(rdev, ib);
2155         if (r) {
2156                 radeon_scratch_free(rdev, scratch);
2157                 radeon_ib_free(rdev, &ib);
2158                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2159                 return r;
2160         }
2161         r = radeon_fence_wait(ib->fence, false);
2162         if (r) {
2163                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2164                 return r;
2165         }
2166         for (i = 0; i < rdev->usec_timeout; i++) {
2167                 tmp = RREG32(scratch);
2168                 if (tmp == 0xDEADBEEF)
2169                         break;
2170                 DRM_UDELAY(1);
2171         }
2172         if (i < rdev->usec_timeout) {
2173                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2174         } else {
2175                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2176                           scratch, tmp);
2177                 r = -EINVAL;
2178         }
2179         radeon_scratch_free(rdev, scratch);
2180         radeon_ib_free(rdev, &ib);
2181         return r;
2182 }
2183
2184 /*
2185  * Interrupts
2186  *
2187  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2188  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2189  * writing to the ring and the GPU consuming, the GPU writes to the ring
2190  * and host consumes.  As the host irq handler processes interrupts, it
2191  * increments the rptr.  When the rptr catches up with the wptr, all the
2192  * current interrupts have been processed.
2193  */
2194
2195 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2196 {
2197         u32 rb_bufsz;
2198
2199         /* Align ring size */
2200         rb_bufsz = drm_order(ring_size / 4);
2201         ring_size = (1 << rb_bufsz) * 4;
2202         rdev->ih.ring_size = ring_size;
2203         rdev->ih.align_mask = 4 - 1;
2204 }
2205
2206 static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
2207 {
2208         int r;
2209
2210         rdev->ih.ring_size = ring_size;
2211         /* Allocate ring buffer */
2212         if (rdev->ih.ring_obj == NULL) {
2213                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2214                                      true,
2215                                      RADEON_GEM_DOMAIN_GTT,
2216                                      &rdev->ih.ring_obj);
2217                 if (r) {
2218                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2219                         return r;
2220                 }
2221                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2222                 if (unlikely(r != 0))
2223                         return r;
2224                 r = radeon_bo_pin(rdev->ih.ring_obj,
2225                                   RADEON_GEM_DOMAIN_GTT,
2226                                   &rdev->ih.gpu_addr);
2227                 if (r) {
2228                         radeon_bo_unreserve(rdev->ih.ring_obj);
2229                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2230                         return r;
2231                 }
2232                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2233                                    (void **)&rdev->ih.ring);
2234                 radeon_bo_unreserve(rdev->ih.ring_obj);
2235                 if (r) {
2236                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2237                         return r;
2238                 }
2239         }
2240         rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
2241         rdev->ih.rptr = 0;
2242
2243         return 0;
2244 }
2245
2246 static void r600_ih_ring_fini(struct radeon_device *rdev)
2247 {
2248         int r;
2249         if (rdev->ih.ring_obj) {
2250                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2251                 if (likely(r == 0)) {
2252                         radeon_bo_kunmap(rdev->ih.ring_obj);
2253                         radeon_bo_unpin(rdev->ih.ring_obj);
2254                         radeon_bo_unreserve(rdev->ih.ring_obj);
2255                 }
2256                 radeon_bo_unref(&rdev->ih.ring_obj);
2257                 rdev->ih.ring = NULL;
2258                 rdev->ih.ring_obj = NULL;
2259         }
2260 }
2261
2262 static void r600_rlc_stop(struct radeon_device *rdev)
2263 {
2264
2265         if (rdev->family >= CHIP_RV770) {
2266                 /* r7xx asics need to soft reset RLC before halting */
2267                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2268                 RREG32(SRBM_SOFT_RESET);
2269                 udelay(15000);
2270                 WREG32(SRBM_SOFT_RESET, 0);
2271                 RREG32(SRBM_SOFT_RESET);
2272         }
2273
2274         WREG32(RLC_CNTL, 0);
2275 }
2276
2277 static void r600_rlc_start(struct radeon_device *rdev)
2278 {
2279         WREG32(RLC_CNTL, RLC_ENABLE);
2280 }
2281
2282 static int r600_rlc_init(struct radeon_device *rdev)
2283 {
2284         u32 i;
2285         const __be32 *fw_data;
2286
2287         if (!rdev->rlc_fw)
2288                 return -EINVAL;
2289
2290         r600_rlc_stop(rdev);
2291
2292         WREG32(RLC_HB_BASE, 0);
2293         WREG32(RLC_HB_CNTL, 0);
2294         WREG32(RLC_HB_RPTR, 0);
2295         WREG32(RLC_HB_WPTR, 0);
2296         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2297         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2298         WREG32(RLC_MC_CNTL, 0);
2299         WREG32(RLC_UCODE_CNTL, 0);
2300
2301         fw_data = (const __be32 *)rdev->rlc_fw->data;
2302         if (rdev->family >= CHIP_RV770) {
2303                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2304                         WREG32(RLC_UCODE_ADDR, i);
2305                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2306                 }
2307         } else {
2308                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2309                         WREG32(RLC_UCODE_ADDR, i);
2310                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2311                 }
2312         }
2313         WREG32(RLC_UCODE_ADDR, 0);
2314
2315         r600_rlc_start(rdev);
2316
2317         return 0;
2318 }
2319
2320 static void r600_enable_interrupts(struct radeon_device *rdev)
2321 {
2322         u32 ih_cntl = RREG32(IH_CNTL);
2323         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2324
2325         ih_cntl |= ENABLE_INTR;
2326         ih_rb_cntl |= IH_RB_ENABLE;
2327         WREG32(IH_CNTL, ih_cntl);
2328         WREG32(IH_RB_CNTL, ih_rb_cntl);
2329         rdev->ih.enabled = true;
2330 }
2331
2332 static void r600_disable_interrupts(struct radeon_device *rdev)
2333 {
2334         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2335         u32 ih_cntl = RREG32(IH_CNTL);
2336
2337         ih_rb_cntl &= ~IH_RB_ENABLE;
2338         ih_cntl &= ~ENABLE_INTR;
2339         WREG32(IH_RB_CNTL, ih_rb_cntl);
2340         WREG32(IH_CNTL, ih_cntl);
2341         /* set rptr, wptr to 0 */
2342         WREG32(IH_RB_RPTR, 0);
2343         WREG32(IH_RB_WPTR, 0);
2344         rdev->ih.enabled = false;
2345         rdev->ih.wptr = 0;
2346         rdev->ih.rptr = 0;
2347 }
2348
2349 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2350 {
2351         u32 tmp;
2352
2353         WREG32(CP_INT_CNTL, 0);
2354         WREG32(GRBM_INT_CNTL, 0);
2355         WREG32(DxMODE_INT_MASK, 0);
2356         if (ASIC_IS_DCE3(rdev)) {
2357                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2358                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2359                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2360                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2361                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2362                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2363                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2364                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2365                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2366                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2367                 if (ASIC_IS_DCE32(rdev)) {
2368                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2369                         WREG32(DC_HPD5_INT_CONTROL, 0);
2370                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2371                         WREG32(DC_HPD6_INT_CONTROL, 0);
2372                 }
2373         } else {
2374                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2375                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2376                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2377                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2378                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2379                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2380                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2381                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2382         }
2383 }
2384
2385 int r600_irq_init(struct radeon_device *rdev)
2386 {
2387         int ret = 0;
2388         int rb_bufsz;
2389         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2390
2391         /* allocate ring */
2392         ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size);
2393         if (ret)
2394                 return ret;
2395
2396         /* disable irqs */
2397         r600_disable_interrupts(rdev);
2398
2399         /* init rlc */
2400         ret = r600_rlc_init(rdev);
2401         if (ret) {
2402                 r600_ih_ring_fini(rdev);
2403                 return ret;
2404         }
2405
2406         /* setup interrupt control */
2407         /* set dummy read address to ring address */
2408         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2409         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2410         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2411          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2412          */
2413         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2414         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2415         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2416         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2417
2418         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2419         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2420
2421         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2422                       IH_WPTR_OVERFLOW_CLEAR |
2423                       (rb_bufsz << 1));
2424         /* WPTR writeback, not yet */
2425         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2426         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2427         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2428
2429         WREG32(IH_RB_CNTL, ih_rb_cntl);
2430
2431         /* set rptr, wptr to 0 */
2432         WREG32(IH_RB_RPTR, 0);
2433         WREG32(IH_RB_WPTR, 0);
2434
2435         /* Default settings for IH_CNTL (disabled at first) */
2436         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2437         /* RPTR_REARM only works if msi's are enabled */
2438         if (rdev->msi_enabled)
2439                 ih_cntl |= RPTR_REARM;
2440
2441 #ifdef __BIG_ENDIAN
2442         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2443 #endif
2444         WREG32(IH_CNTL, ih_cntl);
2445
2446         /* force the active interrupt state to all disabled */
2447         r600_disable_interrupt_state(rdev);
2448
2449         /* enable irqs */
2450         r600_enable_interrupts(rdev);
2451
2452         return ret;
2453 }
2454
2455 void r600_irq_fini(struct radeon_device *rdev)
2456 {
2457         r600_disable_interrupts(rdev);
2458         r600_rlc_stop(rdev);
2459         r600_ih_ring_fini(rdev);
2460 }
2461
2462 int r600_irq_set(struct radeon_device *rdev)
2463 {
2464         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2465         u32 mode_int = 0;
2466         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2467
2468         /* don't enable anything if the ih is disabled */
2469         if (!rdev->ih.enabled)
2470                 return 0;
2471
2472         if (ASIC_IS_DCE3(rdev)) {
2473                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2474                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2475                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2476                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2477                 if (ASIC_IS_DCE32(rdev)) {
2478                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2479                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2480                 }
2481         } else {
2482                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2483                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2484                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2485         }
2486
2487         if (rdev->irq.sw_int) {
2488                 DRM_DEBUG("r600_irq_set: sw int\n");
2489                 cp_int_cntl |= RB_INT_ENABLE;
2490         }
2491         if (rdev->irq.crtc_vblank_int[0]) {
2492                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2493                 mode_int |= D1MODE_VBLANK_INT_MASK;
2494         }
2495         if (rdev->irq.crtc_vblank_int[1]) {
2496                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2497                 mode_int |= D2MODE_VBLANK_INT_MASK;
2498         }
2499         if (rdev->irq.hpd[0]) {
2500                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2501                 hpd1 |= DC_HPDx_INT_EN;
2502         }
2503         if (rdev->irq.hpd[1]) {
2504                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2505                 hpd2 |= DC_HPDx_INT_EN;
2506         }
2507         if (rdev->irq.hpd[2]) {
2508                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2509                 hpd3 |= DC_HPDx_INT_EN;
2510         }
2511         if (rdev->irq.hpd[3]) {
2512                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2513                 hpd4 |= DC_HPDx_INT_EN;
2514         }
2515         if (rdev->irq.hpd[4]) {
2516                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2517                 hpd5 |= DC_HPDx_INT_EN;
2518         }
2519         if (rdev->irq.hpd[5]) {
2520                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2521                 hpd6 |= DC_HPDx_INT_EN;
2522         }
2523
2524         WREG32(CP_INT_CNTL, cp_int_cntl);
2525         WREG32(DxMODE_INT_MASK, mode_int);
2526         if (ASIC_IS_DCE3(rdev)) {
2527                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2528                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2529                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2530                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2531                 if (ASIC_IS_DCE32(rdev)) {
2532                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2533                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2534                 }
2535         } else {
2536                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2537                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2538                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2539         }
2540
2541         return 0;
2542 }
2543
2544 static inline void r600_irq_ack(struct radeon_device *rdev,
2545                                 u32 *disp_int,
2546                                 u32 *disp_int_cont,
2547                                 u32 *disp_int_cont2)
2548 {
2549         u32 tmp;
2550
2551         if (ASIC_IS_DCE3(rdev)) {
2552                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2553                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2554                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2555         } else {
2556                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2557                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2558                 *disp_int_cont2 = 0;
2559         }
2560
2561         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2562                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2563         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2564                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2565         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2566                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2567         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2568                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2569         if (*disp_int & DC_HPD1_INTERRUPT) {
2570                 if (ASIC_IS_DCE3(rdev)) {
2571                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2572                         tmp |= DC_HPDx_INT_ACK;
2573                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2574                 } else {
2575                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2576                         tmp |= DC_HPDx_INT_ACK;
2577                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2578                 }
2579         }
2580         if (*disp_int & DC_HPD2_INTERRUPT) {
2581                 if (ASIC_IS_DCE3(rdev)) {
2582                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2583                         tmp |= DC_HPDx_INT_ACK;
2584                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2585                 } else {
2586                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2587                         tmp |= DC_HPDx_INT_ACK;
2588                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2589                 }
2590         }
2591         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2592                 if (ASIC_IS_DCE3(rdev)) {
2593                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2594                         tmp |= DC_HPDx_INT_ACK;
2595                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2596                 } else {
2597                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2598                         tmp |= DC_HPDx_INT_ACK;
2599                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2600                 }
2601         }
2602         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2603                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2604                 tmp |= DC_HPDx_INT_ACK;
2605                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2606         }
2607         if (ASIC_IS_DCE32(rdev)) {
2608                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2609                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2610                         tmp |= DC_HPDx_INT_ACK;
2611                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2612                 }
2613                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2614                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2615                         tmp |= DC_HPDx_INT_ACK;
2616                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2617                 }
2618         }
2619 }
2620
2621 void r600_irq_disable(struct radeon_device *rdev)
2622 {
2623         u32 disp_int, disp_int_cont, disp_int_cont2;
2624
2625         r600_disable_interrupts(rdev);
2626         /* Wait and acknowledge irq */
2627         mdelay(1);
2628         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2629         r600_disable_interrupt_state(rdev);
2630 }
2631
2632 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2633 {
2634         u32 wptr, tmp;
2635
2636         /* XXX use writeback */
2637         wptr = RREG32(IH_RB_WPTR);
2638
2639         if (wptr & RB_OVERFLOW) {
2640                 WARN_ON(1);
2641                 /* XXX deal with overflow */
2642                 DRM_ERROR("IH RB overflow\n");
2643                 tmp = RREG32(IH_RB_CNTL);
2644                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2645                 WREG32(IH_RB_CNTL, tmp);
2646         }
2647         wptr = wptr & WPTR_OFFSET_MASK;
2648
2649         return wptr;
2650 }
2651
2652 /*        r600 IV Ring
2653  * Each IV ring entry is 128 bits:
2654  * [7:0]    - interrupt source id
2655  * [31:8]   - reserved
2656  * [59:32]  - interrupt source data
2657  * [127:60]  - reserved
2658  *
2659  * The basic interrupt vector entries
2660  * are decoded as follows:
2661  * src_id  src_data  description
2662  *      1         0  D1 Vblank
2663  *      1         1  D1 Vline
2664  *      5         0  D2 Vblank
2665  *      5         1  D2 Vline
2666  *     19         0  FP Hot plug detection A
2667  *     19         1  FP Hot plug detection B
2668  *     19         2  DAC A auto-detection
2669  *     19         3  DAC B auto-detection
2670  *    176         -  CP_INT RB
2671  *    177         -  CP_INT IB1
2672  *    178         -  CP_INT IB2
2673  *    181         -  EOP Interrupt
2674  *    233         -  GUI Idle
2675  *
2676  * Note, these are based on r600 and may need to be
2677  * adjusted or added to on newer asics
2678  */
2679
2680 int r600_irq_process(struct radeon_device *rdev)
2681 {
2682         u32 wptr = r600_get_ih_wptr(rdev);
2683         u32 rptr = rdev->ih.rptr;
2684         u32 src_id, src_data;
2685         u32 last_entry = rdev->ih.ring_size - 16;
2686         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2687         unsigned long flags;
2688         bool queue_hotplug = false;
2689
2690         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2691
2692         spin_lock_irqsave(&rdev->ih.lock, flags);
2693
2694         if (rptr == wptr) {
2695                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2696                 return IRQ_NONE;
2697         }
2698         if (rdev->shutdown) {
2699                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2700                 return IRQ_NONE;
2701         }
2702
2703 restart_ih:
2704         /* display interrupts */
2705         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2706
2707         rdev->ih.wptr = wptr;
2708         while (rptr != wptr) {
2709                 /* wptr/rptr are in bytes! */
2710                 ring_index = rptr / 4;
2711                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2712                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2713
2714                 switch (src_id) {
2715                 case 1: /* D1 vblank/vline */
2716                         switch (src_data) {
2717                         case 0: /* D1 vblank */
2718                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2719                                         drm_handle_vblank(rdev->ddev, 0);
2720                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2721                                         DRM_DEBUG("IH: D1 vblank\n");
2722                                 }
2723                                 break;
2724                         case 1: /* D1 vline */
2725                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2726                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2727                                         DRM_DEBUG("IH: D1 vline\n");
2728                                 }
2729                                 break;
2730                         default:
2731                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2732                                 break;
2733                         }
2734                         break;
2735                 case 5: /* D2 vblank/vline */
2736                         switch (src_data) {
2737                         case 0: /* D2 vblank */
2738                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2739                                         drm_handle_vblank(rdev->ddev, 1);
2740                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2741                                         DRM_DEBUG("IH: D2 vblank\n");
2742                                 }
2743                                 break;
2744                         case 1: /* D1 vline */
2745                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2746                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2747                                         DRM_DEBUG("IH: D2 vline\n");
2748                                 }
2749                                 break;
2750                         default:
2751                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2752                                 break;
2753                         }
2754                         break;
2755                 case 19: /* HPD/DAC hotplug */
2756                         switch (src_data) {
2757                         case 0:
2758                                 if (disp_int & DC_HPD1_INTERRUPT) {
2759                                         disp_int &= ~DC_HPD1_INTERRUPT;
2760                                         queue_hotplug = true;
2761                                         DRM_DEBUG("IH: HPD1\n");
2762                                 }
2763                                 break;
2764                         case 1:
2765                                 if (disp_int & DC_HPD2_INTERRUPT) {
2766                                         disp_int &= ~DC_HPD2_INTERRUPT;
2767                                         queue_hotplug = true;
2768                                         DRM_DEBUG("IH: HPD2\n");
2769                                 }
2770                                 break;
2771                         case 4:
2772                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2773                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2774                                         queue_hotplug = true;
2775                                         DRM_DEBUG("IH: HPD3\n");
2776                                 }
2777                                 break;
2778                         case 5:
2779                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2780                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2781                                         queue_hotplug = true;
2782                                         DRM_DEBUG("IH: HPD4\n");
2783                                 }
2784                                 break;
2785                         case 10:
2786                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2787                                         disp_int_cont &= ~DC_HPD5_INTERRUPT;
2788                                         queue_hotplug = true;
2789                                         DRM_DEBUG("IH: HPD5\n");
2790                                 }
2791                                 break;
2792                         case 12:
2793                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2794                                         disp_int_cont &= ~DC_HPD6_INTERRUPT;
2795                                         queue_hotplug = true;
2796                                         DRM_DEBUG("IH: HPD6\n");
2797                                 }
2798                                 break;
2799                         default:
2800                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2801                                 break;
2802                         }
2803                         break;
2804                 case 176: /* CP_INT in ring buffer */
2805                 case 177: /* CP_INT in IB1 */
2806                 case 178: /* CP_INT in IB2 */
2807                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2808                         radeon_fence_process(rdev);
2809                         break;
2810                 case 181: /* CP EOP event */
2811                         DRM_DEBUG("IH: CP EOP\n");
2812                         break;
2813                 default:
2814                         DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2815                         break;
2816                 }
2817
2818                 /* wptr/rptr are in bytes! */
2819                 if (rptr == last_entry)
2820                         rptr = 0;
2821                 else
2822                         rptr += 16;
2823         }
2824         /* make sure wptr hasn't changed while processing */
2825         wptr = r600_get_ih_wptr(rdev);
2826         if (wptr != rdev->ih.wptr)
2827                 goto restart_ih;
2828         if (queue_hotplug)
2829                 queue_work(rdev->wq, &rdev->hotplug_work);
2830         rdev->ih.rptr = rptr;
2831         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2832         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2833         return IRQ_HANDLED;
2834 }
2835
2836 /*
2837  * Debugfs info
2838  */
2839 #if defined(CONFIG_DEBUG_FS)
2840
2841 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2842 {
2843         struct drm_info_node *node = (struct drm_info_node *) m->private;
2844         struct drm_device *dev = node->minor->dev;
2845         struct radeon_device *rdev = dev->dev_private;
2846         unsigned count, i, j;
2847
2848         radeon_ring_free_size(rdev);
2849         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2850         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2851         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2852         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2853         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2854         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2855         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2856         seq_printf(m, "%u dwords in ring\n", count);
2857         i = rdev->cp.rptr;
2858         for (j = 0; j <= count; j++) {
2859                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2860                 i = (i + 1) & rdev->cp.ptr_mask;
2861         }
2862         return 0;
2863 }
2864
2865 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2866 {
2867         struct drm_info_node *node = (struct drm_info_node *) m->private;
2868         struct drm_device *dev = node->minor->dev;
2869         struct radeon_device *rdev = dev->dev_private;
2870
2871         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2872         DREG32_SYS(m, rdev, VM_L2_STATUS);
2873         return 0;
2874 }
2875
2876 static struct drm_info_list r600_mc_info_list[] = {
2877         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2878         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2879 };
2880 #endif
2881
2882 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2883 {
2884 #if defined(CONFIG_DEBUG_FS)
2885         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2886 #else
2887         return 0;
2888 #endif
2889 }