drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50 #define CAYMAN_RLC_UCODE_SIZE 1024
  51
  52 /* Firmware Names */
  53 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  54 MODULE_FIRMWARE("radeon/R600_me.bin");
  55 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV610_me.bin");
  57 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV630_me.bin");
  59 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV620_me.bin");
  61 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV635_me.bin");
  63 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV670_me.bin");
  65 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RS780_me.bin");
  67 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RV770_me.bin");
  69 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV730_me.bin");
  71 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV710_me.bin");
  73 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  74 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  87 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  88 MODULE_FIRMWARE("radeon/PALM_me.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  90 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  92 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  93 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  94
  95 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  96
  97 /* r600,rv610,rv630,rv620,rv635,rv670 */
  98 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  99 void r600_gpu_init(struct radeon_device *rdev);
 100 void r600_fini(struct radeon_device *rdev);
 101 void r600_irq_disable(struct radeon_device *rdev);
 102 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 103
 104 /* get temperature in millidegrees */
 105 int rv6xx_get_temp(struct radeon_device *rdev)
 106 {
 107         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 108                 ASIC_T_SHIFT;
 109         int actual_temp = temp & 0xff;
 110
 111         if (temp & 0x100)
 112                 actual_temp -= 256;
 113
 114         return actual_temp * 1000;
 115 }
 116
 117 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 118 {
 119         int i;
 120
 121         rdev->pm.dynpm_can_upclock = true;
 122         rdev->pm.dynpm_can_downclock = true;
 123
 124         /* power state array is low to high, default is first */
 125         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 126                 int min_power_state_index = 0;
 127
 128                 if (rdev->pm.num_power_states > 2)
 129                         min_power_state_index = 1;
 130
 131                 switch (rdev->pm.dynpm_planned_action) {
 132                 case DYNPM_ACTION_MINIMUM:
 133                         rdev->pm.requested_power_state_index = min_power_state_index;
 134                         rdev->pm.requested_clock_mode_index = 0;
 135                         rdev->pm.dynpm_can_downclock = false;
 136                         break;
 137                 case DYNPM_ACTION_DOWNCLOCK:
 138                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 139                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 140                                 rdev->pm.dynpm_can_downclock = false;
 141                         } else {
 142                                 if (rdev->pm.active_crtc_count > 1) {
 143                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 144                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 145                                                         continue;
 146                                                 else if (i >= rdev->pm.current_power_state_index) {
 147                                                         rdev->pm.requested_power_state_index =
 148                                                                 rdev->pm.current_power_state_index;
 149                                                         break;
 150                                                 } else {
 151                                                         rdev->pm.requested_power_state_index = i;
 152                                                         break;
 153                                                 }
 154                                         }
 155                                 } else {
 156                                         if (rdev->pm.current_power_state_index == 0)
 157                                                 rdev->pm.requested_power_state_index =
 158                                                         rdev->pm.num_power_states - 1;
 159                                         else
 160                                                 rdev->pm.requested_power_state_index =
 161                                                         rdev->pm.current_power_state_index - 1;
 162                                 }
 163                         }
 164                         rdev->pm.requested_clock_mode_index = 0;
 165                         /* don't use the power state if crtcs are active and no display flag is set */
 166                         if ((rdev->pm.active_crtc_count > 0) &&
 167                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 168                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 169                              RADEON_PM_MODE_NO_DISPLAY)) {
 170                                 rdev->pm.requested_power_state_index++;
 171                         }
 172                         break;
 173                 case DYNPM_ACTION_UPCLOCK:
 174                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 175                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 176                                 rdev->pm.dynpm_can_upclock = false;
 177                         } else {
 178                                 if (rdev->pm.active_crtc_count > 1) {
 179                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 180                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 181                                                         continue;
 182                                                 else if (i <= rdev->pm.current_power_state_index) {
 183                                                         rdev->pm.requested_power_state_index =
 184                                                                 rdev->pm.current_power_state_index;
 185                                                         break;
 186                                                 } else {
 187                                                         rdev->pm.requested_power_state_index = i;
 188                                                         break;
 189                                                 }
 190                                         }
 191                                 } else
 192                                         rdev->pm.requested_power_state_index =
 193                                                 rdev->pm.current_power_state_index + 1;
 194                         }
 195                         rdev->pm.requested_clock_mode_index = 0;
 196                         break;
 197                 case DYNPM_ACTION_DEFAULT:
 198                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 199                         rdev->pm.requested_clock_mode_index = 0;
 200                         rdev->pm.dynpm_can_upclock = false;
 201                         break;
 202                 case DYNPM_ACTION_NONE:
 203                 default:
 204                         DRM_ERROR("Requested mode for not defined action\n");
 205                         return;
 206                 }
 207         } else {
 208                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 209                 /* for now just select the first power state and switch between clock modes */
 210                 /* power state array is low to high, default is first (0) */
 211                 if (rdev->pm.active_crtc_count > 1) {
 212                         rdev->pm.requested_power_state_index = -1;
 213                         /* start at 1 as we don't want the default mode */
 214                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 215                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 216                                         continue;
 217                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 218                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 219                                         rdev->pm.requested_power_state_index = i;
 220                                         break;
 221                                 }
 222                         }
 223                         /* if nothing selected, grab the default state. */
 224                         if (rdev->pm.requested_power_state_index == -1)
 225                                 rdev->pm.requested_power_state_index = 0;
 226                 } else
 227                         rdev->pm.requested_power_state_index = 1;
 228
 229                 switch (rdev->pm.dynpm_planned_action) {
 230                 case DYNPM_ACTION_MINIMUM:
 231                         rdev->pm.requested_clock_mode_index = 0;
 232                         rdev->pm.dynpm_can_downclock = false;
 233                         break;
 234                 case DYNPM_ACTION_DOWNCLOCK:
 235                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 236                                 if (rdev->pm.current_clock_mode_index == 0) {
 237                                         rdev->pm.requested_clock_mode_index = 0;
 238                                         rdev->pm.dynpm_can_downclock = false;
 239                                 } else
 240                                         rdev->pm.requested_clock_mode_index =
 241                                                 rdev->pm.current_clock_mode_index - 1;
 242                         } else {
 243                                 rdev->pm.requested_clock_mode_index = 0;
 244                                 rdev->pm.dynpm_can_downclock = false;
 245                         }
 246                         /* don't use the power state if crtcs are active and no display flag is set */
 247                         if ((rdev->pm.active_crtc_count > 0) &&
 248                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 249                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 250                              RADEON_PM_MODE_NO_DISPLAY)) {
 251                                 rdev->pm.requested_clock_mode_index++;
 252                         }
 253                         break;
 254                 case DYNPM_ACTION_UPCLOCK:
 255                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 256                                 if (rdev->pm.current_clock_mode_index ==
 257                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 258                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 259                                         rdev->pm.dynpm_can_upclock = false;
 260                                 } else
 261                                         rdev->pm.requested_clock_mode_index =
 262                                                 rdev->pm.current_clock_mode_index + 1;
 263                         } else {
 264                                 rdev->pm.requested_clock_mode_index =
 265                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 266                                 rdev->pm.dynpm_can_upclock = false;
 267                         }
 268                         break;
 269                 case DYNPM_ACTION_DEFAULT:
 270                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 271                         rdev->pm.requested_clock_mode_index = 0;
 272                         rdev->pm.dynpm_can_upclock = false;
 273                         break;
 274                 case DYNPM_ACTION_NONE:
 275                 default:
 276                         DRM_ERROR("Requested mode for not defined action\n");
 277                         return;
 278                 }
 279         }
 280
 281         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 282                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 283                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 284                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 285                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   pcie_lanes);
 288 }
 289
 290 static int r600_pm_get_type_index(struct radeon_device *rdev,
 291                                   enum radeon_pm_state_type ps_type,
 292                                   int instance)
 293 {
 294         int i;
 295         int found_instance = -1;
 296
 297         for (i = 0; i < rdev->pm.num_power_states; i++) {
 298                 if (rdev->pm.power_state[i].type == ps_type) {
 299                         found_instance++;
 300                         if (found_instance == instance)
 301                                 return i;
 302                 }
 303         }
 304         /* return default if no match */
 305         return rdev->pm.default_power_state_index;
 306 }
 307
 308 void rs780_pm_init_profile(struct radeon_device *rdev)
 309 {
 310         if (rdev->pm.num_power_states == 2) {
 311                 /* default */
 312                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 313                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 314                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 316                 /* low sh */
 317                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 321                 /* mid sh */
 322                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 326                 /* high sh */
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 331                 /* low mh */
 332                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 336                 /* mid mh */
 337                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 341                 /* high mh */
 342                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 343                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 346         } else if (rdev->pm.num_power_states == 3) {
 347                 /* default */
 348                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 349                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 350                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 351                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 352                 /* low sh */
 353                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 355                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 356                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 357                 /* mid sh */
 358                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 361                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 362                 /* high sh */
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 366                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 367                 /* low mh */
 368                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 369                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 370                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 372                 /* mid mh */
 373                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 374                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 375                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 377                 /* high mh */
 378                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 379                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 381                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 382         } else {
 383                 /* default */
 384                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 385                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 386                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 388                 /* low sh */
 389                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 391                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 392                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 393                 /* mid sh */
 394                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 395                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 396                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 397                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 398                 /* high sh */
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 403                 /* low mh */
 404                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 405                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 406                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 408                 /* mid mh */
 409                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 410                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 411                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 413                 /* high mh */
 414                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 415                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 416                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 417                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 418         }
 419 }
 420
 421 void r600_pm_init_profile(struct radeon_device *rdev)
 422 {
 423         if (rdev->family == CHIP_R600) {
 424                 /* XXX */
 425                 /* default */
 426                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 427                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 429                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 430                 /* low sh */
 431                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 432                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 435                 /* mid sh */
 436                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 437                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 439                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 440                 /* high sh */
 441                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 442                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 445                 /* low mh */
 446                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 447                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 448                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 449                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 450                 /* mid mh */
 451                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 452                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 453                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 454                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 455                 /* high mh */
 456                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 457                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 458                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 459                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 460         } else {
 461                 if (rdev->pm.num_power_states < 4) {
 462                         /* default */
 463                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 464                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 465                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 466                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 467                         /* low sh */
 468                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 469                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 470                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 472                         /* mid sh */
 473                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 474                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 475                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 476                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 477                         /* high sh */
 478                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 479                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 482                         /* low mh */
 483                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 484                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 485                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 486                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 487                         /* low mh */
 488                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 489                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 490                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 491                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 492                         /* high mh */
 493                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 494                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 495                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 496                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 497                 } else {
 498                         /* default */
 499                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 500                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 501                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 502                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 503                         /* low sh */
 504                         if (rdev->flags & RADEON_IS_MOBILITY) {
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 506                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 508                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 509                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 510                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 511                         } else {
 512                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 513                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 514                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 515                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 516                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 517                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 518                         }
 519                         /* mid sh */
 520                         if (rdev->flags & RADEON_IS_MOBILITY) {
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 522                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 524                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 525                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 526                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 527                         } else {
 528                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 529                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 530                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 531                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 532                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 533                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 534                         }
 535                         /* high sh */
 536                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 537                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 538                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 539                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 540                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 541                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 542                         /* low mh */
 543                         if (rdev->flags & RADEON_IS_MOBILITY) {
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 545                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 547                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 548                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 549                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 550                         } else {
 551                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 552                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 553                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 554                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 555                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 556                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 557                         }
 558                         /* mid mh */
 559                         if (rdev->flags & RADEON_IS_MOBILITY) {
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 561                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 563                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 564                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 565                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 566                         } else {
 567                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 568                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 569                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 570                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 571                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 572                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 573                         }
 574                         /* high mh */
 575                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 576                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 577                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 578                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 579                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 580                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 581                 }
 582         }
 583 }
 584
 585 void r600_pm_misc(struct radeon_device *rdev)
 586 {
 587         int req_ps_idx = rdev->pm.requested_power_state_index;
 588         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 589         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 590         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 591
 592         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 593                 if (voltage->voltage != rdev->pm.current_vddc) {
 594                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 595                         rdev->pm.current_vddc = voltage->voltage;
 596                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 597                 }
 598         }
 599 }
 600
 601 bool r600_gui_idle(struct radeon_device *rdev)
 602 {
 603         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 604                 return false;
 605         else
 606                 return true;
 607 }
 608
 609 /* hpd for digital panel detect/disconnect */
 610 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 611 {
 612         bool connected = false;
 613
 614         if (ASIC_IS_DCE3(rdev)) {
 615                 switch (hpd) {
 616                 case RADEON_HPD_1:
 617                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 618                                 connected = true;
 619                         break;
 620                 case RADEON_HPD_2:
 621                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 622                                 connected = true;
 623                         break;
 624                 case RADEON_HPD_3:
 625                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 626                                 connected = true;
 627                         break;
 628                 case RADEON_HPD_4:
 629                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 630                                 connected = true;
 631                         break;
 632                         /* DCE 3.2 */
 633                 case RADEON_HPD_5:
 634                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 635                                 connected = true;
 636                         break;
 637                 case RADEON_HPD_6:
 638                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 639                                 connected = true;
 640                         break;
 641                 default:
 642                         break;
 643                 }
 644         } else {
 645                 switch (hpd) {
 646                 case RADEON_HPD_1:
 647                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 648                                 connected = true;
 649                         break;
 650                 case RADEON_HPD_2:
 651                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 652                                 connected = true;
 653                         break;
 654                 case RADEON_HPD_3:
 655                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 656                                 connected = true;
 657                         break;
 658                 default:
 659                         break;
 660                 }
 661         }
 662         return connected;
 663 }
 664
 665 void r600_hpd_set_polarity(struct radeon_device *rdev,
 666                            enum radeon_hpd_id hpd)
 667 {
 668         u32 tmp;
 669         bool connected = r600_hpd_sense(rdev, hpd);
 670
 671         if (ASIC_IS_DCE3(rdev)) {
 672                 switch (hpd) {
 673                 case RADEON_HPD_1:
 674                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 675                         if (connected)
 676                                 tmp &= ~DC_HPDx_INT_POLARITY;
 677                         else
 678                                 tmp |= DC_HPDx_INT_POLARITY;
 679                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 680                         break;
 681                 case RADEON_HPD_2:
 682                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 683                         if (connected)
 684                                 tmp &= ~DC_HPDx_INT_POLARITY;
 685                         else
 686                                 tmp |= DC_HPDx_INT_POLARITY;
 687                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 688                         break;
 689                 case RADEON_HPD_3:
 690                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 691                         if (connected)
 692                                 tmp &= ~DC_HPDx_INT_POLARITY;
 693                         else
 694                                 tmp |= DC_HPDx_INT_POLARITY;
 695                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 696                         break;
 697                 case RADEON_HPD_4:
 698                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 699                         if (connected)
 700                                 tmp &= ~DC_HPDx_INT_POLARITY;
 701                         else
 702                                 tmp |= DC_HPDx_INT_POLARITY;
 703                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 704                         break;
 705                 case RADEON_HPD_5:
 706                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 707                         if (connected)
 708                                 tmp &= ~DC_HPDx_INT_POLARITY;
 709                         else
 710                                 tmp |= DC_HPDx_INT_POLARITY;
 711                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 712                         break;
 713                         /* DCE 3.2 */
 714                 case RADEON_HPD_6:
 715                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 716                         if (connected)
 717                                 tmp &= ~DC_HPDx_INT_POLARITY;
 718                         else
 719                                 tmp |= DC_HPDx_INT_POLARITY;
 720                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 721                         break;
 722                 default:
 723                         break;
 724                 }
 725         } else {
 726                 switch (hpd) {
 727                 case RADEON_HPD_1:
 728                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 729                         if (connected)
 730                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 731                         else
 732                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 733                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 734                         break;
 735                 case RADEON_HPD_2:
 736                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 737                         if (connected)
 738                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 739                         else
 740                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 741                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 742                         break;
 743                 case RADEON_HPD_3:
 744                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 745                         if (connected)
 746                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 747                         else
 748                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 749                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 750                         break;
 751                 default:
 752                         break;
 753                 }
 754         }
 755 }
 756
 757 void r600_hpd_init(struct radeon_device *rdev)
 758 {
 759         struct drm_device *dev = rdev->ddev;
 760         struct drm_connector *connector;
 761
 762         if (ASIC_IS_DCE3(rdev)) {
 763                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 764                 if (ASIC_IS_DCE32(rdev))
 765                         tmp |= DC_HPDx_EN;
 766
 767                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 768                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 769                         switch (radeon_connector->hpd.hpd) {
 770                         case RADEON_HPD_1:
 771                                 WREG32(DC_HPD1_CONTROL, tmp);
 772                                 rdev->irq.hpd[0] = true;
 773                                 break;
 774                         case RADEON_HPD_2:
 775                                 WREG32(DC_HPD2_CONTROL, tmp);
 776                                 rdev->irq.hpd[1] = true;
 777                                 break;
 778                         case RADEON_HPD_3:
 779                                 WREG32(DC_HPD3_CONTROL, tmp);
 780                                 rdev->irq.hpd[2] = true;
 781                                 break;
 782                         case RADEON_HPD_4:
 783                                 WREG32(DC_HPD4_CONTROL, tmp);
 784                                 rdev->irq.hpd[3] = true;
 785                                 break;
 786                                 /* DCE 3.2 */
 787                         case RADEON_HPD_5:
 788                                 WREG32(DC_HPD5_CONTROL, tmp);
 789                                 rdev->irq.hpd[4] = true;
 790                                 break;
 791                         case RADEON_HPD_6:
 792                                 WREG32(DC_HPD6_CONTROL, tmp);
 793                                 rdev->irq.hpd[5] = true;
 794                                 break;
 795                         default:
 796                                 break;
 797                         }
 798                 }
 799         } else {
 800                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 801                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 802                         switch (radeon_connector->hpd.hpd) {
 803                         case RADEON_HPD_1:
 804                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 805                                 rdev->irq.hpd[0] = true;
 806                                 break;
 807                         case RADEON_HPD_2:
 808                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 809                                 rdev->irq.hpd[1] = true;
 810                                 break;
 811                         case RADEON_HPD_3:
 812                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 813                                 rdev->irq.hpd[2] = true;
 814                                 break;
 815                         default:
 816                                 break;
 817                         }
 818                 }
 819         }
 820         if (rdev->irq.installed)
 821                 r600_irq_set(rdev);
 822 }
 823
 824 void r600_hpd_fini(struct radeon_device *rdev)
 825 {
 826         struct drm_device *dev = rdev->ddev;
 827         struct drm_connector *connector;
 828
 829         if (ASIC_IS_DCE3(rdev)) {
 830                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 831                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 832                         switch (radeon_connector->hpd.hpd) {
 833                         case RADEON_HPD_1:
 834                                 WREG32(DC_HPD1_CONTROL, 0);
 835                                 rdev->irq.hpd[0] = false;
 836                                 break;
 837                         case RADEON_HPD_2:
 838                                 WREG32(DC_HPD2_CONTROL, 0);
 839                                 rdev->irq.hpd[1] = false;
 840                                 break;
 841                         case RADEON_HPD_3:
 842                                 WREG32(DC_HPD3_CONTROL, 0);
 843                                 rdev->irq.hpd[2] = false;
 844                                 break;
 845                         case RADEON_HPD_4:
 846                                 WREG32(DC_HPD4_CONTROL, 0);
 847                                 rdev->irq.hpd[3] = false;
 848                                 break;
 849                                 /* DCE 3.2 */
 850                         case RADEON_HPD_5:
 851                                 WREG32(DC_HPD5_CONTROL, 0);
 852                                 rdev->irq.hpd[4] = false;
 853                                 break;
 854                         case RADEON_HPD_6:
 855                                 WREG32(DC_HPD6_CONTROL, 0);
 856                                 rdev->irq.hpd[5] = false;
 857                                 break;
 858                         default:
 859                                 break;
 860                         }
 861                 }
 862         } else {
 863                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 864                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 865                         switch (radeon_connector->hpd.hpd) {
 866                         case RADEON_HPD_1:
 867                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 868                                 rdev->irq.hpd[0] = false;
 869                                 break;
 870                         case RADEON_HPD_2:
 871                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 872                                 rdev->irq.hpd[1] = false;
 873                                 break;
 874                         case RADEON_HPD_3:
 875                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 876                                 rdev->irq.hpd[2] = false;
 877                                 break;
 878                         default:
 879                                 break;
 880                         }
 881                 }
 882         }
 883 }
 884
 885 /*
 886  * R600 PCIE GART
 887  */
 888 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 889 {
 890         unsigned i;
 891         u32 tmp;
 892
 893         /* flush hdp cache so updates hit vram */
 894         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 895             !(rdev->flags & RADEON_IS_AGP)) {
 896                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 897                 u32 tmp;
 898
 899                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 900                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 901                  * This seems to cause problems on some AGP cards. Just use the old
 902                  * method for them.
 903                  */
 904                 WREG32(HDP_DEBUG1, 0);
 905                 tmp = readl((void __iomem *)ptr);
 906         } else
 907                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 908
 909         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 910         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 911         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 912         for (i = 0; i < rdev->usec_timeout; i++) {
 913                 /* read MC_STATUS */
 914                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 915                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 916                 if (tmp == 2) {
 917                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 918                         return;
 919                 }
 920                 if (tmp) {
 921                         return;
 922                 }
 923                 udelay(1);
 924         }
 925 }
 926
 927 int r600_pcie_gart_init(struct radeon_device *rdev)
 928 {
 929         int r;
 930
 931         if (rdev->gart.table.vram.robj) {
 932                 WARN(1, "R600 PCIE GART already initialized\n");
 933                 return 0;
 934         }
 935         /* Initialize common gart structure */
 936         r = radeon_gart_init(rdev);
 937         if (r)
 938                 return r;
 939         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 940         return radeon_gart_table_vram_alloc(rdev);
 941 }
 942
 943 int r600_pcie_gart_enable(struct radeon_device *rdev)
 944 {
 945         u32 tmp;
 946         int r, i;
 947
 948         if (rdev->gart.table.vram.robj == NULL) {
 949                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 950                 return -EINVAL;
 951         }
 952         r = radeon_gart_table_vram_pin(rdev);
 953         if (r)
 954                 return r;
 955         radeon_gart_restore(rdev);
 956
 957         /* Setup L2 cache */
 958         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 959                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 960                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 961         WREG32(VM_L2_CNTL2, 0);
 962         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 963         /* Setup TLB control */
 964         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 965                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 966                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 967                 ENABLE_WAIT_L2_QUERY;
 968         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 971         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 972         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 973         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 974         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 976         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 977         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 978         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 979         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 980         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 981         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 982         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 983         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 984         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 985         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 986                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 987         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 988                         (u32)(rdev->dummy_page.addr >> 12));
 989         for (i = 1; i < 7; i++)
 990                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 991
 992         r600_pcie_gart_tlb_flush(rdev);
 993         rdev->gart.ready = true;
 994         return 0;
 995 }
 996
 997 void r600_pcie_gart_disable(struct radeon_device *rdev)
 998 {
 999         u32 tmp;
1000         int i, r;
1001
1002         /* Disable all tables */
1003         for (i = 0; i < 7; i++)
1004                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1005
1006         /* Disable L2 cache */
1007         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1008                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1009         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1010         /* Setup L1 TLB control */
1011         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1012                 ENABLE_WAIT_L2_QUERY;
1013         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1017         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1018         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1019         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1022         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1023         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1024         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1025         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1026         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1027         if (rdev->gart.table.vram.robj) {
1028                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1029                 if (likely(r == 0)) {
1030                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1031                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1032                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1033                 }
1034         }
1035 }
1036
1037 void r600_pcie_gart_fini(struct radeon_device *rdev)
1038 {
1039         radeon_gart_fini(rdev);
1040         r600_pcie_gart_disable(rdev);
1041         radeon_gart_table_vram_free(rdev);
1042 }
1043
1044 void r600_agp_enable(struct radeon_device *rdev)
1045 {
1046         u32 tmp;
1047         int i;
1048
1049         /* Setup L2 cache */
1050         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1051                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1052                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1053         WREG32(VM_L2_CNTL2, 0);
1054         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1055         /* Setup TLB control */
1056         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1057                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1058                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1059                 ENABLE_WAIT_L2_QUERY;
1060         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1063         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1064         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1065         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1066         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1067         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1068         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1069         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1070         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1071         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1072         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1073         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1074         for (i = 0; i < 7; i++)
1075                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1076 }
1077
1078 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1079 {
1080         unsigned i;
1081         u32 tmp;
1082
1083         for (i = 0; i < rdev->usec_timeout; i++) {
1084                 /* read MC_STATUS */
1085                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1086                 if (!tmp)
1087                         return 0;
1088                 udelay(1);
1089         }
1090         return -1;
1091 }
1092
1093 static void r600_mc_program(struct radeon_device *rdev)
1094 {
1095         struct rv515_mc_save save;
1096         u32 tmp;
1097         int i, j;
1098
1099         /* Initialize HDP */
1100         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1101                 WREG32((0x2c14 + j), 0x00000000);
1102                 WREG32((0x2c18 + j), 0x00000000);
1103                 WREG32((0x2c1c + j), 0x00000000);
1104                 WREG32((0x2c20 + j), 0x00000000);
1105                 WREG32((0x2c24 + j), 0x00000000);
1106         }
1107         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1108
1109         rv515_mc_stop(rdev, &save);
1110         if (r600_mc_wait_for_idle(rdev)) {
1111                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1112         }
1113         /* Lockout access through VGA aperture (doesn't exist before R600) */
1114         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1115         /* Update configuration */
1116         if (rdev->flags & RADEON_IS_AGP) {
1117                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1118                         /* VRAM before AGP */
1119                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1120                                 rdev->mc.vram_start >> 12);
1121                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1122                                 rdev->mc.gtt_end >> 12);
1123                 } else {
1124                         /* VRAM after AGP */
1125                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1126                                 rdev->mc.gtt_start >> 12);
1127                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1128                                 rdev->mc.vram_end >> 12);
1129                 }
1130         } else {
1131                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1132                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1133         }
1134         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1135         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1136         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1137         WREG32(MC_VM_FB_LOCATION, tmp);
1138         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1139         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1140         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1141         if (rdev->flags & RADEON_IS_AGP) {
1142                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1143                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1144                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1145         } else {
1146                 WREG32(MC_VM_AGP_BASE, 0);
1147                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1148                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1149         }
1150         if (r600_mc_wait_for_idle(rdev)) {
1151                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1152         }
1153         rv515_mc_resume(rdev, &save);
1154         /* we need to own VRAM, so turn off the VGA renderer here
1155          * to stop it overwriting our objects */
1156         rv515_vga_render_disable(rdev);
1157 }
1158
1159 /**
1160  * r600_vram_gtt_location - try to find VRAM & GTT location
1161  * @rdev: radeon device structure holding all necessary informations
1162  * @mc: memory controller structure holding memory informations
1163  *
1164  * Function will place try to place VRAM at same place as in CPU (PCI)
1165  * address space as some GPU seems to have issue when we reprogram at
1166  * different address space.
1167  *
1168  * If there is not enough space to fit the unvisible VRAM after the
1169  * aperture then we limit the VRAM size to the aperture.
1170  *
1171  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1172  * them to be in one from GPU point of view so that we can program GPU to
1173  * catch access outside them (weird GPU policy see ??).
1174  *
1175  * This function will never fails, worst case are limiting VRAM or GTT.
1176  *
1177  * Note: GTT start, end, size should be initialized before calling this
1178  * function on AGP platform.
1179  */
1180 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1181 {
1182         u64 size_bf, size_af;
1183
1184         if (mc->mc_vram_size > 0xE0000000) {
1185                 /* leave room for at least 512M GTT */
1186                 dev_warn(rdev->dev, "limiting VRAM\n");
1187                 mc->real_vram_size = 0xE0000000;
1188                 mc->mc_vram_size = 0xE0000000;
1189         }
1190         if (rdev->flags & RADEON_IS_AGP) {
1191                 size_bf = mc->gtt_start;
1192                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1193                 if (size_bf > size_af) {
1194                         if (mc->mc_vram_size > size_bf) {
1195                                 dev_warn(rdev->dev, "limiting VRAM\n");
1196                                 mc->real_vram_size = size_bf;
1197                                 mc->mc_vram_size = size_bf;
1198                         }
1199                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1200                 } else {
1201                         if (mc->mc_vram_size > size_af) {
1202                                 dev_warn(rdev->dev, "limiting VRAM\n");
1203                                 mc->real_vram_size = size_af;
1204                                 mc->mc_vram_size = size_af;
1205                         }
1206                         mc->vram_start = mc->gtt_end;
1207                 }
1208                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1209                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1210                                 mc->mc_vram_size >> 20, mc->vram_start,
1211                                 mc->vram_end, mc->real_vram_size >> 20);
1212         } else {
1213                 u64 base = 0;
1214                 if (rdev->flags & RADEON_IS_IGP) {
1215                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1216                         base <<= 24;
1217                 }
1218                 radeon_vram_location(rdev, &rdev->mc, base);
1219                 rdev->mc.gtt_base_align = 0;
1220                 radeon_gtt_location(rdev, mc);
1221         }
1222 }
1223
1224 int r600_mc_init(struct radeon_device *rdev)
1225 {
1226         u32 tmp;
1227         int chansize, numchan;
1228
1229         /* Get VRAM informations */
1230         rdev->mc.vram_is_ddr = true;
1231         tmp = RREG32(RAMCFG);
1232         if (tmp & CHANSIZE_OVERRIDE) {
1233                 chansize = 16;
1234         } else if (tmp & CHANSIZE_MASK) {
1235                 chansize = 64;
1236         } else {
1237                 chansize = 32;
1238         }
1239         tmp = RREG32(CHMAP);
1240         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1241         case 0:
1242         default:
1243                 numchan = 1;
1244                 break;
1245         case 1:
1246                 numchan = 2;
1247                 break;
1248         case 2:
1249                 numchan = 4;
1250                 break;
1251         case 3:
1252                 numchan = 8;
1253                 break;
1254         }
1255         rdev->mc.vram_width = numchan * chansize;
1256         /* Could aper size report 0 ? */
1257         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1258         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1259         /* Setup GPU memory space */
1260         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1261         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1262         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1263         r600_vram_gtt_location(rdev, &rdev->mc);
1264
1265         if (rdev->flags & RADEON_IS_IGP) {
1266                 rs690_pm_info(rdev);
1267                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1268         }
1269         radeon_update_bandwidth_info(rdev);
1270         return 0;
1271 }
1272
1273 /* We doesn't check that the GPU really needs a reset we simply do the
1274  * reset, it's up to the caller to determine if the GPU needs one. We
1275  * might add an helper function to check that.
1276  */
1277 int r600_gpu_soft_reset(struct radeon_device *rdev)
1278 {
1279         struct rv515_mc_save save;
1280         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1281                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1282                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1283                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1284                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1285                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1286                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1287                                 S_008010_GUI_ACTIVE(1);
1288         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1289                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1290                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1291                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1292                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1293                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1294                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1295                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1296         u32 tmp;
1297
1298         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1299                 return 0;
1300
1301         dev_info(rdev->dev, "GPU softreset \n");
1302         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1303                 RREG32(R_008010_GRBM_STATUS));
1304         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1305                 RREG32(R_008014_GRBM_STATUS2));
1306         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1307                 RREG32(R_000E50_SRBM_STATUS));
1308         rv515_mc_stop(rdev, &save);
1309         if (r600_mc_wait_for_idle(rdev)) {
1310                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1311         }
1312         /* Disable CP parsing/prefetching */
1313         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1314         /* Check if any of the rendering block is busy and reset it */
1315         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1316             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1317                 tmp = S_008020_SOFT_RESET_CR(1) |
1318                         S_008020_SOFT_RESET_DB(1) |
1319                         S_008020_SOFT_RESET_CB(1) |
1320                         S_008020_SOFT_RESET_PA(1) |
1321                         S_008020_SOFT_RESET_SC(1) |
1322                         S_008020_SOFT_RESET_SMX(1) |
1323                         S_008020_SOFT_RESET_SPI(1) |
1324                         S_008020_SOFT_RESET_SX(1) |
1325                         S_008020_SOFT_RESET_SH(1) |
1326                         S_008020_SOFT_RESET_TC(1) |
1327                         S_008020_SOFT_RESET_TA(1) |
1328                         S_008020_SOFT_RESET_VC(1) |
1329                         S_008020_SOFT_RESET_VGT(1);
1330                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1331                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1332                 RREG32(R_008020_GRBM_SOFT_RESET);
1333                 mdelay(15);
1334                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1335         }
1336         /* Reset CP (we always reset CP) */
1337         tmp = S_008020_SOFT_RESET_CP(1);
1338         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1339         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1340         RREG32(R_008020_GRBM_SOFT_RESET);
1341         mdelay(15);
1342         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1343         /* Wait a little for things to settle down */
1344         mdelay(1);
1345         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1346                 RREG32(R_008010_GRBM_STATUS));
1347         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1348                 RREG32(R_008014_GRBM_STATUS2));
1349         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1350                 RREG32(R_000E50_SRBM_STATUS));
1351         rv515_mc_resume(rdev, &save);
1352         return 0;
1353 }
1354
1355 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1356 {
1357         u32 srbm_status;
1358         u32 grbm_status;
1359         u32 grbm_status2;
1360         struct r100_gpu_lockup *lockup;
1361         int r;
1362
1363         if (rdev->family >= CHIP_RV770)
1364                 lockup = &rdev->config.rv770.lockup;
1365         else
1366                 lockup = &rdev->config.r600.lockup;
1367
1368         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1369         grbm_status = RREG32(R_008010_GRBM_STATUS);
1370         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1371         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1372                 r100_gpu_lockup_update(lockup, &rdev->cp);
1373                 return false;
1374         }
1375         /* force CP activities */
1376         r = radeon_ring_lock(rdev, 2);
1377         if (!r) {
1378                 /* PACKET2 NOP */
1379                 radeon_ring_write(rdev, 0x80000000);
1380                 radeon_ring_write(rdev, 0x80000000);
1381                 radeon_ring_unlock_commit(rdev);
1382         }
1383         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1384         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1385 }
1386
1387 int r600_asic_reset(struct radeon_device *rdev)
1388 {
1389         return r600_gpu_soft_reset(rdev);
1390 }
1391
1392 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1393                                              u32 num_backends,
1394                                              u32 backend_disable_mask)
1395 {
1396         u32 backend_map = 0;
1397         u32 enabled_backends_mask;
1398         u32 enabled_backends_count;
1399         u32 cur_pipe;
1400         u32 swizzle_pipe[R6XX_MAX_PIPES];
1401         u32 cur_backend;
1402         u32 i;
1403
1404         if (num_tile_pipes > R6XX_MAX_PIPES)
1405                 num_tile_pipes = R6XX_MAX_PIPES;
1406         if (num_tile_pipes < 1)
1407                 num_tile_pipes = 1;
1408         if (num_backends > R6XX_MAX_BACKENDS)
1409                 num_backends = R6XX_MAX_BACKENDS;
1410         if (num_backends < 1)
1411                 num_backends = 1;
1412
1413         enabled_backends_mask = 0;
1414         enabled_backends_count = 0;
1415         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1416                 if (((backend_disable_mask >> i) & 1) == 0) {
1417                         enabled_backends_mask |= (1 << i);
1418                         ++enabled_backends_count;
1419                 }
1420                 if (enabled_backends_count == num_backends)
1421                         break;
1422         }
1423
1424         if (enabled_backends_count == 0) {
1425                 enabled_backends_mask = 1;
1426                 enabled_backends_count = 1;
1427         }
1428
1429         if (enabled_backends_count != num_backends)
1430                 num_backends = enabled_backends_count;
1431
1432         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1433         switch (num_tile_pipes) {
1434         case 1:
1435                 swizzle_pipe[0] = 0;
1436                 break;
1437         case 2:
1438                 swizzle_pipe[0] = 0;
1439                 swizzle_pipe[1] = 1;
1440                 break;
1441         case 3:
1442                 swizzle_pipe[0] = 0;
1443                 swizzle_pipe[1] = 1;
1444                 swizzle_pipe[2] = 2;
1445                 break;
1446         case 4:
1447                 swizzle_pipe[0] = 0;
1448                 swizzle_pipe[1] = 1;
1449                 swizzle_pipe[2] = 2;
1450                 swizzle_pipe[3] = 3;
1451                 break;
1452         case 5:
1453                 swizzle_pipe[0] = 0;
1454                 swizzle_pipe[1] = 1;
1455                 swizzle_pipe[2] = 2;
1456                 swizzle_pipe[3] = 3;
1457                 swizzle_pipe[4] = 4;
1458                 break;
1459         case 6:
1460                 swizzle_pipe[0] = 0;
1461                 swizzle_pipe[1] = 2;
1462                 swizzle_pipe[2] = 4;
1463                 swizzle_pipe[3] = 5;
1464                 swizzle_pipe[4] = 1;
1465                 swizzle_pipe[5] = 3;
1466                 break;
1467         case 7:
1468                 swizzle_pipe[0] = 0;
1469                 swizzle_pipe[1] = 2;
1470                 swizzle_pipe[2] = 4;
1471                 swizzle_pipe[3] = 6;
1472                 swizzle_pipe[4] = 1;
1473                 swizzle_pipe[5] = 3;
1474                 swizzle_pipe[6] = 5;
1475                 break;
1476         case 8:
1477                 swizzle_pipe[0] = 0;
1478                 swizzle_pipe[1] = 2;
1479                 swizzle_pipe[2] = 4;
1480                 swizzle_pipe[3] = 6;
1481                 swizzle_pipe[4] = 1;
1482                 swizzle_pipe[5] = 3;
1483                 swizzle_pipe[6] = 5;
1484                 swizzle_pipe[7] = 7;
1485                 break;
1486         }
1487
1488         cur_backend = 0;
1489         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1490                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1491                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1492
1493                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1494
1495                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1496         }
1497
1498         return backend_map;
1499 }
1500
1501 int r600_count_pipe_bits(uint32_t val)
1502 {
1503         int i, ret = 0;
1504
1505         for (i = 0; i < 32; i++) {
1506                 ret += val & 1;
1507                 val >>= 1;
1508         }
1509         return ret;
1510 }
1511
1512 void r600_gpu_init(struct radeon_device *rdev)
1513 {
1514         u32 tiling_config;
1515         u32 ramcfg;
1516         u32 backend_map;
1517         u32 cc_rb_backend_disable;
1518         u32 cc_gc_shader_pipe_config;
1519         u32 tmp;
1520         int i, j;
1521         u32 sq_config;
1522         u32 sq_gpr_resource_mgmt_1 = 0;
1523         u32 sq_gpr_resource_mgmt_2 = 0;
1524         u32 sq_thread_resource_mgmt = 0;
1525         u32 sq_stack_resource_mgmt_1 = 0;
1526         u32 sq_stack_resource_mgmt_2 = 0;
1527
1528         /* FIXME: implement */
1529         switch (rdev->family) {
1530         case CHIP_R600:
1531                 rdev->config.r600.max_pipes = 4;
1532                 rdev->config.r600.max_tile_pipes = 8;
1533                 rdev->config.r600.max_simds = 4;
1534                 rdev->config.r600.max_backends = 4;
1535                 rdev->config.r600.max_gprs = 256;
1536                 rdev->config.r600.max_threads = 192;
1537                 rdev->config.r600.max_stack_entries = 256;
1538                 rdev->config.r600.max_hw_contexts = 8;
1539                 rdev->config.r600.max_gs_threads = 16;
1540                 rdev->config.r600.sx_max_export_size = 128;
1541                 rdev->config.r600.sx_max_export_pos_size = 16;
1542                 rdev->config.r600.sx_max_export_smx_size = 128;
1543                 rdev->config.r600.sq_num_cf_insts = 2;
1544                 break;
1545         case CHIP_RV630:
1546         case CHIP_RV635:
1547                 rdev->config.r600.max_pipes = 2;
1548                 rdev->config.r600.max_tile_pipes = 2;
1549                 rdev->config.r600.max_simds = 3;
1550                 rdev->config.r600.max_backends = 1;
1551                 rdev->config.r600.max_gprs = 128;
1552                 rdev->config.r600.max_threads = 192;
1553                 rdev->config.r600.max_stack_entries = 128;
1554                 rdev->config.r600.max_hw_contexts = 8;
1555                 rdev->config.r600.max_gs_threads = 4;
1556                 rdev->config.r600.sx_max_export_size = 128;
1557                 rdev->config.r600.sx_max_export_pos_size = 16;
1558                 rdev->config.r600.sx_max_export_smx_size = 128;
1559                 rdev->config.r600.sq_num_cf_insts = 2;
1560                 break;
1561         case CHIP_RV610:
1562         case CHIP_RV620:
1563         case CHIP_RS780:
1564         case CHIP_RS880:
1565                 rdev->config.r600.max_pipes = 1;
1566                 rdev->config.r600.max_tile_pipes = 1;
1567                 rdev->config.r600.max_simds = 2;
1568                 rdev->config.r600.max_backends = 1;
1569                 rdev->config.r600.max_gprs = 128;
1570                 rdev->config.r600.max_threads = 192;
1571                 rdev->config.r600.max_stack_entries = 128;
1572                 rdev->config.r600.max_hw_contexts = 4;
1573                 rdev->config.r600.max_gs_threads = 4;
1574                 rdev->config.r600.sx_max_export_size = 128;
1575                 rdev->config.r600.sx_max_export_pos_size = 16;
1576                 rdev->config.r600.sx_max_export_smx_size = 128;
1577                 rdev->config.r600.sq_num_cf_insts = 1;
1578                 break;
1579         case CHIP_RV670:
1580                 rdev->config.r600.max_pipes = 4;
1581                 rdev->config.r600.max_tile_pipes = 4;
1582                 rdev->config.r600.max_simds = 4;
1583                 rdev->config.r600.max_backends = 4;
1584                 rdev->config.r600.max_gprs = 192;
1585                 rdev->config.r600.max_threads = 192;
1586                 rdev->config.r600.max_stack_entries = 256;
1587                 rdev->config.r600.max_hw_contexts = 8;
1588                 rdev->config.r600.max_gs_threads = 16;
1589                 rdev->config.r600.sx_max_export_size = 128;
1590                 rdev->config.r600.sx_max_export_pos_size = 16;
1591                 rdev->config.r600.sx_max_export_smx_size = 128;
1592                 rdev->config.r600.sq_num_cf_insts = 2;
1593                 break;
1594         default:
1595                 break;
1596         }
1597
1598         /* Initialize HDP */
1599         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1600                 WREG32((0x2c14 + j), 0x00000000);
1601                 WREG32((0x2c18 + j), 0x00000000);
1602                 WREG32((0x2c1c + j), 0x00000000);
1603                 WREG32((0x2c20 + j), 0x00000000);
1604                 WREG32((0x2c24 + j), 0x00000000);
1605         }
1606
1607         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1608
1609         /* Setup tiling */
1610         tiling_config = 0;
1611         ramcfg = RREG32(RAMCFG);
1612         switch (rdev->config.r600.max_tile_pipes) {
1613         case 1:
1614                 tiling_config |= PIPE_TILING(0);
1615                 break;
1616         case 2:
1617                 tiling_config |= PIPE_TILING(1);
1618                 break;
1619         case 4:
1620                 tiling_config |= PIPE_TILING(2);
1621                 break;
1622         case 8:
1623                 tiling_config |= PIPE_TILING(3);
1624                 break;
1625         default:
1626                 break;
1627         }
1628         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1629         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1630         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1631         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1632         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1633                 rdev->config.r600.tiling_group_size = 512;
1634         else
1635                 rdev->config.r600.tiling_group_size = 256;
1636         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1637         if (tmp > 3) {
1638                 tiling_config |= ROW_TILING(3);
1639                 tiling_config |= SAMPLE_SPLIT(3);
1640         } else {
1641                 tiling_config |= ROW_TILING(tmp);
1642                 tiling_config |= SAMPLE_SPLIT(tmp);
1643         }
1644         tiling_config |= BANK_SWAPS(1);
1645
1646         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1647         cc_rb_backend_disable |=
1648                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1649
1650         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1651         cc_gc_shader_pipe_config |=
1652                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1653         cc_gc_shader_pipe_config |=
1654                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1655
1656         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1657                                                         (R6XX_MAX_BACKENDS -
1658                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1659                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1660                                                         (cc_rb_backend_disable >> 16));
1661         rdev->config.r600.tile_config = tiling_config;
1662         tiling_config |= BACKEND_MAP(backend_map);
1663         WREG32(GB_TILING_CONFIG, tiling_config);
1664         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1665         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1666
1667         /* Setup pipes */
1668         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1669         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1670         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1671
1672         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1673         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1674         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1675
1676         /* Setup some CP states */
1677         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1678         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1679
1680         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1681                              SYNC_WALKER | SYNC_ALIGNER));
1682         /* Setup various GPU states */
1683         if (rdev->family == CHIP_RV670)
1684                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1685
1686         tmp = RREG32(SX_DEBUG_1);
1687         tmp |= SMX_EVENT_RELEASE;
1688         if ((rdev->family > CHIP_R600))
1689                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1690         WREG32(SX_DEBUG_1, tmp);
1691
1692         if (((rdev->family) == CHIP_R600) ||
1693             ((rdev->family) == CHIP_RV630) ||
1694             ((rdev->family) == CHIP_RV610) ||
1695             ((rdev->family) == CHIP_RV620) ||
1696             ((rdev->family) == CHIP_RS780) ||
1697             ((rdev->family) == CHIP_RS880)) {
1698                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1699         } else {
1700                 WREG32(DB_DEBUG, 0);
1701         }
1702         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1703                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1704
1705         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1706         WREG32(VGT_NUM_INSTANCES, 0);
1707
1708         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1709         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1710
1711         tmp = RREG32(SQ_MS_FIFO_SIZES);
1712         if (((rdev->family) == CHIP_RV610) ||
1713             ((rdev->family) == CHIP_RV620) ||
1714             ((rdev->family) == CHIP_RS780) ||
1715             ((rdev->family) == CHIP_RS880)) {
1716                 tmp = (CACHE_FIFO_SIZE(0xa) |
1717                        FETCH_FIFO_HIWATER(0xa) |
1718                        DONE_FIFO_HIWATER(0xe0) |
1719                        ALU_UPDATE_FIFO_HIWATER(0x8));
1720         } else if (((rdev->family) == CHIP_R600) ||
1721                    ((rdev->family) == CHIP_RV630)) {
1722                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1723                 tmp |= DONE_FIFO_HIWATER(0x4);
1724         }
1725         WREG32(SQ_MS_FIFO_SIZES, tmp);
1726
1727         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1728          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1729          */
1730         sq_config = RREG32(SQ_CONFIG);
1731         sq_config &= ~(PS_PRIO(3) |
1732                        VS_PRIO(3) |
1733                        GS_PRIO(3) |
1734                        ES_PRIO(3));
1735         sq_config |= (DX9_CONSTS |
1736                       VC_ENABLE |
1737                       PS_PRIO(0) |
1738                       VS_PRIO(1) |
1739                       GS_PRIO(2) |
1740                       ES_PRIO(3));
1741
1742         if ((rdev->family) == CHIP_R600) {
1743                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1744                                           NUM_VS_GPRS(124) |
1745                                           NUM_CLAUSE_TEMP_GPRS(4));
1746                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1747                                           NUM_ES_GPRS(0));
1748                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1749                                            NUM_VS_THREADS(48) |
1750                                            NUM_GS_THREADS(4) |
1751                                            NUM_ES_THREADS(4));
1752                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1753                                             NUM_VS_STACK_ENTRIES(128));
1754                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1755                                             NUM_ES_STACK_ENTRIES(0));
1756         } else if (((rdev->family) == CHIP_RV610) ||
1757                    ((rdev->family) == CHIP_RV620) ||
1758                    ((rdev->family) == CHIP_RS780) ||
1759                    ((rdev->family) == CHIP_RS880)) {
1760                 /* no vertex cache */
1761                 sq_config &= ~VC_ENABLE;
1762
1763                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1764                                           NUM_VS_GPRS(44) |
1765                                           NUM_CLAUSE_TEMP_GPRS(2));
1766                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1767                                           NUM_ES_GPRS(17));
1768                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1769                                            NUM_VS_THREADS(78) |
1770                                            NUM_GS_THREADS(4) |
1771                                            NUM_ES_THREADS(31));
1772                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1773                                             NUM_VS_STACK_ENTRIES(40));
1774                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1775                                             NUM_ES_STACK_ENTRIES(16));
1776         } else if (((rdev->family) == CHIP_RV630) ||
1777                    ((rdev->family) == CHIP_RV635)) {
1778                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1779                                           NUM_VS_GPRS(44) |
1780                                           NUM_CLAUSE_TEMP_GPRS(2));
1781                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1782                                           NUM_ES_GPRS(18));
1783                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1784                                            NUM_VS_THREADS(78) |
1785                                            NUM_GS_THREADS(4) |
1786                                            NUM_ES_THREADS(31));
1787                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1788                                             NUM_VS_STACK_ENTRIES(40));
1789                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1790                                             NUM_ES_STACK_ENTRIES(16));
1791         } else if ((rdev->family) == CHIP_RV670) {
1792                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1793                                           NUM_VS_GPRS(44) |
1794                                           NUM_CLAUSE_TEMP_GPRS(2));
1795                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1796                                           NUM_ES_GPRS(17));
1797                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1798                                            NUM_VS_THREADS(78) |
1799                                            NUM_GS_THREADS(4) |
1800                                            NUM_ES_THREADS(31));
1801                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1802                                             NUM_VS_STACK_ENTRIES(64));
1803                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1804                                             NUM_ES_STACK_ENTRIES(64));
1805         }
1806
1807         WREG32(SQ_CONFIG, sq_config);
1808         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1809         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1810         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1811         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1812         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1813
1814         if (((rdev->family) == CHIP_RV610) ||
1815             ((rdev->family) == CHIP_RV620) ||
1816             ((rdev->family) == CHIP_RS780) ||
1817             ((rdev->family) == CHIP_RS880)) {
1818                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1819         } else {
1820                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1821         }
1822
1823         /* More default values. 2D/3D driver should adjust as needed */
1824         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1825                                          S1_X(0x4) | S1_Y(0xc)));
1826         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1827                                          S1_X(0x2) | S1_Y(0x2) |
1828                                          S2_X(0xa) | S2_Y(0x6) |
1829                                          S3_X(0x6) | S3_Y(0xa)));
1830         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1831                                              S1_X(0x4) | S1_Y(0xc) |
1832                                              S2_X(0x1) | S2_Y(0x6) |
1833                                              S3_X(0xa) | S3_Y(0xe)));
1834         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1835                                              S5_X(0x0) | S5_Y(0x0) |
1836                                              S6_X(0xb) | S6_Y(0x4) |
1837                                              S7_X(0x7) | S7_Y(0x8)));
1838
1839         WREG32(VGT_STRMOUT_EN, 0);
1840         tmp = rdev->config.r600.max_pipes * 16;
1841         switch (rdev->family) {
1842         case CHIP_RV610:
1843         case CHIP_RV620:
1844         case CHIP_RS780:
1845         case CHIP_RS880:
1846                 tmp += 32;
1847                 break;
1848         case CHIP_RV670:
1849                 tmp += 128;
1850                 break;
1851         default:
1852                 break;
1853         }
1854         if (tmp > 256) {
1855                 tmp = 256;
1856         }
1857         WREG32(VGT_ES_PER_GS, 128);
1858         WREG32(VGT_GS_PER_ES, tmp);
1859         WREG32(VGT_GS_PER_VS, 2);
1860         WREG32(VGT_GS_VERTEX_REUSE, 16);
1861
1862         /* more default values. 2D/3D driver should adjust as needed */
1863         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1864         WREG32(VGT_STRMOUT_EN, 0);
1865         WREG32(SX_MISC, 0);
1866         WREG32(PA_SC_MODE_CNTL, 0);
1867         WREG32(PA_SC_AA_CONFIG, 0);
1868         WREG32(PA_SC_LINE_STIPPLE, 0);
1869         WREG32(SPI_INPUT_Z, 0);
1870         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1871         WREG32(CB_COLOR7_FRAG, 0);
1872
1873         /* Clear render buffer base addresses */
1874         WREG32(CB_COLOR0_BASE, 0);
1875         WREG32(CB_COLOR1_BASE, 0);
1876         WREG32(CB_COLOR2_BASE, 0);
1877         WREG32(CB_COLOR3_BASE, 0);
1878         WREG32(CB_COLOR4_BASE, 0);
1879         WREG32(CB_COLOR5_BASE, 0);
1880         WREG32(CB_COLOR6_BASE, 0);
1881         WREG32(CB_COLOR7_BASE, 0);
1882         WREG32(CB_COLOR7_FRAG, 0);
1883
1884         switch (rdev->family) {
1885         case CHIP_RV610:
1886         case CHIP_RV620:
1887         case CHIP_RS780:
1888         case CHIP_RS880:
1889                 tmp = TC_L2_SIZE(8);
1890                 break;
1891         case CHIP_RV630:
1892         case CHIP_RV635:
1893                 tmp = TC_L2_SIZE(4);
1894                 break;
1895         case CHIP_R600:
1896                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1897                 break;
1898         default:
1899                 tmp = TC_L2_SIZE(0);
1900                 break;
1901         }
1902         WREG32(TC_CNTL, tmp);
1903
1904         tmp = RREG32(HDP_HOST_PATH_CNTL);
1905         WREG32(HDP_HOST_PATH_CNTL, tmp);
1906
1907         tmp = RREG32(ARB_POP);
1908         tmp |= ENABLE_TC128;
1909         WREG32(ARB_POP, tmp);
1910
1911         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1912         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1913                                NUM_CLIP_SEQ(3)));
1914         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1915 }
1916
1917
1918 /*
1919  * Indirect registers accessor
1920  */
1921 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1922 {
1923         u32 r;
1924
1925         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1926         (void)RREG32(PCIE_PORT_INDEX);
1927         r = RREG32(PCIE_PORT_DATA);
1928         return r;
1929 }
1930
1931 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1932 {
1933         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1934         (void)RREG32(PCIE_PORT_INDEX);
1935         WREG32(PCIE_PORT_DATA, (v));
1936         (void)RREG32(PCIE_PORT_DATA);
1937 }
1938
1939 /*
1940  * CP & Ring
1941  */
1942 void r600_cp_stop(struct radeon_device *rdev)
1943 {
1944         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1945         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1946         WREG32(SCRATCH_UMSK, 0);
1947 }
1948
1949 int r600_init_microcode(struct radeon_device *rdev)
1950 {
1951         struct platform_device *pdev;
1952         const char *chip_name;
1953         const char *rlc_chip_name;
1954         size_t pfp_req_size, me_req_size, rlc_req_size;
1955         char fw_name[30];
1956         int err;
1957
1958         DRM_DEBUG("\n");
1959
1960         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1961         err = IS_ERR(pdev);
1962         if (err) {
1963                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1964                 return -EINVAL;
1965         }
1966
1967         switch (rdev->family) {
1968         case CHIP_R600:
1969                 chip_name = "R600";
1970                 rlc_chip_name = "R600";
1971                 break;
1972         case CHIP_RV610:
1973                 chip_name = "RV610";
1974                 rlc_chip_name = "R600";
1975                 break;
1976         case CHIP_RV630:
1977                 chip_name = "RV630";
1978                 rlc_chip_name = "R600";
1979                 break;
1980         case CHIP_RV620:
1981                 chip_name = "RV620";
1982                 rlc_chip_name = "R600";
1983                 break;
1984         case CHIP_RV635:
1985                 chip_name = "RV635";
1986                 rlc_chip_name = "R600";
1987                 break;
1988         case CHIP_RV670:
1989                 chip_name = "RV670";
1990                 rlc_chip_name = "R600";
1991                 break;
1992         case CHIP_RS780:
1993         case CHIP_RS880:
1994                 chip_name = "RS780";
1995                 rlc_chip_name = "R600";
1996                 break;
1997         case CHIP_RV770:
1998                 chip_name = "RV770";
1999                 rlc_chip_name = "R700";
2000                 break;
2001         case CHIP_RV730:
2002         case CHIP_RV740:
2003                 chip_name = "RV730";
2004                 rlc_chip_name = "R700";
2005                 break;
2006         case CHIP_RV710:
2007                 chip_name = "RV710";
2008                 rlc_chip_name = "R700";
2009                 break;
2010         case CHIP_CEDAR:
2011                 chip_name = "CEDAR";
2012                 rlc_chip_name = "CEDAR";
2013                 break;
2014         case CHIP_REDWOOD:
2015                 chip_name = "REDWOOD";
2016                 rlc_chip_name = "REDWOOD";
2017                 break;
2018         case CHIP_JUNIPER:
2019                 chip_name = "JUNIPER";
2020                 rlc_chip_name = "JUNIPER";
2021                 break;
2022         case CHIP_CYPRESS:
2023         case CHIP_HEMLOCK:
2024                 chip_name = "CYPRESS";
2025                 rlc_chip_name = "CYPRESS";
2026                 break;
2027         case CHIP_PALM:
2028                 chip_name = "PALM";
2029                 rlc_chip_name = "SUMO";
2030                 break;
2031         case CHIP_SUMO:
2032                 chip_name = "SUMO";
2033                 rlc_chip_name = "SUMO";
2034                 break;
2035         case CHIP_SUMO2:
2036                 chip_name = "SUMO2";
2037                 rlc_chip_name = "SUMO";
2038                 break;
2039         default: BUG();
2040         }
2041
2042         if (rdev->family >= CHIP_CEDAR) {
2043                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2044                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2045                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2046         } else if (rdev->family >= CHIP_RV770) {
2047                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2048                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2049                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2050         } else {
2051                 pfp_req_size = PFP_UCODE_SIZE * 4;
2052                 me_req_size = PM4_UCODE_SIZE * 12;
2053                 rlc_req_size = RLC_UCODE_SIZE * 4;
2054         }
2055
2056         DRM_INFO("Loading %s Microcode\n", chip_name);
2057
2058         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2059         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2060         if (err)
2061                 goto out;
2062         if (rdev->pfp_fw->size != pfp_req_size) {
2063                 printk(KERN_ERR
2064                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2065                        rdev->pfp_fw->size, fw_name);
2066                 err = -EINVAL;
2067                 goto out;
2068         }
2069
2070         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2071         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2072         if (err)
2073                 goto out;
2074         if (rdev->me_fw->size != me_req_size) {
2075                 printk(KERN_ERR
2076                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2077                        rdev->me_fw->size, fw_name);
2078                 err = -EINVAL;
2079         }
2080
2081         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2082         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2083         if (err)
2084                 goto out;
2085         if (rdev->rlc_fw->size != rlc_req_size) {
2086                 printk(KERN_ERR
2087                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2088                        rdev->rlc_fw->size, fw_name);
2089                 err = -EINVAL;
2090         }
2091
2092 out:
2093         platform_device_unregister(pdev);
2094
2095         if (err) {
2096                 if (err != -EINVAL)
2097                         printk(KERN_ERR
2098                                "r600_cp: Failed to load firmware \"%s\"\n",
2099                                fw_name);
2100                 release_firmware(rdev->pfp_fw);
2101                 rdev->pfp_fw = NULL;
2102                 release_firmware(rdev->me_fw);
2103                 rdev->me_fw = NULL;
2104                 release_firmware(rdev->rlc_fw);
2105                 rdev->rlc_fw = NULL;
2106         }
2107         return err;
2108 }
2109
2110 static int r600_cp_load_microcode(struct radeon_device *rdev)
2111 {
2112         const __be32 *fw_data;
2113         int i;
2114
2115         if (!rdev->me_fw || !rdev->pfp_fw)
2116                 return -EINVAL;
2117
2118         r600_cp_stop(rdev);
2119
2120         WREG32(CP_RB_CNTL,
2121 #ifdef __BIG_ENDIAN
2122                BUF_SWAP_32BIT |
2123 #endif
2124                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2125
2126         /* Reset cp */
2127         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2128         RREG32(GRBM_SOFT_RESET);
2129         mdelay(15);
2130         WREG32(GRBM_SOFT_RESET, 0);
2131
2132         WREG32(CP_ME_RAM_WADDR, 0);
2133
2134         fw_data = (const __be32 *)rdev->me_fw->data;
2135         WREG32(CP_ME_RAM_WADDR, 0);
2136         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2137                 WREG32(CP_ME_RAM_DATA,
2138                        be32_to_cpup(fw_data++));
2139
2140         fw_data = (const __be32 *)rdev->pfp_fw->data;
2141         WREG32(CP_PFP_UCODE_ADDR, 0);
2142         for (i = 0; i < PFP_UCODE_SIZE; i++)
2143                 WREG32(CP_PFP_UCODE_DATA,
2144                        be32_to_cpup(fw_data++));
2145
2146         WREG32(CP_PFP_UCODE_ADDR, 0);
2147         WREG32(CP_ME_RAM_WADDR, 0);
2148         WREG32(CP_ME_RAM_RADDR, 0);
2149         return 0;
2150 }
2151
2152 int r600_cp_start(struct radeon_device *rdev)
2153 {
2154         int r;
2155         uint32_t cp_me;
2156
2157         r = radeon_ring_lock(rdev, 7);
2158         if (r) {
2159                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2160                 return r;
2161         }
2162         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2163         radeon_ring_write(rdev, 0x1);
2164         if (rdev->family >= CHIP_RV770) {
2165                 radeon_ring_write(rdev, 0x0);
2166                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2167         } else {
2168                 radeon_ring_write(rdev, 0x3);
2169                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2170         }
2171         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2172         radeon_ring_write(rdev, 0);
2173         radeon_ring_write(rdev, 0);
2174         radeon_ring_unlock_commit(rdev);
2175
2176         cp_me = 0xff;
2177         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2178         return 0;
2179 }
2180
2181 int r600_cp_resume(struct radeon_device *rdev)
2182 {
2183         u32 tmp;
2184         u32 rb_bufsz;
2185         int r;
2186
2187         /* Reset cp */
2188         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2189         RREG32(GRBM_SOFT_RESET);
2190         mdelay(15);
2191         WREG32(GRBM_SOFT_RESET, 0);
2192
2193         /* Set ring buffer size */
2194         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2195         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2196 #ifdef __BIG_ENDIAN
2197         tmp |= BUF_SWAP_32BIT;
2198 #endif
2199         WREG32(CP_RB_CNTL, tmp);
2200         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2201
2202         /* Set the write pointer delay */
2203         WREG32(CP_RB_WPTR_DELAY, 0);
2204
2205         /* Initialize the ring buffer's read and write pointers */
2206         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2207         WREG32(CP_RB_RPTR_WR, 0);
2208         WREG32(CP_RB_WPTR, 0);
2209
2210         /* set the wb address whether it's enabled or not */
2211         WREG32(CP_RB_RPTR_ADDR,
2212 #ifdef __BIG_ENDIAN
2213                RB_RPTR_SWAP(2) |
2214 #endif
2215                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2216         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2217         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2218
2219         if (rdev->wb.enabled)
2220                 WREG32(SCRATCH_UMSK, 0xff);
2221         else {
2222                 tmp |= RB_NO_UPDATE;
2223                 WREG32(SCRATCH_UMSK, 0);
2224         }
2225
2226         mdelay(1);
2227         WREG32(CP_RB_CNTL, tmp);
2228
2229         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2230         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2231
2232         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2233         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2234
2235         r600_cp_start(rdev);
2236         rdev->cp.ready = true;
2237         r = radeon_ring_test(rdev);
2238         if (r) {
2239                 rdev->cp.ready = false;
2240                 return r;
2241         }
2242         return 0;
2243 }
2244
2245 void r600_cp_commit(struct radeon_device *rdev)
2246 {
2247         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2248         (void)RREG32(CP_RB_WPTR);
2249 }
2250
2251 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2252 {
2253         u32 rb_bufsz;
2254
2255         /* Align ring size */
2256         rb_bufsz = drm_order(ring_size / 8);
2257         ring_size = (1 << (rb_bufsz + 1)) * 4;
2258         rdev->cp.ring_size = ring_size;
2259         rdev->cp.align_mask = 16 - 1;
2260 }
2261
2262 void r600_cp_fini(struct radeon_device *rdev)
2263 {
2264         r600_cp_stop(rdev);
2265         radeon_ring_fini(rdev);
2266 }
2267
2268
2269 /*
2270  * GPU scratch registers helpers function.
2271  */
2272 void r600_scratch_init(struct radeon_device *rdev)
2273 {
2274         int i;
2275
2276         rdev->scratch.num_reg = 7;
2277         rdev->scratch.reg_base = SCRATCH_REG0;
2278         for (i = 0; i < rdev->scratch.num_reg; i++) {
2279                 rdev->scratch.free[i] = true;
2280                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2281         }
2282 }
2283
2284 int r600_ring_test(struct radeon_device *rdev)
2285 {
2286         uint32_t scratch;
2287         uint32_t tmp = 0;
2288         unsigned i;
2289         int r;
2290
2291         r = radeon_scratch_get(rdev, &scratch);
2292         if (r) {
2293                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2294                 return r;
2295         }
2296         WREG32(scratch, 0xCAFEDEAD);
2297         r = radeon_ring_lock(rdev, 3);
2298         if (r) {
2299                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2300                 radeon_scratch_free(rdev, scratch);
2301                 return r;
2302         }
2303         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2304         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2305         radeon_ring_write(rdev, 0xDEADBEEF);
2306         radeon_ring_unlock_commit(rdev);
2307         for (i = 0; i < rdev->usec_timeout; i++) {
2308                 tmp = RREG32(scratch);
2309                 if (tmp == 0xDEADBEEF)
2310                         break;
2311                 DRM_UDELAY(1);
2312         }
2313         if (i < rdev->usec_timeout) {
2314                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2315         } else {
2316                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2317                           scratch, tmp);
2318                 r = -EINVAL;
2319         }
2320         radeon_scratch_free(rdev, scratch);
2321         return r;
2322 }
2323
2324 void r600_fence_ring_emit(struct radeon_device *rdev,
2325                           struct radeon_fence *fence)
2326 {
2327         if (rdev->wb.use_event) {
2328                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2329                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2330                 /* EVENT_WRITE_EOP - flush caches, send int */
2331                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2332                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2333                 radeon_ring_write(rdev, addr & 0xffffffff);
2334                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2335                 radeon_ring_write(rdev, fence->seq);
2336                 radeon_ring_write(rdev, 0);
2337         } else {
2338                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2339                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2340                 /* wait for 3D idle clean */
2341                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2342                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2343                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2344                 /* Emit fence sequence & fire IRQ */
2345                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2346                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2347                 radeon_ring_write(rdev, fence->seq);
2348                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2349                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2350                 radeon_ring_write(rdev, RB_INT_STAT);
2351         }
2352 }
2353
2354 int r600_copy_blit(struct radeon_device *rdev,
2355                    uint64_t src_offset, uint64_t dst_offset,
2356                    unsigned num_pages, struct radeon_fence *fence)
2357 {
2358         int r;
2359
2360         mutex_lock(&rdev->r600_blit.mutex);
2361         rdev->r600_blit.vb_ib = NULL;
2362         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2363         if (r) {
2364                 if (rdev->r600_blit.vb_ib)
2365                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2366                 mutex_unlock(&rdev->r600_blit.mutex);
2367                 return r;
2368         }
2369         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2370         r600_blit_done_copy(rdev, fence);
2371         mutex_unlock(&rdev->r600_blit.mutex);
2372         return 0;
2373 }
2374
2375 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2376                          uint32_t tiling_flags, uint32_t pitch,
2377                          uint32_t offset, uint32_t obj_size)
2378 {
2379         /* FIXME: implement */
2380         return 0;
2381 }
2382
2383 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2384 {
2385         /* FIXME: implement */
2386 }
2387
2388 int r600_startup(struct radeon_device *rdev)
2389 {
2390         int r;
2391
2392         /* enable pcie gen2 link */
2393         r600_pcie_gen2_enable(rdev);
2394
2395         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2396                 r = r600_init_microcode(rdev);
2397                 if (r) {
2398                         DRM_ERROR("Failed to load firmware!\n");
2399                         return r;
2400                 }
2401         }
2402
2403         r600_mc_program(rdev);
2404         if (rdev->flags & RADEON_IS_AGP) {
2405                 r600_agp_enable(rdev);
2406         } else {
2407                 r = r600_pcie_gart_enable(rdev);
2408                 if (r)
2409                         return r;
2410         }
2411         r600_gpu_init(rdev);
2412         r = r600_blit_init(rdev);
2413         if (r) {
2414                 r600_blit_fini(rdev);
2415                 rdev->asic->copy = NULL;
2416                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2417         }
2418
2419         /* allocate wb buffer */
2420         r = radeon_wb_init(rdev);
2421         if (r)
2422                 return r;
2423
2424         /* Enable IRQ */
2425         r = r600_irq_init(rdev);
2426         if (r) {
2427                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2428                 radeon_irq_kms_fini(rdev);
2429                 return r;
2430         }
2431         r600_irq_set(rdev);
2432
2433         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2434         if (r)
2435                 return r;
2436         r = r600_cp_load_microcode(rdev);
2437         if (r)
2438                 return r;
2439         r = r600_cp_resume(rdev);
2440         if (r)
2441                 return r;
2442
2443         return 0;
2444 }
2445
2446 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2447 {
2448         uint32_t temp;
2449
2450         temp = RREG32(CONFIG_CNTL);
2451         if (state == false) {
2452                 temp &= ~(1<<0);
2453                 temp |= (1<<1);
2454         } else {
2455                 temp &= ~(1<<1);
2456         }
2457         WREG32(CONFIG_CNTL, temp);
2458 }
2459
2460 int r600_resume(struct radeon_device *rdev)
2461 {
2462         int r;
2463
2464         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2465          * posting will perform necessary task to bring back GPU into good
2466          * shape.
2467          */
2468         /* post card */
2469         atom_asic_init(rdev->mode_info.atom_context);
2470
2471         r = r600_startup(rdev);
2472         if (r) {
2473                 DRM_ERROR("r600 startup failed on resume\n");
2474                 return r;
2475         }
2476
2477         r = r600_ib_test(rdev);
2478         if (r) {
2479                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2480                 return r;
2481         }
2482
2483         r = r600_audio_init(rdev);
2484         if (r) {
2485                 DRM_ERROR("radeon: audio resume failed\n");
2486                 return r;
2487         }
2488
2489         return r;
2490 }
2491
2492 int r600_suspend(struct radeon_device *rdev)
2493 {
2494         int r;
2495
2496         r600_audio_fini(rdev);
2497         /* FIXME: we should wait for ring to be empty */
2498         r600_cp_stop(rdev);
2499         rdev->cp.ready = false;
2500         r600_irq_suspend(rdev);
2501         radeon_wb_disable(rdev);
2502         r600_pcie_gart_disable(rdev);
2503         /* unpin shaders bo */
2504         if (rdev->r600_blit.shader_obj) {
2505                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2506                 if (!r) {
2507                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2508                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2509                 }
2510         }
2511         return 0;
2512 }
2513
2514 /* Plan is to move initialization in that function and use
2515  * helper function so that radeon_device_init pretty much
2516  * do nothing more than calling asic specific function. This
2517  * should also allow to remove a bunch of callback function
2518  * like vram_info.
2519  */
2520 int r600_init(struct radeon_device *rdev)
2521 {
2522         int r;
2523
2524         if (r600_debugfs_mc_info_init(rdev)) {
2525                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2526         }
2527         /* This don't do much */
2528         r = radeon_gem_init(rdev);
2529         if (r)
2530                 return r;
2531         /* Read BIOS */
2532         if (!radeon_get_bios(rdev)) {
2533                 if (ASIC_IS_AVIVO(rdev))
2534                         return -EINVAL;
2535         }
2536         /* Must be an ATOMBIOS */
2537         if (!rdev->is_atom_bios) {
2538                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2539                 return -EINVAL;
2540         }
2541         r = radeon_atombios_init(rdev);
2542         if (r)
2543                 return r;
2544         /* Post card if necessary */
2545         if (!radeon_card_posted(rdev)) {
2546                 if (!rdev->bios) {
2547                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2548                         return -EINVAL;
2549                 }
2550                 DRM_INFO("GPU not posted. posting now...\n");
2551                 atom_asic_init(rdev->mode_info.atom_context);
2552         }
2553         /* Initialize scratch registers */
2554         r600_scratch_init(rdev);
2555         /* Initialize surface registers */
2556         radeon_surface_init(rdev);
2557         /* Initialize clocks */
2558         radeon_get_clock_info(rdev->ddev);
2559         /* Fence driver */
2560         r = radeon_fence_driver_init(rdev);
2561         if (r)
2562                 return r;
2563         if (rdev->flags & RADEON_IS_AGP) {
2564                 r = radeon_agp_init(rdev);
2565                 if (r)
2566                         radeon_agp_disable(rdev);
2567         }
2568         r = r600_mc_init(rdev);
2569         if (r)
2570                 return r;
2571         /* Memory manager */
2572         r = radeon_bo_init(rdev);
2573         if (r)
2574                 return r;
2575
2576         r = radeon_irq_kms_init(rdev);
2577         if (r)
2578                 return r;
2579
2580         rdev->cp.ring_obj = NULL;
2581         r600_ring_init(rdev, 1024 * 1024);
2582
2583         rdev->ih.ring_obj = NULL;
2584         r600_ih_ring_init(rdev, 64 * 1024);
2585
2586         r = r600_pcie_gart_init(rdev);
2587         if (r)
2588                 return r;
2589
2590         rdev->accel_working = true;
2591         r = r600_startup(rdev);
2592         if (r) {
2593                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2594                 r600_cp_fini(rdev);
2595                 r600_irq_fini(rdev);
2596                 radeon_wb_fini(rdev);
2597                 radeon_irq_kms_fini(rdev);
2598                 r600_pcie_gart_fini(rdev);
2599                 rdev->accel_working = false;
2600         }
2601         if (rdev->accel_working) {
2602                 r = radeon_ib_pool_init(rdev);
2603                 if (r) {
2604                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2605                         rdev->accel_working = false;
2606                 } else {
2607                         r = r600_ib_test(rdev);
2608                         if (r) {
2609                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2610                                 rdev->accel_working = false;
2611                         }
2612                 }
2613         }
2614
2615         r = r600_audio_init(rdev);
2616         if (r)
2617                 return r; /* TODO error handling */
2618         return 0;
2619 }
2620
2621 void r600_fini(struct radeon_device *rdev)
2622 {
2623         r600_audio_fini(rdev);
2624         r600_blit_fini(rdev);
2625         r600_cp_fini(rdev);
2626         r600_irq_fini(rdev);
2627         radeon_wb_fini(rdev);
2628         radeon_irq_kms_fini(rdev);
2629         r600_pcie_gart_fini(rdev);
2630         radeon_agp_fini(rdev);
2631         radeon_gem_fini(rdev);
2632         radeon_fence_driver_fini(rdev);
2633         radeon_bo_fini(rdev);
2634         radeon_atombios_fini(rdev);
2635         kfree(rdev->bios);
2636         rdev->bios = NULL;
2637 }
2638
2639
2640 /*
2641  * CS stuff
2642  */
2643 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2644 {
2645         /* FIXME: implement */
2646         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2647         radeon_ring_write(rdev,
2648 #ifdef __BIG_ENDIAN
2649                           (2 << 0) |
2650 #endif
2651                           (ib->gpu_addr & 0xFFFFFFFC));
2652         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2653         radeon_ring_write(rdev, ib->length_dw);
2654 }
2655
2656 int r600_ib_test(struct radeon_device *rdev)
2657 {
2658         struct radeon_ib *ib;
2659         uint32_t scratch;
2660         uint32_t tmp = 0;
2661         unsigned i;
2662         int r;
2663
2664         r = radeon_scratch_get(rdev, &scratch);
2665         if (r) {
2666                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2667                 return r;
2668         }
2669         WREG32(scratch, 0xCAFEDEAD);
2670         r = radeon_ib_get(rdev, &ib);
2671         if (r) {
2672                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2673                 return r;
2674         }
2675         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2676         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2677         ib->ptr[2] = 0xDEADBEEF;
2678         ib->ptr[3] = PACKET2(0);
2679         ib->ptr[4] = PACKET2(0);
2680         ib->ptr[5] = PACKET2(0);
2681         ib->ptr[6] = PACKET2(0);
2682         ib->ptr[7] = PACKET2(0);
2683         ib->ptr[8] = PACKET2(0);
2684         ib->ptr[9] = PACKET2(0);
2685         ib->ptr[10] = PACKET2(0);
2686         ib->ptr[11] = PACKET2(0);
2687         ib->ptr[12] = PACKET2(0);
2688         ib->ptr[13] = PACKET2(0);
2689         ib->ptr[14] = PACKET2(0);
2690         ib->ptr[15] = PACKET2(0);
2691         ib->length_dw = 16;
2692         r = radeon_ib_schedule(rdev, ib);
2693         if (r) {
2694                 radeon_scratch_free(rdev, scratch);
2695                 radeon_ib_free(rdev, &ib);
2696                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2697                 return r;
2698         }
2699         r = radeon_fence_wait(ib->fence, false);
2700         if (r) {
2701                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2702                 return r;
2703         }
2704         for (i = 0; i < rdev->usec_timeout; i++) {
2705                 tmp = RREG32(scratch);
2706                 if (tmp == 0xDEADBEEF)
2707                         break;
2708                 DRM_UDELAY(1);
2709         }
2710         if (i < rdev->usec_timeout) {
2711                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2712         } else {
2713                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2714                           scratch, tmp);
2715                 r = -EINVAL;
2716         }
2717         radeon_scratch_free(rdev, scratch);
2718         radeon_ib_free(rdev, &ib);
2719         return r;
2720 }
2721
2722 /*
2723  * Interrupts
2724  *
2725  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2726  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2727  * writing to the ring and the GPU consuming, the GPU writes to the ring
2728  * and host consumes.  As the host irq handler processes interrupts, it
2729  * increments the rptr.  When the rptr catches up with the wptr, all the
2730  * current interrupts have been processed.
2731  */
2732
2733 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2734 {
2735         u32 rb_bufsz;
2736
2737         /* Align ring size */
2738         rb_bufsz = drm_order(ring_size / 4);
2739         ring_size = (1 << rb_bufsz) * 4;
2740         rdev->ih.ring_size = ring_size;
2741         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2742         rdev->ih.rptr = 0;
2743 }
2744
2745 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2746 {
2747         int r;
2748
2749         /* Allocate ring buffer */
2750         if (rdev->ih.ring_obj == NULL) {
2751                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2752                                      PAGE_SIZE, true,
2753                                      RADEON_GEM_DOMAIN_GTT,
2754                                      &rdev->ih.ring_obj);
2755                 if (r) {
2756                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2757                         return r;
2758                 }
2759                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2760                 if (unlikely(r != 0))
2761                         return r;
2762                 r = radeon_bo_pin(rdev->ih.ring_obj,
2763                                   RADEON_GEM_DOMAIN_GTT,
2764                                   &rdev->ih.gpu_addr);
2765                 if (r) {
2766                         radeon_bo_unreserve(rdev->ih.ring_obj);
2767                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2768                         return r;
2769                 }
2770                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2771                                    (void **)&rdev->ih.ring);
2772                 radeon_bo_unreserve(rdev->ih.ring_obj);
2773                 if (r) {
2774                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2775                         return r;
2776                 }
2777         }
2778         return 0;
2779 }
2780
2781 static void r600_ih_ring_fini(struct radeon_device *rdev)
2782 {
2783         int r;
2784         if (rdev->ih.ring_obj) {
2785                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2786                 if (likely(r == 0)) {
2787                         radeon_bo_kunmap(rdev->ih.ring_obj);
2788                         radeon_bo_unpin(rdev->ih.ring_obj);
2789                         radeon_bo_unreserve(rdev->ih.ring_obj);
2790                 }
2791                 radeon_bo_unref(&rdev->ih.ring_obj);
2792                 rdev->ih.ring = NULL;
2793                 rdev->ih.ring_obj = NULL;
2794         }
2795 }
2796
2797 void r600_rlc_stop(struct radeon_device *rdev)
2798 {
2799
2800         if ((rdev->family >= CHIP_RV770) &&
2801             (rdev->family <= CHIP_RV740)) {
2802                 /* r7xx asics need to soft reset RLC before halting */
2803                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2804                 RREG32(SRBM_SOFT_RESET);
2805                 udelay(15000);
2806                 WREG32(SRBM_SOFT_RESET, 0);
2807                 RREG32(SRBM_SOFT_RESET);
2808         }
2809
2810         WREG32(RLC_CNTL, 0);
2811 }
2812
2813 static void r600_rlc_start(struct radeon_device *rdev)
2814 {
2815         WREG32(RLC_CNTL, RLC_ENABLE);
2816 }
2817
2818 static int r600_rlc_init(struct radeon_device *rdev)
2819 {
2820         u32 i;
2821         const __be32 *fw_data;
2822
2823         if (!rdev->rlc_fw)
2824                 return -EINVAL;
2825
2826         r600_rlc_stop(rdev);
2827
2828         WREG32(RLC_HB_BASE, 0);
2829         WREG32(RLC_HB_CNTL, 0);
2830         WREG32(RLC_HB_RPTR, 0);
2831         WREG32(RLC_HB_WPTR, 0);
2832         if (rdev->family <= CHIP_CAICOS) {
2833                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2834                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2835         }
2836         WREG32(RLC_MC_CNTL, 0);
2837         WREG32(RLC_UCODE_CNTL, 0);
2838
2839         fw_data = (const __be32 *)rdev->rlc_fw->data;
2840         if (rdev->family >= CHIP_CAYMAN) {
2841                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2842                         WREG32(RLC_UCODE_ADDR, i);
2843                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2844                 }
2845         } else if (rdev->family >= CHIP_CEDAR) {
2846                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2847                         WREG32(RLC_UCODE_ADDR, i);
2848                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2849                 }
2850         } else if (rdev->family >= CHIP_RV770) {
2851                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2852                         WREG32(RLC_UCODE_ADDR, i);
2853                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2854                 }
2855         } else {
2856                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2857                         WREG32(RLC_UCODE_ADDR, i);
2858                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2859                 }
2860         }
2861         WREG32(RLC_UCODE_ADDR, 0);
2862
2863         r600_rlc_start(rdev);
2864
2865         return 0;
2866 }
2867
2868 static void r600_enable_interrupts(struct radeon_device *rdev)
2869 {
2870         u32 ih_cntl = RREG32(IH_CNTL);
2871         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2872
2873         ih_cntl |= ENABLE_INTR;
2874         ih_rb_cntl |= IH_RB_ENABLE;
2875         WREG32(IH_CNTL, ih_cntl);
2876         WREG32(IH_RB_CNTL, ih_rb_cntl);
2877         rdev->ih.enabled = true;
2878 }
2879
2880 void r600_disable_interrupts(struct radeon_device *rdev)
2881 {
2882         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2883         u32 ih_cntl = RREG32(IH_CNTL);
2884
2885         ih_rb_cntl &= ~IH_RB_ENABLE;
2886         ih_cntl &= ~ENABLE_INTR;
2887         WREG32(IH_RB_CNTL, ih_rb_cntl);
2888         WREG32(IH_CNTL, ih_cntl);
2889         /* set rptr, wptr to 0 */
2890         WREG32(IH_RB_RPTR, 0);
2891         WREG32(IH_RB_WPTR, 0);
2892         rdev->ih.enabled = false;
2893         rdev->ih.wptr = 0;
2894         rdev->ih.rptr = 0;
2895 }
2896
2897 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2898 {
2899         u32 tmp;
2900
2901         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2902         WREG32(GRBM_INT_CNTL, 0);
2903         WREG32(DxMODE_INT_MASK, 0);
2904         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2905         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2906         if (ASIC_IS_DCE3(rdev)) {
2907                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2908                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2909                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2910                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2911                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2912                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2913                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2914                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2915                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2916                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2917                 if (ASIC_IS_DCE32(rdev)) {
2918                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2919                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2920                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2921                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2922                 }
2923         } else {
2924                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2925                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2926                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2927                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2928                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2929                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2930                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2931                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2932         }
2933 }
2934
2935 int r600_irq_init(struct radeon_device *rdev)
2936 {
2937         int ret = 0;
2938         int rb_bufsz;
2939         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2940
2941         /* allocate ring */
2942         ret = r600_ih_ring_alloc(rdev);
2943         if (ret)
2944                 return ret;
2945
2946         /* disable irqs */
2947         r600_disable_interrupts(rdev);
2948
2949         /* init rlc */
2950         ret = r600_rlc_init(rdev);
2951         if (ret) {
2952                 r600_ih_ring_fini(rdev);
2953                 return ret;
2954         }
2955
2956         /* setup interrupt control */
2957         /* set dummy read address to ring address */
2958         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2959         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2960         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2961          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2962          */
2963         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2964         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2965         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2966         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2967
2968         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2969         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2970
2971         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2972                       IH_WPTR_OVERFLOW_CLEAR |
2973                       (rb_bufsz << 1));
2974
2975         if (rdev->wb.enabled)
2976                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2977
2978         /* set the writeback address whether it's enabled or not */
2979         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2980         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2981
2982         WREG32(IH_RB_CNTL, ih_rb_cntl);
2983
2984         /* set rptr, wptr to 0 */
2985         WREG32(IH_RB_RPTR, 0);
2986         WREG32(IH_RB_WPTR, 0);
2987
2988         /* Default settings for IH_CNTL (disabled at first) */
2989         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2990         /* RPTR_REARM only works if msi's are enabled */
2991         if (rdev->msi_enabled)
2992                 ih_cntl |= RPTR_REARM;
2993
2994 #ifdef __BIG_ENDIAN
2995         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2996 #endif
2997         WREG32(IH_CNTL, ih_cntl);
2998
2999         /* force the active interrupt state to all disabled */
3000         if (rdev->family >= CHIP_CEDAR)
3001                 evergreen_disable_interrupt_state(rdev);
3002         else
3003                 r600_disable_interrupt_state(rdev);
3004
3005         /* enable irqs */
3006         r600_enable_interrupts(rdev);
3007
3008         return ret;
3009 }
3010
3011 void r600_irq_suspend(struct radeon_device *rdev)
3012 {
3013         r600_irq_disable(rdev);
3014         r600_rlc_stop(rdev);
3015 }
3016
3017 void r600_irq_fini(struct radeon_device *rdev)
3018 {
3019         r600_irq_suspend(rdev);
3020         r600_ih_ring_fini(rdev);
3021 }
3022
3023 int r600_irq_set(struct radeon_device *rdev)
3024 {
3025         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3026         u32 mode_int = 0;
3027         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3028         u32 grbm_int_cntl = 0;
3029         u32 hdmi1, hdmi2;
3030         u32 d1grph = 0, d2grph = 0;
3031
3032         if (!rdev->irq.installed) {
3033                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3034                 return -EINVAL;
3035         }
3036         /* don't enable anything if the ih is disabled */
3037         if (!rdev->ih.enabled) {
3038                 r600_disable_interrupts(rdev);
3039                 /* force the active interrupt state to all disabled */
3040                 r600_disable_interrupt_state(rdev);
3041                 return 0;
3042         }
3043
3044         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3045         if (ASIC_IS_DCE3(rdev)) {
3046                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3047                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3048                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3049                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3050                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3051                 if (ASIC_IS_DCE32(rdev)) {
3052                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3053                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3054                 }
3055         } else {
3056                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3057                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3058                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3059                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3060         }
3061
3062         if (rdev->irq.sw_int) {
3063                 DRM_DEBUG("r600_irq_set: sw int\n");
3064                 cp_int_cntl |= RB_INT_ENABLE;
3065                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3066         }
3067         if (rdev->irq.crtc_vblank_int[0] ||
3068             rdev->irq.pflip[0]) {
3069                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3070                 mode_int |= D1MODE_VBLANK_INT_MASK;
3071         }
3072         if (rdev->irq.crtc_vblank_int[1] ||
3073             rdev->irq.pflip[1]) {
3074                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3075                 mode_int |= D2MODE_VBLANK_INT_MASK;
3076         }
3077         if (rdev->irq.hpd[0]) {
3078                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3079                 hpd1 |= DC_HPDx_INT_EN;
3080         }
3081         if (rdev->irq.hpd[1]) {
3082                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3083                 hpd2 |= DC_HPDx_INT_EN;
3084         }
3085         if (rdev->irq.hpd[2]) {
3086                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3087                 hpd3 |= DC_HPDx_INT_EN;
3088         }
3089         if (rdev->irq.hpd[3]) {
3090                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3091                 hpd4 |= DC_HPDx_INT_EN;
3092         }
3093         if (rdev->irq.hpd[4]) {
3094                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3095                 hpd5 |= DC_HPDx_INT_EN;
3096         }
3097         if (rdev->irq.hpd[5]) {
3098                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3099                 hpd6 |= DC_HPDx_INT_EN;
3100         }
3101         if (rdev->irq.hdmi[0]) {
3102                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3103                 hdmi1 |= R600_HDMI_INT_EN;
3104         }
3105         if (rdev->irq.hdmi[1]) {
3106                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3107                 hdmi2 |= R600_HDMI_INT_EN;
3108         }
3109         if (rdev->irq.gui_idle) {
3110                 DRM_DEBUG("gui idle\n");
3111                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3112         }
3113
3114         WREG32(CP_INT_CNTL, cp_int_cntl);
3115         WREG32(DxMODE_INT_MASK, mode_int);
3116         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3117         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3118         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3119         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3120         if (ASIC_IS_DCE3(rdev)) {
3121                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3122                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3123                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3124                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3125                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3126                 if (ASIC_IS_DCE32(rdev)) {
3127                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3128                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3129                 }
3130         } else {
3131                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3132                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3133                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3134                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3135         }
3136
3137         return 0;
3138 }
3139
3140 static inline void r600_irq_ack(struct radeon_device *rdev)
3141 {
3142         u32 tmp;
3143
3144         if (ASIC_IS_DCE3(rdev)) {
3145                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3146                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3147                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3148         } else {
3149                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3150                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3151                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3152         }
3153         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3154         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3155
3156         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3157                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3158         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3159                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3160         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3161                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3162         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3163                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3164         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3165                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3166         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3167                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3168         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3169                 if (ASIC_IS_DCE3(rdev)) {
3170                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3171                         tmp |= DC_HPDx_INT_ACK;
3172                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3173                 } else {
3174                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3175                         tmp |= DC_HPDx_INT_ACK;
3176                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3177                 }
3178         }
3179         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3180                 if (ASIC_IS_DCE3(rdev)) {
3181                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3182                         tmp |= DC_HPDx_INT_ACK;
3183                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3184                 } else {
3185                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3186                         tmp |= DC_HPDx_INT_ACK;
3187                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3188                 }
3189         }
3190         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3191                 if (ASIC_IS_DCE3(rdev)) {
3192                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3193                         tmp |= DC_HPDx_INT_ACK;
3194                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3195                 } else {
3196                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3197                         tmp |= DC_HPDx_INT_ACK;
3198                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3199                 }
3200         }
3201         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3202                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3203                 tmp |= DC_HPDx_INT_ACK;
3204                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3205         }
3206         if (ASIC_IS_DCE32(rdev)) {
3207                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3208                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3209                         tmp |= DC_HPDx_INT_ACK;
3210                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3211                 }
3212                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3213                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3214                         tmp |= DC_HPDx_INT_ACK;
3215                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3216                 }
3217         }
3218         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3219                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3220         }
3221         if (ASIC_IS_DCE3(rdev)) {
3222                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3223                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3224                 }
3225         } else {
3226                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3227                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3228                 }
3229         }
3230 }
3231
3232 void r600_irq_disable(struct radeon_device *rdev)
3233 {
3234         r600_disable_interrupts(rdev);
3235         /* Wait and acknowledge irq */
3236         mdelay(1);
3237         r600_irq_ack(rdev);
3238         r600_disable_interrupt_state(rdev);
3239 }
3240
3241 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3242 {
3243         u32 wptr, tmp;
3244
3245         if (rdev->wb.enabled)
3246                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3247         else
3248                 wptr = RREG32(IH_RB_WPTR);
3249
3250         if (wptr & RB_OVERFLOW) {
3251                 /* When a ring buffer overflow happen start parsing interrupt
3252                  * from the last not overwritten vector (wptr + 16). Hopefully
3253                  * this should allow us to catchup.
3254                  */
3255                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3256                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3257                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3258                 tmp = RREG32(IH_RB_CNTL);
3259                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3260                 WREG32(IH_RB_CNTL, tmp);
3261         }
3262         return (wptr & rdev->ih.ptr_mask);
3263 }
3264
3265 /*        r600 IV Ring
3266  * Each IV ring entry is 128 bits:
3267  * [7:0]    - interrupt source id
3268  * [31:8]   - reserved
3269  * [59:32]  - interrupt source data
3270  * [127:60]  - reserved
3271  *
3272  * The basic interrupt vector entries
3273  * are decoded as follows:
3274  * src_id  src_data  description
3275  *      1         0  D1 Vblank
3276  *      1         1  D1 Vline
3277  *      5         0  D2 Vblank
3278  *      5         1  D2 Vline
3279  *     19         0  FP Hot plug detection A
3280  *     19         1  FP Hot plug detection B
3281  *     19         2  DAC A auto-detection
3282  *     19         3  DAC B auto-detection
3283  *     21         4  HDMI block A
3284  *     21         5  HDMI block B
3285  *    176         -  CP_INT RB
3286  *    177         -  CP_INT IB1
3287  *    178         -  CP_INT IB2
3288  *    181         -  EOP Interrupt
3289  *    233         -  GUI Idle
3290  *
3291  * Note, these are based on r600 and may need to be
3292  * adjusted or added to on newer asics
3293  */
3294
3295 int r600_irq_process(struct radeon_device *rdev)
3296 {
3297         u32 wptr = r600_get_ih_wptr(rdev);
3298         u32 rptr = rdev->ih.rptr;
3299         u32 src_id, src_data;
3300         u32 ring_index;
3301         unsigned long flags;
3302         bool queue_hotplug = false;
3303
3304         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3305         if (!rdev->ih.enabled)
3306                 return IRQ_NONE;
3307
3308         spin_lock_irqsave(&rdev->ih.lock, flags);
3309
3310         if (rptr == wptr) {
3311                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3312                 return IRQ_NONE;
3313         }
3314         if (rdev->shutdown) {
3315                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3316                 return IRQ_NONE;
3317         }
3318
3319 restart_ih:
3320         /* display interrupts */
3321         r600_irq_ack(rdev);
3322
3323         rdev->ih.wptr = wptr;
3324         while (rptr != wptr) {
3325                 /* wptr/rptr are in bytes! */
3326                 ring_index = rptr / 4;
3327                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3328                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3329
3330                 switch (src_id) {
3331                 case 1: /* D1 vblank/vline */
3332                         switch (src_data) {
3333                         case 0: /* D1 vblank */
3334                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3335                                         if (rdev->irq.crtc_vblank_int[0]) {
3336                                                 drm_handle_vblank(rdev->ddev, 0);
3337                                                 rdev->pm.vblank_sync = true;
3338                                                 wake_up(&rdev->irq.vblank_queue);
3339                                         }
3340                                         if (rdev->irq.pflip[0])
3341                                                 radeon_crtc_handle_flip(rdev, 0);
3342                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3343                                         DRM_DEBUG("IH: D1 vblank\n");
3344                                 }
3345                                 break;
3346                         case 1: /* D1 vline */
3347                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3348                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3349                                         DRM_DEBUG("IH: D1 vline\n");
3350                                 }
3351                                 break;
3352                         default:
3353                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3354                                 break;
3355                         }
3356                         break;
3357                 case 5: /* D2 vblank/vline */
3358                         switch (src_data) {
3359                         case 0: /* D2 vblank */
3360                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3361                                         if (rdev->irq.crtc_vblank_int[1]) {
3362                                                 drm_handle_vblank(rdev->ddev, 1);
3363                                                 rdev->pm.vblank_sync = true;
3364                                                 wake_up(&rdev->irq.vblank_queue);
3365                                         }
3366                                         if (rdev->irq.pflip[1])
3367                                                 radeon_crtc_handle_flip(rdev, 1);
3368                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3369                                         DRM_DEBUG("IH: D2 vblank\n");
3370                                 }
3371                                 break;
3372                         case 1: /* D1 vline */
3373                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3374                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3375                                         DRM_DEBUG("IH: D2 vline\n");
3376                                 }
3377                                 break;
3378                         default:
3379                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3380                                 break;
3381                         }
3382                         break;
3383                 case 19: /* HPD/DAC hotplug */
3384                         switch (src_data) {
3385                         case 0:
3386                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3387                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3388                                         queue_hotplug = true;
3389                                         DRM_DEBUG("IH: HPD1\n");
3390                                 }
3391                                 break;
3392                         case 1:
3393                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3394                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3395                                         queue_hotplug = true;
3396                                         DRM_DEBUG("IH: HPD2\n");
3397                                 }
3398                                 break;
3399                         case 4:
3400                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3401                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3402                                         queue_hotplug = true;
3403                                         DRM_DEBUG("IH: HPD3\n");
3404                                 }
3405                                 break;
3406                         case 5:
3407                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3408                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3409                                         queue_hotplug = true;
3410                                         DRM_DEBUG("IH: HPD4\n");
3411                                 }
3412                                 break;
3413                         case 10:
3414                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3415                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3416                                         queue_hotplug = true;
3417                                         DRM_DEBUG("IH: HPD5\n");
3418                                 }
3419                                 break;
3420                         case 12:
3421                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3422                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3423                                         queue_hotplug = true;
3424                                         DRM_DEBUG("IH: HPD6\n");
3425                                 }
3426                                 break;
3427                         default:
3428                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3429                                 break;
3430                         }
3431                         break;
3432                 case 21: /* HDMI */
3433                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3434                         r600_audio_schedule_polling(rdev);
3435                         break;
3436                 case 176: /* CP_INT in ring buffer */
3437                 case 177: /* CP_INT in IB1 */
3438                 case 178: /* CP_INT in IB2 */
3439                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3440                         radeon_fence_process(rdev);
3441                         break;
3442                 case 181: /* CP EOP event */
3443                         DRM_DEBUG("IH: CP EOP\n");
3444                         radeon_fence_process(rdev);
3445                         break;
3446                 case 233: /* GUI IDLE */
3447                         DRM_DEBUG("IH: CP EOP\n");
3448                         rdev->pm.gui_idle = true;
3449                         wake_up(&rdev->irq.idle_queue);
3450                         break;
3451                 default:
3452                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3453                         break;
3454                 }
3455
3456                 /* wptr/rptr are in bytes! */
3457                 rptr += 16;
3458                 rptr &= rdev->ih.ptr_mask;
3459         }
3460         /* make sure wptr hasn't changed while processing */
3461         wptr = r600_get_ih_wptr(rdev);
3462         if (wptr != rdev->ih.wptr)
3463                 goto restart_ih;
3464         if (queue_hotplug)
3465                 schedule_work(&rdev->hotplug_work);
3466         rdev->ih.rptr = rptr;
3467         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3468         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3469         return IRQ_HANDLED;
3470 }
3471
3472 /*
3473  * Debugfs info
3474  */
3475 #if defined(CONFIG_DEBUG_FS)
3476
3477 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3478 {
3479         struct drm_info_node *node = (struct drm_info_node *) m->private;
3480         struct drm_device *dev = node->minor->dev;
3481         struct radeon_device *rdev = dev->dev_private;
3482         unsigned count, i, j;
3483
3484         radeon_ring_free_size(rdev);
3485         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3486         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3487         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3488         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3489         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3490         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3491         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3492         seq_printf(m, "%u dwords in ring\n", count);
3493         i = rdev->cp.rptr;
3494         for (j = 0; j <= count; j++) {
3495                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3496                 i = (i + 1) & rdev->cp.ptr_mask;
3497         }
3498         return 0;
3499 }
3500
3501 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3502 {
3503         struct drm_info_node *node = (struct drm_info_node *) m->private;
3504         struct drm_device *dev = node->minor->dev;
3505         struct radeon_device *rdev = dev->dev_private;
3506
3507         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3508         DREG32_SYS(m, rdev, VM_L2_STATUS);
3509         return 0;
3510 }
3511
3512 static struct drm_info_list r600_mc_info_list[] = {
3513         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3514         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3515 };
3516 #endif
3517
3518 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3519 {
3520 #if defined(CONFIG_DEBUG_FS)
3521         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3522 #else
3523         return 0;
3524 #endif
3525 }
3526
3527 /**
3528  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3529  * rdev: radeon device structure
3530  * bo: buffer object struct which userspace is waiting for idle
3531  *
3532  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3533  * through ring buffer, this leads to corruption in rendering, see
3534  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3535  * directly perform HDP flush by writing register through MMIO.
3536  */
3537 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3538 {
3539         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3540          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3541          * This seems to cause problems on some AGP cards. Just use the old
3542          * method for them.
3543          */
3544         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3545             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3546                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3547                 u32 tmp;
3548
3549                 WREG32(HDP_DEBUG1, 0);
3550                 tmp = readl((void __iomem *)ptr);
3551         } else
3552                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3553 }
3554
3555 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3556 {
3557         u32 link_width_cntl, mask, target_reg;
3558
3559         if (rdev->flags & RADEON_IS_IGP)
3560                 return;
3561
3562         if (!(rdev->flags & RADEON_IS_PCIE))
3563                 return;
3564
3565         /* x2 cards have a special sequence */
3566         if (ASIC_IS_X2(rdev))
3567                 return;
3568
3569         /* FIXME wait for idle */
3570
3571         switch (lanes) {
3572         case 0:
3573                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3574                 break;
3575         case 1:
3576                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3577                 break;
3578         case 2:
3579                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3580                 break;
3581         case 4:
3582                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3583                 break;
3584         case 8:
3585                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3586                 break;
3587         case 12:
3588                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3589                 break;
3590         case 16:
3591         default:
3592                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3593                 break;
3594         }
3595
3596         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3597
3598         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3599             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3600                 return;
3601
3602         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3603                 return;
3604
3605         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3606                              RADEON_PCIE_LC_RECONFIG_NOW |
3607                              R600_PCIE_LC_RENEGOTIATE_EN |
3608                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3609         link_width_cntl |= mask;
3610
3611         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3612
3613         /* some northbridges can renegotiate the link rather than requiring
3614          * a complete re-config.
3615          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3616          */
3617         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3618                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3619         else
3620                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3621
3622         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3623                                                        RADEON_PCIE_LC_RECONFIG_NOW));
3624
3625         if (rdev->family >= CHIP_RV770)
3626                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3627         else
3628                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3629
3630         /* wait for lane set to complete */
3631         link_width_cntl = RREG32(target_reg);
3632         while (link_width_cntl == 0xffffffff)
3633                 link_width_cntl = RREG32(target_reg);
3634
3635 }
3636
3637 int r600_get_pcie_lanes(struct radeon_device *rdev)
3638 {
3639         u32 link_width_cntl;
3640
3641         if (rdev->flags & RADEON_IS_IGP)
3642                 return 0;
3643
3644         if (!(rdev->flags & RADEON_IS_PCIE))
3645                 return 0;
3646
3647         /* x2 cards have a special sequence */
3648         if (ASIC_IS_X2(rdev))
3649                 return 0;
3650
3651         /* FIXME wait for idle */
3652
3653         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3654
3655         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3656         case RADEON_PCIE_LC_LINK_WIDTH_X0:
3657                 return 0;
3658         case RADEON_PCIE_LC_LINK_WIDTH_X1:
3659                 return 1;
3660         case RADEON_PCIE_LC_LINK_WIDTH_X2:
3661                 return 2;
3662         case RADEON_PCIE_LC_LINK_WIDTH_X4:
3663                 return 4;
3664         case RADEON_PCIE_LC_LINK_WIDTH_X8:
3665                 return 8;
3666         case RADEON_PCIE_LC_LINK_WIDTH_X16:
3667         default:
3668                 return 16;
3669         }
3670 }
3671
3672 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3673 {
3674         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3675         u16 link_cntl2;
3676
3677         if (radeon_pcie_gen2 == 0)
3678                 return;
3679
3680         if (rdev->flags & RADEON_IS_IGP)
3681                 return;
3682
3683         if (!(rdev->flags & RADEON_IS_PCIE))
3684                 return;
3685
3686         /* x2 cards have a special sequence */
3687         if (ASIC_IS_X2(rdev))
3688                 return;
3689
3690         /* only RV6xx+ chips are supported */
3691         if (rdev->family <= CHIP_R600)
3692                 return;
3693
3694         /* 55 nm r6xx asics */
3695         if ((rdev->family == CHIP_RV670) ||
3696             (rdev->family == CHIP_RV620) ||
3697             (rdev->family == CHIP_RV635)) {
3698                 /* advertise upconfig capability */
3699                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3700                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3701                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3702                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3703                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3704                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3705                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3706                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
3707                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3708                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3709                 } else {
3710                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3711                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3712                 }
3713         }
3714
3715         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3716         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3717             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3718
3719                 /* 55 nm r6xx asics */
3720                 if ((rdev->family == CHIP_RV670) ||
3721                     (rdev->family == CHIP_RV620) ||
3722                     (rdev->family == CHIP_RV635)) {
3723                         WREG32(MM_CFGREGS_CNTL, 0x8);
3724                         link_cntl2 = RREG32(0x4088);
3725                         WREG32(MM_CFGREGS_CNTL, 0);
3726                         /* not supported yet */
3727                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3728                                 return;
3729                 }
3730
3731                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3732                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3733                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3734                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3735                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3736                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3737
3738                 tmp = RREG32(0x541c);
3739                 WREG32(0x541c, tmp | 0x8);
3740                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3741                 link_cntl2 = RREG16(0x4088);
3742                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3743                 link_cntl2 |= 0x2;
3744                 WREG16(0x4088, link_cntl2);
3745                 WREG32(MM_CFGREGS_CNTL, 0);
3746
3747                 if ((rdev->family == CHIP_RV670) ||
3748                     (rdev->family == CHIP_RV620) ||
3749                     (rdev->family == CHIP_RV635)) {
3750                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3751                         training_cntl &= ~LC_POINT_7_PLUS_EN;
3752                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3753                 } else {
3754                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3755                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3756                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3757                 }
3758
3759                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3760                 speed_cntl |= LC_GEN2_EN_STRAP;
3761                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3762
3763         } else {
3764                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3765                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3766                 if (1)
3767                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3768                 else
3769                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3770                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3771         }
3772 }