drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  87 MODULE_FIRMWARE("radeon/PALM_me.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  89
  90 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  91
  92 /* r600,rv610,rv630,rv620,rv635,rv670 */
  93 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  94 void r600_gpu_init(struct radeon_device *rdev);
  95 void r600_fini(struct radeon_device *rdev);
  96 void r600_irq_disable(struct radeon_device *rdev);
  97 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  98
  99 /* get temperature in millidegrees */
 100 int rv6xx_get_temp(struct radeon_device *rdev)
 101 {
 102         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 103                 ASIC_T_SHIFT;
 104         int actual_temp = temp & 0xff;
 105
 106         if (temp & 0x100)
 107                 actual_temp -= 256;
 108
 109         return actual_temp * 1000;
 110 }
 111
 112 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 113 {
 114         int i;
 115
 116         rdev->pm.dynpm_can_upclock = true;
 117         rdev->pm.dynpm_can_downclock = true;
 118
 119         /* power state array is low to high, default is first */
 120         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 121                 int min_power_state_index = 0;
 122
 123                 if (rdev->pm.num_power_states > 2)
 124                         min_power_state_index = 1;
 125
 126                 switch (rdev->pm.dynpm_planned_action) {
 127                 case DYNPM_ACTION_MINIMUM:
 128                         rdev->pm.requested_power_state_index = min_power_state_index;
 129                         rdev->pm.requested_clock_mode_index = 0;
 130                         rdev->pm.dynpm_can_downclock = false;
 131                         break;
 132                 case DYNPM_ACTION_DOWNCLOCK:
 133                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 134                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 135                                 rdev->pm.dynpm_can_downclock = false;
 136                         } else {
 137                                 if (rdev->pm.active_crtc_count > 1) {
 138                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 139                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 140                                                         continue;
 141                                                 else if (i >= rdev->pm.current_power_state_index) {
 142                                                         rdev->pm.requested_power_state_index =
 143                                                                 rdev->pm.current_power_state_index;
 144                                                         break;
 145                                                 } else {
 146                                                         rdev->pm.requested_power_state_index = i;
 147                                                         break;
 148                                                 }
 149                                         }
 150                                 } else {
 151                                         if (rdev->pm.current_power_state_index == 0)
 152                                                 rdev->pm.requested_power_state_index =
 153                                                         rdev->pm.num_power_states - 1;
 154                                         else
 155                                                 rdev->pm.requested_power_state_index =
 156                                                         rdev->pm.current_power_state_index - 1;
 157                                 }
 158                         }
 159                         rdev->pm.requested_clock_mode_index = 0;
 160                         /* don't use the power state if crtcs are active and no display flag is set */
 161                         if ((rdev->pm.active_crtc_count > 0) &&
 162                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 163                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 164                              RADEON_PM_MODE_NO_DISPLAY)) {
 165                                 rdev->pm.requested_power_state_index++;
 166                         }
 167                         break;
 168                 case DYNPM_ACTION_UPCLOCK:
 169                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 170                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 171                                 rdev->pm.dynpm_can_upclock = false;
 172                         } else {
 173                                 if (rdev->pm.active_crtc_count > 1) {
 174                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 175                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 176                                                         continue;
 177                                                 else if (i <= rdev->pm.current_power_state_index) {
 178                                                         rdev->pm.requested_power_state_index =
 179                                                                 rdev->pm.current_power_state_index;
 180                                                         break;
 181                                                 } else {
 182                                                         rdev->pm.requested_power_state_index = i;
 183                                                         break;
 184                                                 }
 185                                         }
 186                                 } else
 187                                         rdev->pm.requested_power_state_index =
 188                                                 rdev->pm.current_power_state_index + 1;
 189                         }
 190                         rdev->pm.requested_clock_mode_index = 0;
 191                         break;
 192                 case DYNPM_ACTION_DEFAULT:
 193                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 194                         rdev->pm.requested_clock_mode_index = 0;
 195                         rdev->pm.dynpm_can_upclock = false;
 196                         break;
 197                 case DYNPM_ACTION_NONE:
 198                 default:
 199                         DRM_ERROR("Requested mode for not defined action\n");
 200                         return;
 201                 }
 202         } else {
 203                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 204                 /* for now just select the first power state and switch between clock modes */
 205                 /* power state array is low to high, default is first (0) */
 206                 if (rdev->pm.active_crtc_count > 1) {
 207                         rdev->pm.requested_power_state_index = -1;
 208                         /* start at 1 as we don't want the default mode */
 209                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 210                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 211                                         continue;
 212                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 213                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 214                                         rdev->pm.requested_power_state_index = i;
 215                                         break;
 216                                 }
 217                         }
 218                         /* if nothing selected, grab the default state. */
 219                         if (rdev->pm.requested_power_state_index == -1)
 220                                 rdev->pm.requested_power_state_index = 0;
 221                 } else
 222                         rdev->pm.requested_power_state_index = 1;
 223
 224                 switch (rdev->pm.dynpm_planned_action) {
 225                 case DYNPM_ACTION_MINIMUM:
 226                         rdev->pm.requested_clock_mode_index = 0;
 227                         rdev->pm.dynpm_can_downclock = false;
 228                         break;
 229                 case DYNPM_ACTION_DOWNCLOCK:
 230                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 231                                 if (rdev->pm.current_clock_mode_index == 0) {
 232                                         rdev->pm.requested_clock_mode_index = 0;
 233                                         rdev->pm.dynpm_can_downclock = false;
 234                                 } else
 235                                         rdev->pm.requested_clock_mode_index =
 236                                                 rdev->pm.current_clock_mode_index - 1;
 237                         } else {
 238                                 rdev->pm.requested_clock_mode_index = 0;
 239                                 rdev->pm.dynpm_can_downclock = false;
 240                         }
 241                         /* don't use the power state if crtcs are active and no display flag is set */
 242                         if ((rdev->pm.active_crtc_count > 0) &&
 243                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 244                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 245                              RADEON_PM_MODE_NO_DISPLAY)) {
 246                                 rdev->pm.requested_clock_mode_index++;
 247                         }
 248                         break;
 249                 case DYNPM_ACTION_UPCLOCK:
 250                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 251                                 if (rdev->pm.current_clock_mode_index ==
 252                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 253                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 254                                         rdev->pm.dynpm_can_upclock = false;
 255                                 } else
 256                                         rdev->pm.requested_clock_mode_index =
 257                                                 rdev->pm.current_clock_mode_index + 1;
 258                         } else {
 259                                 rdev->pm.requested_clock_mode_index =
 260                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 261                                 rdev->pm.dynpm_can_upclock = false;
 262                         }
 263                         break;
 264                 case DYNPM_ACTION_DEFAULT:
 265                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 266                         rdev->pm.requested_clock_mode_index = 0;
 267                         rdev->pm.dynpm_can_upclock = false;
 268                         break;
 269                 case DYNPM_ACTION_NONE:
 270                 default:
 271                         DRM_ERROR("Requested mode for not defined action\n");
 272                         return;
 273                 }
 274         }
 275
 276         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 277                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 278                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 279                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 280                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 281                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 282                   pcie_lanes);
 283 }
 284
 285 static int r600_pm_get_type_index(struct radeon_device *rdev,
 286                                   enum radeon_pm_state_type ps_type,
 287                                   int instance)
 288 {
 289         int i;
 290         int found_instance = -1;
 291
 292         for (i = 0; i < rdev->pm.num_power_states; i++) {
 293                 if (rdev->pm.power_state[i].type == ps_type) {
 294                         found_instance++;
 295                         if (found_instance == instance)
 296                                 return i;
 297                 }
 298         }
 299         /* return default if no match */
 300         return rdev->pm.default_power_state_index;
 301 }
 302
 303 void rs780_pm_init_profile(struct radeon_device *rdev)
 304 {
 305         if (rdev->pm.num_power_states == 2) {
 306                 /* default */
 307                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 308                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 309                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 310                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 311                 /* low sh */
 312                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 316                 /* mid sh */
 317                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 321                 /* high sh */
 322                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 324                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 326                 /* low mh */
 327                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 331                 /* mid mh */
 332                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 336                 /* high mh */
 337                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 339                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 341         } else if (rdev->pm.num_power_states == 3) {
 342                 /* default */
 343                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 344                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 345                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 346                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 347                 /* low sh */
 348                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 349                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 350                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 351                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 352                 /* mid sh */
 353                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 355                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 356                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 357                 /* high sh */
 358                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 360                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 361                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 362                 /* low mh */
 363                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 364                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 365                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 366                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 367                 /* mid mh */
 368                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 369                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 370                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 372                 /* high mh */
 373                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 375                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 377         } else {
 378                 /* default */
 379                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 380                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 381                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 382                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 383                 /* low sh */
 384                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 385                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 386                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 388                 /* mid sh */
 389                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 390                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 391                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 392                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 393                 /* high sh */
 394                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 396                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 397                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 398                 /* low mh */
 399                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 400                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 403                 /* mid mh */
 404                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 405                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 406                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 408                 /* high mh */
 409                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 410                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 411                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 413         }
 414 }
 415
 416 void r600_pm_init_profile(struct radeon_device *rdev)
 417 {
 418         if (rdev->family == CHIP_R600) {
 419                 /* XXX */
 420                 /* default */
 421                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 422                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 424                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 425                 /* low sh */
 426                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 427                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 429                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 430                 /* mid sh */
 431                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 432                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 434                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 435                 /* high sh */
 436                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 439                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 440                 /* low mh */
 441                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 442                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 444                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 445                 /* mid mh */
 446                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 447                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 448                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 449                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 450                 /* high mh */
 451                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 453                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 454                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 455         } else {
 456                 if (rdev->pm.num_power_states < 4) {
 457                         /* default */
 458                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 459                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 460                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 461                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 462                         /* low sh */
 463                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 464                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 466                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 467                         /* mid sh */
 468                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 469                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 470                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 471                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 472                         /* high sh */
 473                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 475                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 476                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 477                         /* low mh */
 478                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 479                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 481                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 482                         /* low mh */
 483                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 484                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 485                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 486                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 487                         /* high mh */
 488                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 490                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 491                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 492                 } else {
 493                         /* default */
 494                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 495                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 496                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 497                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 498                         /* low sh */
 499                         if (rdev->flags & RADEON_IS_MOBILITY) {
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 501                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 502                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 503                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 504                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 506                         } else {
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 508                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 509                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 510                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 511                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 512                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 513                         }
 514                         /* mid sh */
 515                         if (rdev->flags & RADEON_IS_MOBILITY) {
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 517                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 518                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 519                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 520                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 522                         } else {
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 524                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 525                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 526                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 527                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 528                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 529                         }
 530                         /* high sh */
 531                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 532                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 533                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 534                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 535                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 536                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 537                         /* low mh */
 538                         if (rdev->flags & RADEON_IS_MOBILITY) {
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 540                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 541                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 542                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 543                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 545                         } else {
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 547                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 548                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 549                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 550                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 551                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 552                         }
 553                         /* mid mh */
 554                         if (rdev->flags & RADEON_IS_MOBILITY) {
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 556                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 557                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 558                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 559                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 561                         } else {
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 563                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 564                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 565                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 566                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 567                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 568                         }
 569                         /* high mh */
 570                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 571                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 572                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 573                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 574                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 575                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 576                 }
 577         }
 578 }
 579
 580 void r600_pm_misc(struct radeon_device *rdev)
 581 {
 582         int req_ps_idx = rdev->pm.requested_power_state_index;
 583         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 584         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 585         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 586
 587         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 588                 if (voltage->voltage != rdev->pm.current_vddc) {
 589                         radeon_atom_set_voltage(rdev, voltage->voltage);
 590                         rdev->pm.current_vddc = voltage->voltage;
 591                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 592                 }
 593         }
 594 }
 595
 596 bool r600_gui_idle(struct radeon_device *rdev)
 597 {
 598         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 599                 return false;
 600         else
 601                 return true;
 602 }
 603
 604 /* hpd for digital panel detect/disconnect */
 605 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 606 {
 607         bool connected = false;
 608
 609         if (ASIC_IS_DCE3(rdev)) {
 610                 switch (hpd) {
 611                 case RADEON_HPD_1:
 612                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 613                                 connected = true;
 614                         break;
 615                 case RADEON_HPD_2:
 616                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 617                                 connected = true;
 618                         break;
 619                 case RADEON_HPD_3:
 620                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 621                                 connected = true;
 622                         break;
 623                 case RADEON_HPD_4:
 624                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 625                                 connected = true;
 626                         break;
 627                         /* DCE 3.2 */
 628                 case RADEON_HPD_5:
 629                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 630                                 connected = true;
 631                         break;
 632                 case RADEON_HPD_6:
 633                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 634                                 connected = true;
 635                         break;
 636                 default:
 637                         break;
 638                 }
 639         } else {
 640                 switch (hpd) {
 641                 case RADEON_HPD_1:
 642                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 643                                 connected = true;
 644                         break;
 645                 case RADEON_HPD_2:
 646                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 647                                 connected = true;
 648                         break;
 649                 case RADEON_HPD_3:
 650                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 651                                 connected = true;
 652                         break;
 653                 default:
 654                         break;
 655                 }
 656         }
 657         return connected;
 658 }
 659
 660 void r600_hpd_set_polarity(struct radeon_device *rdev,
 661                            enum radeon_hpd_id hpd)
 662 {
 663         u32 tmp;
 664         bool connected = r600_hpd_sense(rdev, hpd);
 665
 666         if (ASIC_IS_DCE3(rdev)) {
 667                 switch (hpd) {
 668                 case RADEON_HPD_1:
 669                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 670                         if (connected)
 671                                 tmp &= ~DC_HPDx_INT_POLARITY;
 672                         else
 673                                 tmp |= DC_HPDx_INT_POLARITY;
 674                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 675                         break;
 676                 case RADEON_HPD_2:
 677                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 678                         if (connected)
 679                                 tmp &= ~DC_HPDx_INT_POLARITY;
 680                         else
 681                                 tmp |= DC_HPDx_INT_POLARITY;
 682                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 683                         break;
 684                 case RADEON_HPD_3:
 685                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 686                         if (connected)
 687                                 tmp &= ~DC_HPDx_INT_POLARITY;
 688                         else
 689                                 tmp |= DC_HPDx_INT_POLARITY;
 690                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 691                         break;
 692                 case RADEON_HPD_4:
 693                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 694                         if (connected)
 695                                 tmp &= ~DC_HPDx_INT_POLARITY;
 696                         else
 697                                 tmp |= DC_HPDx_INT_POLARITY;
 698                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 699                         break;
 700                 case RADEON_HPD_5:
 701                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 702                         if (connected)
 703                                 tmp &= ~DC_HPDx_INT_POLARITY;
 704                         else
 705                                 tmp |= DC_HPDx_INT_POLARITY;
 706                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 707                         break;
 708                         /* DCE 3.2 */
 709                 case RADEON_HPD_6:
 710                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 711                         if (connected)
 712                                 tmp &= ~DC_HPDx_INT_POLARITY;
 713                         else
 714                                 tmp |= DC_HPDx_INT_POLARITY;
 715                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 716                         break;
 717                 default:
 718                         break;
 719                 }
 720         } else {
 721                 switch (hpd) {
 722                 case RADEON_HPD_1:
 723                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 724                         if (connected)
 725                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 726                         else
 727                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 728                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 729                         break;
 730                 case RADEON_HPD_2:
 731                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 732                         if (connected)
 733                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 734                         else
 735                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 736                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 737                         break;
 738                 case RADEON_HPD_3:
 739                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 740                         if (connected)
 741                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 742                         else
 743                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 744                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 745                         break;
 746                 default:
 747                         break;
 748                 }
 749         }
 750 }
 751
 752 void r600_hpd_init(struct radeon_device *rdev)
 753 {
 754         struct drm_device *dev = rdev->ddev;
 755         struct drm_connector *connector;
 756
 757         if (ASIC_IS_DCE3(rdev)) {
 758                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 759                 if (ASIC_IS_DCE32(rdev))
 760                         tmp |= DC_HPDx_EN;
 761
 762                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 763                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 764                         switch (radeon_connector->hpd.hpd) {
 765                         case RADEON_HPD_1:
 766                                 WREG32(DC_HPD1_CONTROL, tmp);
 767                                 rdev->irq.hpd[0] = true;
 768                                 break;
 769                         case RADEON_HPD_2:
 770                                 WREG32(DC_HPD2_CONTROL, tmp);
 771                                 rdev->irq.hpd[1] = true;
 772                                 break;
 773                         case RADEON_HPD_3:
 774                                 WREG32(DC_HPD3_CONTROL, tmp);
 775                                 rdev->irq.hpd[2] = true;
 776                                 break;
 777                         case RADEON_HPD_4:
 778                                 WREG32(DC_HPD4_CONTROL, tmp);
 779                                 rdev->irq.hpd[3] = true;
 780                                 break;
 781                                 /* DCE 3.2 */
 782                         case RADEON_HPD_5:
 783                                 WREG32(DC_HPD5_CONTROL, tmp);
 784                                 rdev->irq.hpd[4] = true;
 785                                 break;
 786                         case RADEON_HPD_6:
 787                                 WREG32(DC_HPD6_CONTROL, tmp);
 788                                 rdev->irq.hpd[5] = true;
 789                                 break;
 790                         default:
 791                                 break;
 792                         }
 793                 }
 794         } else {
 795                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 796                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 797                         switch (radeon_connector->hpd.hpd) {
 798                         case RADEON_HPD_1:
 799                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 800                                 rdev->irq.hpd[0] = true;
 801                                 break;
 802                         case RADEON_HPD_2:
 803                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 804                                 rdev->irq.hpd[1] = true;
 805                                 break;
 806                         case RADEON_HPD_3:
 807                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 808                                 rdev->irq.hpd[2] = true;
 809                                 break;
 810                         default:
 811                                 break;
 812                         }
 813                 }
 814         }
 815         if (rdev->irq.installed)
 816                 r600_irq_set(rdev);
 817 }
 818
 819 void r600_hpd_fini(struct radeon_device *rdev)
 820 {
 821         struct drm_device *dev = rdev->ddev;
 822         struct drm_connector *connector;
 823
 824         if (ASIC_IS_DCE3(rdev)) {
 825                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 826                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 827                         switch (radeon_connector->hpd.hpd) {
 828                         case RADEON_HPD_1:
 829                                 WREG32(DC_HPD1_CONTROL, 0);
 830                                 rdev->irq.hpd[0] = false;
 831                                 break;
 832                         case RADEON_HPD_2:
 833                                 WREG32(DC_HPD2_CONTROL, 0);
 834                                 rdev->irq.hpd[1] = false;
 835                                 break;
 836                         case RADEON_HPD_3:
 837                                 WREG32(DC_HPD3_CONTROL, 0);
 838                                 rdev->irq.hpd[2] = false;
 839                                 break;
 840                         case RADEON_HPD_4:
 841                                 WREG32(DC_HPD4_CONTROL, 0);
 842                                 rdev->irq.hpd[3] = false;
 843                                 break;
 844                                 /* DCE 3.2 */
 845                         case RADEON_HPD_5:
 846                                 WREG32(DC_HPD5_CONTROL, 0);
 847                                 rdev->irq.hpd[4] = false;
 848                                 break;
 849                         case RADEON_HPD_6:
 850                                 WREG32(DC_HPD6_CONTROL, 0);
 851                                 rdev->irq.hpd[5] = false;
 852                                 break;
 853                         default:
 854                                 break;
 855                         }
 856                 }
 857         } else {
 858                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 859                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 860                         switch (radeon_connector->hpd.hpd) {
 861                         case RADEON_HPD_1:
 862                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 863                                 rdev->irq.hpd[0] = false;
 864                                 break;
 865                         case RADEON_HPD_2:
 866                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 867                                 rdev->irq.hpd[1] = false;
 868                                 break;
 869                         case RADEON_HPD_3:
 870                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 871                                 rdev->irq.hpd[2] = false;
 872                                 break;
 873                         default:
 874                                 break;
 875                         }
 876                 }
 877         }
 878 }
 879
 880 /*
 881  * R600 PCIE GART
 882  */
 883 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 884 {
 885         unsigned i;
 886         u32 tmp;
 887
 888         /* flush hdp cache so updates hit vram */
 889         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 890             !(rdev->flags & RADEON_IS_AGP)) {
 891                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 892                 u32 tmp;
 893
 894                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 895                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 896                  * This seems to cause problems on some AGP cards. Just use the old
 897                  * method for them.
 898                  */
 899                 WREG32(HDP_DEBUG1, 0);
 900                 tmp = readl((void __iomem *)ptr);
 901         } else
 902                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 903
 904         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 905         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 906         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 907         for (i = 0; i < rdev->usec_timeout; i++) {
 908                 /* read MC_STATUS */
 909                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 910                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 911                 if (tmp == 2) {
 912                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 913                         return;
 914                 }
 915                 if (tmp) {
 916                         return;
 917                 }
 918                 udelay(1);
 919         }
 920 }
 921
 922 int r600_pcie_gart_init(struct radeon_device *rdev)
 923 {
 924         int r;
 925
 926         if (rdev->gart.table.vram.robj) {
 927                 WARN(1, "R600 PCIE GART already initialized\n");
 928                 return 0;
 929         }
 930         /* Initialize common gart structure */
 931         r = radeon_gart_init(rdev);
 932         if (r)
 933                 return r;
 934         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 935         return radeon_gart_table_vram_alloc(rdev);
 936 }
 937
 938 int r600_pcie_gart_enable(struct radeon_device *rdev)
 939 {
 940         u32 tmp;
 941         int r, i;
 942
 943         if (rdev->gart.table.vram.robj == NULL) {
 944                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 945                 return -EINVAL;
 946         }
 947         r = radeon_gart_table_vram_pin(rdev);
 948         if (r)
 949                 return r;
 950         radeon_gart_restore(rdev);
 951
 952         /* Setup L2 cache */
 953         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 954                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 955                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 956         WREG32(VM_L2_CNTL2, 0);
 957         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 958         /* Setup TLB control */
 959         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 960                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 961                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 962                 ENABLE_WAIT_L2_QUERY;
 963         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 966         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 971         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 972         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 973         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 974         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 976         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 977         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 978         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 979         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 980         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 981                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 982         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 983                         (u32)(rdev->dummy_page.addr >> 12));
 984         for (i = 1; i < 7; i++)
 985                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 986
 987         r600_pcie_gart_tlb_flush(rdev);
 988         rdev->gart.ready = true;
 989         return 0;
 990 }
 991
 992 void r600_pcie_gart_disable(struct radeon_device *rdev)
 993 {
 994         u32 tmp;
 995         int i, r;
 996
 997         /* Disable all tables */
 998         for (i = 0; i < 7; i++)
 999                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1000
1001         /* Disable L2 cache */
1002         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1003                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1004         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1005         /* Setup L1 TLB control */
1006         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1007                 ENABLE_WAIT_L2_QUERY;
1008         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1017         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1018         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1019         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1022         if (rdev->gart.table.vram.robj) {
1023                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1024                 if (likely(r == 0)) {
1025                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1026                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1027                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1028                 }
1029         }
1030 }
1031
1032 void r600_pcie_gart_fini(struct radeon_device *rdev)
1033 {
1034         radeon_gart_fini(rdev);
1035         r600_pcie_gart_disable(rdev);
1036         radeon_gart_table_vram_free(rdev);
1037 }
1038
1039 void r600_agp_enable(struct radeon_device *rdev)
1040 {
1041         u32 tmp;
1042         int i;
1043
1044         /* Setup L2 cache */
1045         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1046                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1047                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1048         WREG32(VM_L2_CNTL2, 0);
1049         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1050         /* Setup TLB control */
1051         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1052                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1053                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1054                 ENABLE_WAIT_L2_QUERY;
1055         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1058         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1059         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1063         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1064         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1065         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1066         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1067         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1068         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1069         for (i = 0; i < 7; i++)
1070                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1071 }
1072
1073 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1074 {
1075         unsigned i;
1076         u32 tmp;
1077
1078         for (i = 0; i < rdev->usec_timeout; i++) {
1079                 /* read MC_STATUS */
1080                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1081                 if (!tmp)
1082                         return 0;
1083                 udelay(1);
1084         }
1085         return -1;
1086 }
1087
1088 static void r600_mc_program(struct radeon_device *rdev)
1089 {
1090         struct rv515_mc_save save;
1091         u32 tmp;
1092         int i, j;
1093
1094         /* Initialize HDP */
1095         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1096                 WREG32((0x2c14 + j), 0x00000000);
1097                 WREG32((0x2c18 + j), 0x00000000);
1098                 WREG32((0x2c1c + j), 0x00000000);
1099                 WREG32((0x2c20 + j), 0x00000000);
1100                 WREG32((0x2c24 + j), 0x00000000);
1101         }
1102         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1103
1104         rv515_mc_stop(rdev, &save);
1105         if (r600_mc_wait_for_idle(rdev)) {
1106                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1107         }
1108         /* Lockout access through VGA aperture (doesn't exist before R600) */
1109         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1110         /* Update configuration */
1111         if (rdev->flags & RADEON_IS_AGP) {
1112                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1113                         /* VRAM before AGP */
1114                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1115                                 rdev->mc.vram_start >> 12);
1116                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1117                                 rdev->mc.gtt_end >> 12);
1118                 } else {
1119                         /* VRAM after AGP */
1120                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1121                                 rdev->mc.gtt_start >> 12);
1122                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1123                                 rdev->mc.vram_end >> 12);
1124                 }
1125         } else {
1126                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1127                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1128         }
1129         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1130         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1131         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1132         WREG32(MC_VM_FB_LOCATION, tmp);
1133         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1134         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1135         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1136         if (rdev->flags & RADEON_IS_AGP) {
1137                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1138                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1139                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1140         } else {
1141                 WREG32(MC_VM_AGP_BASE, 0);
1142                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1143                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1144         }
1145         if (r600_mc_wait_for_idle(rdev)) {
1146                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1147         }
1148         rv515_mc_resume(rdev, &save);
1149         /* we need to own VRAM, so turn off the VGA renderer here
1150          * to stop it overwriting our objects */
1151         rv515_vga_render_disable(rdev);
1152 }
1153
1154 /**
1155  * r600_vram_gtt_location - try to find VRAM & GTT location
1156  * @rdev: radeon device structure holding all necessary informations
1157  * @mc: memory controller structure holding memory informations
1158  *
1159  * Function will place try to place VRAM at same place as in CPU (PCI)
1160  * address space as some GPU seems to have issue when we reprogram at
1161  * different address space.
1162  *
1163  * If there is not enough space to fit the unvisible VRAM after the
1164  * aperture then we limit the VRAM size to the aperture.
1165  *
1166  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1167  * them to be in one from GPU point of view so that we can program GPU to
1168  * catch access outside them (weird GPU policy see ??).
1169  *
1170  * This function will never fails, worst case are limiting VRAM or GTT.
1171  *
1172  * Note: GTT start, end, size should be initialized before calling this
1173  * function on AGP platform.
1174  */
1175 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1176 {
1177         u64 size_bf, size_af;
1178
1179         if (mc->mc_vram_size > 0xE0000000) {
1180                 /* leave room for at least 512M GTT */
1181                 dev_warn(rdev->dev, "limiting VRAM\n");
1182                 mc->real_vram_size = 0xE0000000;
1183                 mc->mc_vram_size = 0xE0000000;
1184         }
1185         if (rdev->flags & RADEON_IS_AGP) {
1186                 size_bf = mc->gtt_start;
1187                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1188                 if (size_bf > size_af) {
1189                         if (mc->mc_vram_size > size_bf) {
1190                                 dev_warn(rdev->dev, "limiting VRAM\n");
1191                                 mc->real_vram_size = size_bf;
1192                                 mc->mc_vram_size = size_bf;
1193                         }
1194                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1195                 } else {
1196                         if (mc->mc_vram_size > size_af) {
1197                                 dev_warn(rdev->dev, "limiting VRAM\n");
1198                                 mc->real_vram_size = size_af;
1199                                 mc->mc_vram_size = size_af;
1200                         }
1201                         mc->vram_start = mc->gtt_end;
1202                 }
1203                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1204                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1205                                 mc->mc_vram_size >> 20, mc->vram_start,
1206                                 mc->vram_end, mc->real_vram_size >> 20);
1207         } else {
1208                 u64 base = 0;
1209                 if (rdev->flags & RADEON_IS_IGP) {
1210                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1211                         base <<= 24;
1212                 }
1213                 radeon_vram_location(rdev, &rdev->mc, base);
1214                 rdev->mc.gtt_base_align = 0;
1215                 radeon_gtt_location(rdev, mc);
1216         }
1217 }
1218
1219 int r600_mc_init(struct radeon_device *rdev)
1220 {
1221         u32 tmp;
1222         int chansize, numchan;
1223
1224         /* Get VRAM informations */
1225         rdev->mc.vram_is_ddr = true;
1226         tmp = RREG32(RAMCFG);
1227         if (tmp & CHANSIZE_OVERRIDE) {
1228                 chansize = 16;
1229         } else if (tmp & CHANSIZE_MASK) {
1230                 chansize = 64;
1231         } else {
1232                 chansize = 32;
1233         }
1234         tmp = RREG32(CHMAP);
1235         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1236         case 0:
1237         default:
1238                 numchan = 1;
1239                 break;
1240         case 1:
1241                 numchan = 2;
1242                 break;
1243         case 2:
1244                 numchan = 4;
1245                 break;
1246         case 3:
1247                 numchan = 8;
1248                 break;
1249         }
1250         rdev->mc.vram_width = numchan * chansize;
1251         /* Could aper size report 0 ? */
1252         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1253         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1254         /* Setup GPU memory space */
1255         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1256         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1257         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1258         r600_vram_gtt_location(rdev, &rdev->mc);
1259
1260         if (rdev->flags & RADEON_IS_IGP) {
1261                 rs690_pm_info(rdev);
1262                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1263         }
1264         radeon_update_bandwidth_info(rdev);
1265         return 0;
1266 }
1267
1268 /* We doesn't check that the GPU really needs a reset we simply do the
1269  * reset, it's up to the caller to determine if the GPU needs one. We
1270  * might add an helper function to check that.
1271  */
1272 int r600_gpu_soft_reset(struct radeon_device *rdev)
1273 {
1274         struct rv515_mc_save save;
1275         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1276                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1277                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1278                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1279                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1280                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1281                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1282                                 S_008010_GUI_ACTIVE(1);
1283         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1284                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1285                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1286                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1287                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1288                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1289                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1290                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1291         u32 tmp;
1292
1293         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1294                 return 0;
1295
1296         dev_info(rdev->dev, "GPU softreset \n");
1297         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1298                 RREG32(R_008010_GRBM_STATUS));
1299         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1300                 RREG32(R_008014_GRBM_STATUS2));
1301         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1302                 RREG32(R_000E50_SRBM_STATUS));
1303         rv515_mc_stop(rdev, &save);
1304         if (r600_mc_wait_for_idle(rdev)) {
1305                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1306         }
1307         /* Disable CP parsing/prefetching */
1308         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1309         /* Check if any of the rendering block is busy and reset it */
1310         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1311             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1312                 tmp = S_008020_SOFT_RESET_CR(1) |
1313                         S_008020_SOFT_RESET_DB(1) |
1314                         S_008020_SOFT_RESET_CB(1) |
1315                         S_008020_SOFT_RESET_PA(1) |
1316                         S_008020_SOFT_RESET_SC(1) |
1317                         S_008020_SOFT_RESET_SMX(1) |
1318                         S_008020_SOFT_RESET_SPI(1) |
1319                         S_008020_SOFT_RESET_SX(1) |
1320                         S_008020_SOFT_RESET_SH(1) |
1321                         S_008020_SOFT_RESET_TC(1) |
1322                         S_008020_SOFT_RESET_TA(1) |
1323                         S_008020_SOFT_RESET_VC(1) |
1324                         S_008020_SOFT_RESET_VGT(1);
1325                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1326                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1327                 RREG32(R_008020_GRBM_SOFT_RESET);
1328                 mdelay(15);
1329                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1330         }
1331         /* Reset CP (we always reset CP) */
1332         tmp = S_008020_SOFT_RESET_CP(1);
1333         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1334         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1335         RREG32(R_008020_GRBM_SOFT_RESET);
1336         mdelay(15);
1337         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1338         /* Wait a little for things to settle down */
1339         mdelay(1);
1340         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1341                 RREG32(R_008010_GRBM_STATUS));
1342         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1343                 RREG32(R_008014_GRBM_STATUS2));
1344         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1345                 RREG32(R_000E50_SRBM_STATUS));
1346         rv515_mc_resume(rdev, &save);
1347         return 0;
1348 }
1349
1350 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1351 {
1352         u32 srbm_status;
1353         u32 grbm_status;
1354         u32 grbm_status2;
1355         struct r100_gpu_lockup *lockup;
1356         int r;
1357
1358         if (rdev->family >= CHIP_RV770)
1359                 lockup = &rdev->config.rv770.lockup;
1360         else
1361                 lockup = &rdev->config.r600.lockup;
1362
1363         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1364         grbm_status = RREG32(R_008010_GRBM_STATUS);
1365         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1366         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1367                 r100_gpu_lockup_update(lockup, &rdev->cp);
1368                 return false;
1369         }
1370         /* force CP activities */
1371         r = radeon_ring_lock(rdev, 2);
1372         if (!r) {
1373                 /* PACKET2 NOP */
1374                 radeon_ring_write(rdev, 0x80000000);
1375                 radeon_ring_write(rdev, 0x80000000);
1376                 radeon_ring_unlock_commit(rdev);
1377         }
1378         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1379         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1380 }
1381
1382 int r600_asic_reset(struct radeon_device *rdev)
1383 {
1384         return r600_gpu_soft_reset(rdev);
1385 }
1386
1387 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1388                                              u32 num_backends,
1389                                              u32 backend_disable_mask)
1390 {
1391         u32 backend_map = 0;
1392         u32 enabled_backends_mask;
1393         u32 enabled_backends_count;
1394         u32 cur_pipe;
1395         u32 swizzle_pipe[R6XX_MAX_PIPES];
1396         u32 cur_backend;
1397         u32 i;
1398
1399         if (num_tile_pipes > R6XX_MAX_PIPES)
1400                 num_tile_pipes = R6XX_MAX_PIPES;
1401         if (num_tile_pipes < 1)
1402                 num_tile_pipes = 1;
1403         if (num_backends > R6XX_MAX_BACKENDS)
1404                 num_backends = R6XX_MAX_BACKENDS;
1405         if (num_backends < 1)
1406                 num_backends = 1;
1407
1408         enabled_backends_mask = 0;
1409         enabled_backends_count = 0;
1410         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1411                 if (((backend_disable_mask >> i) & 1) == 0) {
1412                         enabled_backends_mask |= (1 << i);
1413                         ++enabled_backends_count;
1414                 }
1415                 if (enabled_backends_count == num_backends)
1416                         break;
1417         }
1418
1419         if (enabled_backends_count == 0) {
1420                 enabled_backends_mask = 1;
1421                 enabled_backends_count = 1;
1422         }
1423
1424         if (enabled_backends_count != num_backends)
1425                 num_backends = enabled_backends_count;
1426
1427         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1428         switch (num_tile_pipes) {
1429         case 1:
1430                 swizzle_pipe[0] = 0;
1431                 break;
1432         case 2:
1433                 swizzle_pipe[0] = 0;
1434                 swizzle_pipe[1] = 1;
1435                 break;
1436         case 3:
1437                 swizzle_pipe[0] = 0;
1438                 swizzle_pipe[1] = 1;
1439                 swizzle_pipe[2] = 2;
1440                 break;
1441         case 4:
1442                 swizzle_pipe[0] = 0;
1443                 swizzle_pipe[1] = 1;
1444                 swizzle_pipe[2] = 2;
1445                 swizzle_pipe[3] = 3;
1446                 break;
1447         case 5:
1448                 swizzle_pipe[0] = 0;
1449                 swizzle_pipe[1] = 1;
1450                 swizzle_pipe[2] = 2;
1451                 swizzle_pipe[3] = 3;
1452                 swizzle_pipe[4] = 4;
1453                 break;
1454         case 6:
1455                 swizzle_pipe[0] = 0;
1456                 swizzle_pipe[1] = 2;
1457                 swizzle_pipe[2] = 4;
1458                 swizzle_pipe[3] = 5;
1459                 swizzle_pipe[4] = 1;
1460                 swizzle_pipe[5] = 3;
1461                 break;
1462         case 7:
1463                 swizzle_pipe[0] = 0;
1464                 swizzle_pipe[1] = 2;
1465                 swizzle_pipe[2] = 4;
1466                 swizzle_pipe[3] = 6;
1467                 swizzle_pipe[4] = 1;
1468                 swizzle_pipe[5] = 3;
1469                 swizzle_pipe[6] = 5;
1470                 break;
1471         case 8:
1472                 swizzle_pipe[0] = 0;
1473                 swizzle_pipe[1] = 2;
1474                 swizzle_pipe[2] = 4;
1475                 swizzle_pipe[3] = 6;
1476                 swizzle_pipe[4] = 1;
1477                 swizzle_pipe[5] = 3;
1478                 swizzle_pipe[6] = 5;
1479                 swizzle_pipe[7] = 7;
1480                 break;
1481         }
1482
1483         cur_backend = 0;
1484         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1485                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1486                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1487
1488                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1489
1490                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1491         }
1492
1493         return backend_map;
1494 }
1495
1496 int r600_count_pipe_bits(uint32_t val)
1497 {
1498         int i, ret = 0;
1499
1500         for (i = 0; i < 32; i++) {
1501                 ret += val & 1;
1502                 val >>= 1;
1503         }
1504         return ret;
1505 }
1506
1507 void r600_gpu_init(struct radeon_device *rdev)
1508 {
1509         u32 tiling_config;
1510         u32 ramcfg;
1511         u32 backend_map;
1512         u32 cc_rb_backend_disable;
1513         u32 cc_gc_shader_pipe_config;
1514         u32 tmp;
1515         int i, j;
1516         u32 sq_config;
1517         u32 sq_gpr_resource_mgmt_1 = 0;
1518         u32 sq_gpr_resource_mgmt_2 = 0;
1519         u32 sq_thread_resource_mgmt = 0;
1520         u32 sq_stack_resource_mgmt_1 = 0;
1521         u32 sq_stack_resource_mgmt_2 = 0;
1522
1523         /* FIXME: implement */
1524         switch (rdev->family) {
1525         case CHIP_R600:
1526                 rdev->config.r600.max_pipes = 4;
1527                 rdev->config.r600.max_tile_pipes = 8;
1528                 rdev->config.r600.max_simds = 4;
1529                 rdev->config.r600.max_backends = 4;
1530                 rdev->config.r600.max_gprs = 256;
1531                 rdev->config.r600.max_threads = 192;
1532                 rdev->config.r600.max_stack_entries = 256;
1533                 rdev->config.r600.max_hw_contexts = 8;
1534                 rdev->config.r600.max_gs_threads = 16;
1535                 rdev->config.r600.sx_max_export_size = 128;
1536                 rdev->config.r600.sx_max_export_pos_size = 16;
1537                 rdev->config.r600.sx_max_export_smx_size = 128;
1538                 rdev->config.r600.sq_num_cf_insts = 2;
1539                 break;
1540         case CHIP_RV630:
1541         case CHIP_RV635:
1542                 rdev->config.r600.max_pipes = 2;
1543                 rdev->config.r600.max_tile_pipes = 2;
1544                 rdev->config.r600.max_simds = 3;
1545                 rdev->config.r600.max_backends = 1;
1546                 rdev->config.r600.max_gprs = 128;
1547                 rdev->config.r600.max_threads = 192;
1548                 rdev->config.r600.max_stack_entries = 128;
1549                 rdev->config.r600.max_hw_contexts = 8;
1550                 rdev->config.r600.max_gs_threads = 4;
1551                 rdev->config.r600.sx_max_export_size = 128;
1552                 rdev->config.r600.sx_max_export_pos_size = 16;
1553                 rdev->config.r600.sx_max_export_smx_size = 128;
1554                 rdev->config.r600.sq_num_cf_insts = 2;
1555                 break;
1556         case CHIP_RV610:
1557         case CHIP_RV620:
1558         case CHIP_RS780:
1559         case CHIP_RS880:
1560                 rdev->config.r600.max_pipes = 1;
1561                 rdev->config.r600.max_tile_pipes = 1;
1562                 rdev->config.r600.max_simds = 2;
1563                 rdev->config.r600.max_backends = 1;
1564                 rdev->config.r600.max_gprs = 128;
1565                 rdev->config.r600.max_threads = 192;
1566                 rdev->config.r600.max_stack_entries = 128;
1567                 rdev->config.r600.max_hw_contexts = 4;
1568                 rdev->config.r600.max_gs_threads = 4;
1569                 rdev->config.r600.sx_max_export_size = 128;
1570                 rdev->config.r600.sx_max_export_pos_size = 16;
1571                 rdev->config.r600.sx_max_export_smx_size = 128;
1572                 rdev->config.r600.sq_num_cf_insts = 1;
1573                 break;
1574         case CHIP_RV670:
1575                 rdev->config.r600.max_pipes = 4;
1576                 rdev->config.r600.max_tile_pipes = 4;
1577                 rdev->config.r600.max_simds = 4;
1578                 rdev->config.r600.max_backends = 4;
1579                 rdev->config.r600.max_gprs = 192;
1580                 rdev->config.r600.max_threads = 192;
1581                 rdev->config.r600.max_stack_entries = 256;
1582                 rdev->config.r600.max_hw_contexts = 8;
1583                 rdev->config.r600.max_gs_threads = 16;
1584                 rdev->config.r600.sx_max_export_size = 128;
1585                 rdev->config.r600.sx_max_export_pos_size = 16;
1586                 rdev->config.r600.sx_max_export_smx_size = 128;
1587                 rdev->config.r600.sq_num_cf_insts = 2;
1588                 break;
1589         default:
1590                 break;
1591         }
1592
1593         /* Initialize HDP */
1594         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1595                 WREG32((0x2c14 + j), 0x00000000);
1596                 WREG32((0x2c18 + j), 0x00000000);
1597                 WREG32((0x2c1c + j), 0x00000000);
1598                 WREG32((0x2c20 + j), 0x00000000);
1599                 WREG32((0x2c24 + j), 0x00000000);
1600         }
1601
1602         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1603
1604         /* Setup tiling */
1605         tiling_config = 0;
1606         ramcfg = RREG32(RAMCFG);
1607         switch (rdev->config.r600.max_tile_pipes) {
1608         case 1:
1609                 tiling_config |= PIPE_TILING(0);
1610                 break;
1611         case 2:
1612                 tiling_config |= PIPE_TILING(1);
1613                 break;
1614         case 4:
1615                 tiling_config |= PIPE_TILING(2);
1616                 break;
1617         case 8:
1618                 tiling_config |= PIPE_TILING(3);
1619                 break;
1620         default:
1621                 break;
1622         }
1623         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1624         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1625         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1626         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1627         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1628                 rdev->config.r600.tiling_group_size = 512;
1629         else
1630                 rdev->config.r600.tiling_group_size = 256;
1631         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1632         if (tmp > 3) {
1633                 tiling_config |= ROW_TILING(3);
1634                 tiling_config |= SAMPLE_SPLIT(3);
1635         } else {
1636                 tiling_config |= ROW_TILING(tmp);
1637                 tiling_config |= SAMPLE_SPLIT(tmp);
1638         }
1639         tiling_config |= BANK_SWAPS(1);
1640
1641         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1642         cc_rb_backend_disable |=
1643                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1644
1645         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1646         cc_gc_shader_pipe_config |=
1647                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1648         cc_gc_shader_pipe_config |=
1649                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1650
1651         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1652                                                         (R6XX_MAX_BACKENDS -
1653                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1654                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1655                                                         (cc_rb_backend_disable >> 16));
1656         rdev->config.r600.tile_config = tiling_config;
1657         tiling_config |= BACKEND_MAP(backend_map);
1658         WREG32(GB_TILING_CONFIG, tiling_config);
1659         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1660         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1661
1662         /* Setup pipes */
1663         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1664         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1665         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1666
1667         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1668         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1669         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1670
1671         /* Setup some CP states */
1672         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1673         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1674
1675         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1676                              SYNC_WALKER | SYNC_ALIGNER));
1677         /* Setup various GPU states */
1678         if (rdev->family == CHIP_RV670)
1679                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1680
1681         tmp = RREG32(SX_DEBUG_1);
1682         tmp |= SMX_EVENT_RELEASE;
1683         if ((rdev->family > CHIP_R600))
1684                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1685         WREG32(SX_DEBUG_1, tmp);
1686
1687         if (((rdev->family) == CHIP_R600) ||
1688             ((rdev->family) == CHIP_RV630) ||
1689             ((rdev->family) == CHIP_RV610) ||
1690             ((rdev->family) == CHIP_RV620) ||
1691             ((rdev->family) == CHIP_RS780) ||
1692             ((rdev->family) == CHIP_RS880)) {
1693                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1694         } else {
1695                 WREG32(DB_DEBUG, 0);
1696         }
1697         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1698                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1699
1700         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1701         WREG32(VGT_NUM_INSTANCES, 0);
1702
1703         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1704         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1705
1706         tmp = RREG32(SQ_MS_FIFO_SIZES);
1707         if (((rdev->family) == CHIP_RV610) ||
1708             ((rdev->family) == CHIP_RV620) ||
1709             ((rdev->family) == CHIP_RS780) ||
1710             ((rdev->family) == CHIP_RS880)) {
1711                 tmp = (CACHE_FIFO_SIZE(0xa) |
1712                        FETCH_FIFO_HIWATER(0xa) |
1713                        DONE_FIFO_HIWATER(0xe0) |
1714                        ALU_UPDATE_FIFO_HIWATER(0x8));
1715         } else if (((rdev->family) == CHIP_R600) ||
1716                    ((rdev->family) == CHIP_RV630)) {
1717                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1718                 tmp |= DONE_FIFO_HIWATER(0x4);
1719         }
1720         WREG32(SQ_MS_FIFO_SIZES, tmp);
1721
1722         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1723          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1724          */
1725         sq_config = RREG32(SQ_CONFIG);
1726         sq_config &= ~(PS_PRIO(3) |
1727                        VS_PRIO(3) |
1728                        GS_PRIO(3) |
1729                        ES_PRIO(3));
1730         sq_config |= (DX9_CONSTS |
1731                       VC_ENABLE |
1732                       PS_PRIO(0) |
1733                       VS_PRIO(1) |
1734                       GS_PRIO(2) |
1735                       ES_PRIO(3));
1736
1737         if ((rdev->family) == CHIP_R600) {
1738                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1739                                           NUM_VS_GPRS(124) |
1740                                           NUM_CLAUSE_TEMP_GPRS(4));
1741                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1742                                           NUM_ES_GPRS(0));
1743                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1744                                            NUM_VS_THREADS(48) |
1745                                            NUM_GS_THREADS(4) |
1746                                            NUM_ES_THREADS(4));
1747                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1748                                             NUM_VS_STACK_ENTRIES(128));
1749                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1750                                             NUM_ES_STACK_ENTRIES(0));
1751         } else if (((rdev->family) == CHIP_RV610) ||
1752                    ((rdev->family) == CHIP_RV620) ||
1753                    ((rdev->family) == CHIP_RS780) ||
1754                    ((rdev->family) == CHIP_RS880)) {
1755                 /* no vertex cache */
1756                 sq_config &= ~VC_ENABLE;
1757
1758                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1759                                           NUM_VS_GPRS(44) |
1760                                           NUM_CLAUSE_TEMP_GPRS(2));
1761                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1762                                           NUM_ES_GPRS(17));
1763                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1764                                            NUM_VS_THREADS(78) |
1765                                            NUM_GS_THREADS(4) |
1766                                            NUM_ES_THREADS(31));
1767                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1768                                             NUM_VS_STACK_ENTRIES(40));
1769                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1770                                             NUM_ES_STACK_ENTRIES(16));
1771         } else if (((rdev->family) == CHIP_RV630) ||
1772                    ((rdev->family) == CHIP_RV635)) {
1773                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1774                                           NUM_VS_GPRS(44) |
1775                                           NUM_CLAUSE_TEMP_GPRS(2));
1776                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1777                                           NUM_ES_GPRS(18));
1778                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1779                                            NUM_VS_THREADS(78) |
1780                                            NUM_GS_THREADS(4) |
1781                                            NUM_ES_THREADS(31));
1782                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1783                                             NUM_VS_STACK_ENTRIES(40));
1784                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1785                                             NUM_ES_STACK_ENTRIES(16));
1786         } else if ((rdev->family) == CHIP_RV670) {
1787                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1788                                           NUM_VS_GPRS(44) |
1789                                           NUM_CLAUSE_TEMP_GPRS(2));
1790                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1791                                           NUM_ES_GPRS(17));
1792                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1793                                            NUM_VS_THREADS(78) |
1794                                            NUM_GS_THREADS(4) |
1795                                            NUM_ES_THREADS(31));
1796                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1797                                             NUM_VS_STACK_ENTRIES(64));
1798                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1799                                             NUM_ES_STACK_ENTRIES(64));
1800         }
1801
1802         WREG32(SQ_CONFIG, sq_config);
1803         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1804         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1805         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1806         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1807         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1808
1809         if (((rdev->family) == CHIP_RV610) ||
1810             ((rdev->family) == CHIP_RV620) ||
1811             ((rdev->family) == CHIP_RS780) ||
1812             ((rdev->family) == CHIP_RS880)) {
1813                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1814         } else {
1815                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1816         }
1817
1818         /* More default values. 2D/3D driver should adjust as needed */
1819         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1820                                          S1_X(0x4) | S1_Y(0xc)));
1821         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1822                                          S1_X(0x2) | S1_Y(0x2) |
1823                                          S2_X(0xa) | S2_Y(0x6) |
1824                                          S3_X(0x6) | S3_Y(0xa)));
1825         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1826                                              S1_X(0x4) | S1_Y(0xc) |
1827                                              S2_X(0x1) | S2_Y(0x6) |
1828                                              S3_X(0xa) | S3_Y(0xe)));
1829         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1830                                              S5_X(0x0) | S5_Y(0x0) |
1831                                              S6_X(0xb) | S6_Y(0x4) |
1832                                              S7_X(0x7) | S7_Y(0x8)));
1833
1834         WREG32(VGT_STRMOUT_EN, 0);
1835         tmp = rdev->config.r600.max_pipes * 16;
1836         switch (rdev->family) {
1837         case CHIP_RV610:
1838         case CHIP_RV620:
1839         case CHIP_RS780:
1840         case CHIP_RS880:
1841                 tmp += 32;
1842                 break;
1843         case CHIP_RV670:
1844                 tmp += 128;
1845                 break;
1846         default:
1847                 break;
1848         }
1849         if (tmp > 256) {
1850                 tmp = 256;
1851         }
1852         WREG32(VGT_ES_PER_GS, 128);
1853         WREG32(VGT_GS_PER_ES, tmp);
1854         WREG32(VGT_GS_PER_VS, 2);
1855         WREG32(VGT_GS_VERTEX_REUSE, 16);
1856
1857         /* more default values. 2D/3D driver should adjust as needed */
1858         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1859         WREG32(VGT_STRMOUT_EN, 0);
1860         WREG32(SX_MISC, 0);
1861         WREG32(PA_SC_MODE_CNTL, 0);
1862         WREG32(PA_SC_AA_CONFIG, 0);
1863         WREG32(PA_SC_LINE_STIPPLE, 0);
1864         WREG32(SPI_INPUT_Z, 0);
1865         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1866         WREG32(CB_COLOR7_FRAG, 0);
1867
1868         /* Clear render buffer base addresses */
1869         WREG32(CB_COLOR0_BASE, 0);
1870         WREG32(CB_COLOR1_BASE, 0);
1871         WREG32(CB_COLOR2_BASE, 0);
1872         WREG32(CB_COLOR3_BASE, 0);
1873         WREG32(CB_COLOR4_BASE, 0);
1874         WREG32(CB_COLOR5_BASE, 0);
1875         WREG32(CB_COLOR6_BASE, 0);
1876         WREG32(CB_COLOR7_BASE, 0);
1877         WREG32(CB_COLOR7_FRAG, 0);
1878
1879         switch (rdev->family) {
1880         case CHIP_RV610:
1881         case CHIP_RV620:
1882         case CHIP_RS780:
1883         case CHIP_RS880:
1884                 tmp = TC_L2_SIZE(8);
1885                 break;
1886         case CHIP_RV630:
1887         case CHIP_RV635:
1888                 tmp = TC_L2_SIZE(4);
1889                 break;
1890         case CHIP_R600:
1891                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1892                 break;
1893         default:
1894                 tmp = TC_L2_SIZE(0);
1895                 break;
1896         }
1897         WREG32(TC_CNTL, tmp);
1898
1899         tmp = RREG32(HDP_HOST_PATH_CNTL);
1900         WREG32(HDP_HOST_PATH_CNTL, tmp);
1901
1902         tmp = RREG32(ARB_POP);
1903         tmp |= ENABLE_TC128;
1904         WREG32(ARB_POP, tmp);
1905
1906         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1907         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1908                                NUM_CLIP_SEQ(3)));
1909         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1910 }
1911
1912
1913 /*
1914  * Indirect registers accessor
1915  */
1916 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1917 {
1918         u32 r;
1919
1920         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1921         (void)RREG32(PCIE_PORT_INDEX);
1922         r = RREG32(PCIE_PORT_DATA);
1923         return r;
1924 }
1925
1926 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1927 {
1928         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1929         (void)RREG32(PCIE_PORT_INDEX);
1930         WREG32(PCIE_PORT_DATA, (v));
1931         (void)RREG32(PCIE_PORT_DATA);
1932 }
1933
1934 /*
1935  * CP & Ring
1936  */
1937 void r600_cp_stop(struct radeon_device *rdev)
1938 {
1939         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1940         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1941         WREG32(SCRATCH_UMSK, 0);
1942 }
1943
1944 int r600_init_microcode(struct radeon_device *rdev)
1945 {
1946         struct platform_device *pdev;
1947         const char *chip_name;
1948         const char *rlc_chip_name;
1949         size_t pfp_req_size, me_req_size, rlc_req_size;
1950         char fw_name[30];
1951         int err;
1952
1953         DRM_DEBUG("\n");
1954
1955         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1956         err = IS_ERR(pdev);
1957         if (err) {
1958                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1959                 return -EINVAL;
1960         }
1961
1962         switch (rdev->family) {
1963         case CHIP_R600:
1964                 chip_name = "R600";
1965                 rlc_chip_name = "R600";
1966                 break;
1967         case CHIP_RV610:
1968                 chip_name = "RV610";
1969                 rlc_chip_name = "R600";
1970                 break;
1971         case CHIP_RV630:
1972                 chip_name = "RV630";
1973                 rlc_chip_name = "R600";
1974                 break;
1975         case CHIP_RV620:
1976                 chip_name = "RV620";
1977                 rlc_chip_name = "R600";
1978                 break;
1979         case CHIP_RV635:
1980                 chip_name = "RV635";
1981                 rlc_chip_name = "R600";
1982                 break;
1983         case CHIP_RV670:
1984                 chip_name = "RV670";
1985                 rlc_chip_name = "R600";
1986                 break;
1987         case CHIP_RS780:
1988         case CHIP_RS880:
1989                 chip_name = "RS780";
1990                 rlc_chip_name = "R600";
1991                 break;
1992         case CHIP_RV770:
1993                 chip_name = "RV770";
1994                 rlc_chip_name = "R700";
1995                 break;
1996         case CHIP_RV730:
1997         case CHIP_RV740:
1998                 chip_name = "RV730";
1999                 rlc_chip_name = "R700";
2000                 break;
2001         case CHIP_RV710:
2002                 chip_name = "RV710";
2003                 rlc_chip_name = "R700";
2004                 break;
2005         case CHIP_CEDAR:
2006                 chip_name = "CEDAR";
2007                 rlc_chip_name = "CEDAR";
2008                 break;
2009         case CHIP_REDWOOD:
2010                 chip_name = "REDWOOD";
2011                 rlc_chip_name = "REDWOOD";
2012                 break;
2013         case CHIP_JUNIPER:
2014                 chip_name = "JUNIPER";
2015                 rlc_chip_name = "JUNIPER";
2016                 break;
2017         case CHIP_CYPRESS:
2018         case CHIP_HEMLOCK:
2019                 chip_name = "CYPRESS";
2020                 rlc_chip_name = "CYPRESS";
2021                 break;
2022         case CHIP_PALM:
2023                 chip_name = "PALM";
2024                 rlc_chip_name = "SUMO";
2025                 break;
2026         default: BUG();
2027         }
2028
2029         if (rdev->family >= CHIP_CEDAR) {
2030                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2031                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2032                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2033         } else if (rdev->family >= CHIP_RV770) {
2034                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2035                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2036                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2037         } else {
2038                 pfp_req_size = PFP_UCODE_SIZE * 4;
2039                 me_req_size = PM4_UCODE_SIZE * 12;
2040                 rlc_req_size = RLC_UCODE_SIZE * 4;
2041         }
2042
2043         DRM_INFO("Loading %s Microcode\n", chip_name);
2044
2045         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2046         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2047         if (err)
2048                 goto out;
2049         if (rdev->pfp_fw->size != pfp_req_size) {
2050                 printk(KERN_ERR
2051                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2052                        rdev->pfp_fw->size, fw_name);
2053                 err = -EINVAL;
2054                 goto out;
2055         }
2056
2057         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2058         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2059         if (err)
2060                 goto out;
2061         if (rdev->me_fw->size != me_req_size) {
2062                 printk(KERN_ERR
2063                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2064                        rdev->me_fw->size, fw_name);
2065                 err = -EINVAL;
2066         }
2067
2068         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2069         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2070         if (err)
2071                 goto out;
2072         if (rdev->rlc_fw->size != rlc_req_size) {
2073                 printk(KERN_ERR
2074                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2075                        rdev->rlc_fw->size, fw_name);
2076                 err = -EINVAL;
2077         }
2078
2079 out:
2080         platform_device_unregister(pdev);
2081
2082         if (err) {
2083                 if (err != -EINVAL)
2084                         printk(KERN_ERR
2085                                "r600_cp: Failed to load firmware \"%s\"\n",
2086                                fw_name);
2087                 release_firmware(rdev->pfp_fw);
2088                 rdev->pfp_fw = NULL;
2089                 release_firmware(rdev->me_fw);
2090                 rdev->me_fw = NULL;
2091                 release_firmware(rdev->rlc_fw);
2092                 rdev->rlc_fw = NULL;
2093         }
2094         return err;
2095 }
2096
2097 static int r600_cp_load_microcode(struct radeon_device *rdev)
2098 {
2099         const __be32 *fw_data;
2100         int i;
2101
2102         if (!rdev->me_fw || !rdev->pfp_fw)
2103                 return -EINVAL;
2104
2105         r600_cp_stop(rdev);
2106
2107         WREG32(CP_RB_CNTL,
2108 #ifdef __BIG_ENDIAN
2109                BUF_SWAP_32BIT |
2110 #endif
2111                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2112
2113         /* Reset cp */
2114         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2115         RREG32(GRBM_SOFT_RESET);
2116         mdelay(15);
2117         WREG32(GRBM_SOFT_RESET, 0);
2118
2119         WREG32(CP_ME_RAM_WADDR, 0);
2120
2121         fw_data = (const __be32 *)rdev->me_fw->data;
2122         WREG32(CP_ME_RAM_WADDR, 0);
2123         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2124                 WREG32(CP_ME_RAM_DATA,
2125                        be32_to_cpup(fw_data++));
2126
2127         fw_data = (const __be32 *)rdev->pfp_fw->data;
2128         WREG32(CP_PFP_UCODE_ADDR, 0);
2129         for (i = 0; i < PFP_UCODE_SIZE; i++)
2130                 WREG32(CP_PFP_UCODE_DATA,
2131                        be32_to_cpup(fw_data++));
2132
2133         WREG32(CP_PFP_UCODE_ADDR, 0);
2134         WREG32(CP_ME_RAM_WADDR, 0);
2135         WREG32(CP_ME_RAM_RADDR, 0);
2136         return 0;
2137 }
2138
2139 int r600_cp_start(struct radeon_device *rdev)
2140 {
2141         int r;
2142         uint32_t cp_me;
2143
2144         r = radeon_ring_lock(rdev, 7);
2145         if (r) {
2146                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2147                 return r;
2148         }
2149         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2150         radeon_ring_write(rdev, 0x1);
2151         if (rdev->family >= CHIP_RV770) {
2152                 radeon_ring_write(rdev, 0x0);
2153                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2154         } else {
2155                 radeon_ring_write(rdev, 0x3);
2156                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2157         }
2158         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2159         radeon_ring_write(rdev, 0);
2160         radeon_ring_write(rdev, 0);
2161         radeon_ring_unlock_commit(rdev);
2162
2163         cp_me = 0xff;
2164         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2165         return 0;
2166 }
2167
2168 int r600_cp_resume(struct radeon_device *rdev)
2169 {
2170         u32 tmp;
2171         u32 rb_bufsz;
2172         int r;
2173
2174         /* Reset cp */
2175         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2176         RREG32(GRBM_SOFT_RESET);
2177         mdelay(15);
2178         WREG32(GRBM_SOFT_RESET, 0);
2179
2180         /* Set ring buffer size */
2181         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2182         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2183 #ifdef __BIG_ENDIAN
2184         tmp |= BUF_SWAP_32BIT;
2185 #endif
2186         WREG32(CP_RB_CNTL, tmp);
2187         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2188
2189         /* Set the write pointer delay */
2190         WREG32(CP_RB_WPTR_DELAY, 0);
2191
2192         /* Initialize the ring buffer's read and write pointers */
2193         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2194         WREG32(CP_RB_RPTR_WR, 0);
2195         WREG32(CP_RB_WPTR, 0);
2196
2197         /* set the wb address whether it's enabled or not */
2198         WREG32(CP_RB_RPTR_ADDR,
2199 #ifdef __BIG_ENDIAN
2200                RB_RPTR_SWAP(2) |
2201 #endif
2202                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2203         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2204         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2205
2206         if (rdev->wb.enabled)
2207                 WREG32(SCRATCH_UMSK, 0xff);
2208         else {
2209                 tmp |= RB_NO_UPDATE;
2210                 WREG32(SCRATCH_UMSK, 0);
2211         }
2212
2213         mdelay(1);
2214         WREG32(CP_RB_CNTL, tmp);
2215
2216         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2217         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2218
2219         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2220         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2221
2222         r600_cp_start(rdev);
2223         rdev->cp.ready = true;
2224         r = radeon_ring_test(rdev);
2225         if (r) {
2226                 rdev->cp.ready = false;
2227                 return r;
2228         }
2229         return 0;
2230 }
2231
2232 void r600_cp_commit(struct radeon_device *rdev)
2233 {
2234         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2235         (void)RREG32(CP_RB_WPTR);
2236 }
2237
2238 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2239 {
2240         u32 rb_bufsz;
2241
2242         /* Align ring size */
2243         rb_bufsz = drm_order(ring_size / 8);
2244         ring_size = (1 << (rb_bufsz + 1)) * 4;
2245         rdev->cp.ring_size = ring_size;
2246         rdev->cp.align_mask = 16 - 1;
2247 }
2248
2249 void r600_cp_fini(struct radeon_device *rdev)
2250 {
2251         r600_cp_stop(rdev);
2252         radeon_ring_fini(rdev);
2253 }
2254
2255
2256 /*
2257  * GPU scratch registers helpers function.
2258  */
2259 void r600_scratch_init(struct radeon_device *rdev)
2260 {
2261         int i;
2262
2263         rdev->scratch.num_reg = 7;
2264         rdev->scratch.reg_base = SCRATCH_REG0;
2265         for (i = 0; i < rdev->scratch.num_reg; i++) {
2266                 rdev->scratch.free[i] = true;
2267                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2268         }
2269 }
2270
2271 int r600_ring_test(struct radeon_device *rdev)
2272 {
2273         uint32_t scratch;
2274         uint32_t tmp = 0;
2275         unsigned i;
2276         int r;
2277
2278         r = radeon_scratch_get(rdev, &scratch);
2279         if (r) {
2280                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2281                 return r;
2282         }
2283         WREG32(scratch, 0xCAFEDEAD);
2284         r = radeon_ring_lock(rdev, 3);
2285         if (r) {
2286                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2287                 radeon_scratch_free(rdev, scratch);
2288                 return r;
2289         }
2290         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2291         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2292         radeon_ring_write(rdev, 0xDEADBEEF);
2293         radeon_ring_unlock_commit(rdev);
2294         for (i = 0; i < rdev->usec_timeout; i++) {
2295                 tmp = RREG32(scratch);
2296                 if (tmp == 0xDEADBEEF)
2297                         break;
2298                 DRM_UDELAY(1);
2299         }
2300         if (i < rdev->usec_timeout) {
2301                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2302         } else {
2303                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2304                           scratch, tmp);
2305                 r = -EINVAL;
2306         }
2307         radeon_scratch_free(rdev, scratch);
2308         return r;
2309 }
2310
2311 void r600_fence_ring_emit(struct radeon_device *rdev,
2312                           struct radeon_fence *fence)
2313 {
2314         if (rdev->wb.use_event) {
2315                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2316                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2317                 /* EVENT_WRITE_EOP - flush caches, send int */
2318                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2319                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2320                 radeon_ring_write(rdev, addr & 0xffffffff);
2321                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2322                 radeon_ring_write(rdev, fence->seq);
2323                 radeon_ring_write(rdev, 0);
2324         } else {
2325                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2326                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2327                 /* wait for 3D idle clean */
2328                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2329                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2330                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2331                 /* Emit fence sequence & fire IRQ */
2332                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2333                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2334                 radeon_ring_write(rdev, fence->seq);
2335                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2336                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2337                 radeon_ring_write(rdev, RB_INT_STAT);
2338         }
2339 }
2340
2341 int r600_copy_blit(struct radeon_device *rdev,
2342                    uint64_t src_offset, uint64_t dst_offset,
2343                    unsigned num_pages, struct radeon_fence *fence)
2344 {
2345         int r;
2346
2347         mutex_lock(&rdev->r600_blit.mutex);
2348         rdev->r600_blit.vb_ib = NULL;
2349         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2350         if (r) {
2351                 if (rdev->r600_blit.vb_ib)
2352                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2353                 mutex_unlock(&rdev->r600_blit.mutex);
2354                 return r;
2355         }
2356         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2357         r600_blit_done_copy(rdev, fence);
2358         mutex_unlock(&rdev->r600_blit.mutex);
2359         return 0;
2360 }
2361
2362 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2363                          uint32_t tiling_flags, uint32_t pitch,
2364                          uint32_t offset, uint32_t obj_size)
2365 {
2366         /* FIXME: implement */
2367         return 0;
2368 }
2369
2370 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2371 {
2372         /* FIXME: implement */
2373 }
2374
2375 int r600_startup(struct radeon_device *rdev)
2376 {
2377         int r;
2378
2379         /* enable pcie gen2 link */
2380         r600_pcie_gen2_enable(rdev);
2381
2382         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2383                 r = r600_init_microcode(rdev);
2384                 if (r) {
2385                         DRM_ERROR("Failed to load firmware!\n");
2386                         return r;
2387                 }
2388         }
2389
2390         r600_mc_program(rdev);
2391         if (rdev->flags & RADEON_IS_AGP) {
2392                 r600_agp_enable(rdev);
2393         } else {
2394                 r = r600_pcie_gart_enable(rdev);
2395                 if (r)
2396                         return r;
2397         }
2398         r600_gpu_init(rdev);
2399         r = r600_blit_init(rdev);
2400         if (r) {
2401                 r600_blit_fini(rdev);
2402                 rdev->asic->copy = NULL;
2403                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2404         }
2405
2406         /* allocate wb buffer */
2407         r = radeon_wb_init(rdev);
2408         if (r)
2409                 return r;
2410
2411         /* Enable IRQ */
2412         r = r600_irq_init(rdev);
2413         if (r) {
2414                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2415                 radeon_irq_kms_fini(rdev);
2416                 return r;
2417         }
2418         r600_irq_set(rdev);
2419
2420         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2421         if (r)
2422                 return r;
2423         r = r600_cp_load_microcode(rdev);
2424         if (r)
2425                 return r;
2426         r = r600_cp_resume(rdev);
2427         if (r)
2428                 return r;
2429
2430         return 0;
2431 }
2432
2433 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2434 {
2435         uint32_t temp;
2436
2437         temp = RREG32(CONFIG_CNTL);
2438         if (state == false) {
2439                 temp &= ~(1<<0);
2440                 temp |= (1<<1);
2441         } else {
2442                 temp &= ~(1<<1);
2443         }
2444         WREG32(CONFIG_CNTL, temp);
2445 }
2446
2447 int r600_resume(struct radeon_device *rdev)
2448 {
2449         int r;
2450
2451         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2452          * posting will perform necessary task to bring back GPU into good
2453          * shape.
2454          */
2455         /* post card */
2456         atom_asic_init(rdev->mode_info.atom_context);
2457
2458         r = r600_startup(rdev);
2459         if (r) {
2460                 DRM_ERROR("r600 startup failed on resume\n");
2461                 return r;
2462         }
2463
2464         r = r600_ib_test(rdev);
2465         if (r) {
2466                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2467                 return r;
2468         }
2469
2470         r = r600_audio_init(rdev);
2471         if (r) {
2472                 DRM_ERROR("radeon: audio resume failed\n");
2473                 return r;
2474         }
2475
2476         return r;
2477 }
2478
2479 int r600_suspend(struct radeon_device *rdev)
2480 {
2481         int r;
2482
2483         r600_audio_fini(rdev);
2484         /* FIXME: we should wait for ring to be empty */
2485         r600_cp_stop(rdev);
2486         rdev->cp.ready = false;
2487         r600_irq_suspend(rdev);
2488         radeon_wb_disable(rdev);
2489         r600_pcie_gart_disable(rdev);
2490         /* unpin shaders bo */
2491         if (rdev->r600_blit.shader_obj) {
2492                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2493                 if (!r) {
2494                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2495                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2496                 }
2497         }
2498         return 0;
2499 }
2500
2501 /* Plan is to move initialization in that function and use
2502  * helper function so that radeon_device_init pretty much
2503  * do nothing more than calling asic specific function. This
2504  * should also allow to remove a bunch of callback function
2505  * like vram_info.
2506  */
2507 int r600_init(struct radeon_device *rdev)
2508 {
2509         int r;
2510
2511         r = radeon_dummy_page_init(rdev);
2512         if (r)
2513                 return r;
2514         if (r600_debugfs_mc_info_init(rdev)) {
2515                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2516         }
2517         /* This don't do much */
2518         r = radeon_gem_init(rdev);
2519         if (r)
2520                 return r;
2521         /* Read BIOS */
2522         if (!radeon_get_bios(rdev)) {
2523                 if (ASIC_IS_AVIVO(rdev))
2524                         return -EINVAL;
2525         }
2526         /* Must be an ATOMBIOS */
2527         if (!rdev->is_atom_bios) {
2528                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2529                 return -EINVAL;
2530         }
2531         r = radeon_atombios_init(rdev);
2532         if (r)
2533                 return r;
2534         /* Post card if necessary */
2535         if (!radeon_card_posted(rdev)) {
2536                 if (!rdev->bios) {
2537                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2538                         return -EINVAL;
2539                 }
2540                 DRM_INFO("GPU not posted. posting now...\n");
2541                 atom_asic_init(rdev->mode_info.atom_context);
2542         }
2543         /* Initialize scratch registers */
2544         r600_scratch_init(rdev);
2545         /* Initialize surface registers */
2546         radeon_surface_init(rdev);
2547         /* Initialize clocks */
2548         radeon_get_clock_info(rdev->ddev);
2549         /* Fence driver */
2550         r = radeon_fence_driver_init(rdev);
2551         if (r)
2552                 return r;
2553         if (rdev->flags & RADEON_IS_AGP) {
2554                 r = radeon_agp_init(rdev);
2555                 if (r)
2556                         radeon_agp_disable(rdev);
2557         }
2558         r = r600_mc_init(rdev);
2559         if (r)
2560                 return r;
2561         /* Memory manager */
2562         r = radeon_bo_init(rdev);
2563         if (r)
2564                 return r;
2565
2566         r = radeon_irq_kms_init(rdev);
2567         if (r)
2568                 return r;
2569
2570         rdev->cp.ring_obj = NULL;
2571         r600_ring_init(rdev, 1024 * 1024);
2572
2573         rdev->ih.ring_obj = NULL;
2574         r600_ih_ring_init(rdev, 64 * 1024);
2575
2576         r = r600_pcie_gart_init(rdev);
2577         if (r)
2578                 return r;
2579
2580         rdev->accel_working = true;
2581         r = r600_startup(rdev);
2582         if (r) {
2583                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2584                 r600_cp_fini(rdev);
2585                 r600_irq_fini(rdev);
2586                 radeon_wb_fini(rdev);
2587                 radeon_irq_kms_fini(rdev);
2588                 r600_pcie_gart_fini(rdev);
2589                 rdev->accel_working = false;
2590         }
2591         if (rdev->accel_working) {
2592                 r = radeon_ib_pool_init(rdev);
2593                 if (r) {
2594                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2595                         rdev->accel_working = false;
2596                 } else {
2597                         r = r600_ib_test(rdev);
2598                         if (r) {
2599                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2600                                 rdev->accel_working = false;
2601                         }
2602                 }
2603         }
2604
2605         r = r600_audio_init(rdev);
2606         if (r)
2607                 return r; /* TODO error handling */
2608         return 0;
2609 }
2610
2611 void r600_fini(struct radeon_device *rdev)
2612 {
2613         r600_audio_fini(rdev);
2614         r600_blit_fini(rdev);
2615         r600_cp_fini(rdev);
2616         r600_irq_fini(rdev);
2617         radeon_wb_fini(rdev);
2618         radeon_irq_kms_fini(rdev);
2619         r600_pcie_gart_fini(rdev);
2620         radeon_agp_fini(rdev);
2621         radeon_gem_fini(rdev);
2622         radeon_fence_driver_fini(rdev);
2623         radeon_bo_fini(rdev);
2624         radeon_atombios_fini(rdev);
2625         kfree(rdev->bios);
2626         rdev->bios = NULL;
2627         radeon_dummy_page_fini(rdev);
2628 }
2629
2630
2631 /*
2632  * CS stuff
2633  */
2634 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2635 {
2636         /* FIXME: implement */
2637         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2638         radeon_ring_write(rdev,
2639 #ifdef __BIG_ENDIAN
2640                           (2 << 0) |
2641 #endif
2642                           (ib->gpu_addr & 0xFFFFFFFC));
2643         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2644         radeon_ring_write(rdev, ib->length_dw);
2645 }
2646
2647 int r600_ib_test(struct radeon_device *rdev)
2648 {
2649         struct radeon_ib *ib;
2650         uint32_t scratch;
2651         uint32_t tmp = 0;
2652         unsigned i;
2653         int r;
2654
2655         r = radeon_scratch_get(rdev, &scratch);
2656         if (r) {
2657                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2658                 return r;
2659         }
2660         WREG32(scratch, 0xCAFEDEAD);
2661         r = radeon_ib_get(rdev, &ib);
2662         if (r) {
2663                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2664                 return r;
2665         }
2666         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2667         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2668         ib->ptr[2] = 0xDEADBEEF;
2669         ib->ptr[3] = PACKET2(0);
2670         ib->ptr[4] = PACKET2(0);
2671         ib->ptr[5] = PACKET2(0);
2672         ib->ptr[6] = PACKET2(0);
2673         ib->ptr[7] = PACKET2(0);
2674         ib->ptr[8] = PACKET2(0);
2675         ib->ptr[9] = PACKET2(0);
2676         ib->ptr[10] = PACKET2(0);
2677         ib->ptr[11] = PACKET2(0);
2678         ib->ptr[12] = PACKET2(0);
2679         ib->ptr[13] = PACKET2(0);
2680         ib->ptr[14] = PACKET2(0);
2681         ib->ptr[15] = PACKET2(0);
2682         ib->length_dw = 16;
2683         r = radeon_ib_schedule(rdev, ib);
2684         if (r) {
2685                 radeon_scratch_free(rdev, scratch);
2686                 radeon_ib_free(rdev, &ib);
2687                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2688                 return r;
2689         }
2690         r = radeon_fence_wait(ib->fence, false);
2691         if (r) {
2692                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2693                 return r;
2694         }
2695         for (i = 0; i < rdev->usec_timeout; i++) {
2696                 tmp = RREG32(scratch);
2697                 if (tmp == 0xDEADBEEF)
2698                         break;
2699                 DRM_UDELAY(1);
2700         }
2701         if (i < rdev->usec_timeout) {
2702                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2703         } else {
2704                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2705                           scratch, tmp);
2706                 r = -EINVAL;
2707         }
2708         radeon_scratch_free(rdev, scratch);
2709         radeon_ib_free(rdev, &ib);
2710         return r;
2711 }
2712
2713 /*
2714  * Interrupts
2715  *
2716  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2717  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2718  * writing to the ring and the GPU consuming, the GPU writes to the ring
2719  * and host consumes.  As the host irq handler processes interrupts, it
2720  * increments the rptr.  When the rptr catches up with the wptr, all the
2721  * current interrupts have been processed.
2722  */
2723
2724 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2725 {
2726         u32 rb_bufsz;
2727
2728         /* Align ring size */
2729         rb_bufsz = drm_order(ring_size / 4);
2730         ring_size = (1 << rb_bufsz) * 4;
2731         rdev->ih.ring_size = ring_size;
2732         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2733         rdev->ih.rptr = 0;
2734 }
2735
2736 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2737 {
2738         int r;
2739
2740         /* Allocate ring buffer */
2741         if (rdev->ih.ring_obj == NULL) {
2742                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2743                                      PAGE_SIZE, true,
2744                                      RADEON_GEM_DOMAIN_GTT,
2745                                      &rdev->ih.ring_obj);
2746                 if (r) {
2747                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2748                         return r;
2749                 }
2750                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2751                 if (unlikely(r != 0))
2752                         return r;
2753                 r = radeon_bo_pin(rdev->ih.ring_obj,
2754                                   RADEON_GEM_DOMAIN_GTT,
2755                                   &rdev->ih.gpu_addr);
2756                 if (r) {
2757                         radeon_bo_unreserve(rdev->ih.ring_obj);
2758                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2759                         return r;
2760                 }
2761                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2762                                    (void **)&rdev->ih.ring);
2763                 radeon_bo_unreserve(rdev->ih.ring_obj);
2764                 if (r) {
2765                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2766                         return r;
2767                 }
2768         }
2769         return 0;
2770 }
2771
2772 static void r600_ih_ring_fini(struct radeon_device *rdev)
2773 {
2774         int r;
2775         if (rdev->ih.ring_obj) {
2776                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2777                 if (likely(r == 0)) {
2778                         radeon_bo_kunmap(rdev->ih.ring_obj);
2779                         radeon_bo_unpin(rdev->ih.ring_obj);
2780                         radeon_bo_unreserve(rdev->ih.ring_obj);
2781                 }
2782                 radeon_bo_unref(&rdev->ih.ring_obj);
2783                 rdev->ih.ring = NULL;
2784                 rdev->ih.ring_obj = NULL;
2785         }
2786 }
2787
2788 void r600_rlc_stop(struct radeon_device *rdev)
2789 {
2790
2791         if ((rdev->family >= CHIP_RV770) &&
2792             (rdev->family <= CHIP_RV740)) {
2793                 /* r7xx asics need to soft reset RLC before halting */
2794                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2795                 RREG32(SRBM_SOFT_RESET);
2796                 udelay(15000);
2797                 WREG32(SRBM_SOFT_RESET, 0);
2798                 RREG32(SRBM_SOFT_RESET);
2799         }
2800
2801         WREG32(RLC_CNTL, 0);
2802 }
2803
2804 static void r600_rlc_start(struct radeon_device *rdev)
2805 {
2806         WREG32(RLC_CNTL, RLC_ENABLE);
2807 }
2808
2809 static int r600_rlc_init(struct radeon_device *rdev)
2810 {
2811         u32 i;
2812         const __be32 *fw_data;
2813
2814         if (!rdev->rlc_fw)
2815                 return -EINVAL;
2816
2817         r600_rlc_stop(rdev);
2818
2819         WREG32(RLC_HB_BASE, 0);
2820         WREG32(RLC_HB_CNTL, 0);
2821         WREG32(RLC_HB_RPTR, 0);
2822         WREG32(RLC_HB_WPTR, 0);
2823         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2824         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2825         WREG32(RLC_MC_CNTL, 0);
2826         WREG32(RLC_UCODE_CNTL, 0);
2827
2828         fw_data = (const __be32 *)rdev->rlc_fw->data;
2829         if (rdev->family >= CHIP_CEDAR) {
2830                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2831                         WREG32(RLC_UCODE_ADDR, i);
2832                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2833                 }
2834         } else if (rdev->family >= CHIP_RV770) {
2835                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2836                         WREG32(RLC_UCODE_ADDR, i);
2837                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2838                 }
2839         } else {
2840                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2841                         WREG32(RLC_UCODE_ADDR, i);
2842                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2843                 }
2844         }
2845         WREG32(RLC_UCODE_ADDR, 0);
2846
2847         r600_rlc_start(rdev);
2848
2849         return 0;
2850 }
2851
2852 static void r600_enable_interrupts(struct radeon_device *rdev)
2853 {
2854         u32 ih_cntl = RREG32(IH_CNTL);
2855         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2856
2857         ih_cntl |= ENABLE_INTR;
2858         ih_rb_cntl |= IH_RB_ENABLE;
2859         WREG32(IH_CNTL, ih_cntl);
2860         WREG32(IH_RB_CNTL, ih_rb_cntl);
2861         rdev->ih.enabled = true;
2862 }
2863
2864 void r600_disable_interrupts(struct radeon_device *rdev)
2865 {
2866         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2867         u32 ih_cntl = RREG32(IH_CNTL);
2868
2869         ih_rb_cntl &= ~IH_RB_ENABLE;
2870         ih_cntl &= ~ENABLE_INTR;
2871         WREG32(IH_RB_CNTL, ih_rb_cntl);
2872         WREG32(IH_CNTL, ih_cntl);
2873         /* set rptr, wptr to 0 */
2874         WREG32(IH_RB_RPTR, 0);
2875         WREG32(IH_RB_WPTR, 0);
2876         rdev->ih.enabled = false;
2877         rdev->ih.wptr = 0;
2878         rdev->ih.rptr = 0;
2879 }
2880
2881 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2882 {
2883         u32 tmp;
2884
2885         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2886         WREG32(GRBM_INT_CNTL, 0);
2887         WREG32(DxMODE_INT_MASK, 0);
2888         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2889         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2890         if (ASIC_IS_DCE3(rdev)) {
2891                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2892                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2893                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2894                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2895                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2896                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2897                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2898                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2899                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2900                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2901                 if (ASIC_IS_DCE32(rdev)) {
2902                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2903                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2904                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2905                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2906                 }
2907         } else {
2908                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2909                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2910                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2911                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2912                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2913                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2914                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2915                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2916         }
2917 }
2918
2919 int r600_irq_init(struct radeon_device *rdev)
2920 {
2921         int ret = 0;
2922         int rb_bufsz;
2923         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2924
2925         /* allocate ring */
2926         ret = r600_ih_ring_alloc(rdev);
2927         if (ret)
2928                 return ret;
2929
2930         /* disable irqs */
2931         r600_disable_interrupts(rdev);
2932
2933         /* init rlc */
2934         ret = r600_rlc_init(rdev);
2935         if (ret) {
2936                 r600_ih_ring_fini(rdev);
2937                 return ret;
2938         }
2939
2940         /* setup interrupt control */
2941         /* set dummy read address to ring address */
2942         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2943         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2944         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2945          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2946          */
2947         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2948         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2949         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2950         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2951
2952         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2953         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2954
2955         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2956                       IH_WPTR_OVERFLOW_CLEAR |
2957                       (rb_bufsz << 1));
2958
2959         if (rdev->wb.enabled)
2960                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2961
2962         /* set the writeback address whether it's enabled or not */
2963         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2964         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2965
2966         WREG32(IH_RB_CNTL, ih_rb_cntl);
2967
2968         /* set rptr, wptr to 0 */
2969         WREG32(IH_RB_RPTR, 0);
2970         WREG32(IH_RB_WPTR, 0);
2971
2972         /* Default settings for IH_CNTL (disabled at first) */
2973         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2974         /* RPTR_REARM only works if msi's are enabled */
2975         if (rdev->msi_enabled)
2976                 ih_cntl |= RPTR_REARM;
2977
2978 #ifdef __BIG_ENDIAN
2979         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2980 #endif
2981         WREG32(IH_CNTL, ih_cntl);
2982
2983         /* force the active interrupt state to all disabled */
2984         if (rdev->family >= CHIP_CEDAR)
2985                 evergreen_disable_interrupt_state(rdev);
2986         else
2987                 r600_disable_interrupt_state(rdev);
2988
2989         /* enable irqs */
2990         r600_enable_interrupts(rdev);
2991
2992         return ret;
2993 }
2994
2995 void r600_irq_suspend(struct radeon_device *rdev)
2996 {
2997         r600_irq_disable(rdev);
2998         r600_rlc_stop(rdev);
2999 }
3000
3001 void r600_irq_fini(struct radeon_device *rdev)
3002 {
3003         r600_irq_suspend(rdev);
3004         r600_ih_ring_fini(rdev);
3005 }
3006
3007 int r600_irq_set(struct radeon_device *rdev)
3008 {
3009         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3010         u32 mode_int = 0;
3011         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3012         u32 grbm_int_cntl = 0;
3013         u32 hdmi1, hdmi2;
3014         u32 d1grph = 0, d2grph = 0;
3015
3016         if (!rdev->irq.installed) {
3017                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3018                 return -EINVAL;
3019         }
3020         /* don't enable anything if the ih is disabled */
3021         if (!rdev->ih.enabled) {
3022                 r600_disable_interrupts(rdev);
3023                 /* force the active interrupt state to all disabled */
3024                 r600_disable_interrupt_state(rdev);
3025                 return 0;
3026         }
3027
3028         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3029         if (ASIC_IS_DCE3(rdev)) {
3030                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3031                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3032                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3033                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3034                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3035                 if (ASIC_IS_DCE32(rdev)) {
3036                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3037                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038                 }
3039         } else {
3040                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3041                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3042                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3043                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3044         }
3045
3046         if (rdev->irq.sw_int) {
3047                 DRM_DEBUG("r600_irq_set: sw int\n");
3048                 cp_int_cntl |= RB_INT_ENABLE;
3049                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3050         }
3051         if (rdev->irq.crtc_vblank_int[0] ||
3052             rdev->irq.pflip[0]) {
3053                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3054                 mode_int |= D1MODE_VBLANK_INT_MASK;
3055         }
3056         if (rdev->irq.crtc_vblank_int[1] ||
3057             rdev->irq.pflip[1]) {
3058                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3059                 mode_int |= D2MODE_VBLANK_INT_MASK;
3060         }
3061         if (rdev->irq.hpd[0]) {
3062                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3063                 hpd1 |= DC_HPDx_INT_EN;
3064         }
3065         if (rdev->irq.hpd[1]) {
3066                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3067                 hpd2 |= DC_HPDx_INT_EN;
3068         }
3069         if (rdev->irq.hpd[2]) {
3070                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3071                 hpd3 |= DC_HPDx_INT_EN;
3072         }
3073         if (rdev->irq.hpd[3]) {
3074                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3075                 hpd4 |= DC_HPDx_INT_EN;
3076         }
3077         if (rdev->irq.hpd[4]) {
3078                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3079                 hpd5 |= DC_HPDx_INT_EN;
3080         }
3081         if (rdev->irq.hpd[5]) {
3082                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3083                 hpd6 |= DC_HPDx_INT_EN;
3084         }
3085         if (rdev->irq.hdmi[0]) {
3086                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3087                 hdmi1 |= R600_HDMI_INT_EN;
3088         }
3089         if (rdev->irq.hdmi[1]) {
3090                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3091                 hdmi2 |= R600_HDMI_INT_EN;
3092         }
3093         if (rdev->irq.gui_idle) {
3094                 DRM_DEBUG("gui idle\n");
3095                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3096         }
3097
3098         WREG32(CP_INT_CNTL, cp_int_cntl);
3099         WREG32(DxMODE_INT_MASK, mode_int);
3100         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3101         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3102         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3103         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3104         if (ASIC_IS_DCE3(rdev)) {
3105                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3106                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3107                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3108                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3109                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3110                 if (ASIC_IS_DCE32(rdev)) {
3111                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3112                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3113                 }
3114         } else {
3115                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3116                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3117                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3118                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3119         }
3120
3121         return 0;
3122 }
3123
3124 static inline void r600_irq_ack(struct radeon_device *rdev)
3125 {
3126         u32 tmp;
3127
3128         if (ASIC_IS_DCE3(rdev)) {
3129                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3130                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3131                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3132         } else {
3133                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3134                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3135                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3136         }
3137         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3138         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3139
3140         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3141                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3142         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3143                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3144         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3145                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3146         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3147                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3148         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3149                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3150         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3151                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3152         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3153                 if (ASIC_IS_DCE3(rdev)) {
3154                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3155                         tmp |= DC_HPDx_INT_ACK;
3156                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3157                 } else {
3158                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3159                         tmp |= DC_HPDx_INT_ACK;
3160                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3161                 }
3162         }
3163         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3164                 if (ASIC_IS_DCE3(rdev)) {
3165                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3166                         tmp |= DC_HPDx_INT_ACK;
3167                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3168                 } else {
3169                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3170                         tmp |= DC_HPDx_INT_ACK;
3171                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3172                 }
3173         }
3174         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3175                 if (ASIC_IS_DCE3(rdev)) {
3176                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3177                         tmp |= DC_HPDx_INT_ACK;
3178                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3179                 } else {
3180                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3181                         tmp |= DC_HPDx_INT_ACK;
3182                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3183                 }
3184         }
3185         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3186                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3187                 tmp |= DC_HPDx_INT_ACK;
3188                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3189         }
3190         if (ASIC_IS_DCE32(rdev)) {
3191                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3192                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3193                         tmp |= DC_HPDx_INT_ACK;
3194                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3195                 }
3196                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3197                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3198                         tmp |= DC_HPDx_INT_ACK;
3199                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3200                 }
3201         }
3202         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3203                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3204         }
3205         if (ASIC_IS_DCE3(rdev)) {
3206                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3207                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3208                 }
3209         } else {
3210                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3211                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3212                 }
3213         }
3214 }
3215
3216 void r600_irq_disable(struct radeon_device *rdev)
3217 {
3218         r600_disable_interrupts(rdev);
3219         /* Wait and acknowledge irq */
3220         mdelay(1);
3221         r600_irq_ack(rdev);
3222         r600_disable_interrupt_state(rdev);
3223 }
3224
3225 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3226 {
3227         u32 wptr, tmp;
3228
3229         if (rdev->wb.enabled)
3230                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3231         else
3232                 wptr = RREG32(IH_RB_WPTR);
3233
3234         if (wptr & RB_OVERFLOW) {
3235                 /* When a ring buffer overflow happen start parsing interrupt
3236                  * from the last not overwritten vector (wptr + 16). Hopefully
3237                  * this should allow us to catchup.
3238                  */
3239                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3240                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3241                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3242                 tmp = RREG32(IH_RB_CNTL);
3243                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3244                 WREG32(IH_RB_CNTL, tmp);
3245         }
3246         return (wptr & rdev->ih.ptr_mask);
3247 }
3248
3249 /*        r600 IV Ring
3250  * Each IV ring entry is 128 bits:
3251  * [7:0]    - interrupt source id
3252  * [31:8]   - reserved
3253  * [59:32]  - interrupt source data
3254  * [127:60]  - reserved
3255  *
3256  * The basic interrupt vector entries
3257  * are decoded as follows:
3258  * src_id  src_data  description
3259  *      1         0  D1 Vblank
3260  *      1         1  D1 Vline
3261  *      5         0  D2 Vblank
3262  *      5         1  D2 Vline
3263  *     19         0  FP Hot plug detection A
3264  *     19         1  FP Hot plug detection B
3265  *     19         2  DAC A auto-detection
3266  *     19         3  DAC B auto-detection
3267  *     21         4  HDMI block A
3268  *     21         5  HDMI block B
3269  *    176         -  CP_INT RB
3270  *    177         -  CP_INT IB1
3271  *    178         -  CP_INT IB2
3272  *    181         -  EOP Interrupt
3273  *    233         -  GUI Idle
3274  *
3275  * Note, these are based on r600 and may need to be
3276  * adjusted or added to on newer asics
3277  */
3278
3279 int r600_irq_process(struct radeon_device *rdev)
3280 {
3281         u32 wptr = r600_get_ih_wptr(rdev);
3282         u32 rptr = rdev->ih.rptr;
3283         u32 src_id, src_data;
3284         u32 ring_index;
3285         unsigned long flags;
3286         bool queue_hotplug = false;
3287
3288         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3289         if (!rdev->ih.enabled)
3290                 return IRQ_NONE;
3291
3292         spin_lock_irqsave(&rdev->ih.lock, flags);
3293
3294         if (rptr == wptr) {
3295                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3296                 return IRQ_NONE;
3297         }
3298         if (rdev->shutdown) {
3299                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3300                 return IRQ_NONE;
3301         }
3302
3303 restart_ih:
3304         /* display interrupts */
3305         r600_irq_ack(rdev);
3306
3307         rdev->ih.wptr = wptr;
3308         while (rptr != wptr) {
3309                 /* wptr/rptr are in bytes! */
3310                 ring_index = rptr / 4;
3311                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3312                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3313
3314                 switch (src_id) {
3315                 case 1: /* D1 vblank/vline */
3316                         switch (src_data) {
3317                         case 0: /* D1 vblank */
3318                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3319                                         if (rdev->irq.crtc_vblank_int[0]) {
3320                                                 drm_handle_vblank(rdev->ddev, 0);
3321                                                 rdev->pm.vblank_sync = true;
3322                                                 wake_up(&rdev->irq.vblank_queue);
3323                                         }
3324                                         if (rdev->irq.pflip[0])
3325                                                 radeon_crtc_handle_flip(rdev, 0);
3326                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3327                                         DRM_DEBUG("IH: D1 vblank\n");
3328                                 }
3329                                 break;
3330                         case 1: /* D1 vline */
3331                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3332                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3333                                         DRM_DEBUG("IH: D1 vline\n");
3334                                 }
3335                                 break;
3336                         default:
3337                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3338                                 break;
3339                         }
3340                         break;
3341                 case 5: /* D2 vblank/vline */
3342                         switch (src_data) {
3343                         case 0: /* D2 vblank */
3344                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3345                                         if (rdev->irq.crtc_vblank_int[1]) {
3346                                                 drm_handle_vblank(rdev->ddev, 1);
3347                                                 rdev->pm.vblank_sync = true;
3348                                                 wake_up(&rdev->irq.vblank_queue);
3349                                         }
3350                                         if (rdev->irq.pflip[1])
3351                                                 radeon_crtc_handle_flip(rdev, 1);
3352                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3353                                         DRM_DEBUG("IH: D2 vblank\n");
3354                                 }
3355                                 break;
3356                         case 1: /* D1 vline */
3357                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3358                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3359                                         DRM_DEBUG("IH: D2 vline\n");
3360                                 }
3361                                 break;
3362                         default:
3363                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3364                                 break;
3365                         }
3366                         break;
3367                 case 19: /* HPD/DAC hotplug */
3368                         switch (src_data) {
3369                         case 0:
3370                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3371                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3372                                         queue_hotplug = true;
3373                                         DRM_DEBUG("IH: HPD1\n");
3374                                 }
3375                                 break;
3376                         case 1:
3377                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3378                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3379                                         queue_hotplug = true;
3380                                         DRM_DEBUG("IH: HPD2\n");
3381                                 }
3382                                 break;
3383                         case 4:
3384                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3385                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3386                                         queue_hotplug = true;
3387                                         DRM_DEBUG("IH: HPD3\n");
3388                                 }
3389                                 break;
3390                         case 5:
3391                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3392                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3393                                         queue_hotplug = true;
3394                                         DRM_DEBUG("IH: HPD4\n");
3395                                 }
3396                                 break;
3397                         case 10:
3398                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3399                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3400                                         queue_hotplug = true;
3401                                         DRM_DEBUG("IH: HPD5\n");
3402                                 }
3403                                 break;
3404                         case 12:
3405                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3406                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3407                                         queue_hotplug = true;
3408                                         DRM_DEBUG("IH: HPD6\n");
3409                                 }
3410                                 break;
3411                         default:
3412                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3413                                 break;
3414                         }
3415                         break;
3416                 case 21: /* HDMI */
3417                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3418                         r600_audio_schedule_polling(rdev);
3419                         break;
3420                 case 176: /* CP_INT in ring buffer */
3421                 case 177: /* CP_INT in IB1 */
3422                 case 178: /* CP_INT in IB2 */
3423                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3424                         radeon_fence_process(rdev);
3425                         break;
3426                 case 181: /* CP EOP event */
3427                         DRM_DEBUG("IH: CP EOP\n");
3428                         radeon_fence_process(rdev);
3429                         break;
3430                 case 233: /* GUI IDLE */
3431                         DRM_DEBUG("IH: CP EOP\n");
3432                         rdev->pm.gui_idle = true;
3433                         wake_up(&rdev->irq.idle_queue);
3434                         break;
3435                 default:
3436                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3437                         break;
3438                 }
3439
3440                 /* wptr/rptr are in bytes! */
3441                 rptr += 16;
3442                 rptr &= rdev->ih.ptr_mask;
3443         }
3444         /* make sure wptr hasn't changed while processing */
3445         wptr = r600_get_ih_wptr(rdev);
3446         if (wptr != rdev->ih.wptr)
3447                 goto restart_ih;
3448         if (queue_hotplug)
3449                 schedule_work(&rdev->hotplug_work);
3450         rdev->ih.rptr = rptr;
3451         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3452         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3453         return IRQ_HANDLED;
3454 }
3455
3456 /*
3457  * Debugfs info
3458  */
3459 #if defined(CONFIG_DEBUG_FS)
3460
3461 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3462 {
3463         struct drm_info_node *node = (struct drm_info_node *) m->private;
3464         struct drm_device *dev = node->minor->dev;
3465         struct radeon_device *rdev = dev->dev_private;
3466         unsigned count, i, j;
3467
3468         radeon_ring_free_size(rdev);
3469         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3470         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3471         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3472         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3473         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3474         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3475         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3476         seq_printf(m, "%u dwords in ring\n", count);
3477         i = rdev->cp.rptr;
3478         for (j = 0; j <= count; j++) {
3479                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3480                 i = (i + 1) & rdev->cp.ptr_mask;
3481         }
3482         return 0;
3483 }
3484
3485 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3486 {
3487         struct drm_info_node *node = (struct drm_info_node *) m->private;
3488         struct drm_device *dev = node->minor->dev;
3489         struct radeon_device *rdev = dev->dev_private;
3490
3491         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3492         DREG32_SYS(m, rdev, VM_L2_STATUS);
3493         return 0;
3494 }
3495
3496 static struct drm_info_list r600_mc_info_list[] = {
3497         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3498         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3499 };
3500 #endif
3501
3502 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3503 {
3504 #if defined(CONFIG_DEBUG_FS)
3505         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3506 #else
3507         return 0;
3508 #endif
3509 }
3510
3511 /**
3512  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3513  * rdev: radeon device structure
3514  * bo: buffer object struct which userspace is waiting for idle
3515  *
3516  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3517  * through ring buffer, this leads to corruption in rendering, see
3518  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3519  * directly perform HDP flush by writing register through MMIO.
3520  */
3521 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3522 {
3523         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3524          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3525          * This seems to cause problems on some AGP cards. Just use the old
3526          * method for them.
3527          */
3528         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3529             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3530                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3531                 u32 tmp;
3532
3533                 WREG32(HDP_DEBUG1, 0);
3534                 tmp = readl((void __iomem *)ptr);
3535         } else
3536                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3537 }
3538
3539 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3540 {
3541         u32 link_width_cntl, mask, target_reg;
3542
3543         if (rdev->flags & RADEON_IS_IGP)
3544                 return;
3545
3546         if (!(rdev->flags & RADEON_IS_PCIE))
3547                 return;
3548
3549         /* x2 cards have a special sequence */
3550         if (ASIC_IS_X2(rdev))
3551                 return;
3552
3553         /* FIXME wait for idle */
3554
3555         switch (lanes) {
3556         case 0:
3557                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3558                 break;
3559         case 1:
3560                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3561                 break;
3562         case 2:
3563                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3564                 break;
3565         case 4:
3566                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3567                 break;
3568         case 8:
3569                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3570                 break;
3571         case 12:
3572                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3573                 break;
3574         case 16:
3575         default:
3576                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3577                 break;
3578         }
3579
3580         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3581
3582         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3583             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3584                 return;
3585
3586         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3587                 return;
3588
3589         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3590                              RADEON_PCIE_LC_RECONFIG_NOW |
3591                              R600_PCIE_LC_RENEGOTIATE_EN |
3592                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3593         link_width_cntl |= mask;
3594
3595         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3596
3597         /* some northbridges can renegotiate the link rather than requiring
3598          * a complete re-config.
3599          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3600          */
3601         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3602                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3603         else
3604                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3605
3606         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3607                                                        RADEON_PCIE_LC_RECONFIG_NOW));
3608
3609         if (rdev->family >= CHIP_RV770)
3610                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3611         else
3612                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3613
3614         /* wait for lane set to complete */
3615         link_width_cntl = RREG32(target_reg);
3616         while (link_width_cntl == 0xffffffff)
3617                 link_width_cntl = RREG32(target_reg);
3618
3619 }
3620
3621 int r600_get_pcie_lanes(struct radeon_device *rdev)
3622 {
3623         u32 link_width_cntl;
3624
3625         if (rdev->flags & RADEON_IS_IGP)
3626                 return 0;
3627
3628         if (!(rdev->flags & RADEON_IS_PCIE))
3629                 return 0;
3630
3631         /* x2 cards have a special sequence */
3632         if (ASIC_IS_X2(rdev))
3633                 return 0;
3634
3635         /* FIXME wait for idle */
3636
3637         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3638
3639         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3640         case RADEON_PCIE_LC_LINK_WIDTH_X0:
3641                 return 0;
3642         case RADEON_PCIE_LC_LINK_WIDTH_X1:
3643                 return 1;
3644         case RADEON_PCIE_LC_LINK_WIDTH_X2:
3645                 return 2;
3646         case RADEON_PCIE_LC_LINK_WIDTH_X4:
3647                 return 4;
3648         case RADEON_PCIE_LC_LINK_WIDTH_X8:
3649                 return 8;
3650         case RADEON_PCIE_LC_LINK_WIDTH_X16:
3651         default:
3652                 return 16;
3653         }
3654 }
3655
3656 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3657 {
3658         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3659         u16 link_cntl2;
3660
3661         if (radeon_pcie_gen2 == 0)
3662                 return;
3663
3664         if (rdev->flags & RADEON_IS_IGP)
3665                 return;
3666
3667         if (!(rdev->flags & RADEON_IS_PCIE))
3668                 return;
3669
3670         /* x2 cards have a special sequence */
3671         if (ASIC_IS_X2(rdev))
3672                 return;
3673
3674         /* only RV6xx+ chips are supported */
3675         if (rdev->family <= CHIP_R600)
3676                 return;
3677
3678         /* 55 nm r6xx asics */
3679         if ((rdev->family == CHIP_RV670) ||
3680             (rdev->family == CHIP_RV620) ||
3681             (rdev->family == CHIP_RV635)) {
3682                 /* advertise upconfig capability */
3683                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3684                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3685                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3686                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3687                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3688                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3689                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3690                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
3691                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3692                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3693                 } else {
3694                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3695                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3696                 }
3697         }
3698
3699         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3700         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3701             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3702
3703                 /* 55 nm r6xx asics */
3704                 if ((rdev->family == CHIP_RV670) ||
3705                     (rdev->family == CHIP_RV620) ||
3706                     (rdev->family == CHIP_RV635)) {
3707                         WREG32(MM_CFGREGS_CNTL, 0x8);
3708                         link_cntl2 = RREG32(0x4088);
3709                         WREG32(MM_CFGREGS_CNTL, 0);
3710                         /* not supported yet */
3711                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3712                                 return;
3713                 }
3714
3715                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3716                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3717                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3718                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3719                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3720                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3721
3722                 tmp = RREG32(0x541c);
3723                 WREG32(0x541c, tmp | 0x8);
3724                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3725                 link_cntl2 = RREG16(0x4088);
3726                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3727                 link_cntl2 |= 0x2;
3728                 WREG16(0x4088, link_cntl2);
3729                 WREG32(MM_CFGREGS_CNTL, 0);
3730
3731                 if ((rdev->family == CHIP_RV670) ||
3732                     (rdev->family == CHIP_RV620) ||
3733                     (rdev->family == CHIP_RV635)) {
3734                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3735                         training_cntl &= ~LC_POINT_7_PLUS_EN;
3736                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3737                 } else {
3738                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3739                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3740                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3741                 }
3742
3743                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3744                 speed_cntl |= LC_GEN2_EN_STRAP;
3745                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3746
3747         } else {
3748                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3749                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3750                 if (1)
3751                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3752                 else
3753                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3754                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3755         }
3756 }