drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 /* get temperature in millidegrees */
  96 u32 rv6xx_get_temp(struct radeon_device *rdev)
  97 {
  98         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
  99                 ASIC_T_SHIFT;
 100         u32 actual_temp = 0;
 101
 102         if ((temp >> 7) & 1)
 103                 actual_temp = 0;
 104         else
 105                 actual_temp = (temp >> 1) & 0xff;
 106
 107         return actual_temp * 1000;
 108 }
 109
 110 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 111 {
 112         int i;
 113
 114         rdev->pm.dynpm_can_upclock = true;
 115         rdev->pm.dynpm_can_downclock = true;
 116
 117         /* power state array is low to high, default is first */
 118         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 119                 int min_power_state_index = 0;
 120
 121                 if (rdev->pm.num_power_states > 2)
 122                         min_power_state_index = 1;
 123
 124                 switch (rdev->pm.dynpm_planned_action) {
 125                 case DYNPM_ACTION_MINIMUM:
 126                         rdev->pm.requested_power_state_index = min_power_state_index;
 127                         rdev->pm.requested_clock_mode_index = 0;
 128                         rdev->pm.dynpm_can_downclock = false;
 129                         break;
 130                 case DYNPM_ACTION_DOWNCLOCK:
 131                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 132                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 133                                 rdev->pm.dynpm_can_downclock = false;
 134                         } else {
 135                                 if (rdev->pm.active_crtc_count > 1) {
 136                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 137                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 138                                                         continue;
 139                                                 else if (i >= rdev->pm.current_power_state_index) {
 140                                                         rdev->pm.requested_power_state_index =
 141                                                                 rdev->pm.current_power_state_index;
 142                                                         break;
 143                                                 } else {
 144                                                         rdev->pm.requested_power_state_index = i;
 145                                                         break;
 146                                                 }
 147                                         }
 148                                 } else {
 149                                         if (rdev->pm.current_power_state_index == 0)
 150                                                 rdev->pm.requested_power_state_index =
 151                                                         rdev->pm.num_power_states - 1;
 152                                         else
 153                                                 rdev->pm.requested_power_state_index =
 154                                                         rdev->pm.current_power_state_index - 1;
 155                                 }
 156                         }
 157                         rdev->pm.requested_clock_mode_index = 0;
 158                         /* don't use the power state if crtcs are active and no display flag is set */
 159                         if ((rdev->pm.active_crtc_count > 0) &&
 160                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 161                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 162                              RADEON_PM_MODE_NO_DISPLAY)) {
 163                                 rdev->pm.requested_power_state_index++;
 164                         }
 165                         break;
 166                 case DYNPM_ACTION_UPCLOCK:
 167                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 168                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 169                                 rdev->pm.dynpm_can_upclock = false;
 170                         } else {
 171                                 if (rdev->pm.active_crtc_count > 1) {
 172                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 173                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 174                                                         continue;
 175                                                 else if (i <= rdev->pm.current_power_state_index) {
 176                                                         rdev->pm.requested_power_state_index =
 177                                                                 rdev->pm.current_power_state_index;
 178                                                         break;
 179                                                 } else {
 180                                                         rdev->pm.requested_power_state_index = i;
 181                                                         break;
 182                                                 }
 183                                         }
 184                                 } else
 185                                         rdev->pm.requested_power_state_index =
 186                                                 rdev->pm.current_power_state_index + 1;
 187                         }
 188                         rdev->pm.requested_clock_mode_index = 0;
 189                         break;
 190                 case DYNPM_ACTION_DEFAULT:
 191                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 192                         rdev->pm.requested_clock_mode_index = 0;
 193                         rdev->pm.dynpm_can_upclock = false;
 194                         break;
 195                 case DYNPM_ACTION_NONE:
 196                 default:
 197                         DRM_ERROR("Requested mode for not defined action\n");
 198                         return;
 199                 }
 200         } else {
 201                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 202                 /* for now just select the first power state and switch between clock modes */
 203                 /* power state array is low to high, default is first (0) */
 204                 if (rdev->pm.active_crtc_count > 1) {
 205                         rdev->pm.requested_power_state_index = -1;
 206                         /* start at 1 as we don't want the default mode */
 207                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 208                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 209                                         continue;
 210                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 211                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 212                                         rdev->pm.requested_power_state_index = i;
 213                                         break;
 214                                 }
 215                         }
 216                         /* if nothing selected, grab the default state. */
 217                         if (rdev->pm.requested_power_state_index == -1)
 218                                 rdev->pm.requested_power_state_index = 0;
 219                 } else
 220                         rdev->pm.requested_power_state_index = 1;
 221
 222                 switch (rdev->pm.dynpm_planned_action) {
 223                 case DYNPM_ACTION_MINIMUM:
 224                         rdev->pm.requested_clock_mode_index = 0;
 225                         rdev->pm.dynpm_can_downclock = false;
 226                         break;
 227                 case DYNPM_ACTION_DOWNCLOCK:
 228                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 229                                 if (rdev->pm.current_clock_mode_index == 0) {
 230                                         rdev->pm.requested_clock_mode_index = 0;
 231                                         rdev->pm.dynpm_can_downclock = false;
 232                                 } else
 233                                         rdev->pm.requested_clock_mode_index =
 234                                                 rdev->pm.current_clock_mode_index - 1;
 235                         } else {
 236                                 rdev->pm.requested_clock_mode_index = 0;
 237                                 rdev->pm.dynpm_can_downclock = false;
 238                         }
 239                         /* don't use the power state if crtcs are active and no display flag is set */
 240                         if ((rdev->pm.active_crtc_count > 0) &&
 241                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 242                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 243                              RADEON_PM_MODE_NO_DISPLAY)) {
 244                                 rdev->pm.requested_clock_mode_index++;
 245                         }
 246                         break;
 247                 case DYNPM_ACTION_UPCLOCK:
 248                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 249                                 if (rdev->pm.current_clock_mode_index ==
 250                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 251                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 252                                         rdev->pm.dynpm_can_upclock = false;
 253                                 } else
 254                                         rdev->pm.requested_clock_mode_index =
 255                                                 rdev->pm.current_clock_mode_index + 1;
 256                         } else {
 257                                 rdev->pm.requested_clock_mode_index =
 258                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 259                                 rdev->pm.dynpm_can_upclock = false;
 260                         }
 261                         break;
 262                 case DYNPM_ACTION_DEFAULT:
 263                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 264                         rdev->pm.requested_clock_mode_index = 0;
 265                         rdev->pm.dynpm_can_upclock = false;
 266                         break;
 267                 case DYNPM_ACTION_NONE:
 268                 default:
 269                         DRM_ERROR("Requested mode for not defined action\n");
 270                         return;
 271                 }
 272         }
 273
 274         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 275                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 276                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 277                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 278                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 279                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 280                   pcie_lanes);
 281 }
 282
 283 static int r600_pm_get_type_index(struct radeon_device *rdev,
 284                                   enum radeon_pm_state_type ps_type,
 285                                   int instance)
 286 {
 287         int i;
 288         int found_instance = -1;
 289
 290         for (i = 0; i < rdev->pm.num_power_states; i++) {
 291                 if (rdev->pm.power_state[i].type == ps_type) {
 292                         found_instance++;
 293                         if (found_instance == instance)
 294                                 return i;
 295                 }
 296         }
 297         /* return default if no match */
 298         return rdev->pm.default_power_state_index;
 299 }
 300
 301 void rs780_pm_init_profile(struct radeon_device *rdev)
 302 {
 303         if (rdev->pm.num_power_states == 2) {
 304                 /* default */
 305                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 306                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 307                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 309                 /* low sh */
 310                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 314                 /* mid sh */
 315                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 319                 /* high sh */
 320                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 322                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 324                 /* low mh */
 325                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 329                 /* mid mh */
 330                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 331                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 332                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 334                 /* high mh */
 335                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 336                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 337                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 339         } else if (rdev->pm.num_power_states == 3) {
 340                 /* default */
 341                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 342                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 343                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 345                 /* low sh */
 346                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 350                 /* mid sh */
 351                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 352                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 354                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 355                 /* high sh */
 356                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 357                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 358                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 360                 /* low mh */
 361                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 362                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 364                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 365                 /* mid mh */
 366                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 367                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 368                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 369                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 370                 /* high mh */
 371                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 372                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 373                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 375         } else {
 376                 /* default */
 377                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 378                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 379                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 381                 /* low sh */
 382                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 386                 /* mid sh */
 387                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 388                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 391                 /* high sh */
 392                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 393                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 394                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 396                 /* low mh */
 397                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 398                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 399                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 400                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 401                 /* mid mh */
 402                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 403                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 404                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 405                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 406                 /* high mh */
 407                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 408                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 409                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 410                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 411         }
 412 }
 413
 414 void r600_pm_init_profile(struct radeon_device *rdev)
 415 {
 416         if (rdev->family == CHIP_R600) {
 417                 /* XXX */
 418                 /* default */
 419                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 421                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 422                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 423                 /* low sh */
 424                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 426                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 427                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 428                 /* mid sh */
 429                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 431                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 432                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 433                 /* high sh */
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 436                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 438                 /* low mh */
 439                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 441                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 442                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 443                 /* mid mh */
 444                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 446                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 447                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 448                 /* high mh */
 449                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 453         } else {
 454                 if (rdev->pm.num_power_states < 4) {
 455                         /* default */
 456                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 457                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 458                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 459                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 460                         /* low sh */
 461                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 462                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 463                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 464                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 465                         /* mid sh */
 466                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 467                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 468                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 469                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 470                         /* high sh */
 471                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 472                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 473                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 475                         /* low mh */
 476                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 477                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 478                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 479                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 480                         /* low mh */
 481                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 482                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 483                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 484                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 485                         /* high mh */
 486                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 487                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 488                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 490                 } else {
 491                         /* default */
 492                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 493                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 494                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 495                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 496                         /* low sh */
 497                         if (rdev->flags & RADEON_IS_MOBILITY) {
 498                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 499                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 501                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 502                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 503                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 504                         } else {
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 506                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 508                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 509                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 510                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 511                         }
 512                         /* mid sh */
 513                         if (rdev->flags & RADEON_IS_MOBILITY) {
 514                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 515                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 517                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 518                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 519                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 520                         } else {
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 522                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 524                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 525                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 526                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 527                         }
 528                         /* high sh */
 529                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 530                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 531                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 532                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 533                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 534                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 535                         /* low mh */
 536                         if (rdev->flags & RADEON_IS_MOBILITY) {
 537                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 538                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 540                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 541                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 542                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 543                         } else {
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 545                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 547                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 548                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 549                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 550                         }
 551                         /* mid mh */
 552                         if (rdev->flags & RADEON_IS_MOBILITY) {
 553                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 554                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 556                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 557                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 558                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 559                         } else {
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 561                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 563                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 564                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 565                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 566                         }
 567                         /* high mh */
 568                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 569                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 570                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 571                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 572                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 573                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 574                 }
 575         }
 576 }
 577
 578 void r600_pm_misc(struct radeon_device *rdev)
 579 {
 580         int req_ps_idx = rdev->pm.requested_power_state_index;
 581         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 582         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 583         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 584
 585         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 586                 if (voltage->voltage != rdev->pm.current_vddc) {
 587                         radeon_atom_set_voltage(rdev, voltage->voltage);
 588                         rdev->pm.current_vddc = voltage->voltage;
 589                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 590                 }
 591         }
 592 }
 593
 594 bool r600_gui_idle(struct radeon_device *rdev)
 595 {
 596         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 597                 return false;
 598         else
 599                 return true;
 600 }
 601
 602 /* hpd for digital panel detect/disconnect */
 603 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 604 {
 605         bool connected = false;
 606
 607         if (ASIC_IS_DCE3(rdev)) {
 608                 switch (hpd) {
 609                 case RADEON_HPD_1:
 610                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 611                                 connected = true;
 612                         break;
 613                 case RADEON_HPD_2:
 614                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 615                                 connected = true;
 616                         break;
 617                 case RADEON_HPD_3:
 618                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 619                                 connected = true;
 620                         break;
 621                 case RADEON_HPD_4:
 622                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 623                                 connected = true;
 624                         break;
 625                         /* DCE 3.2 */
 626                 case RADEON_HPD_5:
 627                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 628                                 connected = true;
 629                         break;
 630                 case RADEON_HPD_6:
 631                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 632                                 connected = true;
 633                         break;
 634                 default:
 635                         break;
 636                 }
 637         } else {
 638                 switch (hpd) {
 639                 case RADEON_HPD_1:
 640                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 641                                 connected = true;
 642                         break;
 643                 case RADEON_HPD_2:
 644                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 645                                 connected = true;
 646                         break;
 647                 case RADEON_HPD_3:
 648                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 649                                 connected = true;
 650                         break;
 651                 default:
 652                         break;
 653                 }
 654         }
 655         return connected;
 656 }
 657
 658 void r600_hpd_set_polarity(struct radeon_device *rdev,
 659                            enum radeon_hpd_id hpd)
 660 {
 661         u32 tmp;
 662         bool connected = r600_hpd_sense(rdev, hpd);
 663
 664         if (ASIC_IS_DCE3(rdev)) {
 665                 switch (hpd) {
 666                 case RADEON_HPD_1:
 667                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 668                         if (connected)
 669                                 tmp &= ~DC_HPDx_INT_POLARITY;
 670                         else
 671                                 tmp |= DC_HPDx_INT_POLARITY;
 672                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 673                         break;
 674                 case RADEON_HPD_2:
 675                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 676                         if (connected)
 677                                 tmp &= ~DC_HPDx_INT_POLARITY;
 678                         else
 679                                 tmp |= DC_HPDx_INT_POLARITY;
 680                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 681                         break;
 682                 case RADEON_HPD_3:
 683                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 684                         if (connected)
 685                                 tmp &= ~DC_HPDx_INT_POLARITY;
 686                         else
 687                                 tmp |= DC_HPDx_INT_POLARITY;
 688                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 689                         break;
 690                 case RADEON_HPD_4:
 691                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 692                         if (connected)
 693                                 tmp &= ~DC_HPDx_INT_POLARITY;
 694                         else
 695                                 tmp |= DC_HPDx_INT_POLARITY;
 696                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 697                         break;
 698                 case RADEON_HPD_5:
 699                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 700                         if (connected)
 701                                 tmp &= ~DC_HPDx_INT_POLARITY;
 702                         else
 703                                 tmp |= DC_HPDx_INT_POLARITY;
 704                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 705                         break;
 706                         /* DCE 3.2 */
 707                 case RADEON_HPD_6:
 708                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 709                         if (connected)
 710                                 tmp &= ~DC_HPDx_INT_POLARITY;
 711                         else
 712                                 tmp |= DC_HPDx_INT_POLARITY;
 713                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 714                         break;
 715                 default:
 716                         break;
 717                 }
 718         } else {
 719                 switch (hpd) {
 720                 case RADEON_HPD_1:
 721                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 722                         if (connected)
 723                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 724                         else
 725                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 726                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 727                         break;
 728                 case RADEON_HPD_2:
 729                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 730                         if (connected)
 731                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 732                         else
 733                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 734                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 735                         break;
 736                 case RADEON_HPD_3:
 737                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 738                         if (connected)
 739                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 740                         else
 741                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 742                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 743                         break;
 744                 default:
 745                         break;
 746                 }
 747         }
 748 }
 749
 750 void r600_hpd_init(struct radeon_device *rdev)
 751 {
 752         struct drm_device *dev = rdev->ddev;
 753         struct drm_connector *connector;
 754
 755         if (ASIC_IS_DCE3(rdev)) {
 756                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 757                 if (ASIC_IS_DCE32(rdev))
 758                         tmp |= DC_HPDx_EN;
 759
 760                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 761                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 762                         switch (radeon_connector->hpd.hpd) {
 763                         case RADEON_HPD_1:
 764                                 WREG32(DC_HPD1_CONTROL, tmp);
 765                                 rdev->irq.hpd[0] = true;
 766                                 break;
 767                         case RADEON_HPD_2:
 768                                 WREG32(DC_HPD2_CONTROL, tmp);
 769                                 rdev->irq.hpd[1] = true;
 770                                 break;
 771                         case RADEON_HPD_3:
 772                                 WREG32(DC_HPD3_CONTROL, tmp);
 773                                 rdev->irq.hpd[2] = true;
 774                                 break;
 775                         case RADEON_HPD_4:
 776                                 WREG32(DC_HPD4_CONTROL, tmp);
 777                                 rdev->irq.hpd[3] = true;
 778                                 break;
 779                                 /* DCE 3.2 */
 780                         case RADEON_HPD_5:
 781                                 WREG32(DC_HPD5_CONTROL, tmp);
 782                                 rdev->irq.hpd[4] = true;
 783                                 break;
 784                         case RADEON_HPD_6:
 785                                 WREG32(DC_HPD6_CONTROL, tmp);
 786                                 rdev->irq.hpd[5] = true;
 787                                 break;
 788                         default:
 789                                 break;
 790                         }
 791                 }
 792         } else {
 793                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 794                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 795                         switch (radeon_connector->hpd.hpd) {
 796                         case RADEON_HPD_1:
 797                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 798                                 rdev->irq.hpd[0] = true;
 799                                 break;
 800                         case RADEON_HPD_2:
 801                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 802                                 rdev->irq.hpd[1] = true;
 803                                 break;
 804                         case RADEON_HPD_3:
 805                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 806                                 rdev->irq.hpd[2] = true;
 807                                 break;
 808                         default:
 809                                 break;
 810                         }
 811                 }
 812         }
 813         if (rdev->irq.installed)
 814                 r600_irq_set(rdev);
 815 }
 816
 817 void r600_hpd_fini(struct radeon_device *rdev)
 818 {
 819         struct drm_device *dev = rdev->ddev;
 820         struct drm_connector *connector;
 821
 822         if (ASIC_IS_DCE3(rdev)) {
 823                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 824                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 825                         switch (radeon_connector->hpd.hpd) {
 826                         case RADEON_HPD_1:
 827                                 WREG32(DC_HPD1_CONTROL, 0);
 828                                 rdev->irq.hpd[0] = false;
 829                                 break;
 830                         case RADEON_HPD_2:
 831                                 WREG32(DC_HPD2_CONTROL, 0);
 832                                 rdev->irq.hpd[1] = false;
 833                                 break;
 834                         case RADEON_HPD_3:
 835                                 WREG32(DC_HPD3_CONTROL, 0);
 836                                 rdev->irq.hpd[2] = false;
 837                                 break;
 838                         case RADEON_HPD_4:
 839                                 WREG32(DC_HPD4_CONTROL, 0);
 840                                 rdev->irq.hpd[3] = false;
 841                                 break;
 842                                 /* DCE 3.2 */
 843                         case RADEON_HPD_5:
 844                                 WREG32(DC_HPD5_CONTROL, 0);
 845                                 rdev->irq.hpd[4] = false;
 846                                 break;
 847                         case RADEON_HPD_6:
 848                                 WREG32(DC_HPD6_CONTROL, 0);
 849                                 rdev->irq.hpd[5] = false;
 850                                 break;
 851                         default:
 852                                 break;
 853                         }
 854                 }
 855         } else {
 856                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 857                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 858                         switch (radeon_connector->hpd.hpd) {
 859                         case RADEON_HPD_1:
 860                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 861                                 rdev->irq.hpd[0] = false;
 862                                 break;
 863                         case RADEON_HPD_2:
 864                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 865                                 rdev->irq.hpd[1] = false;
 866                                 break;
 867                         case RADEON_HPD_3:
 868                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 869                                 rdev->irq.hpd[2] = false;
 870                                 break;
 871                         default:
 872                                 break;
 873                         }
 874                 }
 875         }
 876 }
 877
 878 /*
 879  * R600 PCIE GART
 880  */
 881 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 882 {
 883         unsigned i;
 884         u32 tmp;
 885
 886         /* flush hdp cache so updates hit vram */
 887         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
 888                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 889                 u32 tmp;
 890
 891                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 892                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 893                  */
 894                 WREG32(HDP_DEBUG1, 0);
 895                 tmp = readl((void __iomem *)ptr);
 896         } else
 897                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 898
 899         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 900         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 901         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 902         for (i = 0; i < rdev->usec_timeout; i++) {
 903                 /* read MC_STATUS */
 904                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 905                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 906                 if (tmp == 2) {
 907                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 908                         return;
 909                 }
 910                 if (tmp) {
 911                         return;
 912                 }
 913                 udelay(1);
 914         }
 915 }
 916
 917 int r600_pcie_gart_init(struct radeon_device *rdev)
 918 {
 919         int r;
 920
 921         if (rdev->gart.table.vram.robj) {
 922                 WARN(1, "R600 PCIE GART already initialized.\n");
 923                 return 0;
 924         }
 925         /* Initialize common gart structure */
 926         r = radeon_gart_init(rdev);
 927         if (r)
 928                 return r;
 929         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 930         return radeon_gart_table_vram_alloc(rdev);
 931 }
 932
 933 int r600_pcie_gart_enable(struct radeon_device *rdev)
 934 {
 935         u32 tmp;
 936         int r, i;
 937
 938         if (rdev->gart.table.vram.robj == NULL) {
 939                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 940                 return -EINVAL;
 941         }
 942         r = radeon_gart_table_vram_pin(rdev);
 943         if (r)
 944                 return r;
 945         radeon_gart_restore(rdev);
 946
 947         /* Setup L2 cache */
 948         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 949                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 950                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 951         WREG32(VM_L2_CNTL2, 0);
 952         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 953         /* Setup TLB control */
 954         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 955                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 956                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 957                 ENABLE_WAIT_L2_QUERY;
 958         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 961         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 971         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 972         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 973         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 974         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 975         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 976                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 977         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 978                         (u32)(rdev->dummy_page.addr >> 12));
 979         for (i = 1; i < 7; i++)
 980                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 981
 982         r600_pcie_gart_tlb_flush(rdev);
 983         rdev->gart.ready = true;
 984         return 0;
 985 }
 986
 987 void r600_pcie_gart_disable(struct radeon_device *rdev)
 988 {
 989         u32 tmp;
 990         int i, r;
 991
 992         /* Disable all tables */
 993         for (i = 0; i < 7; i++)
 994                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 995
 996         /* Disable L2 cache */
 997         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 998                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 999         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000         /* Setup L1 TLB control */
1001         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1002                 ENABLE_WAIT_L2_QUERY;
1003         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1017         if (rdev->gart.table.vram.robj) {
1018                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1019                 if (likely(r == 0)) {
1020                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1021                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1022                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1023                 }
1024         }
1025 }
1026
1027 void r600_pcie_gart_fini(struct radeon_device *rdev)
1028 {
1029         radeon_gart_fini(rdev);
1030         r600_pcie_gart_disable(rdev);
1031         radeon_gart_table_vram_free(rdev);
1032 }
1033
1034 void r600_agp_enable(struct radeon_device *rdev)
1035 {
1036         u32 tmp;
1037         int i;
1038
1039         /* Setup L2 cache */
1040         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1041                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1042                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1043         WREG32(VM_L2_CNTL2, 0);
1044         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1045         /* Setup TLB control */
1046         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1047                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1048                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1049                 ENABLE_WAIT_L2_QUERY;
1050         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1053         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1054         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1055         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1059         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1063         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064         for (i = 0; i < 7; i++)
1065                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1066 }
1067
1068 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1069 {
1070         unsigned i;
1071         u32 tmp;
1072
1073         for (i = 0; i < rdev->usec_timeout; i++) {
1074                 /* read MC_STATUS */
1075                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1076                 if (!tmp)
1077                         return 0;
1078                 udelay(1);
1079         }
1080         return -1;
1081 }
1082
1083 static void r600_mc_program(struct radeon_device *rdev)
1084 {
1085         struct rv515_mc_save save;
1086         u32 tmp;
1087         int i, j;
1088
1089         /* Initialize HDP */
1090         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1091                 WREG32((0x2c14 + j), 0x00000000);
1092                 WREG32((0x2c18 + j), 0x00000000);
1093                 WREG32((0x2c1c + j), 0x00000000);
1094                 WREG32((0x2c20 + j), 0x00000000);
1095                 WREG32((0x2c24 + j), 0x00000000);
1096         }
1097         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1098
1099         rv515_mc_stop(rdev, &save);
1100         if (r600_mc_wait_for_idle(rdev)) {
1101                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1102         }
1103         /* Lockout access through VGA aperture (doesn't exist before R600) */
1104         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1105         /* Update configuration */
1106         if (rdev->flags & RADEON_IS_AGP) {
1107                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1108                         /* VRAM before AGP */
1109                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1110                                 rdev->mc.vram_start >> 12);
1111                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112                                 rdev->mc.gtt_end >> 12);
1113                 } else {
1114                         /* VRAM after AGP */
1115                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116                                 rdev->mc.gtt_start >> 12);
1117                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118                                 rdev->mc.vram_end >> 12);
1119                 }
1120         } else {
1121                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1122                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1123         }
1124         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1125         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1126         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1127         WREG32(MC_VM_FB_LOCATION, tmp);
1128         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1129         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1130         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1131         if (rdev->flags & RADEON_IS_AGP) {
1132                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1133                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1134                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1135         } else {
1136                 WREG32(MC_VM_AGP_BASE, 0);
1137                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1138                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1139         }
1140         if (r600_mc_wait_for_idle(rdev)) {
1141                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1142         }
1143         rv515_mc_resume(rdev, &save);
1144         /* we need to own VRAM, so turn off the VGA renderer here
1145          * to stop it overwriting our objects */
1146         rv515_vga_render_disable(rdev);
1147 }
1148
1149 /**
1150  * r600_vram_gtt_location - try to find VRAM & GTT location
1151  * @rdev: radeon device structure holding all necessary informations
1152  * @mc: memory controller structure holding memory informations
1153  *
1154  * Function will place try to place VRAM at same place as in CPU (PCI)
1155  * address space as some GPU seems to have issue when we reprogram at
1156  * different address space.
1157  *
1158  * If there is not enough space to fit the unvisible VRAM after the
1159  * aperture then we limit the VRAM size to the aperture.
1160  *
1161  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1162  * them to be in one from GPU point of view so that we can program GPU to
1163  * catch access outside them (weird GPU policy see ??).
1164  *
1165  * This function will never fails, worst case are limiting VRAM or GTT.
1166  *
1167  * Note: GTT start, end, size should be initialized before calling this
1168  * function on AGP platform.
1169  */
1170 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1171 {
1172         u64 size_bf, size_af;
1173
1174         if (mc->mc_vram_size > 0xE0000000) {
1175                 /* leave room for at least 512M GTT */
1176                 dev_warn(rdev->dev, "limiting VRAM\n");
1177                 mc->real_vram_size = 0xE0000000;
1178                 mc->mc_vram_size = 0xE0000000;
1179         }
1180         if (rdev->flags & RADEON_IS_AGP) {
1181                 size_bf = mc->gtt_start;
1182                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1183                 if (size_bf > size_af) {
1184                         if (mc->mc_vram_size > size_bf) {
1185                                 dev_warn(rdev->dev, "limiting VRAM\n");
1186                                 mc->real_vram_size = size_bf;
1187                                 mc->mc_vram_size = size_bf;
1188                         }
1189                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1190                 } else {
1191                         if (mc->mc_vram_size > size_af) {
1192                                 dev_warn(rdev->dev, "limiting VRAM\n");
1193                                 mc->real_vram_size = size_af;
1194                                 mc->mc_vram_size = size_af;
1195                         }
1196                         mc->vram_start = mc->gtt_end;
1197                 }
1198                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1199                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1200                                 mc->mc_vram_size >> 20, mc->vram_start,
1201                                 mc->vram_end, mc->real_vram_size >> 20);
1202         } else {
1203                 u64 base = 0;
1204                 if (rdev->flags & RADEON_IS_IGP)
1205                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1206                 radeon_vram_location(rdev, &rdev->mc, base);
1207                 rdev->mc.gtt_base_align = 0;
1208                 radeon_gtt_location(rdev, mc);
1209         }
1210 }
1211
1212 int r600_mc_init(struct radeon_device *rdev)
1213 {
1214         u32 tmp;
1215         int chansize, numchan;
1216
1217         /* Get VRAM informations */
1218         rdev->mc.vram_is_ddr = true;
1219         tmp = RREG32(RAMCFG);
1220         if (tmp & CHANSIZE_OVERRIDE) {
1221                 chansize = 16;
1222         } else if (tmp & CHANSIZE_MASK) {
1223                 chansize = 64;
1224         } else {
1225                 chansize = 32;
1226         }
1227         tmp = RREG32(CHMAP);
1228         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1229         case 0:
1230         default:
1231                 numchan = 1;
1232                 break;
1233         case 1:
1234                 numchan = 2;
1235                 break;
1236         case 2:
1237                 numchan = 4;
1238                 break;
1239         case 3:
1240                 numchan = 8;
1241                 break;
1242         }
1243         rdev->mc.vram_width = numchan * chansize;
1244         /* Could aper size report 0 ? */
1245         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1246         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1247         /* Setup GPU memory space */
1248         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1249         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1250         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1251         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1252         r600_vram_gtt_location(rdev, &rdev->mc);
1253
1254         if (rdev->flags & RADEON_IS_IGP) {
1255                 rs690_pm_info(rdev);
1256                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1257         }
1258         radeon_update_bandwidth_info(rdev);
1259         return 0;
1260 }
1261
1262 /* We doesn't check that the GPU really needs a reset we simply do the
1263  * reset, it's up to the caller to determine if the GPU needs one. We
1264  * might add an helper function to check that.
1265  */
1266 int r600_gpu_soft_reset(struct radeon_device *rdev)
1267 {
1268         struct rv515_mc_save save;
1269         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1270                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1271                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1272                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1273                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1274                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1275                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1276                                 S_008010_GUI_ACTIVE(1);
1277         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1278                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1279                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1280                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1281                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1282                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1283                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1284                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1285         u32 tmp;
1286
1287         dev_info(rdev->dev, "GPU softreset \n");
1288         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1289                 RREG32(R_008010_GRBM_STATUS));
1290         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1291                 RREG32(R_008014_GRBM_STATUS2));
1292         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1293                 RREG32(R_000E50_SRBM_STATUS));
1294         rv515_mc_stop(rdev, &save);
1295         if (r600_mc_wait_for_idle(rdev)) {
1296                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1297         }
1298         /* Disable CP parsing/prefetching */
1299         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1300         /* Check if any of the rendering block is busy and reset it */
1301         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1302             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1303                 tmp = S_008020_SOFT_RESET_CR(1) |
1304                         S_008020_SOFT_RESET_DB(1) |
1305                         S_008020_SOFT_RESET_CB(1) |
1306                         S_008020_SOFT_RESET_PA(1) |
1307                         S_008020_SOFT_RESET_SC(1) |
1308                         S_008020_SOFT_RESET_SMX(1) |
1309                         S_008020_SOFT_RESET_SPI(1) |
1310                         S_008020_SOFT_RESET_SX(1) |
1311                         S_008020_SOFT_RESET_SH(1) |
1312                         S_008020_SOFT_RESET_TC(1) |
1313                         S_008020_SOFT_RESET_TA(1) |
1314                         S_008020_SOFT_RESET_VC(1) |
1315                         S_008020_SOFT_RESET_VGT(1);
1316                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1317                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1318                 RREG32(R_008020_GRBM_SOFT_RESET);
1319                 mdelay(15);
1320                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1321         }
1322         /* Reset CP (we always reset CP) */
1323         tmp = S_008020_SOFT_RESET_CP(1);
1324         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1325         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1326         RREG32(R_008020_GRBM_SOFT_RESET);
1327         mdelay(15);
1328         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1329         /* Wait a little for things to settle down */
1330         mdelay(1);
1331         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1332                 RREG32(R_008010_GRBM_STATUS));
1333         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1334                 RREG32(R_008014_GRBM_STATUS2));
1335         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1336                 RREG32(R_000E50_SRBM_STATUS));
1337         rv515_mc_resume(rdev, &save);
1338         return 0;
1339 }
1340
1341 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1342 {
1343         u32 srbm_status;
1344         u32 grbm_status;
1345         u32 grbm_status2;
1346         int r;
1347
1348         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1349         grbm_status = RREG32(R_008010_GRBM_STATUS);
1350         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1351         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1352                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1353                 return false;
1354         }
1355         /* force CP activities */
1356         r = radeon_ring_lock(rdev, 2);
1357         if (!r) {
1358                 /* PACKET2 NOP */
1359                 radeon_ring_write(rdev, 0x80000000);
1360                 radeon_ring_write(rdev, 0x80000000);
1361                 radeon_ring_unlock_commit(rdev);
1362         }
1363         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1364         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1365 }
1366
1367 int r600_asic_reset(struct radeon_device *rdev)
1368 {
1369         return r600_gpu_soft_reset(rdev);
1370 }
1371
1372 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1373                                              u32 num_backends,
1374                                              u32 backend_disable_mask)
1375 {
1376         u32 backend_map = 0;
1377         u32 enabled_backends_mask;
1378         u32 enabled_backends_count;
1379         u32 cur_pipe;
1380         u32 swizzle_pipe[R6XX_MAX_PIPES];
1381         u32 cur_backend;
1382         u32 i;
1383
1384         if (num_tile_pipes > R6XX_MAX_PIPES)
1385                 num_tile_pipes = R6XX_MAX_PIPES;
1386         if (num_tile_pipes < 1)
1387                 num_tile_pipes = 1;
1388         if (num_backends > R6XX_MAX_BACKENDS)
1389                 num_backends = R6XX_MAX_BACKENDS;
1390         if (num_backends < 1)
1391                 num_backends = 1;
1392
1393         enabled_backends_mask = 0;
1394         enabled_backends_count = 0;
1395         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1396                 if (((backend_disable_mask >> i) & 1) == 0) {
1397                         enabled_backends_mask |= (1 << i);
1398                         ++enabled_backends_count;
1399                 }
1400                 if (enabled_backends_count == num_backends)
1401                         break;
1402         }
1403
1404         if (enabled_backends_count == 0) {
1405                 enabled_backends_mask = 1;
1406                 enabled_backends_count = 1;
1407         }
1408
1409         if (enabled_backends_count != num_backends)
1410                 num_backends = enabled_backends_count;
1411
1412         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1413         switch (num_tile_pipes) {
1414         case 1:
1415                 swizzle_pipe[0] = 0;
1416                 break;
1417         case 2:
1418                 swizzle_pipe[0] = 0;
1419                 swizzle_pipe[1] = 1;
1420                 break;
1421         case 3:
1422                 swizzle_pipe[0] = 0;
1423                 swizzle_pipe[1] = 1;
1424                 swizzle_pipe[2] = 2;
1425                 break;
1426         case 4:
1427                 swizzle_pipe[0] = 0;
1428                 swizzle_pipe[1] = 1;
1429                 swizzle_pipe[2] = 2;
1430                 swizzle_pipe[3] = 3;
1431                 break;
1432         case 5:
1433                 swizzle_pipe[0] = 0;
1434                 swizzle_pipe[1] = 1;
1435                 swizzle_pipe[2] = 2;
1436                 swizzle_pipe[3] = 3;
1437                 swizzle_pipe[4] = 4;
1438                 break;
1439         case 6:
1440                 swizzle_pipe[0] = 0;
1441                 swizzle_pipe[1] = 2;
1442                 swizzle_pipe[2] = 4;
1443                 swizzle_pipe[3] = 5;
1444                 swizzle_pipe[4] = 1;
1445                 swizzle_pipe[5] = 3;
1446                 break;
1447         case 7:
1448                 swizzle_pipe[0] = 0;
1449                 swizzle_pipe[1] = 2;
1450                 swizzle_pipe[2] = 4;
1451                 swizzle_pipe[3] = 6;
1452                 swizzle_pipe[4] = 1;
1453                 swizzle_pipe[5] = 3;
1454                 swizzle_pipe[6] = 5;
1455                 break;
1456         case 8:
1457                 swizzle_pipe[0] = 0;
1458                 swizzle_pipe[1] = 2;
1459                 swizzle_pipe[2] = 4;
1460                 swizzle_pipe[3] = 6;
1461                 swizzle_pipe[4] = 1;
1462                 swizzle_pipe[5] = 3;
1463                 swizzle_pipe[6] = 5;
1464                 swizzle_pipe[7] = 7;
1465                 break;
1466         }
1467
1468         cur_backend = 0;
1469         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1470                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1471                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1472
1473                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1474
1475                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1476         }
1477
1478         return backend_map;
1479 }
1480
1481 int r600_count_pipe_bits(uint32_t val)
1482 {
1483         int i, ret = 0;
1484
1485         for (i = 0; i < 32; i++) {
1486                 ret += val & 1;
1487                 val >>= 1;
1488         }
1489         return ret;
1490 }
1491
1492 void r600_gpu_init(struct radeon_device *rdev)
1493 {
1494         u32 tiling_config;
1495         u32 ramcfg;
1496         u32 backend_map;
1497         u32 cc_rb_backend_disable;
1498         u32 cc_gc_shader_pipe_config;
1499         u32 tmp;
1500         int i, j;
1501         u32 sq_config;
1502         u32 sq_gpr_resource_mgmt_1 = 0;
1503         u32 sq_gpr_resource_mgmt_2 = 0;
1504         u32 sq_thread_resource_mgmt = 0;
1505         u32 sq_stack_resource_mgmt_1 = 0;
1506         u32 sq_stack_resource_mgmt_2 = 0;
1507
1508         /* FIXME: implement */
1509         switch (rdev->family) {
1510         case CHIP_R600:
1511                 rdev->config.r600.max_pipes = 4;
1512                 rdev->config.r600.max_tile_pipes = 8;
1513                 rdev->config.r600.max_simds = 4;
1514                 rdev->config.r600.max_backends = 4;
1515                 rdev->config.r600.max_gprs = 256;
1516                 rdev->config.r600.max_threads = 192;
1517                 rdev->config.r600.max_stack_entries = 256;
1518                 rdev->config.r600.max_hw_contexts = 8;
1519                 rdev->config.r600.max_gs_threads = 16;
1520                 rdev->config.r600.sx_max_export_size = 128;
1521                 rdev->config.r600.sx_max_export_pos_size = 16;
1522                 rdev->config.r600.sx_max_export_smx_size = 128;
1523                 rdev->config.r600.sq_num_cf_insts = 2;
1524                 break;
1525         case CHIP_RV630:
1526         case CHIP_RV635:
1527                 rdev->config.r600.max_pipes = 2;
1528                 rdev->config.r600.max_tile_pipes = 2;
1529                 rdev->config.r600.max_simds = 3;
1530                 rdev->config.r600.max_backends = 1;
1531                 rdev->config.r600.max_gprs = 128;
1532                 rdev->config.r600.max_threads = 192;
1533                 rdev->config.r600.max_stack_entries = 128;
1534                 rdev->config.r600.max_hw_contexts = 8;
1535                 rdev->config.r600.max_gs_threads = 4;
1536                 rdev->config.r600.sx_max_export_size = 128;
1537                 rdev->config.r600.sx_max_export_pos_size = 16;
1538                 rdev->config.r600.sx_max_export_smx_size = 128;
1539                 rdev->config.r600.sq_num_cf_insts = 2;
1540                 break;
1541         case CHIP_RV610:
1542         case CHIP_RV620:
1543         case CHIP_RS780:
1544         case CHIP_RS880:
1545                 rdev->config.r600.max_pipes = 1;
1546                 rdev->config.r600.max_tile_pipes = 1;
1547                 rdev->config.r600.max_simds = 2;
1548                 rdev->config.r600.max_backends = 1;
1549                 rdev->config.r600.max_gprs = 128;
1550                 rdev->config.r600.max_threads = 192;
1551                 rdev->config.r600.max_stack_entries = 128;
1552                 rdev->config.r600.max_hw_contexts = 4;
1553                 rdev->config.r600.max_gs_threads = 4;
1554                 rdev->config.r600.sx_max_export_size = 128;
1555                 rdev->config.r600.sx_max_export_pos_size = 16;
1556                 rdev->config.r600.sx_max_export_smx_size = 128;
1557                 rdev->config.r600.sq_num_cf_insts = 1;
1558                 break;
1559         case CHIP_RV670:
1560                 rdev->config.r600.max_pipes = 4;
1561                 rdev->config.r600.max_tile_pipes = 4;
1562                 rdev->config.r600.max_simds = 4;
1563                 rdev->config.r600.max_backends = 4;
1564                 rdev->config.r600.max_gprs = 192;
1565                 rdev->config.r600.max_threads = 192;
1566                 rdev->config.r600.max_stack_entries = 256;
1567                 rdev->config.r600.max_hw_contexts = 8;
1568                 rdev->config.r600.max_gs_threads = 16;
1569                 rdev->config.r600.sx_max_export_size = 128;
1570                 rdev->config.r600.sx_max_export_pos_size = 16;
1571                 rdev->config.r600.sx_max_export_smx_size = 128;
1572                 rdev->config.r600.sq_num_cf_insts = 2;
1573                 break;
1574         default:
1575                 break;
1576         }
1577
1578         /* Initialize HDP */
1579         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1580                 WREG32((0x2c14 + j), 0x00000000);
1581                 WREG32((0x2c18 + j), 0x00000000);
1582                 WREG32((0x2c1c + j), 0x00000000);
1583                 WREG32((0x2c20 + j), 0x00000000);
1584                 WREG32((0x2c24 + j), 0x00000000);
1585         }
1586
1587         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1588
1589         /* Setup tiling */
1590         tiling_config = 0;
1591         ramcfg = RREG32(RAMCFG);
1592         switch (rdev->config.r600.max_tile_pipes) {
1593         case 1:
1594                 tiling_config |= PIPE_TILING(0);
1595                 break;
1596         case 2:
1597                 tiling_config |= PIPE_TILING(1);
1598                 break;
1599         case 4:
1600                 tiling_config |= PIPE_TILING(2);
1601                 break;
1602         case 8:
1603                 tiling_config |= PIPE_TILING(3);
1604                 break;
1605         default:
1606                 break;
1607         }
1608         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1609         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1610         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1611         tiling_config |= GROUP_SIZE(0);
1612         rdev->config.r600.tiling_group_size = 256;
1613         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1614         if (tmp > 3) {
1615                 tiling_config |= ROW_TILING(3);
1616                 tiling_config |= SAMPLE_SPLIT(3);
1617         } else {
1618                 tiling_config |= ROW_TILING(tmp);
1619                 tiling_config |= SAMPLE_SPLIT(tmp);
1620         }
1621         tiling_config |= BANK_SWAPS(1);
1622
1623         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1624         cc_rb_backend_disable |=
1625                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1626
1627         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1628         cc_gc_shader_pipe_config |=
1629                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1630         cc_gc_shader_pipe_config |=
1631                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1632
1633         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1634                                                         (R6XX_MAX_BACKENDS -
1635                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1636                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1637                                                         (cc_rb_backend_disable >> 16));
1638         rdev->config.r600.tile_config = tiling_config;
1639         tiling_config |= BACKEND_MAP(backend_map);
1640         WREG32(GB_TILING_CONFIG, tiling_config);
1641         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1642         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1643
1644         /* Setup pipes */
1645         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1646         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1647         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1648
1649         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1650         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1651         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1652
1653         /* Setup some CP states */
1654         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1655         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1656
1657         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1658                              SYNC_WALKER | SYNC_ALIGNER));
1659         /* Setup various GPU states */
1660         if (rdev->family == CHIP_RV670)
1661                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1662
1663         tmp = RREG32(SX_DEBUG_1);
1664         tmp |= SMX_EVENT_RELEASE;
1665         if ((rdev->family > CHIP_R600))
1666                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1667         WREG32(SX_DEBUG_1, tmp);
1668
1669         if (((rdev->family) == CHIP_R600) ||
1670             ((rdev->family) == CHIP_RV630) ||
1671             ((rdev->family) == CHIP_RV610) ||
1672             ((rdev->family) == CHIP_RV620) ||
1673             ((rdev->family) == CHIP_RS780) ||
1674             ((rdev->family) == CHIP_RS880)) {
1675                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1676         } else {
1677                 WREG32(DB_DEBUG, 0);
1678         }
1679         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1680                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1681
1682         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1683         WREG32(VGT_NUM_INSTANCES, 0);
1684
1685         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1686         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1687
1688         tmp = RREG32(SQ_MS_FIFO_SIZES);
1689         if (((rdev->family) == CHIP_RV610) ||
1690             ((rdev->family) == CHIP_RV620) ||
1691             ((rdev->family) == CHIP_RS780) ||
1692             ((rdev->family) == CHIP_RS880)) {
1693                 tmp = (CACHE_FIFO_SIZE(0xa) |
1694                        FETCH_FIFO_HIWATER(0xa) |
1695                        DONE_FIFO_HIWATER(0xe0) |
1696                        ALU_UPDATE_FIFO_HIWATER(0x8));
1697         } else if (((rdev->family) == CHIP_R600) ||
1698                    ((rdev->family) == CHIP_RV630)) {
1699                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1700                 tmp |= DONE_FIFO_HIWATER(0x4);
1701         }
1702         WREG32(SQ_MS_FIFO_SIZES, tmp);
1703
1704         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1705          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1706          */
1707         sq_config = RREG32(SQ_CONFIG);
1708         sq_config &= ~(PS_PRIO(3) |
1709                        VS_PRIO(3) |
1710                        GS_PRIO(3) |
1711                        ES_PRIO(3));
1712         sq_config |= (DX9_CONSTS |
1713                       VC_ENABLE |
1714                       PS_PRIO(0) |
1715                       VS_PRIO(1) |
1716                       GS_PRIO(2) |
1717                       ES_PRIO(3));
1718
1719         if ((rdev->family) == CHIP_R600) {
1720                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1721                                           NUM_VS_GPRS(124) |
1722                                           NUM_CLAUSE_TEMP_GPRS(4));
1723                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1724                                           NUM_ES_GPRS(0));
1725                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1726                                            NUM_VS_THREADS(48) |
1727                                            NUM_GS_THREADS(4) |
1728                                            NUM_ES_THREADS(4));
1729                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1730                                             NUM_VS_STACK_ENTRIES(128));
1731                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1732                                             NUM_ES_STACK_ENTRIES(0));
1733         } else if (((rdev->family) == CHIP_RV610) ||
1734                    ((rdev->family) == CHIP_RV620) ||
1735                    ((rdev->family) == CHIP_RS780) ||
1736                    ((rdev->family) == CHIP_RS880)) {
1737                 /* no vertex cache */
1738                 sq_config &= ~VC_ENABLE;
1739
1740                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1741                                           NUM_VS_GPRS(44) |
1742                                           NUM_CLAUSE_TEMP_GPRS(2));
1743                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1744                                           NUM_ES_GPRS(17));
1745                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1746                                            NUM_VS_THREADS(78) |
1747                                            NUM_GS_THREADS(4) |
1748                                            NUM_ES_THREADS(31));
1749                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1750                                             NUM_VS_STACK_ENTRIES(40));
1751                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1752                                             NUM_ES_STACK_ENTRIES(16));
1753         } else if (((rdev->family) == CHIP_RV630) ||
1754                    ((rdev->family) == CHIP_RV635)) {
1755                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1756                                           NUM_VS_GPRS(44) |
1757                                           NUM_CLAUSE_TEMP_GPRS(2));
1758                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1759                                           NUM_ES_GPRS(18));
1760                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1761                                            NUM_VS_THREADS(78) |
1762                                            NUM_GS_THREADS(4) |
1763                                            NUM_ES_THREADS(31));
1764                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1765                                             NUM_VS_STACK_ENTRIES(40));
1766                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1767                                             NUM_ES_STACK_ENTRIES(16));
1768         } else if ((rdev->family) == CHIP_RV670) {
1769                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1770                                           NUM_VS_GPRS(44) |
1771                                           NUM_CLAUSE_TEMP_GPRS(2));
1772                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1773                                           NUM_ES_GPRS(17));
1774                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1775                                            NUM_VS_THREADS(78) |
1776                                            NUM_GS_THREADS(4) |
1777                                            NUM_ES_THREADS(31));
1778                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1779                                             NUM_VS_STACK_ENTRIES(64));
1780                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1781                                             NUM_ES_STACK_ENTRIES(64));
1782         }
1783
1784         WREG32(SQ_CONFIG, sq_config);
1785         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1786         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1787         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1788         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1789         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1790
1791         if (((rdev->family) == CHIP_RV610) ||
1792             ((rdev->family) == CHIP_RV620) ||
1793             ((rdev->family) == CHIP_RS780) ||
1794             ((rdev->family) == CHIP_RS880)) {
1795                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1796         } else {
1797                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1798         }
1799
1800         /* More default values. 2D/3D driver should adjust as needed */
1801         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1802                                          S1_X(0x4) | S1_Y(0xc)));
1803         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1804                                          S1_X(0x2) | S1_Y(0x2) |
1805                                          S2_X(0xa) | S2_Y(0x6) |
1806                                          S3_X(0x6) | S3_Y(0xa)));
1807         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1808                                              S1_X(0x4) | S1_Y(0xc) |
1809                                              S2_X(0x1) | S2_Y(0x6) |
1810                                              S3_X(0xa) | S3_Y(0xe)));
1811         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1812                                              S5_X(0x0) | S5_Y(0x0) |
1813                                              S6_X(0xb) | S6_Y(0x4) |
1814                                              S7_X(0x7) | S7_Y(0x8)));
1815
1816         WREG32(VGT_STRMOUT_EN, 0);
1817         tmp = rdev->config.r600.max_pipes * 16;
1818         switch (rdev->family) {
1819         case CHIP_RV610:
1820         case CHIP_RV620:
1821         case CHIP_RS780:
1822         case CHIP_RS880:
1823                 tmp += 32;
1824                 break;
1825         case CHIP_RV670:
1826                 tmp += 128;
1827                 break;
1828         default:
1829                 break;
1830         }
1831         if (tmp > 256) {
1832                 tmp = 256;
1833         }
1834         WREG32(VGT_ES_PER_GS, 128);
1835         WREG32(VGT_GS_PER_ES, tmp);
1836         WREG32(VGT_GS_PER_VS, 2);
1837         WREG32(VGT_GS_VERTEX_REUSE, 16);
1838
1839         /* more default values. 2D/3D driver should adjust as needed */
1840         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1841         WREG32(VGT_STRMOUT_EN, 0);
1842         WREG32(SX_MISC, 0);
1843         WREG32(PA_SC_MODE_CNTL, 0);
1844         WREG32(PA_SC_AA_CONFIG, 0);
1845         WREG32(PA_SC_LINE_STIPPLE, 0);
1846         WREG32(SPI_INPUT_Z, 0);
1847         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1848         WREG32(CB_COLOR7_FRAG, 0);
1849
1850         /* Clear render buffer base addresses */
1851         WREG32(CB_COLOR0_BASE, 0);
1852         WREG32(CB_COLOR1_BASE, 0);
1853         WREG32(CB_COLOR2_BASE, 0);
1854         WREG32(CB_COLOR3_BASE, 0);
1855         WREG32(CB_COLOR4_BASE, 0);
1856         WREG32(CB_COLOR5_BASE, 0);
1857         WREG32(CB_COLOR6_BASE, 0);
1858         WREG32(CB_COLOR7_BASE, 0);
1859         WREG32(CB_COLOR7_FRAG, 0);
1860
1861         switch (rdev->family) {
1862         case CHIP_RV610:
1863         case CHIP_RV620:
1864         case CHIP_RS780:
1865         case CHIP_RS880:
1866                 tmp = TC_L2_SIZE(8);
1867                 break;
1868         case CHIP_RV630:
1869         case CHIP_RV635:
1870                 tmp = TC_L2_SIZE(4);
1871                 break;
1872         case CHIP_R600:
1873                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1874                 break;
1875         default:
1876                 tmp = TC_L2_SIZE(0);
1877                 break;
1878         }
1879         WREG32(TC_CNTL, tmp);
1880
1881         tmp = RREG32(HDP_HOST_PATH_CNTL);
1882         WREG32(HDP_HOST_PATH_CNTL, tmp);
1883
1884         tmp = RREG32(ARB_POP);
1885         tmp |= ENABLE_TC128;
1886         WREG32(ARB_POP, tmp);
1887
1888         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1889         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1890                                NUM_CLIP_SEQ(3)));
1891         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1892 }
1893
1894
1895 /*
1896  * Indirect registers accessor
1897  */
1898 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1899 {
1900         u32 r;
1901
1902         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1903         (void)RREG32(PCIE_PORT_INDEX);
1904         r = RREG32(PCIE_PORT_DATA);
1905         return r;
1906 }
1907
1908 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1909 {
1910         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1911         (void)RREG32(PCIE_PORT_INDEX);
1912         WREG32(PCIE_PORT_DATA, (v));
1913         (void)RREG32(PCIE_PORT_DATA);
1914 }
1915
1916 /*
1917  * CP & Ring
1918  */
1919 void r600_cp_stop(struct radeon_device *rdev)
1920 {
1921         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1922         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1923 }
1924
1925 int r600_init_microcode(struct radeon_device *rdev)
1926 {
1927         struct platform_device *pdev;
1928         const char *chip_name;
1929         const char *rlc_chip_name;
1930         size_t pfp_req_size, me_req_size, rlc_req_size;
1931         char fw_name[30];
1932         int err;
1933
1934         DRM_DEBUG("\n");
1935
1936         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1937         err = IS_ERR(pdev);
1938         if (err) {
1939                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1940                 return -EINVAL;
1941         }
1942
1943         switch (rdev->family) {
1944         case CHIP_R600:
1945                 chip_name = "R600";
1946                 rlc_chip_name = "R600";
1947                 break;
1948         case CHIP_RV610:
1949                 chip_name = "RV610";
1950                 rlc_chip_name = "R600";
1951                 break;
1952         case CHIP_RV630:
1953                 chip_name = "RV630";
1954                 rlc_chip_name = "R600";
1955                 break;
1956         case CHIP_RV620:
1957                 chip_name = "RV620";
1958                 rlc_chip_name = "R600";
1959                 break;
1960         case CHIP_RV635:
1961                 chip_name = "RV635";
1962                 rlc_chip_name = "R600";
1963                 break;
1964         case CHIP_RV670:
1965                 chip_name = "RV670";
1966                 rlc_chip_name = "R600";
1967                 break;
1968         case CHIP_RS780:
1969         case CHIP_RS880:
1970                 chip_name = "RS780";
1971                 rlc_chip_name = "R600";
1972                 break;
1973         case CHIP_RV770:
1974                 chip_name = "RV770";
1975                 rlc_chip_name = "R700";
1976                 break;
1977         case CHIP_RV730:
1978         case CHIP_RV740:
1979                 chip_name = "RV730";
1980                 rlc_chip_name = "R700";
1981                 break;
1982         case CHIP_RV710:
1983                 chip_name = "RV710";
1984                 rlc_chip_name = "R700";
1985                 break;
1986         case CHIP_CEDAR:
1987                 chip_name = "CEDAR";
1988                 rlc_chip_name = "CEDAR";
1989                 break;
1990         case CHIP_REDWOOD:
1991                 chip_name = "REDWOOD";
1992                 rlc_chip_name = "REDWOOD";
1993                 break;
1994         case CHIP_JUNIPER:
1995                 chip_name = "JUNIPER";
1996                 rlc_chip_name = "JUNIPER";
1997                 break;
1998         case CHIP_CYPRESS:
1999         case CHIP_HEMLOCK:
2000                 chip_name = "CYPRESS";
2001                 rlc_chip_name = "CYPRESS";
2002                 break;
2003         default: BUG();
2004         }
2005
2006         if (rdev->family >= CHIP_CEDAR) {
2007                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2008                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2009                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2010         } else if (rdev->family >= CHIP_RV770) {
2011                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2012                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2013                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2014         } else {
2015                 pfp_req_size = PFP_UCODE_SIZE * 4;
2016                 me_req_size = PM4_UCODE_SIZE * 12;
2017                 rlc_req_size = RLC_UCODE_SIZE * 4;
2018         }
2019
2020         DRM_INFO("Loading %s Microcode\n", chip_name);
2021
2022         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2023         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2024         if (err)
2025                 goto out;
2026         if (rdev->pfp_fw->size != pfp_req_size) {
2027                 printk(KERN_ERR
2028                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2029                        rdev->pfp_fw->size, fw_name);
2030                 err = -EINVAL;
2031                 goto out;
2032         }
2033
2034         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2035         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2036         if (err)
2037                 goto out;
2038         if (rdev->me_fw->size != me_req_size) {
2039                 printk(KERN_ERR
2040                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2041                        rdev->me_fw->size, fw_name);
2042                 err = -EINVAL;
2043         }
2044
2045         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2046         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2047         if (err)
2048                 goto out;
2049         if (rdev->rlc_fw->size != rlc_req_size) {
2050                 printk(KERN_ERR
2051                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2052                        rdev->rlc_fw->size, fw_name);
2053                 err = -EINVAL;
2054         }
2055
2056 out:
2057         platform_device_unregister(pdev);
2058
2059         if (err) {
2060                 if (err != -EINVAL)
2061                         printk(KERN_ERR
2062                                "r600_cp: Failed to load firmware \"%s\"\n",
2063                                fw_name);
2064                 release_firmware(rdev->pfp_fw);
2065                 rdev->pfp_fw = NULL;
2066                 release_firmware(rdev->me_fw);
2067                 rdev->me_fw = NULL;
2068                 release_firmware(rdev->rlc_fw);
2069                 rdev->rlc_fw = NULL;
2070         }
2071         return err;
2072 }
2073
2074 static int r600_cp_load_microcode(struct radeon_device *rdev)
2075 {
2076         const __be32 *fw_data;
2077         int i;
2078
2079         if (!rdev->me_fw || !rdev->pfp_fw)
2080                 return -EINVAL;
2081
2082         r600_cp_stop(rdev);
2083
2084         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2085
2086         /* Reset cp */
2087         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2088         RREG32(GRBM_SOFT_RESET);
2089         mdelay(15);
2090         WREG32(GRBM_SOFT_RESET, 0);
2091
2092         WREG32(CP_ME_RAM_WADDR, 0);
2093
2094         fw_data = (const __be32 *)rdev->me_fw->data;
2095         WREG32(CP_ME_RAM_WADDR, 0);
2096         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2097                 WREG32(CP_ME_RAM_DATA,
2098                        be32_to_cpup(fw_data++));
2099
2100         fw_data = (const __be32 *)rdev->pfp_fw->data;
2101         WREG32(CP_PFP_UCODE_ADDR, 0);
2102         for (i = 0; i < PFP_UCODE_SIZE; i++)
2103                 WREG32(CP_PFP_UCODE_DATA,
2104                        be32_to_cpup(fw_data++));
2105
2106         WREG32(CP_PFP_UCODE_ADDR, 0);
2107         WREG32(CP_ME_RAM_WADDR, 0);
2108         WREG32(CP_ME_RAM_RADDR, 0);
2109         return 0;
2110 }
2111
2112 int r600_cp_start(struct radeon_device *rdev)
2113 {
2114         int r;
2115         uint32_t cp_me;
2116
2117         r = radeon_ring_lock(rdev, 7);
2118         if (r) {
2119                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2120                 return r;
2121         }
2122         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2123         radeon_ring_write(rdev, 0x1);
2124         if (rdev->family >= CHIP_RV770) {
2125                 radeon_ring_write(rdev, 0x0);
2126                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2127         } else {
2128                 radeon_ring_write(rdev, 0x3);
2129                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2130         }
2131         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2132         radeon_ring_write(rdev, 0);
2133         radeon_ring_write(rdev, 0);
2134         radeon_ring_unlock_commit(rdev);
2135
2136         cp_me = 0xff;
2137         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2138         return 0;
2139 }
2140
2141 int r600_cp_resume(struct radeon_device *rdev)
2142 {
2143         u32 tmp;
2144         u32 rb_bufsz;
2145         int r;
2146
2147         /* Reset cp */
2148         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2149         RREG32(GRBM_SOFT_RESET);
2150         mdelay(15);
2151         WREG32(GRBM_SOFT_RESET, 0);
2152
2153         /* Set ring buffer size */
2154         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2155         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2156 #ifdef __BIG_ENDIAN
2157         tmp |= BUF_SWAP_32BIT;
2158 #endif
2159         WREG32(CP_RB_CNTL, tmp);
2160         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2161
2162         /* Set the write pointer delay */
2163         WREG32(CP_RB_WPTR_DELAY, 0);
2164
2165         /* Initialize the ring buffer's read and write pointers */
2166         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2167         WREG32(CP_RB_RPTR_WR, 0);
2168         WREG32(CP_RB_WPTR, 0);
2169         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2170         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2171         mdelay(1);
2172         WREG32(CP_RB_CNTL, tmp);
2173
2174         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2175         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2176
2177         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2178         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2179
2180         r600_cp_start(rdev);
2181         rdev->cp.ready = true;
2182         r = radeon_ring_test(rdev);
2183         if (r) {
2184                 rdev->cp.ready = false;
2185                 return r;
2186         }
2187         return 0;
2188 }
2189
2190 void r600_cp_commit(struct radeon_device *rdev)
2191 {
2192         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2193         (void)RREG32(CP_RB_WPTR);
2194 }
2195
2196 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2197 {
2198         u32 rb_bufsz;
2199
2200         /* Align ring size */
2201         rb_bufsz = drm_order(ring_size / 8);
2202         ring_size = (1 << (rb_bufsz + 1)) * 4;
2203         rdev->cp.ring_size = ring_size;
2204         rdev->cp.align_mask = 16 - 1;
2205 }
2206
2207 void r600_cp_fini(struct radeon_device *rdev)
2208 {
2209         r600_cp_stop(rdev);
2210         radeon_ring_fini(rdev);
2211 }
2212
2213
2214 /*
2215  * GPU scratch registers helpers function.
2216  */
2217 void r600_scratch_init(struct radeon_device *rdev)
2218 {
2219         int i;
2220
2221         rdev->scratch.num_reg = 7;
2222         for (i = 0; i < rdev->scratch.num_reg; i++) {
2223                 rdev->scratch.free[i] = true;
2224                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2225         }
2226 }
2227
2228 int r600_ring_test(struct radeon_device *rdev)
2229 {
2230         uint32_t scratch;
2231         uint32_t tmp = 0;
2232         unsigned i;
2233         int r;
2234
2235         r = radeon_scratch_get(rdev, &scratch);
2236         if (r) {
2237                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2238                 return r;
2239         }
2240         WREG32(scratch, 0xCAFEDEAD);
2241         r = radeon_ring_lock(rdev, 3);
2242         if (r) {
2243                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2244                 radeon_scratch_free(rdev, scratch);
2245                 return r;
2246         }
2247         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2248         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2249         radeon_ring_write(rdev, 0xDEADBEEF);
2250         radeon_ring_unlock_commit(rdev);
2251         for (i = 0; i < rdev->usec_timeout; i++) {
2252                 tmp = RREG32(scratch);
2253                 if (tmp == 0xDEADBEEF)
2254                         break;
2255                 DRM_UDELAY(1);
2256         }
2257         if (i < rdev->usec_timeout) {
2258                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2259         } else {
2260                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2261                           scratch, tmp);
2262                 r = -EINVAL;
2263         }
2264         radeon_scratch_free(rdev, scratch);
2265         return r;
2266 }
2267
2268 void r600_wb_disable(struct radeon_device *rdev)
2269 {
2270         int r;
2271
2272         WREG32(SCRATCH_UMSK, 0);
2273         if (rdev->wb.wb_obj) {
2274                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2275                 if (unlikely(r != 0))
2276                         return;
2277                 radeon_bo_kunmap(rdev->wb.wb_obj);
2278                 radeon_bo_unpin(rdev->wb.wb_obj);
2279                 radeon_bo_unreserve(rdev->wb.wb_obj);
2280         }
2281 }
2282
2283 void r600_wb_fini(struct radeon_device *rdev)
2284 {
2285         r600_wb_disable(rdev);
2286         if (rdev->wb.wb_obj) {
2287                 radeon_bo_unref(&rdev->wb.wb_obj);
2288                 rdev->wb.wb = NULL;
2289                 rdev->wb.wb_obj = NULL;
2290         }
2291 }
2292
2293 int r600_wb_enable(struct radeon_device *rdev)
2294 {
2295         int r;
2296
2297         if (rdev->wb.wb_obj == NULL) {
2298                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2299                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2300                 if (r) {
2301                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2302                         return r;
2303                 }
2304                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2305                 if (unlikely(r != 0)) {
2306                         r600_wb_fini(rdev);
2307                         return r;
2308                 }
2309                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2310                                 &rdev->wb.gpu_addr);
2311                 if (r) {
2312                         radeon_bo_unreserve(rdev->wb.wb_obj);
2313                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2314                         r600_wb_fini(rdev);
2315                         return r;
2316                 }
2317                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2318                 radeon_bo_unreserve(rdev->wb.wb_obj);
2319                 if (r) {
2320                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2321                         r600_wb_fini(rdev);
2322                         return r;
2323                 }
2324         }
2325         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2326         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2327         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2328         WREG32(SCRATCH_UMSK, 0xff);
2329         return 0;
2330 }
2331
2332 void r600_fence_ring_emit(struct radeon_device *rdev,
2333                           struct radeon_fence *fence)
2334 {
2335         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
2336
2337         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2338         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2339         /* wait for 3D idle clean */
2340         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2341         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2342         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2343         /* Emit fence sequence & fire IRQ */
2344         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2345         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2346         radeon_ring_write(rdev, fence->seq);
2347         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2348         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2349         radeon_ring_write(rdev, RB_INT_STAT);
2350 }
2351
2352 int r600_copy_blit(struct radeon_device *rdev,
2353                    uint64_t src_offset, uint64_t dst_offset,
2354                    unsigned num_pages, struct radeon_fence *fence)
2355 {
2356         int r;
2357
2358         mutex_lock(&rdev->r600_blit.mutex);
2359         rdev->r600_blit.vb_ib = NULL;
2360         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2361         if (r) {
2362                 if (rdev->r600_blit.vb_ib)
2363                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2364                 mutex_unlock(&rdev->r600_blit.mutex);
2365                 return r;
2366         }
2367         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2368         r600_blit_done_copy(rdev, fence);
2369         mutex_unlock(&rdev->r600_blit.mutex);
2370         return 0;
2371 }
2372
2373 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2374                          uint32_t tiling_flags, uint32_t pitch,
2375                          uint32_t offset, uint32_t obj_size)
2376 {
2377         /* FIXME: implement */
2378         return 0;
2379 }
2380
2381 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2382 {
2383         /* FIXME: implement */
2384 }
2385
2386
2387 bool r600_card_posted(struct radeon_device *rdev)
2388 {
2389         uint32_t reg;
2390
2391         /* first check CRTCs */
2392         reg = RREG32(D1CRTC_CONTROL) |
2393                 RREG32(D2CRTC_CONTROL);
2394         if (reg & CRTC_EN)
2395                 return true;
2396
2397         /* then check MEM_SIZE, in case the crtcs are off */
2398         if (RREG32(CONFIG_MEMSIZE))
2399                 return true;
2400
2401         return false;
2402 }
2403
2404 int r600_startup(struct radeon_device *rdev)
2405 {
2406         int r;
2407
2408         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2409                 r = r600_init_microcode(rdev);
2410                 if (r) {
2411                         DRM_ERROR("Failed to load firmware!\n");
2412                         return r;
2413                 }
2414         }
2415
2416         r600_mc_program(rdev);
2417         if (rdev->flags & RADEON_IS_AGP) {
2418                 r600_agp_enable(rdev);
2419         } else {
2420                 r = r600_pcie_gart_enable(rdev);
2421                 if (r)
2422                         return r;
2423         }
2424         r600_gpu_init(rdev);
2425         r = r600_blit_init(rdev);
2426         if (r) {
2427                 r600_blit_fini(rdev);
2428                 rdev->asic->copy = NULL;
2429                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2430         }
2431         /* pin copy shader into vram */
2432         if (rdev->r600_blit.shader_obj) {
2433                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2434                 if (unlikely(r != 0))
2435                         return r;
2436                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2437                                 &rdev->r600_blit.shader_gpu_addr);
2438                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2439                 if (r) {
2440                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2441                         return r;
2442                 }
2443         }
2444         /* Enable IRQ */
2445         r = r600_irq_init(rdev);
2446         if (r) {
2447                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2448                 radeon_irq_kms_fini(rdev);
2449                 return r;
2450         }
2451         r600_irq_set(rdev);
2452
2453         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2454         if (r)
2455                 return r;
2456         r = r600_cp_load_microcode(rdev);
2457         if (r)
2458                 return r;
2459         r = r600_cp_resume(rdev);
2460         if (r)
2461                 return r;
2462         /* write back buffer are not vital so don't worry about failure */
2463         r600_wb_enable(rdev);
2464         return 0;
2465 }
2466
2467 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2468 {
2469         uint32_t temp;
2470
2471         temp = RREG32(CONFIG_CNTL);
2472         if (state == false) {
2473                 temp &= ~(1<<0);
2474                 temp |= (1<<1);
2475         } else {
2476                 temp &= ~(1<<1);
2477         }
2478         WREG32(CONFIG_CNTL, temp);
2479 }
2480
2481 int r600_resume(struct radeon_device *rdev)
2482 {
2483         int r;
2484
2485         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2486          * posting will perform necessary task to bring back GPU into good
2487          * shape.
2488          */
2489         /* post card */
2490         atom_asic_init(rdev->mode_info.atom_context);
2491
2492         r = r600_startup(rdev);
2493         if (r) {
2494                 DRM_ERROR("r600 startup failed on resume\n");
2495                 return r;
2496         }
2497
2498         r = r600_ib_test(rdev);
2499         if (r) {
2500                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2501                 return r;
2502         }
2503
2504         r = r600_audio_init(rdev);
2505         if (r) {
2506                 DRM_ERROR("radeon: audio resume failed\n");
2507                 return r;
2508         }
2509
2510         return r;
2511 }
2512
2513 int r600_suspend(struct radeon_device *rdev)
2514 {
2515         int r;
2516
2517         r600_audio_fini(rdev);
2518         /* FIXME: we should wait for ring to be empty */
2519         r600_cp_stop(rdev);
2520         rdev->cp.ready = false;
2521         r600_irq_suspend(rdev);
2522         r600_wb_disable(rdev);
2523         r600_pcie_gart_disable(rdev);
2524         /* unpin shaders bo */
2525         if (rdev->r600_blit.shader_obj) {
2526                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2527                 if (!r) {
2528                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2529                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2530                 }
2531         }
2532         return 0;
2533 }
2534
2535 /* Plan is to move initialization in that function and use
2536  * helper function so that radeon_device_init pretty much
2537  * do nothing more than calling asic specific function. This
2538  * should also allow to remove a bunch of callback function
2539  * like vram_info.
2540  */
2541 int r600_init(struct radeon_device *rdev)
2542 {
2543         int r;
2544
2545         r = radeon_dummy_page_init(rdev);
2546         if (r)
2547                 return r;
2548         if (r600_debugfs_mc_info_init(rdev)) {
2549                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2550         }
2551         /* This don't do much */
2552         r = radeon_gem_init(rdev);
2553         if (r)
2554                 return r;
2555         /* Read BIOS */
2556         if (!radeon_get_bios(rdev)) {
2557                 if (ASIC_IS_AVIVO(rdev))
2558                         return -EINVAL;
2559         }
2560         /* Must be an ATOMBIOS */
2561         if (!rdev->is_atom_bios) {
2562                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2563                 return -EINVAL;
2564         }
2565         r = radeon_atombios_init(rdev);
2566         if (r)
2567                 return r;
2568         /* Post card if necessary */
2569         if (!r600_card_posted(rdev)) {
2570                 if (!rdev->bios) {
2571                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2572                         return -EINVAL;
2573                 }
2574                 DRM_INFO("GPU not posted. posting now...\n");
2575                 atom_asic_init(rdev->mode_info.atom_context);
2576         }
2577         /* Initialize scratch registers */
2578         r600_scratch_init(rdev);
2579         /* Initialize surface registers */
2580         radeon_surface_init(rdev);
2581         /* Initialize clocks */
2582         radeon_get_clock_info(rdev->ddev);
2583         /* Fence driver */
2584         r = radeon_fence_driver_init(rdev);
2585         if (r)
2586                 return r;
2587         if (rdev->flags & RADEON_IS_AGP) {
2588                 r = radeon_agp_init(rdev);
2589                 if (r)
2590                         radeon_agp_disable(rdev);
2591         }
2592         r = r600_mc_init(rdev);
2593         if (r)
2594                 return r;
2595         /* Memory manager */
2596         r = radeon_bo_init(rdev);
2597         if (r)
2598                 return r;
2599
2600         r = radeon_irq_kms_init(rdev);
2601         if (r)
2602                 return r;
2603
2604         rdev->cp.ring_obj = NULL;
2605         r600_ring_init(rdev, 1024 * 1024);
2606
2607         rdev->ih.ring_obj = NULL;
2608         r600_ih_ring_init(rdev, 64 * 1024);
2609
2610         r = r600_pcie_gart_init(rdev);
2611         if (r)
2612                 return r;
2613
2614         rdev->accel_working = true;
2615         r = r600_startup(rdev);
2616         if (r) {
2617                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2618                 r600_cp_fini(rdev);
2619                 r600_wb_fini(rdev);
2620                 r600_irq_fini(rdev);
2621                 radeon_irq_kms_fini(rdev);
2622                 r600_pcie_gart_fini(rdev);
2623                 rdev->accel_working = false;
2624         }
2625         if (rdev->accel_working) {
2626                 r = radeon_ib_pool_init(rdev);
2627                 if (r) {
2628                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2629                         rdev->accel_working = false;
2630                 } else {
2631                         r = r600_ib_test(rdev);
2632                         if (r) {
2633                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2634                                 rdev->accel_working = false;
2635                         }
2636                 }
2637         }
2638
2639         r = r600_audio_init(rdev);
2640         if (r)
2641                 return r; /* TODO error handling */
2642         return 0;
2643 }
2644
2645 void r600_fini(struct radeon_device *rdev)
2646 {
2647         r600_audio_fini(rdev);
2648         r600_blit_fini(rdev);
2649         r600_cp_fini(rdev);
2650         r600_wb_fini(rdev);
2651         r600_irq_fini(rdev);
2652         radeon_irq_kms_fini(rdev);
2653         r600_pcie_gart_fini(rdev);
2654         radeon_agp_fini(rdev);
2655         radeon_gem_fini(rdev);
2656         radeon_fence_driver_fini(rdev);
2657         radeon_bo_fini(rdev);
2658         radeon_atombios_fini(rdev);
2659         kfree(rdev->bios);
2660         rdev->bios = NULL;
2661         radeon_dummy_page_fini(rdev);
2662 }
2663
2664
2665 /*
2666  * CS stuff
2667  */
2668 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2669 {
2670         /* FIXME: implement */
2671         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2672         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2673         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2674         radeon_ring_write(rdev, ib->length_dw);
2675 }
2676
2677 int r600_ib_test(struct radeon_device *rdev)
2678 {
2679         struct radeon_ib *ib;
2680         uint32_t scratch;
2681         uint32_t tmp = 0;
2682         unsigned i;
2683         int r;
2684
2685         r = radeon_scratch_get(rdev, &scratch);
2686         if (r) {
2687                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2688                 return r;
2689         }
2690         WREG32(scratch, 0xCAFEDEAD);
2691         r = radeon_ib_get(rdev, &ib);
2692         if (r) {
2693                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2694                 return r;
2695         }
2696         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2697         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2698         ib->ptr[2] = 0xDEADBEEF;
2699         ib->ptr[3] = PACKET2(0);
2700         ib->ptr[4] = PACKET2(0);
2701         ib->ptr[5] = PACKET2(0);
2702         ib->ptr[6] = PACKET2(0);
2703         ib->ptr[7] = PACKET2(0);
2704         ib->ptr[8] = PACKET2(0);
2705         ib->ptr[9] = PACKET2(0);
2706         ib->ptr[10] = PACKET2(0);
2707         ib->ptr[11] = PACKET2(0);
2708         ib->ptr[12] = PACKET2(0);
2709         ib->ptr[13] = PACKET2(0);
2710         ib->ptr[14] = PACKET2(0);
2711         ib->ptr[15] = PACKET2(0);
2712         ib->length_dw = 16;
2713         r = radeon_ib_schedule(rdev, ib);
2714         if (r) {
2715                 radeon_scratch_free(rdev, scratch);
2716                 radeon_ib_free(rdev, &ib);
2717                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2718                 return r;
2719         }
2720         r = radeon_fence_wait(ib->fence, false);
2721         if (r) {
2722                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2723                 return r;
2724         }
2725         for (i = 0; i < rdev->usec_timeout; i++) {
2726                 tmp = RREG32(scratch);
2727                 if (tmp == 0xDEADBEEF)
2728                         break;
2729                 DRM_UDELAY(1);
2730         }
2731         if (i < rdev->usec_timeout) {
2732                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2733         } else {
2734                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2735                           scratch, tmp);
2736                 r = -EINVAL;
2737         }
2738         radeon_scratch_free(rdev, scratch);
2739         radeon_ib_free(rdev, &ib);
2740         return r;
2741 }
2742
2743 /*
2744  * Interrupts
2745  *
2746  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2747  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2748  * writing to the ring and the GPU consuming, the GPU writes to the ring
2749  * and host consumes.  As the host irq handler processes interrupts, it
2750  * increments the rptr.  When the rptr catches up with the wptr, all the
2751  * current interrupts have been processed.
2752  */
2753
2754 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2755 {
2756         u32 rb_bufsz;
2757
2758         /* Align ring size */
2759         rb_bufsz = drm_order(ring_size / 4);
2760         ring_size = (1 << rb_bufsz) * 4;
2761         rdev->ih.ring_size = ring_size;
2762         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2763         rdev->ih.rptr = 0;
2764 }
2765
2766 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2767 {
2768         int r;
2769
2770         /* Allocate ring buffer */
2771         if (rdev->ih.ring_obj == NULL) {
2772                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2773                                      true,
2774                                      RADEON_GEM_DOMAIN_GTT,
2775                                      &rdev->ih.ring_obj);
2776                 if (r) {
2777                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2778                         return r;
2779                 }
2780                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2781                 if (unlikely(r != 0))
2782                         return r;
2783                 r = radeon_bo_pin(rdev->ih.ring_obj,
2784                                   RADEON_GEM_DOMAIN_GTT,
2785                                   &rdev->ih.gpu_addr);
2786                 if (r) {
2787                         radeon_bo_unreserve(rdev->ih.ring_obj);
2788                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2789                         return r;
2790                 }
2791                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2792                                    (void **)&rdev->ih.ring);
2793                 radeon_bo_unreserve(rdev->ih.ring_obj);
2794                 if (r) {
2795                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2796                         return r;
2797                 }
2798         }
2799         return 0;
2800 }
2801
2802 static void r600_ih_ring_fini(struct radeon_device *rdev)
2803 {
2804         int r;
2805         if (rdev->ih.ring_obj) {
2806                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2807                 if (likely(r == 0)) {
2808                         radeon_bo_kunmap(rdev->ih.ring_obj);
2809                         radeon_bo_unpin(rdev->ih.ring_obj);
2810                         radeon_bo_unreserve(rdev->ih.ring_obj);
2811                 }
2812                 radeon_bo_unref(&rdev->ih.ring_obj);
2813                 rdev->ih.ring = NULL;
2814                 rdev->ih.ring_obj = NULL;
2815         }
2816 }
2817
2818 void r600_rlc_stop(struct radeon_device *rdev)
2819 {
2820
2821         if ((rdev->family >= CHIP_RV770) &&
2822             (rdev->family <= CHIP_RV740)) {
2823                 /* r7xx asics need to soft reset RLC before halting */
2824                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2825                 RREG32(SRBM_SOFT_RESET);
2826                 udelay(15000);
2827                 WREG32(SRBM_SOFT_RESET, 0);
2828                 RREG32(SRBM_SOFT_RESET);
2829         }
2830
2831         WREG32(RLC_CNTL, 0);
2832 }
2833
2834 static void r600_rlc_start(struct radeon_device *rdev)
2835 {
2836         WREG32(RLC_CNTL, RLC_ENABLE);
2837 }
2838
2839 static int r600_rlc_init(struct radeon_device *rdev)
2840 {
2841         u32 i;
2842         const __be32 *fw_data;
2843
2844         if (!rdev->rlc_fw)
2845                 return -EINVAL;
2846
2847         r600_rlc_stop(rdev);
2848
2849         WREG32(RLC_HB_BASE, 0);
2850         WREG32(RLC_HB_CNTL, 0);
2851         WREG32(RLC_HB_RPTR, 0);
2852         WREG32(RLC_HB_WPTR, 0);
2853         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2854         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2855         WREG32(RLC_MC_CNTL, 0);
2856         WREG32(RLC_UCODE_CNTL, 0);
2857
2858         fw_data = (const __be32 *)rdev->rlc_fw->data;
2859         if (rdev->family >= CHIP_CEDAR) {
2860                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2861                         WREG32(RLC_UCODE_ADDR, i);
2862                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2863                 }
2864         } else if (rdev->family >= CHIP_RV770) {
2865                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2866                         WREG32(RLC_UCODE_ADDR, i);
2867                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2868                 }
2869         } else {
2870                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2871                         WREG32(RLC_UCODE_ADDR, i);
2872                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2873                 }
2874         }
2875         WREG32(RLC_UCODE_ADDR, 0);
2876
2877         r600_rlc_start(rdev);
2878
2879         return 0;
2880 }
2881
2882 static void r600_enable_interrupts(struct radeon_device *rdev)
2883 {
2884         u32 ih_cntl = RREG32(IH_CNTL);
2885         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2886
2887         ih_cntl |= ENABLE_INTR;
2888         ih_rb_cntl |= IH_RB_ENABLE;
2889         WREG32(IH_CNTL, ih_cntl);
2890         WREG32(IH_RB_CNTL, ih_rb_cntl);
2891         rdev->ih.enabled = true;
2892 }
2893
2894 void r600_disable_interrupts(struct radeon_device *rdev)
2895 {
2896         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2897         u32 ih_cntl = RREG32(IH_CNTL);
2898
2899         ih_rb_cntl &= ~IH_RB_ENABLE;
2900         ih_cntl &= ~ENABLE_INTR;
2901         WREG32(IH_RB_CNTL, ih_rb_cntl);
2902         WREG32(IH_CNTL, ih_cntl);
2903         /* set rptr, wptr to 0 */
2904         WREG32(IH_RB_RPTR, 0);
2905         WREG32(IH_RB_WPTR, 0);
2906         rdev->ih.enabled = false;
2907         rdev->ih.wptr = 0;
2908         rdev->ih.rptr = 0;
2909 }
2910
2911 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2912 {
2913         u32 tmp;
2914
2915         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2916         WREG32(GRBM_INT_CNTL, 0);
2917         WREG32(DxMODE_INT_MASK, 0);
2918         if (ASIC_IS_DCE3(rdev)) {
2919                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2920                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2921                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2922                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2923                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2924                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2925                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2926                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2927                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2928                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2929                 if (ASIC_IS_DCE32(rdev)) {
2930                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2931                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2932                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2933                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2934                 }
2935         } else {
2936                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2937                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2938                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2939                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2940                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2941                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2942                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2943                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2944         }
2945 }
2946
2947 int r600_irq_init(struct radeon_device *rdev)
2948 {
2949         int ret = 0;
2950         int rb_bufsz;
2951         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2952
2953         /* allocate ring */
2954         ret = r600_ih_ring_alloc(rdev);
2955         if (ret)
2956                 return ret;
2957
2958         /* disable irqs */
2959         r600_disable_interrupts(rdev);
2960
2961         /* init rlc */
2962         ret = r600_rlc_init(rdev);
2963         if (ret) {
2964                 r600_ih_ring_fini(rdev);
2965                 return ret;
2966         }
2967
2968         /* setup interrupt control */
2969         /* set dummy read address to ring address */
2970         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2971         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2972         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2973          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2974          */
2975         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2976         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2977         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2978         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2979
2980         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2981         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2982
2983         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2984                       IH_WPTR_OVERFLOW_CLEAR |
2985                       (rb_bufsz << 1));
2986         /* WPTR writeback, not yet */
2987         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2988         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2989         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2990
2991         WREG32(IH_RB_CNTL, ih_rb_cntl);
2992
2993         /* set rptr, wptr to 0 */
2994         WREG32(IH_RB_RPTR, 0);
2995         WREG32(IH_RB_WPTR, 0);
2996
2997         /* Default settings for IH_CNTL (disabled at first) */
2998         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2999         /* RPTR_REARM only works if msi's are enabled */
3000         if (rdev->msi_enabled)
3001                 ih_cntl |= RPTR_REARM;
3002
3003 #ifdef __BIG_ENDIAN
3004         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
3005 #endif
3006         WREG32(IH_CNTL, ih_cntl);
3007
3008         /* force the active interrupt state to all disabled */
3009         if (rdev->family >= CHIP_CEDAR)
3010                 evergreen_disable_interrupt_state(rdev);
3011         else
3012                 r600_disable_interrupt_state(rdev);
3013
3014         /* enable irqs */
3015         r600_enable_interrupts(rdev);
3016
3017         return ret;
3018 }
3019
3020 void r600_irq_suspend(struct radeon_device *rdev)
3021 {
3022         r600_irq_disable(rdev);
3023         r600_rlc_stop(rdev);
3024 }
3025
3026 void r600_irq_fini(struct radeon_device *rdev)
3027 {
3028         r600_irq_suspend(rdev);
3029         r600_ih_ring_fini(rdev);
3030 }
3031
3032 int r600_irq_set(struct radeon_device *rdev)
3033 {
3034         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3035         u32 mode_int = 0;
3036         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3037         u32 grbm_int_cntl = 0;
3038         u32 hdmi1, hdmi2;
3039
3040         if (!rdev->irq.installed) {
3041                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3042                 return -EINVAL;
3043         }
3044         /* don't enable anything if the ih is disabled */
3045         if (!rdev->ih.enabled) {
3046                 r600_disable_interrupts(rdev);
3047                 /* force the active interrupt state to all disabled */
3048                 r600_disable_interrupt_state(rdev);
3049                 return 0;
3050         }
3051
3052         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3053         if (ASIC_IS_DCE3(rdev)) {
3054                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3055                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3056                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3057                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3058                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3059                 if (ASIC_IS_DCE32(rdev)) {
3060                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3061                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3062                 }
3063         } else {
3064                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3065                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3066                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3067                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3068         }
3069
3070         if (rdev->irq.sw_int) {
3071                 DRM_DEBUG("r600_irq_set: sw int\n");
3072                 cp_int_cntl |= RB_INT_ENABLE;
3073         }
3074         if (rdev->irq.crtc_vblank_int[0]) {
3075                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3076                 mode_int |= D1MODE_VBLANK_INT_MASK;
3077         }
3078         if (rdev->irq.crtc_vblank_int[1]) {
3079                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3080                 mode_int |= D2MODE_VBLANK_INT_MASK;
3081         }
3082         if (rdev->irq.hpd[0]) {
3083                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3084                 hpd1 |= DC_HPDx_INT_EN;
3085         }
3086         if (rdev->irq.hpd[1]) {
3087                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3088                 hpd2 |= DC_HPDx_INT_EN;
3089         }
3090         if (rdev->irq.hpd[2]) {
3091                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3092                 hpd3 |= DC_HPDx_INT_EN;
3093         }
3094         if (rdev->irq.hpd[3]) {
3095                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3096                 hpd4 |= DC_HPDx_INT_EN;
3097         }
3098         if (rdev->irq.hpd[4]) {
3099                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3100                 hpd5 |= DC_HPDx_INT_EN;
3101         }
3102         if (rdev->irq.hpd[5]) {
3103                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3104                 hpd6 |= DC_HPDx_INT_EN;
3105         }
3106         if (rdev->irq.hdmi[0]) {
3107                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3108                 hdmi1 |= R600_HDMI_INT_EN;
3109         }
3110         if (rdev->irq.hdmi[1]) {
3111                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3112                 hdmi2 |= R600_HDMI_INT_EN;
3113         }
3114         if (rdev->irq.gui_idle) {
3115                 DRM_DEBUG("gui idle\n");
3116                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3117         }
3118
3119         WREG32(CP_INT_CNTL, cp_int_cntl);
3120         WREG32(DxMODE_INT_MASK, mode_int);
3121         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3122         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3123         if (ASIC_IS_DCE3(rdev)) {
3124                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3125                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3126                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3127                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3128                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3129                 if (ASIC_IS_DCE32(rdev)) {
3130                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3131                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3132                 }
3133         } else {
3134                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3135                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3136                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3137                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3138         }
3139
3140         return 0;
3141 }
3142
3143 static inline void r600_irq_ack(struct radeon_device *rdev,
3144                                 u32 *disp_int,
3145                                 u32 *disp_int_cont,
3146                                 u32 *disp_int_cont2)
3147 {
3148         u32 tmp;
3149
3150         if (ASIC_IS_DCE3(rdev)) {
3151                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3152                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3153                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3154         } else {
3155                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3156                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3157                 *disp_int_cont2 = 0;
3158         }
3159
3160         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3161                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3162         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3163                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3164         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3165                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3166         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3167                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3168         if (*disp_int & DC_HPD1_INTERRUPT) {
3169                 if (ASIC_IS_DCE3(rdev)) {
3170                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3171                         tmp |= DC_HPDx_INT_ACK;
3172                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3173                 } else {
3174                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3175                         tmp |= DC_HPDx_INT_ACK;
3176                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3177                 }
3178         }
3179         if (*disp_int & DC_HPD2_INTERRUPT) {
3180                 if (ASIC_IS_DCE3(rdev)) {
3181                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3182                         tmp |= DC_HPDx_INT_ACK;
3183                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3184                 } else {
3185                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3186                         tmp |= DC_HPDx_INT_ACK;
3187                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3188                 }
3189         }
3190         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3191                 if (ASIC_IS_DCE3(rdev)) {
3192                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3193                         tmp |= DC_HPDx_INT_ACK;
3194                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3195                 } else {
3196                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3197                         tmp |= DC_HPDx_INT_ACK;
3198                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3199                 }
3200         }
3201         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3202                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3203                 tmp |= DC_HPDx_INT_ACK;
3204                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3205         }
3206         if (ASIC_IS_DCE32(rdev)) {
3207                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3208                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3209                         tmp |= DC_HPDx_INT_ACK;
3210                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3211                 }
3212                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3213                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3214                         tmp |= DC_HPDx_INT_ACK;
3215                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3216                 }
3217         }
3218         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3219                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3220         }
3221         if (ASIC_IS_DCE3(rdev)) {
3222                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3223                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3224                 }
3225         } else {
3226                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3227                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3228                 }
3229         }
3230 }
3231
3232 void r600_irq_disable(struct radeon_device *rdev)
3233 {
3234         u32 disp_int, disp_int_cont, disp_int_cont2;
3235
3236         r600_disable_interrupts(rdev);
3237         /* Wait and acknowledge irq */
3238         mdelay(1);
3239         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3240         r600_disable_interrupt_state(rdev);
3241 }
3242
3243 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3244 {
3245         u32 wptr, tmp;
3246
3247         /* XXX use writeback */
3248         wptr = RREG32(IH_RB_WPTR);
3249
3250         if (wptr & RB_OVERFLOW) {
3251                 /* When a ring buffer overflow happen start parsing interrupt
3252                  * from the last not overwritten vector (wptr + 16). Hopefully
3253                  * this should allow us to catchup.
3254                  */
3255                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3256                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3257                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3258                 tmp = RREG32(IH_RB_CNTL);
3259                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3260                 WREG32(IH_RB_CNTL, tmp);
3261         }
3262         return (wptr & rdev->ih.ptr_mask);
3263 }
3264
3265 /*        r600 IV Ring
3266  * Each IV ring entry is 128 bits:
3267  * [7:0]    - interrupt source id
3268  * [31:8]   - reserved
3269  * [59:32]  - interrupt source data
3270  * [127:60]  - reserved
3271  *
3272  * The basic interrupt vector entries
3273  * are decoded as follows:
3274  * src_id  src_data  description
3275  *      1         0  D1 Vblank
3276  *      1         1  D1 Vline
3277  *      5         0  D2 Vblank
3278  *      5         1  D2 Vline
3279  *     19         0  FP Hot plug detection A
3280  *     19         1  FP Hot plug detection B
3281  *     19         2  DAC A auto-detection
3282  *     19         3  DAC B auto-detection
3283  *     21         4  HDMI block A
3284  *     21         5  HDMI block B
3285  *    176         -  CP_INT RB
3286  *    177         -  CP_INT IB1
3287  *    178         -  CP_INT IB2
3288  *    181         -  EOP Interrupt
3289  *    233         -  GUI Idle
3290  *
3291  * Note, these are based on r600 and may need to be
3292  * adjusted or added to on newer asics
3293  */
3294
3295 int r600_irq_process(struct radeon_device *rdev)
3296 {
3297         u32 wptr = r600_get_ih_wptr(rdev);
3298         u32 rptr = rdev->ih.rptr;
3299         u32 src_id, src_data;
3300         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3301         unsigned long flags;
3302         bool queue_hotplug = false;
3303
3304         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3305         if (!rdev->ih.enabled)
3306                 return IRQ_NONE;
3307
3308         spin_lock_irqsave(&rdev->ih.lock, flags);
3309
3310         if (rptr == wptr) {
3311                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3312                 return IRQ_NONE;
3313         }
3314         if (rdev->shutdown) {
3315                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3316                 return IRQ_NONE;
3317         }
3318
3319 restart_ih:
3320         /* display interrupts */
3321         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3322
3323         rdev->ih.wptr = wptr;
3324         while (rptr != wptr) {
3325                 /* wptr/rptr are in bytes! */
3326                 ring_index = rptr / 4;
3327                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3328                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3329
3330                 switch (src_id) {
3331                 case 1: /* D1 vblank/vline */
3332                         switch (src_data) {
3333                         case 0: /* D1 vblank */
3334                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3335                                         drm_handle_vblank(rdev->ddev, 0);
3336                                         rdev->pm.vblank_sync = true;
3337                                         wake_up(&rdev->irq.vblank_queue);
3338                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3339                                         DRM_DEBUG("IH: D1 vblank\n");
3340                                 }
3341                                 break;
3342                         case 1: /* D1 vline */
3343                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3344                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3345                                         DRM_DEBUG("IH: D1 vline\n");
3346                                 }
3347                                 break;
3348                         default:
3349                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3350                                 break;
3351                         }
3352                         break;
3353                 case 5: /* D2 vblank/vline */
3354                         switch (src_data) {
3355                         case 0: /* D2 vblank */
3356                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3357                                         drm_handle_vblank(rdev->ddev, 1);
3358                                         rdev->pm.vblank_sync = true;
3359                                         wake_up(&rdev->irq.vblank_queue);
3360                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3361                                         DRM_DEBUG("IH: D2 vblank\n");
3362                                 }
3363                                 break;
3364                         case 1: /* D1 vline */
3365                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3366                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3367                                         DRM_DEBUG("IH: D2 vline\n");
3368                                 }
3369                                 break;
3370                         default:
3371                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3372                                 break;
3373                         }
3374                         break;
3375                 case 19: /* HPD/DAC hotplug */
3376                         switch (src_data) {
3377                         case 0:
3378                                 if (disp_int & DC_HPD1_INTERRUPT) {
3379                                         disp_int &= ~DC_HPD1_INTERRUPT;
3380                                         queue_hotplug = true;
3381                                         DRM_DEBUG("IH: HPD1\n");
3382                                 }
3383                                 break;
3384                         case 1:
3385                                 if (disp_int & DC_HPD2_INTERRUPT) {
3386                                         disp_int &= ~DC_HPD2_INTERRUPT;
3387                                         queue_hotplug = true;
3388                                         DRM_DEBUG("IH: HPD2\n");
3389                                 }
3390                                 break;
3391                         case 4:
3392                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3393                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3394                                         queue_hotplug = true;
3395                                         DRM_DEBUG("IH: HPD3\n");
3396                                 }
3397                                 break;
3398                         case 5:
3399                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3400                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3401                                         queue_hotplug = true;
3402                                         DRM_DEBUG("IH: HPD4\n");
3403                                 }
3404                                 break;
3405                         case 10:
3406                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3407                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3408                                         queue_hotplug = true;
3409                                         DRM_DEBUG("IH: HPD5\n");
3410                                 }
3411                                 break;
3412                         case 12:
3413                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3414                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3415                                         queue_hotplug = true;
3416                                         DRM_DEBUG("IH: HPD6\n");
3417                                 }
3418                                 break;
3419                         default:
3420                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3421                                 break;
3422                         }
3423                         break;
3424                 case 21: /* HDMI */
3425                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3426                         r600_audio_schedule_polling(rdev);
3427                         break;
3428                 case 176: /* CP_INT in ring buffer */
3429                 case 177: /* CP_INT in IB1 */
3430                 case 178: /* CP_INT in IB2 */
3431                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3432                         radeon_fence_process(rdev);
3433                         break;
3434                 case 181: /* CP EOP event */
3435                         DRM_DEBUG("IH: CP EOP\n");
3436                         break;
3437                 case 233: /* GUI IDLE */
3438                         DRM_DEBUG("IH: CP EOP\n");
3439                         rdev->pm.gui_idle = true;
3440                         wake_up(&rdev->irq.idle_queue);
3441                         break;
3442                 default:
3443                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3444                         break;
3445                 }
3446
3447                 /* wptr/rptr are in bytes! */
3448                 rptr += 16;
3449                 rptr &= rdev->ih.ptr_mask;
3450         }
3451         /* make sure wptr hasn't changed while processing */
3452         wptr = r600_get_ih_wptr(rdev);
3453         if (wptr != rdev->ih.wptr)
3454                 goto restart_ih;
3455         if (queue_hotplug)
3456                 queue_work(rdev->wq, &rdev->hotplug_work);
3457         rdev->ih.rptr = rptr;
3458         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3459         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3460         return IRQ_HANDLED;
3461 }
3462
3463 /*
3464  * Debugfs info
3465  */
3466 #if defined(CONFIG_DEBUG_FS)
3467
3468 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3469 {
3470         struct drm_info_node *node = (struct drm_info_node *) m->private;
3471         struct drm_device *dev = node->minor->dev;
3472         struct radeon_device *rdev = dev->dev_private;
3473         unsigned count, i, j;
3474
3475         radeon_ring_free_size(rdev);
3476         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3477         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3478         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3479         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3480         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3481         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3482         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3483         seq_printf(m, "%u dwords in ring\n", count);
3484         i = rdev->cp.rptr;
3485         for (j = 0; j <= count; j++) {
3486                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3487                 i = (i + 1) & rdev->cp.ptr_mask;
3488         }
3489         return 0;
3490 }
3491
3492 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3493 {
3494         struct drm_info_node *node = (struct drm_info_node *) m->private;
3495         struct drm_device *dev = node->minor->dev;
3496         struct radeon_device *rdev = dev->dev_private;
3497
3498         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3499         DREG32_SYS(m, rdev, VM_L2_STATUS);
3500         return 0;
3501 }
3502
3503 static struct drm_info_list r600_mc_info_list[] = {
3504         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3505         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3506 };
3507 #endif
3508
3509 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3510 {
3511 #if defined(CONFIG_DEBUG_FS)
3512         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3513 #else
3514         return 0;
3515 #endif
3516 }
3517
3518 /**
3519  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3520  * rdev: radeon device structure
3521  * bo: buffer object struct which userspace is waiting for idle
3522  *
3523  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3524  * through ring buffer, this leads to corruption in rendering, see
3525  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3526  * directly perform HDP flush by writing register through MMIO.
3527  */
3528 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3529 {
3530         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3531          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3532          */
3533         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3534             rdev->vram_scratch.ptr) {
3535                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3536                 u32 tmp;
3537
3538                 WREG32(HDP_DEBUG1, 0);
3539                 tmp = readl((void __iomem *)ptr);
3540         } else
3541                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3542 }