drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50 #define CAYMAN_RLC_UCODE_SIZE 1024
  51
  52 /* Firmware Names */
  53 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  54 MODULE_FIRMWARE("radeon/R600_me.bin");
  55 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV610_me.bin");
  57 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV630_me.bin");
  59 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV620_me.bin");
  61 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV635_me.bin");
  63 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV670_me.bin");
  65 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RS780_me.bin");
  67 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RV770_me.bin");
  69 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV730_me.bin");
  71 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV710_me.bin");
  73 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  74 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  87 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  88 MODULE_FIRMWARE("radeon/PALM_me.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  90
  91 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  92
  93 /* r600,rv610,rv630,rv620,rv635,rv670 */
  94 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  95 void r600_gpu_init(struct radeon_device *rdev);
  96 void r600_fini(struct radeon_device *rdev);
  97 void r600_irq_disable(struct radeon_device *rdev);
  98 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  99
 100 /* get temperature in millidegrees */
 101 int rv6xx_get_temp(struct radeon_device *rdev)
 102 {
 103         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 104                 ASIC_T_SHIFT;
 105         int actual_temp = temp & 0xff;
 106
 107         if (temp & 0x100)
 108                 actual_temp -= 256;
 109
 110         return actual_temp * 1000;
 111 }
 112
 113 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 114 {
 115         int i;
 116
 117         rdev->pm.dynpm_can_upclock = true;
 118         rdev->pm.dynpm_can_downclock = true;
 119
 120         /* power state array is low to high, default is first */
 121         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 122                 int min_power_state_index = 0;
 123
 124                 if (rdev->pm.num_power_states > 2)
 125                         min_power_state_index = 1;
 126
 127                 switch (rdev->pm.dynpm_planned_action) {
 128                 case DYNPM_ACTION_MINIMUM:
 129                         rdev->pm.requested_power_state_index = min_power_state_index;
 130                         rdev->pm.requested_clock_mode_index = 0;
 131                         rdev->pm.dynpm_can_downclock = false;
 132                         break;
 133                 case DYNPM_ACTION_DOWNCLOCK:
 134                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 135                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 136                                 rdev->pm.dynpm_can_downclock = false;
 137                         } else {
 138                                 if (rdev->pm.active_crtc_count > 1) {
 139                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 140                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 141                                                         continue;
 142                                                 else if (i >= rdev->pm.current_power_state_index) {
 143                                                         rdev->pm.requested_power_state_index =
 144                                                                 rdev->pm.current_power_state_index;
 145                                                         break;
 146                                                 } else {
 147                                                         rdev->pm.requested_power_state_index = i;
 148                                                         break;
 149                                                 }
 150                                         }
 151                                 } else {
 152                                         if (rdev->pm.current_power_state_index == 0)
 153                                                 rdev->pm.requested_power_state_index =
 154                                                         rdev->pm.num_power_states - 1;
 155                                         else
 156                                                 rdev->pm.requested_power_state_index =
 157                                                         rdev->pm.current_power_state_index - 1;
 158                                 }
 159                         }
 160                         rdev->pm.requested_clock_mode_index = 0;
 161                         /* don't use the power state if crtcs are active and no display flag is set */
 162                         if ((rdev->pm.active_crtc_count > 0) &&
 163                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 164                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 165                              RADEON_PM_MODE_NO_DISPLAY)) {
 166                                 rdev->pm.requested_power_state_index++;
 167                         }
 168                         break;
 169                 case DYNPM_ACTION_UPCLOCK:
 170                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 171                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 172                                 rdev->pm.dynpm_can_upclock = false;
 173                         } else {
 174                                 if (rdev->pm.active_crtc_count > 1) {
 175                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 176                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 177                                                         continue;
 178                                                 else if (i <= rdev->pm.current_power_state_index) {
 179                                                         rdev->pm.requested_power_state_index =
 180                                                                 rdev->pm.current_power_state_index;
 181                                                         break;
 182                                                 } else {
 183                                                         rdev->pm.requested_power_state_index = i;
 184                                                         break;
 185                                                 }
 186                                         }
 187                                 } else
 188                                         rdev->pm.requested_power_state_index =
 189                                                 rdev->pm.current_power_state_index + 1;
 190                         }
 191                         rdev->pm.requested_clock_mode_index = 0;
 192                         break;
 193                 case DYNPM_ACTION_DEFAULT:
 194                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 195                         rdev->pm.requested_clock_mode_index = 0;
 196                         rdev->pm.dynpm_can_upclock = false;
 197                         break;
 198                 case DYNPM_ACTION_NONE:
 199                 default:
 200                         DRM_ERROR("Requested mode for not defined action\n");
 201                         return;
 202                 }
 203         } else {
 204                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 205                 /* for now just select the first power state and switch between clock modes */
 206                 /* power state array is low to high, default is first (0) */
 207                 if (rdev->pm.active_crtc_count > 1) {
 208                         rdev->pm.requested_power_state_index = -1;
 209                         /* start at 1 as we don't want the default mode */
 210                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 211                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 212                                         continue;
 213                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 214                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 215                                         rdev->pm.requested_power_state_index = i;
 216                                         break;
 217                                 }
 218                         }
 219                         /* if nothing selected, grab the default state. */
 220                         if (rdev->pm.requested_power_state_index == -1)
 221                                 rdev->pm.requested_power_state_index = 0;
 222                 } else
 223                         rdev->pm.requested_power_state_index = 1;
 224
 225                 switch (rdev->pm.dynpm_planned_action) {
 226                 case DYNPM_ACTION_MINIMUM:
 227                         rdev->pm.requested_clock_mode_index = 0;
 228                         rdev->pm.dynpm_can_downclock = false;
 229                         break;
 230                 case DYNPM_ACTION_DOWNCLOCK:
 231                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 232                                 if (rdev->pm.current_clock_mode_index == 0) {
 233                                         rdev->pm.requested_clock_mode_index = 0;
 234                                         rdev->pm.dynpm_can_downclock = false;
 235                                 } else
 236                                         rdev->pm.requested_clock_mode_index =
 237                                                 rdev->pm.current_clock_mode_index - 1;
 238                         } else {
 239                                 rdev->pm.requested_clock_mode_index = 0;
 240                                 rdev->pm.dynpm_can_downclock = false;
 241                         }
 242                         /* don't use the power state if crtcs are active and no display flag is set */
 243                         if ((rdev->pm.active_crtc_count > 0) &&
 244                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 245                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 246                              RADEON_PM_MODE_NO_DISPLAY)) {
 247                                 rdev->pm.requested_clock_mode_index++;
 248                         }
 249                         break;
 250                 case DYNPM_ACTION_UPCLOCK:
 251                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 252                                 if (rdev->pm.current_clock_mode_index ==
 253                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 254                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 255                                         rdev->pm.dynpm_can_upclock = false;
 256                                 } else
 257                                         rdev->pm.requested_clock_mode_index =
 258                                                 rdev->pm.current_clock_mode_index + 1;
 259                         } else {
 260                                 rdev->pm.requested_clock_mode_index =
 261                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 262                                 rdev->pm.dynpm_can_upclock = false;
 263                         }
 264                         break;
 265                 case DYNPM_ACTION_DEFAULT:
 266                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 267                         rdev->pm.requested_clock_mode_index = 0;
 268                         rdev->pm.dynpm_can_upclock = false;
 269                         break;
 270                 case DYNPM_ACTION_NONE:
 271                 default:
 272                         DRM_ERROR("Requested mode for not defined action\n");
 273                         return;
 274                 }
 275         }
 276
 277         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 278                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 279                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 280                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 281                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 282                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 283                   pcie_lanes);
 284 }
 285
 286 static int r600_pm_get_type_index(struct radeon_device *rdev,
 287                                   enum radeon_pm_state_type ps_type,
 288                                   int instance)
 289 {
 290         int i;
 291         int found_instance = -1;
 292
 293         for (i = 0; i < rdev->pm.num_power_states; i++) {
 294                 if (rdev->pm.power_state[i].type == ps_type) {
 295                         found_instance++;
 296                         if (found_instance == instance)
 297                                 return i;
 298                 }
 299         }
 300         /* return default if no match */
 301         return rdev->pm.default_power_state_index;
 302 }
 303
 304 void rs780_pm_init_profile(struct radeon_device *rdev)
 305 {
 306         if (rdev->pm.num_power_states == 2) {
 307                 /* default */
 308                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 309                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 310                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 312                 /* low sh */
 313                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 317                 /* mid sh */
 318                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 322                 /* high sh */
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 325                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 327                 /* low mh */
 328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 331                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 332                 /* mid mh */
 333                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 336                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 337                 /* high mh */
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 340                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 341                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 342         } else if (rdev->pm.num_power_states == 3) {
 343                 /* default */
 344                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 345                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 346                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 347                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 348                 /* low sh */
 349                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 350                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 351                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 352                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 353                 /* mid sh */
 354                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 355                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 356                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 357                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 358                 /* high sh */
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 361                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 363                 /* low mh */
 364                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 365                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 366                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 367                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 368                 /* mid mh */
 369                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 370                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 371                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 372                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 373                 /* high mh */
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 375                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 376                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 377                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 378         } else {
 379                 /* default */
 380                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 381                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 382                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 383                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 384                 /* low sh */
 385                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 386                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 387                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 388                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 389                 /* mid sh */
 390                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 391                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 392                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 393                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 394                 /* high sh */
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 396                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 397                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 399                 /* low mh */
 400                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 401                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 403                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 404                 /* mid mh */
 405                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 406                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 408                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 409                 /* high mh */
 410                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 411                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 412                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 413                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 414         }
 415 }
 416
 417 void r600_pm_init_profile(struct radeon_device *rdev)
 418 {
 419         if (rdev->family == CHIP_R600) {
 420                 /* XXX */
 421                 /* default */
 422                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 426                 /* low sh */
 427                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 431                 /* mid sh */
 432                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 436                 /* high sh */
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 441                 /* low mh */
 442                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 445                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 446                 /* mid mh */
 447                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 448                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 449                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 450                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 451                 /* high mh */
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 453                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 454                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 455                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 456         } else {
 457                 if (rdev->pm.num_power_states < 4) {
 458                         /* default */
 459                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 460                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 461                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 462                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 463                         /* low sh */
 464                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 467                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 468                         /* mid sh */
 469                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 470                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 471                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 472                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 473                         /* high sh */
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 475                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 476                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 477                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 478                         /* low mh */
 479                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 482                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 483                         /* low mh */
 484                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 485                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 486                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 487                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 488                         /* high mh */
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 490                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 491                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 492                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 493                 } else {
 494                         /* default */
 495                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 496                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 497                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 498                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 499                         /* low sh */
 500                         if (rdev->flags & RADEON_IS_MOBILITY) {
 501                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 502                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 503                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 504                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 506                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 507                         } else {
 508                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 509                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 510                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 511                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 512                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 513                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 514                         }
 515                         /* mid sh */
 516                         if (rdev->flags & RADEON_IS_MOBILITY) {
 517                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 518                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 519                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 520                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 522                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 523                         } else {
 524                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 525                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 526                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 527                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 528                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 529                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 530                         }
 531                         /* high sh */
 532                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 533                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 534                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 535                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 536                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 537                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 538                         /* low mh */
 539                         if (rdev->flags & RADEON_IS_MOBILITY) {
 540                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 541                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 542                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 543                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 545                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 546                         } else {
 547                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 548                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 549                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 550                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 551                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 552                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 553                         }
 554                         /* mid mh */
 555                         if (rdev->flags & RADEON_IS_MOBILITY) {
 556                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 557                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 558                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 559                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 561                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 562                         } else {
 563                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 564                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 565                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 566                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 567                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 568                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 569                         }
 570                         /* high mh */
 571                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 572                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 573                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 574                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 575                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 576                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 577                 }
 578         }
 579 }
 580
 581 void r600_pm_misc(struct radeon_device *rdev)
 582 {
 583         int req_ps_idx = rdev->pm.requested_power_state_index;
 584         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 585         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 586         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 587
 588         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 589                 if (voltage->voltage != rdev->pm.current_vddc) {
 590                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 591                         rdev->pm.current_vddc = voltage->voltage;
 592                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 593                 }
 594         }
 595 }
 596
 597 bool r600_gui_idle(struct radeon_device *rdev)
 598 {
 599         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 600                 return false;
 601         else
 602                 return true;
 603 }
 604
 605 /* hpd for digital panel detect/disconnect */
 606 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 607 {
 608         bool connected = false;
 609
 610         if (ASIC_IS_DCE3(rdev)) {
 611                 switch (hpd) {
 612                 case RADEON_HPD_1:
 613                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 614                                 connected = true;
 615                         break;
 616                 case RADEON_HPD_2:
 617                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 618                                 connected = true;
 619                         break;
 620                 case RADEON_HPD_3:
 621                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 622                                 connected = true;
 623                         break;
 624                 case RADEON_HPD_4:
 625                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 626                                 connected = true;
 627                         break;
 628                         /* DCE 3.2 */
 629                 case RADEON_HPD_5:
 630                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 631                                 connected = true;
 632                         break;
 633                 case RADEON_HPD_6:
 634                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 635                                 connected = true;
 636                         break;
 637                 default:
 638                         break;
 639                 }
 640         } else {
 641                 switch (hpd) {
 642                 case RADEON_HPD_1:
 643                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 644                                 connected = true;
 645                         break;
 646                 case RADEON_HPD_2:
 647                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 648                                 connected = true;
 649                         break;
 650                 case RADEON_HPD_3:
 651                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 652                                 connected = true;
 653                         break;
 654                 default:
 655                         break;
 656                 }
 657         }
 658         return connected;
 659 }
 660
 661 void r600_hpd_set_polarity(struct radeon_device *rdev,
 662                            enum radeon_hpd_id hpd)
 663 {
 664         u32 tmp;
 665         bool connected = r600_hpd_sense(rdev, hpd);
 666
 667         if (ASIC_IS_DCE3(rdev)) {
 668                 switch (hpd) {
 669                 case RADEON_HPD_1:
 670                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 671                         if (connected)
 672                                 tmp &= ~DC_HPDx_INT_POLARITY;
 673                         else
 674                                 tmp |= DC_HPDx_INT_POLARITY;
 675                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 676                         break;
 677                 case RADEON_HPD_2:
 678                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 679                         if (connected)
 680                                 tmp &= ~DC_HPDx_INT_POLARITY;
 681                         else
 682                                 tmp |= DC_HPDx_INT_POLARITY;
 683                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 684                         break;
 685                 case RADEON_HPD_3:
 686                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 687                         if (connected)
 688                                 tmp &= ~DC_HPDx_INT_POLARITY;
 689                         else
 690                                 tmp |= DC_HPDx_INT_POLARITY;
 691                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 692                         break;
 693                 case RADEON_HPD_4:
 694                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 695                         if (connected)
 696                                 tmp &= ~DC_HPDx_INT_POLARITY;
 697                         else
 698                                 tmp |= DC_HPDx_INT_POLARITY;
 699                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 700                         break;
 701                 case RADEON_HPD_5:
 702                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 703                         if (connected)
 704                                 tmp &= ~DC_HPDx_INT_POLARITY;
 705                         else
 706                                 tmp |= DC_HPDx_INT_POLARITY;
 707                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 708                         break;
 709                         /* DCE 3.2 */
 710                 case RADEON_HPD_6:
 711                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 712                         if (connected)
 713                                 tmp &= ~DC_HPDx_INT_POLARITY;
 714                         else
 715                                 tmp |= DC_HPDx_INT_POLARITY;
 716                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 717                         break;
 718                 default:
 719                         break;
 720                 }
 721         } else {
 722                 switch (hpd) {
 723                 case RADEON_HPD_1:
 724                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 725                         if (connected)
 726                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 727                         else
 728                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 729                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 730                         break;
 731                 case RADEON_HPD_2:
 732                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 733                         if (connected)
 734                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 735                         else
 736                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 737                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 738                         break;
 739                 case RADEON_HPD_3:
 740                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 741                         if (connected)
 742                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 743                         else
 744                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 745                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 746                         break;
 747                 default:
 748                         break;
 749                 }
 750         }
 751 }
 752
 753 void r600_hpd_init(struct radeon_device *rdev)
 754 {
 755         struct drm_device *dev = rdev->ddev;
 756         struct drm_connector *connector;
 757
 758         if (ASIC_IS_DCE3(rdev)) {
 759                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 760                 if (ASIC_IS_DCE32(rdev))
 761                         tmp |= DC_HPDx_EN;
 762
 763                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 764                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 765                         switch (radeon_connector->hpd.hpd) {
 766                         case RADEON_HPD_1:
 767                                 WREG32(DC_HPD1_CONTROL, tmp);
 768                                 rdev->irq.hpd[0] = true;
 769                                 break;
 770                         case RADEON_HPD_2:
 771                                 WREG32(DC_HPD2_CONTROL, tmp);
 772                                 rdev->irq.hpd[1] = true;
 773                                 break;
 774                         case RADEON_HPD_3:
 775                                 WREG32(DC_HPD3_CONTROL, tmp);
 776                                 rdev->irq.hpd[2] = true;
 777                                 break;
 778                         case RADEON_HPD_4:
 779                                 WREG32(DC_HPD4_CONTROL, tmp);
 780                                 rdev->irq.hpd[3] = true;
 781                                 break;
 782                                 /* DCE 3.2 */
 783                         case RADEON_HPD_5:
 784                                 WREG32(DC_HPD5_CONTROL, tmp);
 785                                 rdev->irq.hpd[4] = true;
 786                                 break;
 787                         case RADEON_HPD_6:
 788                                 WREG32(DC_HPD6_CONTROL, tmp);
 789                                 rdev->irq.hpd[5] = true;
 790                                 break;
 791                         default:
 792                                 break;
 793                         }
 794                 }
 795         } else {
 796                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 797                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 798                         switch (radeon_connector->hpd.hpd) {
 799                         case RADEON_HPD_1:
 800                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 801                                 rdev->irq.hpd[0] = true;
 802                                 break;
 803                         case RADEON_HPD_2:
 804                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 805                                 rdev->irq.hpd[1] = true;
 806                                 break;
 807                         case RADEON_HPD_3:
 808                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 809                                 rdev->irq.hpd[2] = true;
 810                                 break;
 811                         default:
 812                                 break;
 813                         }
 814                 }
 815         }
 816         if (rdev->irq.installed)
 817                 r600_irq_set(rdev);
 818 }
 819
 820 void r600_hpd_fini(struct radeon_device *rdev)
 821 {
 822         struct drm_device *dev = rdev->ddev;
 823         struct drm_connector *connector;
 824
 825         if (ASIC_IS_DCE3(rdev)) {
 826                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 827                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 828                         switch (radeon_connector->hpd.hpd) {
 829                         case RADEON_HPD_1:
 830                                 WREG32(DC_HPD1_CONTROL, 0);
 831                                 rdev->irq.hpd[0] = false;
 832                                 break;
 833                         case RADEON_HPD_2:
 834                                 WREG32(DC_HPD2_CONTROL, 0);
 835                                 rdev->irq.hpd[1] = false;
 836                                 break;
 837                         case RADEON_HPD_3:
 838                                 WREG32(DC_HPD3_CONTROL, 0);
 839                                 rdev->irq.hpd[2] = false;
 840                                 break;
 841                         case RADEON_HPD_4:
 842                                 WREG32(DC_HPD4_CONTROL, 0);
 843                                 rdev->irq.hpd[3] = false;
 844                                 break;
 845                                 /* DCE 3.2 */
 846                         case RADEON_HPD_5:
 847                                 WREG32(DC_HPD5_CONTROL, 0);
 848                                 rdev->irq.hpd[4] = false;
 849                                 break;
 850                         case RADEON_HPD_6:
 851                                 WREG32(DC_HPD6_CONTROL, 0);
 852                                 rdev->irq.hpd[5] = false;
 853                                 break;
 854                         default:
 855                                 break;
 856                         }
 857                 }
 858         } else {
 859                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 860                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 861                         switch (radeon_connector->hpd.hpd) {
 862                         case RADEON_HPD_1:
 863                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 864                                 rdev->irq.hpd[0] = false;
 865                                 break;
 866                         case RADEON_HPD_2:
 867                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 868                                 rdev->irq.hpd[1] = false;
 869                                 break;
 870                         case RADEON_HPD_3:
 871                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 872                                 rdev->irq.hpd[2] = false;
 873                                 break;
 874                         default:
 875                                 break;
 876                         }
 877                 }
 878         }
 879 }
 880
 881 /*
 882  * R600 PCIE GART
 883  */
 884 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 885 {
 886         unsigned i;
 887         u32 tmp;
 888
 889         /* flush hdp cache so updates hit vram */
 890         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 891             !(rdev->flags & RADEON_IS_AGP)) {
 892                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 893                 u32 tmp;
 894
 895                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 896                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 897                  * This seems to cause problems on some AGP cards. Just use the old
 898                  * method for them.
 899                  */
 900                 WREG32(HDP_DEBUG1, 0);
 901                 tmp = readl((void __iomem *)ptr);
 902         } else
 903                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 904
 905         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 906         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 907         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 908         for (i = 0; i < rdev->usec_timeout; i++) {
 909                 /* read MC_STATUS */
 910                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 911                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 912                 if (tmp == 2) {
 913                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 914                         return;
 915                 }
 916                 if (tmp) {
 917                         return;
 918                 }
 919                 udelay(1);
 920         }
 921 }
 922
 923 int r600_pcie_gart_init(struct radeon_device *rdev)
 924 {
 925         int r;
 926
 927         if (rdev->gart.table.vram.robj) {
 928                 WARN(1, "R600 PCIE GART already initialized\n");
 929                 return 0;
 930         }
 931         /* Initialize common gart structure */
 932         r = radeon_gart_init(rdev);
 933         if (r)
 934                 return r;
 935         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 936         return radeon_gart_table_vram_alloc(rdev);
 937 }
 938
 939 int r600_pcie_gart_enable(struct radeon_device *rdev)
 940 {
 941         u32 tmp;
 942         int r, i;
 943
 944         if (rdev->gart.table.vram.robj == NULL) {
 945                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 946                 return -EINVAL;
 947         }
 948         r = radeon_gart_table_vram_pin(rdev);
 949         if (r)
 950                 return r;
 951         radeon_gart_restore(rdev);
 952
 953         /* Setup L2 cache */
 954         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 955                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 956                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 957         WREG32(VM_L2_CNTL2, 0);
 958         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 959         /* Setup TLB control */
 960         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 961                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 962                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 963                 ENABLE_WAIT_L2_QUERY;
 964         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 967         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 971         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 972         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 973         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 974         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 976         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 977         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 978         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 979         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 980         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 981         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 982                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 983         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 984                         (u32)(rdev->dummy_page.addr >> 12));
 985         for (i = 1; i < 7; i++)
 986                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 987
 988         r600_pcie_gart_tlb_flush(rdev);
 989         rdev->gart.ready = true;
 990         return 0;
 991 }
 992
 993 void r600_pcie_gart_disable(struct radeon_device *rdev)
 994 {
 995         u32 tmp;
 996         int i, r;
 997
 998         /* Disable all tables */
 999         for (i = 0; i < 7; i++)
1000                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1001
1002         /* Disable L2 cache */
1003         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1004                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1005         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1006         /* Setup L1 TLB control */
1007         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1008                 ENABLE_WAIT_L2_QUERY;
1009         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1017         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1018         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1019         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1022         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1023         if (rdev->gart.table.vram.robj) {
1024                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1025                 if (likely(r == 0)) {
1026                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1027                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1028                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1029                 }
1030         }
1031 }
1032
1033 void r600_pcie_gart_fini(struct radeon_device *rdev)
1034 {
1035         radeon_gart_fini(rdev);
1036         r600_pcie_gart_disable(rdev);
1037         radeon_gart_table_vram_free(rdev);
1038 }
1039
1040 void r600_agp_enable(struct radeon_device *rdev)
1041 {
1042         u32 tmp;
1043         int i;
1044
1045         /* Setup L2 cache */
1046         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1047                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1048                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1049         WREG32(VM_L2_CNTL2, 0);
1050         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1051         /* Setup TLB control */
1052         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1053                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1054                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1055                 ENABLE_WAIT_L2_QUERY;
1056         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1059         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1063         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1064         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1065         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1066         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1067         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1068         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1069         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1070         for (i = 0; i < 7; i++)
1071                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1072 }
1073
1074 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1075 {
1076         unsigned i;
1077         u32 tmp;
1078
1079         for (i = 0; i < rdev->usec_timeout; i++) {
1080                 /* read MC_STATUS */
1081                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1082                 if (!tmp)
1083                         return 0;
1084                 udelay(1);
1085         }
1086         return -1;
1087 }
1088
1089 static void r600_mc_program(struct radeon_device *rdev)
1090 {
1091         struct rv515_mc_save save;
1092         u32 tmp;
1093         int i, j;
1094
1095         /* Initialize HDP */
1096         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1097                 WREG32((0x2c14 + j), 0x00000000);
1098                 WREG32((0x2c18 + j), 0x00000000);
1099                 WREG32((0x2c1c + j), 0x00000000);
1100                 WREG32((0x2c20 + j), 0x00000000);
1101                 WREG32((0x2c24 + j), 0x00000000);
1102         }
1103         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1104
1105         rv515_mc_stop(rdev, &save);
1106         if (r600_mc_wait_for_idle(rdev)) {
1107                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1108         }
1109         /* Lockout access through VGA aperture (doesn't exist before R600) */
1110         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1111         /* Update configuration */
1112         if (rdev->flags & RADEON_IS_AGP) {
1113                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1114                         /* VRAM before AGP */
1115                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116                                 rdev->mc.vram_start >> 12);
1117                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118                                 rdev->mc.gtt_end >> 12);
1119                 } else {
1120                         /* VRAM after AGP */
1121                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1122                                 rdev->mc.gtt_start >> 12);
1123                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1124                                 rdev->mc.vram_end >> 12);
1125                 }
1126         } else {
1127                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1128                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1129         }
1130         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1131         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1132         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1133         WREG32(MC_VM_FB_LOCATION, tmp);
1134         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1135         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1136         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1137         if (rdev->flags & RADEON_IS_AGP) {
1138                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1139                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1140                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1141         } else {
1142                 WREG32(MC_VM_AGP_BASE, 0);
1143                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1144                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1145         }
1146         if (r600_mc_wait_for_idle(rdev)) {
1147                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1148         }
1149         rv515_mc_resume(rdev, &save);
1150         /* we need to own VRAM, so turn off the VGA renderer here
1151          * to stop it overwriting our objects */
1152         rv515_vga_render_disable(rdev);
1153 }
1154
1155 /**
1156  * r600_vram_gtt_location - try to find VRAM & GTT location
1157  * @rdev: radeon device structure holding all necessary informations
1158  * @mc: memory controller structure holding memory informations
1159  *
1160  * Function will place try to place VRAM at same place as in CPU (PCI)
1161  * address space as some GPU seems to have issue when we reprogram at
1162  * different address space.
1163  *
1164  * If there is not enough space to fit the unvisible VRAM after the
1165  * aperture then we limit the VRAM size to the aperture.
1166  *
1167  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1168  * them to be in one from GPU point of view so that we can program GPU to
1169  * catch access outside them (weird GPU policy see ??).
1170  *
1171  * This function will never fails, worst case are limiting VRAM or GTT.
1172  *
1173  * Note: GTT start, end, size should be initialized before calling this
1174  * function on AGP platform.
1175  */
1176 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1177 {
1178         u64 size_bf, size_af;
1179
1180         if (mc->mc_vram_size > 0xE0000000) {
1181                 /* leave room for at least 512M GTT */
1182                 dev_warn(rdev->dev, "limiting VRAM\n");
1183                 mc->real_vram_size = 0xE0000000;
1184                 mc->mc_vram_size = 0xE0000000;
1185         }
1186         if (rdev->flags & RADEON_IS_AGP) {
1187                 size_bf = mc->gtt_start;
1188                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1189                 if (size_bf > size_af) {
1190                         if (mc->mc_vram_size > size_bf) {
1191                                 dev_warn(rdev->dev, "limiting VRAM\n");
1192                                 mc->real_vram_size = size_bf;
1193                                 mc->mc_vram_size = size_bf;
1194                         }
1195                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1196                 } else {
1197                         if (mc->mc_vram_size > size_af) {
1198                                 dev_warn(rdev->dev, "limiting VRAM\n");
1199                                 mc->real_vram_size = size_af;
1200                                 mc->mc_vram_size = size_af;
1201                         }
1202                         mc->vram_start = mc->gtt_end;
1203                 }
1204                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1205                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1206                                 mc->mc_vram_size >> 20, mc->vram_start,
1207                                 mc->vram_end, mc->real_vram_size >> 20);
1208         } else {
1209                 u64 base = 0;
1210                 if (rdev->flags & RADEON_IS_IGP) {
1211                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1212                         base <<= 24;
1213                 }
1214                 radeon_vram_location(rdev, &rdev->mc, base);
1215                 rdev->mc.gtt_base_align = 0;
1216                 radeon_gtt_location(rdev, mc);
1217         }
1218 }
1219
1220 int r600_mc_init(struct radeon_device *rdev)
1221 {
1222         u32 tmp;
1223         int chansize, numchan;
1224
1225         /* Get VRAM informations */
1226         rdev->mc.vram_is_ddr = true;
1227         tmp = RREG32(RAMCFG);
1228         if (tmp & CHANSIZE_OVERRIDE) {
1229                 chansize = 16;
1230         } else if (tmp & CHANSIZE_MASK) {
1231                 chansize = 64;
1232         } else {
1233                 chansize = 32;
1234         }
1235         tmp = RREG32(CHMAP);
1236         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1237         case 0:
1238         default:
1239                 numchan = 1;
1240                 break;
1241         case 1:
1242                 numchan = 2;
1243                 break;
1244         case 2:
1245                 numchan = 4;
1246                 break;
1247         case 3:
1248                 numchan = 8;
1249                 break;
1250         }
1251         rdev->mc.vram_width = numchan * chansize;
1252         /* Could aper size report 0 ? */
1253         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1254         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1255         /* Setup GPU memory space */
1256         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1257         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1258         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1259         r600_vram_gtt_location(rdev, &rdev->mc);
1260
1261         if (rdev->flags & RADEON_IS_IGP) {
1262                 rs690_pm_info(rdev);
1263                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1264         }
1265         radeon_update_bandwidth_info(rdev);
1266         return 0;
1267 }
1268
1269 /* We doesn't check that the GPU really needs a reset we simply do the
1270  * reset, it's up to the caller to determine if the GPU needs one. We
1271  * might add an helper function to check that.
1272  */
1273 int r600_gpu_soft_reset(struct radeon_device *rdev)
1274 {
1275         struct rv515_mc_save save;
1276         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1277                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1278                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1279                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1280                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1281                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1282                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1283                                 S_008010_GUI_ACTIVE(1);
1284         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1285                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1286                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1287                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1288                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1289                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1290                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1291                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1292         u32 tmp;
1293
1294         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1295                 return 0;
1296
1297         dev_info(rdev->dev, "GPU softreset \n");
1298         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1299                 RREG32(R_008010_GRBM_STATUS));
1300         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1301                 RREG32(R_008014_GRBM_STATUS2));
1302         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1303                 RREG32(R_000E50_SRBM_STATUS));
1304         rv515_mc_stop(rdev, &save);
1305         if (r600_mc_wait_for_idle(rdev)) {
1306                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1307         }
1308         /* Disable CP parsing/prefetching */
1309         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1310         /* Check if any of the rendering block is busy and reset it */
1311         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1312             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1313                 tmp = S_008020_SOFT_RESET_CR(1) |
1314                         S_008020_SOFT_RESET_DB(1) |
1315                         S_008020_SOFT_RESET_CB(1) |
1316                         S_008020_SOFT_RESET_PA(1) |
1317                         S_008020_SOFT_RESET_SC(1) |
1318                         S_008020_SOFT_RESET_SMX(1) |
1319                         S_008020_SOFT_RESET_SPI(1) |
1320                         S_008020_SOFT_RESET_SX(1) |
1321                         S_008020_SOFT_RESET_SH(1) |
1322                         S_008020_SOFT_RESET_TC(1) |
1323                         S_008020_SOFT_RESET_TA(1) |
1324                         S_008020_SOFT_RESET_VC(1) |
1325                         S_008020_SOFT_RESET_VGT(1);
1326                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1327                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1328                 RREG32(R_008020_GRBM_SOFT_RESET);
1329                 mdelay(15);
1330                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1331         }
1332         /* Reset CP (we always reset CP) */
1333         tmp = S_008020_SOFT_RESET_CP(1);
1334         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1335         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1336         RREG32(R_008020_GRBM_SOFT_RESET);
1337         mdelay(15);
1338         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1339         /* Wait a little for things to settle down */
1340         mdelay(1);
1341         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1342                 RREG32(R_008010_GRBM_STATUS));
1343         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1344                 RREG32(R_008014_GRBM_STATUS2));
1345         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1346                 RREG32(R_000E50_SRBM_STATUS));
1347         rv515_mc_resume(rdev, &save);
1348         return 0;
1349 }
1350
1351 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1352 {
1353         u32 srbm_status;
1354         u32 grbm_status;
1355         u32 grbm_status2;
1356         struct r100_gpu_lockup *lockup;
1357         int r;
1358
1359         if (rdev->family >= CHIP_RV770)
1360                 lockup = &rdev->config.rv770.lockup;
1361         else
1362                 lockup = &rdev->config.r600.lockup;
1363
1364         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1365         grbm_status = RREG32(R_008010_GRBM_STATUS);
1366         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1367         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1368                 r100_gpu_lockup_update(lockup, &rdev->cp);
1369                 return false;
1370         }
1371         /* force CP activities */
1372         r = radeon_ring_lock(rdev, 2);
1373         if (!r) {
1374                 /* PACKET2 NOP */
1375                 radeon_ring_write(rdev, 0x80000000);
1376                 radeon_ring_write(rdev, 0x80000000);
1377                 radeon_ring_unlock_commit(rdev);
1378         }
1379         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1380         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1381 }
1382
1383 int r600_asic_reset(struct radeon_device *rdev)
1384 {
1385         return r600_gpu_soft_reset(rdev);
1386 }
1387
1388 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1389                                              u32 num_backends,
1390                                              u32 backend_disable_mask)
1391 {
1392         u32 backend_map = 0;
1393         u32 enabled_backends_mask;
1394         u32 enabled_backends_count;
1395         u32 cur_pipe;
1396         u32 swizzle_pipe[R6XX_MAX_PIPES];
1397         u32 cur_backend;
1398         u32 i;
1399
1400         if (num_tile_pipes > R6XX_MAX_PIPES)
1401                 num_tile_pipes = R6XX_MAX_PIPES;
1402         if (num_tile_pipes < 1)
1403                 num_tile_pipes = 1;
1404         if (num_backends > R6XX_MAX_BACKENDS)
1405                 num_backends = R6XX_MAX_BACKENDS;
1406         if (num_backends < 1)
1407                 num_backends = 1;
1408
1409         enabled_backends_mask = 0;
1410         enabled_backends_count = 0;
1411         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1412                 if (((backend_disable_mask >> i) & 1) == 0) {
1413                         enabled_backends_mask |= (1 << i);
1414                         ++enabled_backends_count;
1415                 }
1416                 if (enabled_backends_count == num_backends)
1417                         break;
1418         }
1419
1420         if (enabled_backends_count == 0) {
1421                 enabled_backends_mask = 1;
1422                 enabled_backends_count = 1;
1423         }
1424
1425         if (enabled_backends_count != num_backends)
1426                 num_backends = enabled_backends_count;
1427
1428         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1429         switch (num_tile_pipes) {
1430         case 1:
1431                 swizzle_pipe[0] = 0;
1432                 break;
1433         case 2:
1434                 swizzle_pipe[0] = 0;
1435                 swizzle_pipe[1] = 1;
1436                 break;
1437         case 3:
1438                 swizzle_pipe[0] = 0;
1439                 swizzle_pipe[1] = 1;
1440                 swizzle_pipe[2] = 2;
1441                 break;
1442         case 4:
1443                 swizzle_pipe[0] = 0;
1444                 swizzle_pipe[1] = 1;
1445                 swizzle_pipe[2] = 2;
1446                 swizzle_pipe[3] = 3;
1447                 break;
1448         case 5:
1449                 swizzle_pipe[0] = 0;
1450                 swizzle_pipe[1] = 1;
1451                 swizzle_pipe[2] = 2;
1452                 swizzle_pipe[3] = 3;
1453                 swizzle_pipe[4] = 4;
1454                 break;
1455         case 6:
1456                 swizzle_pipe[0] = 0;
1457                 swizzle_pipe[1] = 2;
1458                 swizzle_pipe[2] = 4;
1459                 swizzle_pipe[3] = 5;
1460                 swizzle_pipe[4] = 1;
1461                 swizzle_pipe[5] = 3;
1462                 break;
1463         case 7:
1464                 swizzle_pipe[0] = 0;
1465                 swizzle_pipe[1] = 2;
1466                 swizzle_pipe[2] = 4;
1467                 swizzle_pipe[3] = 6;
1468                 swizzle_pipe[4] = 1;
1469                 swizzle_pipe[5] = 3;
1470                 swizzle_pipe[6] = 5;
1471                 break;
1472         case 8:
1473                 swizzle_pipe[0] = 0;
1474                 swizzle_pipe[1] = 2;
1475                 swizzle_pipe[2] = 4;
1476                 swizzle_pipe[3] = 6;
1477                 swizzle_pipe[4] = 1;
1478                 swizzle_pipe[5] = 3;
1479                 swizzle_pipe[6] = 5;
1480                 swizzle_pipe[7] = 7;
1481                 break;
1482         }
1483
1484         cur_backend = 0;
1485         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1486                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1487                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1488
1489                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1490
1491                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1492         }
1493
1494         return backend_map;
1495 }
1496
1497 int r600_count_pipe_bits(uint32_t val)
1498 {
1499         int i, ret = 0;
1500
1501         for (i = 0; i < 32; i++) {
1502                 ret += val & 1;
1503                 val >>= 1;
1504         }
1505         return ret;
1506 }
1507
1508 void r600_gpu_init(struct radeon_device *rdev)
1509 {
1510         u32 tiling_config;
1511         u32 ramcfg;
1512         u32 backend_map;
1513         u32 cc_rb_backend_disable;
1514         u32 cc_gc_shader_pipe_config;
1515         u32 tmp;
1516         int i, j;
1517         u32 sq_config;
1518         u32 sq_gpr_resource_mgmt_1 = 0;
1519         u32 sq_gpr_resource_mgmt_2 = 0;
1520         u32 sq_thread_resource_mgmt = 0;
1521         u32 sq_stack_resource_mgmt_1 = 0;
1522         u32 sq_stack_resource_mgmt_2 = 0;
1523
1524         /* FIXME: implement */
1525         switch (rdev->family) {
1526         case CHIP_R600:
1527                 rdev->config.r600.max_pipes = 4;
1528                 rdev->config.r600.max_tile_pipes = 8;
1529                 rdev->config.r600.max_simds = 4;
1530                 rdev->config.r600.max_backends = 4;
1531                 rdev->config.r600.max_gprs = 256;
1532                 rdev->config.r600.max_threads = 192;
1533                 rdev->config.r600.max_stack_entries = 256;
1534                 rdev->config.r600.max_hw_contexts = 8;
1535                 rdev->config.r600.max_gs_threads = 16;
1536                 rdev->config.r600.sx_max_export_size = 128;
1537                 rdev->config.r600.sx_max_export_pos_size = 16;
1538                 rdev->config.r600.sx_max_export_smx_size = 128;
1539                 rdev->config.r600.sq_num_cf_insts = 2;
1540                 break;
1541         case CHIP_RV630:
1542         case CHIP_RV635:
1543                 rdev->config.r600.max_pipes = 2;
1544                 rdev->config.r600.max_tile_pipes = 2;
1545                 rdev->config.r600.max_simds = 3;
1546                 rdev->config.r600.max_backends = 1;
1547                 rdev->config.r600.max_gprs = 128;
1548                 rdev->config.r600.max_threads = 192;
1549                 rdev->config.r600.max_stack_entries = 128;
1550                 rdev->config.r600.max_hw_contexts = 8;
1551                 rdev->config.r600.max_gs_threads = 4;
1552                 rdev->config.r600.sx_max_export_size = 128;
1553                 rdev->config.r600.sx_max_export_pos_size = 16;
1554                 rdev->config.r600.sx_max_export_smx_size = 128;
1555                 rdev->config.r600.sq_num_cf_insts = 2;
1556                 break;
1557         case CHIP_RV610:
1558         case CHIP_RV620:
1559         case CHIP_RS780:
1560         case CHIP_RS880:
1561                 rdev->config.r600.max_pipes = 1;
1562                 rdev->config.r600.max_tile_pipes = 1;
1563                 rdev->config.r600.max_simds = 2;
1564                 rdev->config.r600.max_backends = 1;
1565                 rdev->config.r600.max_gprs = 128;
1566                 rdev->config.r600.max_threads = 192;
1567                 rdev->config.r600.max_stack_entries = 128;
1568                 rdev->config.r600.max_hw_contexts = 4;
1569                 rdev->config.r600.max_gs_threads = 4;
1570                 rdev->config.r600.sx_max_export_size = 128;
1571                 rdev->config.r600.sx_max_export_pos_size = 16;
1572                 rdev->config.r600.sx_max_export_smx_size = 128;
1573                 rdev->config.r600.sq_num_cf_insts = 1;
1574                 break;
1575         case CHIP_RV670:
1576                 rdev->config.r600.max_pipes = 4;
1577                 rdev->config.r600.max_tile_pipes = 4;
1578                 rdev->config.r600.max_simds = 4;
1579                 rdev->config.r600.max_backends = 4;
1580                 rdev->config.r600.max_gprs = 192;
1581                 rdev->config.r600.max_threads = 192;
1582                 rdev->config.r600.max_stack_entries = 256;
1583                 rdev->config.r600.max_hw_contexts = 8;
1584                 rdev->config.r600.max_gs_threads = 16;
1585                 rdev->config.r600.sx_max_export_size = 128;
1586                 rdev->config.r600.sx_max_export_pos_size = 16;
1587                 rdev->config.r600.sx_max_export_smx_size = 128;
1588                 rdev->config.r600.sq_num_cf_insts = 2;
1589                 break;
1590         default:
1591                 break;
1592         }
1593
1594         /* Initialize HDP */
1595         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1596                 WREG32((0x2c14 + j), 0x00000000);
1597                 WREG32((0x2c18 + j), 0x00000000);
1598                 WREG32((0x2c1c + j), 0x00000000);
1599                 WREG32((0x2c20 + j), 0x00000000);
1600                 WREG32((0x2c24 + j), 0x00000000);
1601         }
1602
1603         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1604
1605         /* Setup tiling */
1606         tiling_config = 0;
1607         ramcfg = RREG32(RAMCFG);
1608         switch (rdev->config.r600.max_tile_pipes) {
1609         case 1:
1610                 tiling_config |= PIPE_TILING(0);
1611                 break;
1612         case 2:
1613                 tiling_config |= PIPE_TILING(1);
1614                 break;
1615         case 4:
1616                 tiling_config |= PIPE_TILING(2);
1617                 break;
1618         case 8:
1619                 tiling_config |= PIPE_TILING(3);
1620                 break;
1621         default:
1622                 break;
1623         }
1624         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1625         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1626         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1627         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1628         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1629                 rdev->config.r600.tiling_group_size = 512;
1630         else
1631                 rdev->config.r600.tiling_group_size = 256;
1632         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1633         if (tmp > 3) {
1634                 tiling_config |= ROW_TILING(3);
1635                 tiling_config |= SAMPLE_SPLIT(3);
1636         } else {
1637                 tiling_config |= ROW_TILING(tmp);
1638                 tiling_config |= SAMPLE_SPLIT(tmp);
1639         }
1640         tiling_config |= BANK_SWAPS(1);
1641
1642         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1643         cc_rb_backend_disable |=
1644                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1645
1646         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1647         cc_gc_shader_pipe_config |=
1648                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1649         cc_gc_shader_pipe_config |=
1650                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1651
1652         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1653                                                         (R6XX_MAX_BACKENDS -
1654                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1655                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1656                                                         (cc_rb_backend_disable >> 16));
1657         rdev->config.r600.tile_config = tiling_config;
1658         tiling_config |= BACKEND_MAP(backend_map);
1659         WREG32(GB_TILING_CONFIG, tiling_config);
1660         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1661         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1662
1663         /* Setup pipes */
1664         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1665         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1666         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1667
1668         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1669         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1670         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1671
1672         /* Setup some CP states */
1673         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1674         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1675
1676         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1677                              SYNC_WALKER | SYNC_ALIGNER));
1678         /* Setup various GPU states */
1679         if (rdev->family == CHIP_RV670)
1680                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1681
1682         tmp = RREG32(SX_DEBUG_1);
1683         tmp |= SMX_EVENT_RELEASE;
1684         if ((rdev->family > CHIP_R600))
1685                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1686         WREG32(SX_DEBUG_1, tmp);
1687
1688         if (((rdev->family) == CHIP_R600) ||
1689             ((rdev->family) == CHIP_RV630) ||
1690             ((rdev->family) == CHIP_RV610) ||
1691             ((rdev->family) == CHIP_RV620) ||
1692             ((rdev->family) == CHIP_RS780) ||
1693             ((rdev->family) == CHIP_RS880)) {
1694                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1695         } else {
1696                 WREG32(DB_DEBUG, 0);
1697         }
1698         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1699                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1700
1701         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1702         WREG32(VGT_NUM_INSTANCES, 0);
1703
1704         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1705         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1706
1707         tmp = RREG32(SQ_MS_FIFO_SIZES);
1708         if (((rdev->family) == CHIP_RV610) ||
1709             ((rdev->family) == CHIP_RV620) ||
1710             ((rdev->family) == CHIP_RS780) ||
1711             ((rdev->family) == CHIP_RS880)) {
1712                 tmp = (CACHE_FIFO_SIZE(0xa) |
1713                        FETCH_FIFO_HIWATER(0xa) |
1714                        DONE_FIFO_HIWATER(0xe0) |
1715                        ALU_UPDATE_FIFO_HIWATER(0x8));
1716         } else if (((rdev->family) == CHIP_R600) ||
1717                    ((rdev->family) == CHIP_RV630)) {
1718                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1719                 tmp |= DONE_FIFO_HIWATER(0x4);
1720         }
1721         WREG32(SQ_MS_FIFO_SIZES, tmp);
1722
1723         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1724          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1725          */
1726         sq_config = RREG32(SQ_CONFIG);
1727         sq_config &= ~(PS_PRIO(3) |
1728                        VS_PRIO(3) |
1729                        GS_PRIO(3) |
1730                        ES_PRIO(3));
1731         sq_config |= (DX9_CONSTS |
1732                       VC_ENABLE |
1733                       PS_PRIO(0) |
1734                       VS_PRIO(1) |
1735                       GS_PRIO(2) |
1736                       ES_PRIO(3));
1737
1738         if ((rdev->family) == CHIP_R600) {
1739                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1740                                           NUM_VS_GPRS(124) |
1741                                           NUM_CLAUSE_TEMP_GPRS(4));
1742                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1743                                           NUM_ES_GPRS(0));
1744                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1745                                            NUM_VS_THREADS(48) |
1746                                            NUM_GS_THREADS(4) |
1747                                            NUM_ES_THREADS(4));
1748                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1749                                             NUM_VS_STACK_ENTRIES(128));
1750                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1751                                             NUM_ES_STACK_ENTRIES(0));
1752         } else if (((rdev->family) == CHIP_RV610) ||
1753                    ((rdev->family) == CHIP_RV620) ||
1754                    ((rdev->family) == CHIP_RS780) ||
1755                    ((rdev->family) == CHIP_RS880)) {
1756                 /* no vertex cache */
1757                 sq_config &= ~VC_ENABLE;
1758
1759                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1760                                           NUM_VS_GPRS(44) |
1761                                           NUM_CLAUSE_TEMP_GPRS(2));
1762                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1763                                           NUM_ES_GPRS(17));
1764                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1765                                            NUM_VS_THREADS(78) |
1766                                            NUM_GS_THREADS(4) |
1767                                            NUM_ES_THREADS(31));
1768                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1769                                             NUM_VS_STACK_ENTRIES(40));
1770                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1771                                             NUM_ES_STACK_ENTRIES(16));
1772         } else if (((rdev->family) == CHIP_RV630) ||
1773                    ((rdev->family) == CHIP_RV635)) {
1774                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1775                                           NUM_VS_GPRS(44) |
1776                                           NUM_CLAUSE_TEMP_GPRS(2));
1777                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1778                                           NUM_ES_GPRS(18));
1779                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1780                                            NUM_VS_THREADS(78) |
1781                                            NUM_GS_THREADS(4) |
1782                                            NUM_ES_THREADS(31));
1783                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1784                                             NUM_VS_STACK_ENTRIES(40));
1785                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1786                                             NUM_ES_STACK_ENTRIES(16));
1787         } else if ((rdev->family) == CHIP_RV670) {
1788                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1789                                           NUM_VS_GPRS(44) |
1790                                           NUM_CLAUSE_TEMP_GPRS(2));
1791                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1792                                           NUM_ES_GPRS(17));
1793                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1794                                            NUM_VS_THREADS(78) |
1795                                            NUM_GS_THREADS(4) |
1796                                            NUM_ES_THREADS(31));
1797                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1798                                             NUM_VS_STACK_ENTRIES(64));
1799                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1800                                             NUM_ES_STACK_ENTRIES(64));
1801         }
1802
1803         WREG32(SQ_CONFIG, sq_config);
1804         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1805         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1806         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1807         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1808         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1809
1810         if (((rdev->family) == CHIP_RV610) ||
1811             ((rdev->family) == CHIP_RV620) ||
1812             ((rdev->family) == CHIP_RS780) ||
1813             ((rdev->family) == CHIP_RS880)) {
1814                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1815         } else {
1816                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1817         }
1818
1819         /* More default values. 2D/3D driver should adjust as needed */
1820         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1821                                          S1_X(0x4) | S1_Y(0xc)));
1822         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1823                                          S1_X(0x2) | S1_Y(0x2) |
1824                                          S2_X(0xa) | S2_Y(0x6) |
1825                                          S3_X(0x6) | S3_Y(0xa)));
1826         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1827                                              S1_X(0x4) | S1_Y(0xc) |
1828                                              S2_X(0x1) | S2_Y(0x6) |
1829                                              S3_X(0xa) | S3_Y(0xe)));
1830         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1831                                              S5_X(0x0) | S5_Y(0x0) |
1832                                              S6_X(0xb) | S6_Y(0x4) |
1833                                              S7_X(0x7) | S7_Y(0x8)));
1834
1835         WREG32(VGT_STRMOUT_EN, 0);
1836         tmp = rdev->config.r600.max_pipes * 16;
1837         switch (rdev->family) {
1838         case CHIP_RV610:
1839         case CHIP_RV620:
1840         case CHIP_RS780:
1841         case CHIP_RS880:
1842                 tmp += 32;
1843                 break;
1844         case CHIP_RV670:
1845                 tmp += 128;
1846                 break;
1847         default:
1848                 break;
1849         }
1850         if (tmp > 256) {
1851                 tmp = 256;
1852         }
1853         WREG32(VGT_ES_PER_GS, 128);
1854         WREG32(VGT_GS_PER_ES, tmp);
1855         WREG32(VGT_GS_PER_VS, 2);
1856         WREG32(VGT_GS_VERTEX_REUSE, 16);
1857
1858         /* more default values. 2D/3D driver should adjust as needed */
1859         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1860         WREG32(VGT_STRMOUT_EN, 0);
1861         WREG32(SX_MISC, 0);
1862         WREG32(PA_SC_MODE_CNTL, 0);
1863         WREG32(PA_SC_AA_CONFIG, 0);
1864         WREG32(PA_SC_LINE_STIPPLE, 0);
1865         WREG32(SPI_INPUT_Z, 0);
1866         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1867         WREG32(CB_COLOR7_FRAG, 0);
1868
1869         /* Clear render buffer base addresses */
1870         WREG32(CB_COLOR0_BASE, 0);
1871         WREG32(CB_COLOR1_BASE, 0);
1872         WREG32(CB_COLOR2_BASE, 0);
1873         WREG32(CB_COLOR3_BASE, 0);
1874         WREG32(CB_COLOR4_BASE, 0);
1875         WREG32(CB_COLOR5_BASE, 0);
1876         WREG32(CB_COLOR6_BASE, 0);
1877         WREG32(CB_COLOR7_BASE, 0);
1878         WREG32(CB_COLOR7_FRAG, 0);
1879
1880         switch (rdev->family) {
1881         case CHIP_RV610:
1882         case CHIP_RV620:
1883         case CHIP_RS780:
1884         case CHIP_RS880:
1885                 tmp = TC_L2_SIZE(8);
1886                 break;
1887         case CHIP_RV630:
1888         case CHIP_RV635:
1889                 tmp = TC_L2_SIZE(4);
1890                 break;
1891         case CHIP_R600:
1892                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1893                 break;
1894         default:
1895                 tmp = TC_L2_SIZE(0);
1896                 break;
1897         }
1898         WREG32(TC_CNTL, tmp);
1899
1900         tmp = RREG32(HDP_HOST_PATH_CNTL);
1901         WREG32(HDP_HOST_PATH_CNTL, tmp);
1902
1903         tmp = RREG32(ARB_POP);
1904         tmp |= ENABLE_TC128;
1905         WREG32(ARB_POP, tmp);
1906
1907         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1908         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1909                                NUM_CLIP_SEQ(3)));
1910         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1911 }
1912
1913
1914 /*
1915  * Indirect registers accessor
1916  */
1917 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1918 {
1919         u32 r;
1920
1921         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1922         (void)RREG32(PCIE_PORT_INDEX);
1923         r = RREG32(PCIE_PORT_DATA);
1924         return r;
1925 }
1926
1927 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1928 {
1929         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1930         (void)RREG32(PCIE_PORT_INDEX);
1931         WREG32(PCIE_PORT_DATA, (v));
1932         (void)RREG32(PCIE_PORT_DATA);
1933 }
1934
1935 /*
1936  * CP & Ring
1937  */
1938 void r600_cp_stop(struct radeon_device *rdev)
1939 {
1940         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1941         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1942         WREG32(SCRATCH_UMSK, 0);
1943 }
1944
1945 int r600_init_microcode(struct radeon_device *rdev)
1946 {
1947         struct platform_device *pdev;
1948         const char *chip_name;
1949         const char *rlc_chip_name;
1950         size_t pfp_req_size, me_req_size, rlc_req_size;
1951         char fw_name[30];
1952         int err;
1953
1954         DRM_DEBUG("\n");
1955
1956         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1957         err = IS_ERR(pdev);
1958         if (err) {
1959                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1960                 return -EINVAL;
1961         }
1962
1963         switch (rdev->family) {
1964         case CHIP_R600:
1965                 chip_name = "R600";
1966                 rlc_chip_name = "R600";
1967                 break;
1968         case CHIP_RV610:
1969                 chip_name = "RV610";
1970                 rlc_chip_name = "R600";
1971                 break;
1972         case CHIP_RV630:
1973                 chip_name = "RV630";
1974                 rlc_chip_name = "R600";
1975                 break;
1976         case CHIP_RV620:
1977                 chip_name = "RV620";
1978                 rlc_chip_name = "R600";
1979                 break;
1980         case CHIP_RV635:
1981                 chip_name = "RV635";
1982                 rlc_chip_name = "R600";
1983                 break;
1984         case CHIP_RV670:
1985                 chip_name = "RV670";
1986                 rlc_chip_name = "R600";
1987                 break;
1988         case CHIP_RS780:
1989         case CHIP_RS880:
1990                 chip_name = "RS780";
1991                 rlc_chip_name = "R600";
1992                 break;
1993         case CHIP_RV770:
1994                 chip_name = "RV770";
1995                 rlc_chip_name = "R700";
1996                 break;
1997         case CHIP_RV730:
1998         case CHIP_RV740:
1999                 chip_name = "RV730";
2000                 rlc_chip_name = "R700";
2001                 break;
2002         case CHIP_RV710:
2003                 chip_name = "RV710";
2004                 rlc_chip_name = "R700";
2005                 break;
2006         case CHIP_CEDAR:
2007                 chip_name = "CEDAR";
2008                 rlc_chip_name = "CEDAR";
2009                 break;
2010         case CHIP_REDWOOD:
2011                 chip_name = "REDWOOD";
2012                 rlc_chip_name = "REDWOOD";
2013                 break;
2014         case CHIP_JUNIPER:
2015                 chip_name = "JUNIPER";
2016                 rlc_chip_name = "JUNIPER";
2017                 break;
2018         case CHIP_CYPRESS:
2019         case CHIP_HEMLOCK:
2020                 chip_name = "CYPRESS";
2021                 rlc_chip_name = "CYPRESS";
2022                 break;
2023         case CHIP_PALM:
2024                 chip_name = "PALM";
2025                 rlc_chip_name = "SUMO";
2026                 break;
2027         default: BUG();
2028         }
2029
2030         if (rdev->family >= CHIP_CEDAR) {
2031                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2032                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2033                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2034         } else if (rdev->family >= CHIP_RV770) {
2035                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2036                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2037                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2038         } else {
2039                 pfp_req_size = PFP_UCODE_SIZE * 4;
2040                 me_req_size = PM4_UCODE_SIZE * 12;
2041                 rlc_req_size = RLC_UCODE_SIZE * 4;
2042         }
2043
2044         DRM_INFO("Loading %s Microcode\n", chip_name);
2045
2046         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2047         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2048         if (err)
2049                 goto out;
2050         if (rdev->pfp_fw->size != pfp_req_size) {
2051                 printk(KERN_ERR
2052                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2053                        rdev->pfp_fw->size, fw_name);
2054                 err = -EINVAL;
2055                 goto out;
2056         }
2057
2058         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2059         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2060         if (err)
2061                 goto out;
2062         if (rdev->me_fw->size != me_req_size) {
2063                 printk(KERN_ERR
2064                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2065                        rdev->me_fw->size, fw_name);
2066                 err = -EINVAL;
2067         }
2068
2069         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2070         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2071         if (err)
2072                 goto out;
2073         if (rdev->rlc_fw->size != rlc_req_size) {
2074                 printk(KERN_ERR
2075                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2076                        rdev->rlc_fw->size, fw_name);
2077                 err = -EINVAL;
2078         }
2079
2080 out:
2081         platform_device_unregister(pdev);
2082
2083         if (err) {
2084                 if (err != -EINVAL)
2085                         printk(KERN_ERR
2086                                "r600_cp: Failed to load firmware \"%s\"\n",
2087                                fw_name);
2088                 release_firmware(rdev->pfp_fw);
2089                 rdev->pfp_fw = NULL;
2090                 release_firmware(rdev->me_fw);
2091                 rdev->me_fw = NULL;
2092                 release_firmware(rdev->rlc_fw);
2093                 rdev->rlc_fw = NULL;
2094         }
2095         return err;
2096 }
2097
2098 static int r600_cp_load_microcode(struct radeon_device *rdev)
2099 {
2100         const __be32 *fw_data;
2101         int i;
2102
2103         if (!rdev->me_fw || !rdev->pfp_fw)
2104                 return -EINVAL;
2105
2106         r600_cp_stop(rdev);
2107
2108         WREG32(CP_RB_CNTL,
2109 #ifdef __BIG_ENDIAN
2110                BUF_SWAP_32BIT |
2111 #endif
2112                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2113
2114         /* Reset cp */
2115         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2116         RREG32(GRBM_SOFT_RESET);
2117         mdelay(15);
2118         WREG32(GRBM_SOFT_RESET, 0);
2119
2120         WREG32(CP_ME_RAM_WADDR, 0);
2121
2122         fw_data = (const __be32 *)rdev->me_fw->data;
2123         WREG32(CP_ME_RAM_WADDR, 0);
2124         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2125                 WREG32(CP_ME_RAM_DATA,
2126                        be32_to_cpup(fw_data++));
2127
2128         fw_data = (const __be32 *)rdev->pfp_fw->data;
2129         WREG32(CP_PFP_UCODE_ADDR, 0);
2130         for (i = 0; i < PFP_UCODE_SIZE; i++)
2131                 WREG32(CP_PFP_UCODE_DATA,
2132                        be32_to_cpup(fw_data++));
2133
2134         WREG32(CP_PFP_UCODE_ADDR, 0);
2135         WREG32(CP_ME_RAM_WADDR, 0);
2136         WREG32(CP_ME_RAM_RADDR, 0);
2137         return 0;
2138 }
2139
2140 int r600_cp_start(struct radeon_device *rdev)
2141 {
2142         int r;
2143         uint32_t cp_me;
2144
2145         r = radeon_ring_lock(rdev, 7);
2146         if (r) {
2147                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2148                 return r;
2149         }
2150         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2151         radeon_ring_write(rdev, 0x1);
2152         if (rdev->family >= CHIP_RV770) {
2153                 radeon_ring_write(rdev, 0x0);
2154                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2155         } else {
2156                 radeon_ring_write(rdev, 0x3);
2157                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2158         }
2159         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2160         radeon_ring_write(rdev, 0);
2161         radeon_ring_write(rdev, 0);
2162         radeon_ring_unlock_commit(rdev);
2163
2164         cp_me = 0xff;
2165         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2166         return 0;
2167 }
2168
2169 int r600_cp_resume(struct radeon_device *rdev)
2170 {
2171         u32 tmp;
2172         u32 rb_bufsz;
2173         int r;
2174
2175         /* Reset cp */
2176         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2177         RREG32(GRBM_SOFT_RESET);
2178         mdelay(15);
2179         WREG32(GRBM_SOFT_RESET, 0);
2180
2181         /* Set ring buffer size */
2182         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2183         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2184 #ifdef __BIG_ENDIAN
2185         tmp |= BUF_SWAP_32BIT;
2186 #endif
2187         WREG32(CP_RB_CNTL, tmp);
2188         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2189
2190         /* Set the write pointer delay */
2191         WREG32(CP_RB_WPTR_DELAY, 0);
2192
2193         /* Initialize the ring buffer's read and write pointers */
2194         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2195         WREG32(CP_RB_RPTR_WR, 0);
2196         WREG32(CP_RB_WPTR, 0);
2197
2198         /* set the wb address whether it's enabled or not */
2199         WREG32(CP_RB_RPTR_ADDR,
2200 #ifdef __BIG_ENDIAN
2201                RB_RPTR_SWAP(2) |
2202 #endif
2203                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2204         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2205         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2206
2207         if (rdev->wb.enabled)
2208                 WREG32(SCRATCH_UMSK, 0xff);
2209         else {
2210                 tmp |= RB_NO_UPDATE;
2211                 WREG32(SCRATCH_UMSK, 0);
2212         }
2213
2214         mdelay(1);
2215         WREG32(CP_RB_CNTL, tmp);
2216
2217         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2218         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2219
2220         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2221         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2222
2223         r600_cp_start(rdev);
2224         rdev->cp.ready = true;
2225         r = radeon_ring_test(rdev);
2226         if (r) {
2227                 rdev->cp.ready = false;
2228                 return r;
2229         }
2230         return 0;
2231 }
2232
2233 void r600_cp_commit(struct radeon_device *rdev)
2234 {
2235         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2236         (void)RREG32(CP_RB_WPTR);
2237 }
2238
2239 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2240 {
2241         u32 rb_bufsz;
2242
2243         /* Align ring size */
2244         rb_bufsz = drm_order(ring_size / 8);
2245         ring_size = (1 << (rb_bufsz + 1)) * 4;
2246         rdev->cp.ring_size = ring_size;
2247         rdev->cp.align_mask = 16 - 1;
2248 }
2249
2250 void r600_cp_fini(struct radeon_device *rdev)
2251 {
2252         r600_cp_stop(rdev);
2253         radeon_ring_fini(rdev);
2254 }
2255
2256
2257 /*
2258  * GPU scratch registers helpers function.
2259  */
2260 void r600_scratch_init(struct radeon_device *rdev)
2261 {
2262         int i;
2263
2264         rdev->scratch.num_reg = 7;
2265         rdev->scratch.reg_base = SCRATCH_REG0;
2266         for (i = 0; i < rdev->scratch.num_reg; i++) {
2267                 rdev->scratch.free[i] = true;
2268                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2269         }
2270 }
2271
2272 int r600_ring_test(struct radeon_device *rdev)
2273 {
2274         uint32_t scratch;
2275         uint32_t tmp = 0;
2276         unsigned i;
2277         int r;
2278
2279         r = radeon_scratch_get(rdev, &scratch);
2280         if (r) {
2281                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2282                 return r;
2283         }
2284         WREG32(scratch, 0xCAFEDEAD);
2285         r = radeon_ring_lock(rdev, 3);
2286         if (r) {
2287                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2288                 radeon_scratch_free(rdev, scratch);
2289                 return r;
2290         }
2291         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2292         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2293         radeon_ring_write(rdev, 0xDEADBEEF);
2294         radeon_ring_unlock_commit(rdev);
2295         for (i = 0; i < rdev->usec_timeout; i++) {
2296                 tmp = RREG32(scratch);
2297                 if (tmp == 0xDEADBEEF)
2298                         break;
2299                 DRM_UDELAY(1);
2300         }
2301         if (i < rdev->usec_timeout) {
2302                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2303         } else {
2304                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2305                           scratch, tmp);
2306                 r = -EINVAL;
2307         }
2308         radeon_scratch_free(rdev, scratch);
2309         return r;
2310 }
2311
2312 void r600_fence_ring_emit(struct radeon_device *rdev,
2313                           struct radeon_fence *fence)
2314 {
2315         if (rdev->wb.use_event) {
2316                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2317                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2318                 /* EVENT_WRITE_EOP - flush caches, send int */
2319                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2320                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2321                 radeon_ring_write(rdev, addr & 0xffffffff);
2322                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2323                 radeon_ring_write(rdev, fence->seq);
2324                 radeon_ring_write(rdev, 0);
2325         } else {
2326                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2327                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2328                 /* wait for 3D idle clean */
2329                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2330                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2331                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2332                 /* Emit fence sequence & fire IRQ */
2333                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2334                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2335                 radeon_ring_write(rdev, fence->seq);
2336                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2337                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2338                 radeon_ring_write(rdev, RB_INT_STAT);
2339         }
2340 }
2341
2342 int r600_copy_blit(struct radeon_device *rdev,
2343                    uint64_t src_offset, uint64_t dst_offset,
2344                    unsigned num_pages, struct radeon_fence *fence)
2345 {
2346         int r;
2347
2348         mutex_lock(&rdev->r600_blit.mutex);
2349         rdev->r600_blit.vb_ib = NULL;
2350         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2351         if (r) {
2352                 if (rdev->r600_blit.vb_ib)
2353                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2354                 mutex_unlock(&rdev->r600_blit.mutex);
2355                 return r;
2356         }
2357         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2358         r600_blit_done_copy(rdev, fence);
2359         mutex_unlock(&rdev->r600_blit.mutex);
2360         return 0;
2361 }
2362
2363 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2364                          uint32_t tiling_flags, uint32_t pitch,
2365                          uint32_t offset, uint32_t obj_size)
2366 {
2367         /* FIXME: implement */
2368         return 0;
2369 }
2370
2371 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2372 {
2373         /* FIXME: implement */
2374 }
2375
2376 int r600_startup(struct radeon_device *rdev)
2377 {
2378         int r;
2379
2380         /* enable pcie gen2 link */
2381         r600_pcie_gen2_enable(rdev);
2382
2383         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2384                 r = r600_init_microcode(rdev);
2385                 if (r) {
2386                         DRM_ERROR("Failed to load firmware!\n");
2387                         return r;
2388                 }
2389         }
2390
2391         r600_mc_program(rdev);
2392         if (rdev->flags & RADEON_IS_AGP) {
2393                 r600_agp_enable(rdev);
2394         } else {
2395                 r = r600_pcie_gart_enable(rdev);
2396                 if (r)
2397                         return r;
2398         }
2399         r600_gpu_init(rdev);
2400         r = r600_blit_init(rdev);
2401         if (r) {
2402                 r600_blit_fini(rdev);
2403                 rdev->asic->copy = NULL;
2404                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2405         }
2406
2407         /* allocate wb buffer */
2408         r = radeon_wb_init(rdev);
2409         if (r)
2410                 return r;
2411
2412         /* Enable IRQ */
2413         r = r600_irq_init(rdev);
2414         if (r) {
2415                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2416                 radeon_irq_kms_fini(rdev);
2417                 return r;
2418         }
2419         r600_irq_set(rdev);
2420
2421         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2422         if (r)
2423                 return r;
2424         r = r600_cp_load_microcode(rdev);
2425         if (r)
2426                 return r;
2427         r = r600_cp_resume(rdev);
2428         if (r)
2429                 return r;
2430
2431         return 0;
2432 }
2433
2434 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2435 {
2436         uint32_t temp;
2437
2438         temp = RREG32(CONFIG_CNTL);
2439         if (state == false) {
2440                 temp &= ~(1<<0);
2441                 temp |= (1<<1);
2442         } else {
2443                 temp &= ~(1<<1);
2444         }
2445         WREG32(CONFIG_CNTL, temp);
2446 }
2447
2448 int r600_resume(struct radeon_device *rdev)
2449 {
2450         int r;
2451
2452         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2453          * posting will perform necessary task to bring back GPU into good
2454          * shape.
2455          */
2456         /* post card */
2457         atom_asic_init(rdev->mode_info.atom_context);
2458
2459         r = r600_startup(rdev);
2460         if (r) {
2461                 DRM_ERROR("r600 startup failed on resume\n");
2462                 return r;
2463         }
2464
2465         r = r600_ib_test(rdev);
2466         if (r) {
2467                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2468                 return r;
2469         }
2470
2471         r = r600_audio_init(rdev);
2472         if (r) {
2473                 DRM_ERROR("radeon: audio resume failed\n");
2474                 return r;
2475         }
2476
2477         return r;
2478 }
2479
2480 int r600_suspend(struct radeon_device *rdev)
2481 {
2482         int r;
2483
2484         r600_audio_fini(rdev);
2485         /* FIXME: we should wait for ring to be empty */
2486         r600_cp_stop(rdev);
2487         rdev->cp.ready = false;
2488         r600_irq_suspend(rdev);
2489         radeon_wb_disable(rdev);
2490         r600_pcie_gart_disable(rdev);
2491         /* unpin shaders bo */
2492         if (rdev->r600_blit.shader_obj) {
2493                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2494                 if (!r) {
2495                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2496                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2497                 }
2498         }
2499         return 0;
2500 }
2501
2502 /* Plan is to move initialization in that function and use
2503  * helper function so that radeon_device_init pretty much
2504  * do nothing more than calling asic specific function. This
2505  * should also allow to remove a bunch of callback function
2506  * like vram_info.
2507  */
2508 int r600_init(struct radeon_device *rdev)
2509 {
2510         int r;
2511
2512         if (r600_debugfs_mc_info_init(rdev)) {
2513                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2514         }
2515         /* This don't do much */
2516         r = radeon_gem_init(rdev);
2517         if (r)
2518                 return r;
2519         /* Read BIOS */
2520         if (!radeon_get_bios(rdev)) {
2521                 if (ASIC_IS_AVIVO(rdev))
2522                         return -EINVAL;
2523         }
2524         /* Must be an ATOMBIOS */
2525         if (!rdev->is_atom_bios) {
2526                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2527                 return -EINVAL;
2528         }
2529         r = radeon_atombios_init(rdev);
2530         if (r)
2531                 return r;
2532         /* Post card if necessary */
2533         if (!radeon_card_posted(rdev)) {
2534                 if (!rdev->bios) {
2535                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2536                         return -EINVAL;
2537                 }
2538                 DRM_INFO("GPU not posted. posting now...\n");
2539                 atom_asic_init(rdev->mode_info.atom_context);
2540         }
2541         /* Initialize scratch registers */
2542         r600_scratch_init(rdev);
2543         /* Initialize surface registers */
2544         radeon_surface_init(rdev);
2545         /* Initialize clocks */
2546         radeon_get_clock_info(rdev->ddev);
2547         /* Fence driver */
2548         r = radeon_fence_driver_init(rdev);
2549         if (r)
2550                 return r;
2551         if (rdev->flags & RADEON_IS_AGP) {
2552                 r = radeon_agp_init(rdev);
2553                 if (r)
2554                         radeon_agp_disable(rdev);
2555         }
2556         r = r600_mc_init(rdev);
2557         if (r)
2558                 return r;
2559         /* Memory manager */
2560         r = radeon_bo_init(rdev);
2561         if (r)
2562                 return r;
2563
2564         r = radeon_irq_kms_init(rdev);
2565         if (r)
2566                 return r;
2567
2568         rdev->cp.ring_obj = NULL;
2569         r600_ring_init(rdev, 1024 * 1024);
2570
2571         rdev->ih.ring_obj = NULL;
2572         r600_ih_ring_init(rdev, 64 * 1024);
2573
2574         r = r600_pcie_gart_init(rdev);
2575         if (r)
2576                 return r;
2577
2578         rdev->accel_working = true;
2579         r = r600_startup(rdev);
2580         if (r) {
2581                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2582                 r600_cp_fini(rdev);
2583                 r600_irq_fini(rdev);
2584                 radeon_wb_fini(rdev);
2585                 radeon_irq_kms_fini(rdev);
2586                 r600_pcie_gart_fini(rdev);
2587                 rdev->accel_working = false;
2588         }
2589         if (rdev->accel_working) {
2590                 r = radeon_ib_pool_init(rdev);
2591                 if (r) {
2592                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2593                         rdev->accel_working = false;
2594                 } else {
2595                         r = r600_ib_test(rdev);
2596                         if (r) {
2597                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2598                                 rdev->accel_working = false;
2599                         }
2600                 }
2601         }
2602
2603         r = r600_audio_init(rdev);
2604         if (r)
2605                 return r; /* TODO error handling */
2606         return 0;
2607 }
2608
2609 void r600_fini(struct radeon_device *rdev)
2610 {
2611         r600_audio_fini(rdev);
2612         r600_blit_fini(rdev);
2613         r600_cp_fini(rdev);
2614         r600_irq_fini(rdev);
2615         radeon_wb_fini(rdev);
2616         radeon_irq_kms_fini(rdev);
2617         r600_pcie_gart_fini(rdev);
2618         radeon_agp_fini(rdev);
2619         radeon_gem_fini(rdev);
2620         radeon_fence_driver_fini(rdev);
2621         radeon_bo_fini(rdev);
2622         radeon_atombios_fini(rdev);
2623         kfree(rdev->bios);
2624         rdev->bios = NULL;
2625 }
2626
2627
2628 /*
2629  * CS stuff
2630  */
2631 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2632 {
2633         /* FIXME: implement */
2634         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2635         radeon_ring_write(rdev,
2636 #ifdef __BIG_ENDIAN
2637                           (2 << 0) |
2638 #endif
2639                           (ib->gpu_addr & 0xFFFFFFFC));
2640         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2641         radeon_ring_write(rdev, ib->length_dw);
2642 }
2643
2644 int r600_ib_test(struct radeon_device *rdev)
2645 {
2646         struct radeon_ib *ib;
2647         uint32_t scratch;
2648         uint32_t tmp = 0;
2649         unsigned i;
2650         int r;
2651
2652         r = radeon_scratch_get(rdev, &scratch);
2653         if (r) {
2654                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2655                 return r;
2656         }
2657         WREG32(scratch, 0xCAFEDEAD);
2658         r = radeon_ib_get(rdev, &ib);
2659         if (r) {
2660                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2661                 return r;
2662         }
2663         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2664         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2665         ib->ptr[2] = 0xDEADBEEF;
2666         ib->ptr[3] = PACKET2(0);
2667         ib->ptr[4] = PACKET2(0);
2668         ib->ptr[5] = PACKET2(0);
2669         ib->ptr[6] = PACKET2(0);
2670         ib->ptr[7] = PACKET2(0);
2671         ib->ptr[8] = PACKET2(0);
2672         ib->ptr[9] = PACKET2(0);
2673         ib->ptr[10] = PACKET2(0);
2674         ib->ptr[11] = PACKET2(0);
2675         ib->ptr[12] = PACKET2(0);
2676         ib->ptr[13] = PACKET2(0);
2677         ib->ptr[14] = PACKET2(0);
2678         ib->ptr[15] = PACKET2(0);
2679         ib->length_dw = 16;
2680         r = radeon_ib_schedule(rdev, ib);
2681         if (r) {
2682                 radeon_scratch_free(rdev, scratch);
2683                 radeon_ib_free(rdev, &ib);
2684                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2685                 return r;
2686         }
2687         r = radeon_fence_wait(ib->fence, false);
2688         if (r) {
2689                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2690                 return r;
2691         }
2692         for (i = 0; i < rdev->usec_timeout; i++) {
2693                 tmp = RREG32(scratch);
2694                 if (tmp == 0xDEADBEEF)
2695                         break;
2696                 DRM_UDELAY(1);
2697         }
2698         if (i < rdev->usec_timeout) {
2699                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2700         } else {
2701                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2702                           scratch, tmp);
2703                 r = -EINVAL;
2704         }
2705         radeon_scratch_free(rdev, scratch);
2706         radeon_ib_free(rdev, &ib);
2707         return r;
2708 }
2709
2710 /*
2711  * Interrupts
2712  *
2713  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2714  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2715  * writing to the ring and the GPU consuming, the GPU writes to the ring
2716  * and host consumes.  As the host irq handler processes interrupts, it
2717  * increments the rptr.  When the rptr catches up with the wptr, all the
2718  * current interrupts have been processed.
2719  */
2720
2721 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2722 {
2723         u32 rb_bufsz;
2724
2725         /* Align ring size */
2726         rb_bufsz = drm_order(ring_size / 4);
2727         ring_size = (1 << rb_bufsz) * 4;
2728         rdev->ih.ring_size = ring_size;
2729         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2730         rdev->ih.rptr = 0;
2731 }
2732
2733 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2734 {
2735         int r;
2736
2737         /* Allocate ring buffer */
2738         if (rdev->ih.ring_obj == NULL) {
2739                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2740                                      PAGE_SIZE, true,
2741                                      RADEON_GEM_DOMAIN_GTT,
2742                                      &rdev->ih.ring_obj);
2743                 if (r) {
2744                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2745                         return r;
2746                 }
2747                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2748                 if (unlikely(r != 0))
2749                         return r;
2750                 r = radeon_bo_pin(rdev->ih.ring_obj,
2751                                   RADEON_GEM_DOMAIN_GTT,
2752                                   &rdev->ih.gpu_addr);
2753                 if (r) {
2754                         radeon_bo_unreserve(rdev->ih.ring_obj);
2755                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2756                         return r;
2757                 }
2758                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2759                                    (void **)&rdev->ih.ring);
2760                 radeon_bo_unreserve(rdev->ih.ring_obj);
2761                 if (r) {
2762                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2763                         return r;
2764                 }
2765         }
2766         return 0;
2767 }
2768
2769 static void r600_ih_ring_fini(struct radeon_device *rdev)
2770 {
2771         int r;
2772         if (rdev->ih.ring_obj) {
2773                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2774                 if (likely(r == 0)) {
2775                         radeon_bo_kunmap(rdev->ih.ring_obj);
2776                         radeon_bo_unpin(rdev->ih.ring_obj);
2777                         radeon_bo_unreserve(rdev->ih.ring_obj);
2778                 }
2779                 radeon_bo_unref(&rdev->ih.ring_obj);
2780                 rdev->ih.ring = NULL;
2781                 rdev->ih.ring_obj = NULL;
2782         }
2783 }
2784
2785 void r600_rlc_stop(struct radeon_device *rdev)
2786 {
2787
2788         if ((rdev->family >= CHIP_RV770) &&
2789             (rdev->family <= CHIP_RV740)) {
2790                 /* r7xx asics need to soft reset RLC before halting */
2791                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2792                 RREG32(SRBM_SOFT_RESET);
2793                 udelay(15000);
2794                 WREG32(SRBM_SOFT_RESET, 0);
2795                 RREG32(SRBM_SOFT_RESET);
2796         }
2797
2798         WREG32(RLC_CNTL, 0);
2799 }
2800
2801 static void r600_rlc_start(struct radeon_device *rdev)
2802 {
2803         WREG32(RLC_CNTL, RLC_ENABLE);
2804 }
2805
2806 static int r600_rlc_init(struct radeon_device *rdev)
2807 {
2808         u32 i;
2809         const __be32 *fw_data;
2810
2811         if (!rdev->rlc_fw)
2812                 return -EINVAL;
2813
2814         r600_rlc_stop(rdev);
2815
2816         WREG32(RLC_HB_BASE, 0);
2817         WREG32(RLC_HB_CNTL, 0);
2818         WREG32(RLC_HB_RPTR, 0);
2819         WREG32(RLC_HB_WPTR, 0);
2820         if (rdev->family <= CHIP_CAICOS) {
2821                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2822                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2823         }
2824         WREG32(RLC_MC_CNTL, 0);
2825         WREG32(RLC_UCODE_CNTL, 0);
2826
2827         fw_data = (const __be32 *)rdev->rlc_fw->data;
2828         if (rdev->family >= CHIP_CAYMAN) {
2829                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2830                         WREG32(RLC_UCODE_ADDR, i);
2831                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2832                 }
2833         } else if (rdev->family >= CHIP_CEDAR) {
2834                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2835                         WREG32(RLC_UCODE_ADDR, i);
2836                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2837                 }
2838         } else if (rdev->family >= CHIP_RV770) {
2839                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2840                         WREG32(RLC_UCODE_ADDR, i);
2841                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2842                 }
2843         } else {
2844                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2845                         WREG32(RLC_UCODE_ADDR, i);
2846                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2847                 }
2848         }
2849         WREG32(RLC_UCODE_ADDR, 0);
2850
2851         r600_rlc_start(rdev);
2852
2853         return 0;
2854 }
2855
2856 static void r600_enable_interrupts(struct radeon_device *rdev)
2857 {
2858         u32 ih_cntl = RREG32(IH_CNTL);
2859         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2860
2861         ih_cntl |= ENABLE_INTR;
2862         ih_rb_cntl |= IH_RB_ENABLE;
2863         WREG32(IH_CNTL, ih_cntl);
2864         WREG32(IH_RB_CNTL, ih_rb_cntl);
2865         rdev->ih.enabled = true;
2866 }
2867
2868 void r600_disable_interrupts(struct radeon_device *rdev)
2869 {
2870         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2871         u32 ih_cntl = RREG32(IH_CNTL);
2872
2873         ih_rb_cntl &= ~IH_RB_ENABLE;
2874         ih_cntl &= ~ENABLE_INTR;
2875         WREG32(IH_RB_CNTL, ih_rb_cntl);
2876         WREG32(IH_CNTL, ih_cntl);
2877         /* set rptr, wptr to 0 */
2878         WREG32(IH_RB_RPTR, 0);
2879         WREG32(IH_RB_WPTR, 0);
2880         rdev->ih.enabled = false;
2881         rdev->ih.wptr = 0;
2882         rdev->ih.rptr = 0;
2883 }
2884
2885 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2886 {
2887         u32 tmp;
2888
2889         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2890         WREG32(GRBM_INT_CNTL, 0);
2891         WREG32(DxMODE_INT_MASK, 0);
2892         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2893         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2894         if (ASIC_IS_DCE3(rdev)) {
2895                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2896                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2897                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2898                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2899                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2900                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2901                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2902                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2903                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2904                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2905                 if (ASIC_IS_DCE32(rdev)) {
2906                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2907                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2908                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2909                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2910                 }
2911         } else {
2912                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2913                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2914                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2915                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2916                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2917                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2918                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2919                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2920         }
2921 }
2922
2923 int r600_irq_init(struct radeon_device *rdev)
2924 {
2925         int ret = 0;
2926         int rb_bufsz;
2927         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2928
2929         /* allocate ring */
2930         ret = r600_ih_ring_alloc(rdev);
2931         if (ret)
2932                 return ret;
2933
2934         /* disable irqs */
2935         r600_disable_interrupts(rdev);
2936
2937         /* init rlc */
2938         ret = r600_rlc_init(rdev);
2939         if (ret) {
2940                 r600_ih_ring_fini(rdev);
2941                 return ret;
2942         }
2943
2944         /* setup interrupt control */
2945         /* set dummy read address to ring address */
2946         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2947         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2948         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2949          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2950          */
2951         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2952         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2953         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2954         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2955
2956         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2957         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2958
2959         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2960                       IH_WPTR_OVERFLOW_CLEAR |
2961                       (rb_bufsz << 1));
2962
2963         if (rdev->wb.enabled)
2964                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2965
2966         /* set the writeback address whether it's enabled or not */
2967         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2968         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2969
2970         WREG32(IH_RB_CNTL, ih_rb_cntl);
2971
2972         /* set rptr, wptr to 0 */
2973         WREG32(IH_RB_RPTR, 0);
2974         WREG32(IH_RB_WPTR, 0);
2975
2976         /* Default settings for IH_CNTL (disabled at first) */
2977         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2978         /* RPTR_REARM only works if msi's are enabled */
2979         if (rdev->msi_enabled)
2980                 ih_cntl |= RPTR_REARM;
2981
2982 #ifdef __BIG_ENDIAN
2983         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2984 #endif
2985         WREG32(IH_CNTL, ih_cntl);
2986
2987         /* force the active interrupt state to all disabled */
2988         if (rdev->family >= CHIP_CEDAR)
2989                 evergreen_disable_interrupt_state(rdev);
2990         else
2991                 r600_disable_interrupt_state(rdev);
2992
2993         /* enable irqs */
2994         r600_enable_interrupts(rdev);
2995
2996         return ret;
2997 }
2998
2999 void r600_irq_suspend(struct radeon_device *rdev)
3000 {
3001         r600_irq_disable(rdev);
3002         r600_rlc_stop(rdev);
3003 }
3004
3005 void r600_irq_fini(struct radeon_device *rdev)
3006 {
3007         r600_irq_suspend(rdev);
3008         r600_ih_ring_fini(rdev);
3009 }
3010
3011 int r600_irq_set(struct radeon_device *rdev)
3012 {
3013         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3014         u32 mode_int = 0;
3015         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3016         u32 grbm_int_cntl = 0;
3017         u32 hdmi1, hdmi2;
3018         u32 d1grph = 0, d2grph = 0;
3019
3020         if (!rdev->irq.installed) {
3021                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3022                 return -EINVAL;
3023         }
3024         /* don't enable anything if the ih is disabled */
3025         if (!rdev->ih.enabled) {
3026                 r600_disable_interrupts(rdev);
3027                 /* force the active interrupt state to all disabled */
3028                 r600_disable_interrupt_state(rdev);
3029                 return 0;
3030         }
3031
3032         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3033         if (ASIC_IS_DCE3(rdev)) {
3034                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3035                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3036                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3037                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3039                 if (ASIC_IS_DCE32(rdev)) {
3040                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3041                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3042                 }
3043         } else {
3044                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3045                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3046                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3047                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3048         }
3049
3050         if (rdev->irq.sw_int) {
3051                 DRM_DEBUG("r600_irq_set: sw int\n");
3052                 cp_int_cntl |= RB_INT_ENABLE;
3053                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3054         }
3055         if (rdev->irq.crtc_vblank_int[0] ||
3056             rdev->irq.pflip[0]) {
3057                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3058                 mode_int |= D1MODE_VBLANK_INT_MASK;
3059         }
3060         if (rdev->irq.crtc_vblank_int[1] ||
3061             rdev->irq.pflip[1]) {
3062                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3063                 mode_int |= D2MODE_VBLANK_INT_MASK;
3064         }
3065         if (rdev->irq.hpd[0]) {
3066                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3067                 hpd1 |= DC_HPDx_INT_EN;
3068         }
3069         if (rdev->irq.hpd[1]) {
3070                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3071                 hpd2 |= DC_HPDx_INT_EN;
3072         }
3073         if (rdev->irq.hpd[2]) {
3074                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3075                 hpd3 |= DC_HPDx_INT_EN;
3076         }
3077         if (rdev->irq.hpd[3]) {
3078                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3079                 hpd4 |= DC_HPDx_INT_EN;
3080         }
3081         if (rdev->irq.hpd[4]) {
3082                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3083                 hpd5 |= DC_HPDx_INT_EN;
3084         }
3085         if (rdev->irq.hpd[5]) {
3086                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3087                 hpd6 |= DC_HPDx_INT_EN;
3088         }
3089         if (rdev->irq.hdmi[0]) {
3090                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3091                 hdmi1 |= R600_HDMI_INT_EN;
3092         }
3093         if (rdev->irq.hdmi[1]) {
3094                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3095                 hdmi2 |= R600_HDMI_INT_EN;
3096         }
3097         if (rdev->irq.gui_idle) {
3098                 DRM_DEBUG("gui idle\n");
3099                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3100         }
3101
3102         WREG32(CP_INT_CNTL, cp_int_cntl);
3103         WREG32(DxMODE_INT_MASK, mode_int);
3104         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3105         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3106         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3107         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3108         if (ASIC_IS_DCE3(rdev)) {
3109                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3110                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3111                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3112                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3113                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3114                 if (ASIC_IS_DCE32(rdev)) {
3115                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3116                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3117                 }
3118         } else {
3119                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3120                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3121                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3122                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3123         }
3124
3125         return 0;
3126 }
3127
3128 static inline void r600_irq_ack(struct radeon_device *rdev)
3129 {
3130         u32 tmp;
3131
3132         if (ASIC_IS_DCE3(rdev)) {
3133                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3134                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3135                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3136         } else {
3137                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3138                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3139                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3140         }
3141         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3142         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3143
3144         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3145                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3146         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3147                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3148         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3149                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3150         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3151                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3152         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3153                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3154         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3155                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3156         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3157                 if (ASIC_IS_DCE3(rdev)) {
3158                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3159                         tmp |= DC_HPDx_INT_ACK;
3160                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3161                 } else {
3162                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3163                         tmp |= DC_HPDx_INT_ACK;
3164                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3165                 }
3166         }
3167         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3168                 if (ASIC_IS_DCE3(rdev)) {
3169                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3170                         tmp |= DC_HPDx_INT_ACK;
3171                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3172                 } else {
3173                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3174                         tmp |= DC_HPDx_INT_ACK;
3175                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3176                 }
3177         }
3178         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3179                 if (ASIC_IS_DCE3(rdev)) {
3180                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3181                         tmp |= DC_HPDx_INT_ACK;
3182                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3183                 } else {
3184                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3185                         tmp |= DC_HPDx_INT_ACK;
3186                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3187                 }
3188         }
3189         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3190                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3191                 tmp |= DC_HPDx_INT_ACK;
3192                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3193         }
3194         if (ASIC_IS_DCE32(rdev)) {
3195                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3196                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3197                         tmp |= DC_HPDx_INT_ACK;
3198                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3199                 }
3200                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3201                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3202                         tmp |= DC_HPDx_INT_ACK;
3203                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3204                 }
3205         }
3206         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3207                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3208         }
3209         if (ASIC_IS_DCE3(rdev)) {
3210                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3211                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3212                 }
3213         } else {
3214                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3215                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3216                 }
3217         }
3218 }
3219
3220 void r600_irq_disable(struct radeon_device *rdev)
3221 {
3222         r600_disable_interrupts(rdev);
3223         /* Wait and acknowledge irq */
3224         mdelay(1);
3225         r600_irq_ack(rdev);
3226         r600_disable_interrupt_state(rdev);
3227 }
3228
3229 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3230 {
3231         u32 wptr, tmp;
3232
3233         if (rdev->wb.enabled)
3234                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3235         else
3236                 wptr = RREG32(IH_RB_WPTR);
3237
3238         if (wptr & RB_OVERFLOW) {
3239                 /* When a ring buffer overflow happen start parsing interrupt
3240                  * from the last not overwritten vector (wptr + 16). Hopefully
3241                  * this should allow us to catchup.
3242                  */
3243                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3244                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3245                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3246                 tmp = RREG32(IH_RB_CNTL);
3247                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3248                 WREG32(IH_RB_CNTL, tmp);
3249         }
3250         return (wptr & rdev->ih.ptr_mask);
3251 }
3252
3253 /*        r600 IV Ring
3254  * Each IV ring entry is 128 bits:
3255  * [7:0]    - interrupt source id
3256  * [31:8]   - reserved
3257  * [59:32]  - interrupt source data
3258  * [127:60]  - reserved
3259  *
3260  * The basic interrupt vector entries
3261  * are decoded as follows:
3262  * src_id  src_data  description
3263  *      1         0  D1 Vblank
3264  *      1         1  D1 Vline
3265  *      5         0  D2 Vblank
3266  *      5         1  D2 Vline
3267  *     19         0  FP Hot plug detection A
3268  *     19         1  FP Hot plug detection B
3269  *     19         2  DAC A auto-detection
3270  *     19         3  DAC B auto-detection
3271  *     21         4  HDMI block A
3272  *     21         5  HDMI block B
3273  *    176         -  CP_INT RB
3274  *    177         -  CP_INT IB1
3275  *    178         -  CP_INT IB2
3276  *    181         -  EOP Interrupt
3277  *    233         -  GUI Idle
3278  *
3279  * Note, these are based on r600 and may need to be
3280  * adjusted or added to on newer asics
3281  */
3282
3283 int r600_irq_process(struct radeon_device *rdev)
3284 {
3285         u32 wptr = r600_get_ih_wptr(rdev);
3286         u32 rptr = rdev->ih.rptr;
3287         u32 src_id, src_data;
3288         u32 ring_index;
3289         unsigned long flags;
3290         bool queue_hotplug = false;
3291
3292         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3293         if (!rdev->ih.enabled)
3294                 return IRQ_NONE;
3295
3296         spin_lock_irqsave(&rdev->ih.lock, flags);
3297
3298         if (rptr == wptr) {
3299                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3300                 return IRQ_NONE;
3301         }
3302         if (rdev->shutdown) {
3303                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3304                 return IRQ_NONE;
3305         }
3306
3307 restart_ih:
3308         /* display interrupts */
3309         r600_irq_ack(rdev);
3310
3311         rdev->ih.wptr = wptr;
3312         while (rptr != wptr) {
3313                 /* wptr/rptr are in bytes! */
3314                 ring_index = rptr / 4;
3315                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3316                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3317
3318                 switch (src_id) {
3319                 case 1: /* D1 vblank/vline */
3320                         switch (src_data) {
3321                         case 0: /* D1 vblank */
3322                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3323                                         if (rdev->irq.crtc_vblank_int[0]) {
3324                                                 drm_handle_vblank(rdev->ddev, 0);
3325                                                 rdev->pm.vblank_sync = true;
3326                                                 wake_up(&rdev->irq.vblank_queue);
3327                                         }
3328                                         if (rdev->irq.pflip[0])
3329                                                 radeon_crtc_handle_flip(rdev, 0);
3330                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3331                                         DRM_DEBUG("IH: D1 vblank\n");
3332                                 }
3333                                 break;
3334                         case 1: /* D1 vline */
3335                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3336                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3337                                         DRM_DEBUG("IH: D1 vline\n");
3338                                 }
3339                                 break;
3340                         default:
3341                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3342                                 break;
3343                         }
3344                         break;
3345                 case 5: /* D2 vblank/vline */
3346                         switch (src_data) {
3347                         case 0: /* D2 vblank */
3348                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3349                                         if (rdev->irq.crtc_vblank_int[1]) {
3350                                                 drm_handle_vblank(rdev->ddev, 1);
3351                                                 rdev->pm.vblank_sync = true;
3352                                                 wake_up(&rdev->irq.vblank_queue);
3353                                         }
3354                                         if (rdev->irq.pflip[1])
3355                                                 radeon_crtc_handle_flip(rdev, 1);
3356                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3357                                         DRM_DEBUG("IH: D2 vblank\n");
3358                                 }
3359                                 break;
3360                         case 1: /* D1 vline */
3361                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3362                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3363                                         DRM_DEBUG("IH: D2 vline\n");
3364                                 }
3365                                 break;
3366                         default:
3367                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3368                                 break;
3369                         }
3370                         break;
3371                 case 19: /* HPD/DAC hotplug */
3372                         switch (src_data) {
3373                         case 0:
3374                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3375                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3376                                         queue_hotplug = true;
3377                                         DRM_DEBUG("IH: HPD1\n");
3378                                 }
3379                                 break;
3380                         case 1:
3381                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3382                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3383                                         queue_hotplug = true;
3384                                         DRM_DEBUG("IH: HPD2\n");
3385                                 }
3386                                 break;
3387                         case 4:
3388                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3389                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3390                                         queue_hotplug = true;
3391                                         DRM_DEBUG("IH: HPD3\n");
3392                                 }
3393                                 break;
3394                         case 5:
3395                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3396                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3397                                         queue_hotplug = true;
3398                                         DRM_DEBUG("IH: HPD4\n");
3399                                 }
3400                                 break;
3401                         case 10:
3402                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3403                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3404                                         queue_hotplug = true;
3405                                         DRM_DEBUG("IH: HPD5\n");
3406                                 }
3407                                 break;
3408                         case 12:
3409                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3410                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3411                                         queue_hotplug = true;
3412                                         DRM_DEBUG("IH: HPD6\n");
3413                                 }
3414                                 break;
3415                         default:
3416                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3417                                 break;
3418                         }
3419                         break;
3420                 case 21: /* HDMI */
3421                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3422                         r600_audio_schedule_polling(rdev);
3423                         break;
3424                 case 176: /* CP_INT in ring buffer */
3425                 case 177: /* CP_INT in IB1 */
3426                 case 178: /* CP_INT in IB2 */
3427                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3428                         radeon_fence_process(rdev);
3429                         break;
3430                 case 181: /* CP EOP event */
3431                         DRM_DEBUG("IH: CP EOP\n");
3432                         radeon_fence_process(rdev);
3433                         break;
3434                 case 233: /* GUI IDLE */
3435                         DRM_DEBUG("IH: CP EOP\n");
3436                         rdev->pm.gui_idle = true;
3437                         wake_up(&rdev->irq.idle_queue);
3438                         break;
3439                 default:
3440                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3441                         break;
3442                 }
3443
3444                 /* wptr/rptr are in bytes! */
3445                 rptr += 16;
3446                 rptr &= rdev->ih.ptr_mask;
3447         }
3448         /* make sure wptr hasn't changed while processing */
3449         wptr = r600_get_ih_wptr(rdev);
3450         if (wptr != rdev->ih.wptr)
3451                 goto restart_ih;
3452         if (queue_hotplug)
3453                 schedule_work(&rdev->hotplug_work);
3454         rdev->ih.rptr = rptr;
3455         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3456         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3457         return IRQ_HANDLED;
3458 }
3459
3460 /*
3461  * Debugfs info
3462  */
3463 #if defined(CONFIG_DEBUG_FS)
3464
3465 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3466 {
3467         struct drm_info_node *node = (struct drm_info_node *) m->private;
3468         struct drm_device *dev = node->minor->dev;
3469         struct radeon_device *rdev = dev->dev_private;
3470         unsigned count, i, j;
3471
3472         radeon_ring_free_size(rdev);
3473         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3474         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3475         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3476         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3477         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3478         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3479         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3480         seq_printf(m, "%u dwords in ring\n", count);
3481         i = rdev->cp.rptr;
3482         for (j = 0; j <= count; j++) {
3483                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3484                 i = (i + 1) & rdev->cp.ptr_mask;
3485         }
3486         return 0;
3487 }
3488
3489 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3490 {
3491         struct drm_info_node *node = (struct drm_info_node *) m->private;
3492         struct drm_device *dev = node->minor->dev;
3493         struct radeon_device *rdev = dev->dev_private;
3494
3495         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3496         DREG32_SYS(m, rdev, VM_L2_STATUS);
3497         return 0;
3498 }
3499
3500 static struct drm_info_list r600_mc_info_list[] = {
3501         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3502         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3503 };
3504 #endif
3505
3506 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3507 {
3508 #if defined(CONFIG_DEBUG_FS)
3509         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3510 #else
3511         return 0;
3512 #endif
3513 }
3514
3515 /**
3516  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3517  * rdev: radeon device structure
3518  * bo: buffer object struct which userspace is waiting for idle
3519  *
3520  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3521  * through ring buffer, this leads to corruption in rendering, see
3522  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3523  * directly perform HDP flush by writing register through MMIO.
3524  */
3525 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3526 {
3527         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3528          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3529          * This seems to cause problems on some AGP cards. Just use the old
3530          * method for them.
3531          */
3532         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3533             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3534                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3535                 u32 tmp;
3536
3537                 WREG32(HDP_DEBUG1, 0);
3538                 tmp = readl((void __iomem *)ptr);
3539         } else
3540                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3541 }
3542
3543 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3544 {
3545         u32 link_width_cntl, mask, target_reg;
3546
3547         if (rdev->flags & RADEON_IS_IGP)
3548                 return;
3549
3550         if (!(rdev->flags & RADEON_IS_PCIE))
3551                 return;
3552
3553         /* x2 cards have a special sequence */
3554         if (ASIC_IS_X2(rdev))
3555                 return;
3556
3557         /* FIXME wait for idle */
3558
3559         switch (lanes) {
3560         case 0:
3561                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3562                 break;
3563         case 1:
3564                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3565                 break;
3566         case 2:
3567                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3568                 break;
3569         case 4:
3570                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3571                 break;
3572         case 8:
3573                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3574                 break;
3575         case 12:
3576                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3577                 break;
3578         case 16:
3579         default:
3580                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3581                 break;
3582         }
3583
3584         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3585
3586         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3587             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3588                 return;
3589
3590         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3591                 return;
3592
3593         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3594                              RADEON_PCIE_LC_RECONFIG_NOW |
3595                              R600_PCIE_LC_RENEGOTIATE_EN |
3596                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3597         link_width_cntl |= mask;
3598
3599         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3600
3601         /* some northbridges can renegotiate the link rather than requiring
3602          * a complete re-config.
3603          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3604          */
3605         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3606                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3607         else
3608                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3609
3610         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3611                                                        RADEON_PCIE_LC_RECONFIG_NOW));
3612
3613         if (rdev->family >= CHIP_RV770)
3614                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3615         else
3616                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3617
3618         /* wait for lane set to complete */
3619         link_width_cntl = RREG32(target_reg);
3620         while (link_width_cntl == 0xffffffff)
3621                 link_width_cntl = RREG32(target_reg);
3622
3623 }
3624
3625 int r600_get_pcie_lanes(struct radeon_device *rdev)
3626 {
3627         u32 link_width_cntl;
3628
3629         if (rdev->flags & RADEON_IS_IGP)
3630                 return 0;
3631
3632         if (!(rdev->flags & RADEON_IS_PCIE))
3633                 return 0;
3634
3635         /* x2 cards have a special sequence */
3636         if (ASIC_IS_X2(rdev))
3637                 return 0;
3638
3639         /* FIXME wait for idle */
3640
3641         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3642
3643         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3644         case RADEON_PCIE_LC_LINK_WIDTH_X0:
3645                 return 0;
3646         case RADEON_PCIE_LC_LINK_WIDTH_X1:
3647                 return 1;
3648         case RADEON_PCIE_LC_LINK_WIDTH_X2:
3649                 return 2;
3650         case RADEON_PCIE_LC_LINK_WIDTH_X4:
3651                 return 4;
3652         case RADEON_PCIE_LC_LINK_WIDTH_X8:
3653                 return 8;
3654         case RADEON_PCIE_LC_LINK_WIDTH_X16:
3655         default:
3656                 return 16;
3657         }
3658 }
3659
3660 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3661 {
3662         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3663         u16 link_cntl2;
3664
3665         if (radeon_pcie_gen2 == 0)
3666                 return;
3667
3668         if (rdev->flags & RADEON_IS_IGP)
3669                 return;
3670
3671         if (!(rdev->flags & RADEON_IS_PCIE))
3672                 return;
3673
3674         /* x2 cards have a special sequence */
3675         if (ASIC_IS_X2(rdev))
3676                 return;
3677
3678         /* only RV6xx+ chips are supported */
3679         if (rdev->family <= CHIP_R600)
3680                 return;
3681
3682         /* 55 nm r6xx asics */
3683         if ((rdev->family == CHIP_RV670) ||
3684             (rdev->family == CHIP_RV620) ||
3685             (rdev->family == CHIP_RV635)) {
3686                 /* advertise upconfig capability */
3687                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3688                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3689                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3690                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3691                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3692                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3693                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3694                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
3695                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3696                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3697                 } else {
3698                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3699                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3700                 }
3701         }
3702
3703         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3704         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3705             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3706
3707                 /* 55 nm r6xx asics */
3708                 if ((rdev->family == CHIP_RV670) ||
3709                     (rdev->family == CHIP_RV620) ||
3710                     (rdev->family == CHIP_RV635)) {
3711                         WREG32(MM_CFGREGS_CNTL, 0x8);
3712                         link_cntl2 = RREG32(0x4088);
3713                         WREG32(MM_CFGREGS_CNTL, 0);
3714                         /* not supported yet */
3715                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3716                                 return;
3717                 }
3718
3719                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3720                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3721                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3722                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3723                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3724                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3725
3726                 tmp = RREG32(0x541c);
3727                 WREG32(0x541c, tmp | 0x8);
3728                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3729                 link_cntl2 = RREG16(0x4088);
3730                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3731                 link_cntl2 |= 0x2;
3732                 WREG16(0x4088, link_cntl2);
3733                 WREG32(MM_CFGREGS_CNTL, 0);
3734
3735                 if ((rdev->family == CHIP_RV670) ||
3736                     (rdev->family == CHIP_RV620) ||
3737                     (rdev->family == CHIP_RV635)) {
3738                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3739                         training_cntl &= ~LC_POINT_7_PLUS_EN;
3740                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3741                 } else {
3742                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3743                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3744                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3745                 }
3746
3747                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3748                 speed_cntl |= LC_GEN2_EN_STRAP;
3749                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3750
3751         } else {
3752                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3753                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3754                 if (1)
3755                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3756                 else
3757                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3758                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3759         }
3760 }