drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 /* get temperature in millidegrees */
  96 u32 rv6xx_get_temp(struct radeon_device *rdev)
  97 {
  98         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
  99                 ASIC_T_SHIFT;
 100
 101         return temp * 1000;
 102 }
 103
 104 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 105 {
 106         int i;
 107
 108         rdev->pm.dynpm_can_upclock = true;
 109         rdev->pm.dynpm_can_downclock = true;
 110
 111         /* power state array is low to high, default is first */
 112         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 113                 int min_power_state_index = 0;
 114
 115                 if (rdev->pm.num_power_states > 2)
 116                         min_power_state_index = 1;
 117
 118                 switch (rdev->pm.dynpm_planned_action) {
 119                 case DYNPM_ACTION_MINIMUM:
 120                         rdev->pm.requested_power_state_index = min_power_state_index;
 121                         rdev->pm.requested_clock_mode_index = 0;
 122                         rdev->pm.dynpm_can_downclock = false;
 123                         break;
 124                 case DYNPM_ACTION_DOWNCLOCK:
 125                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 126                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 127                                 rdev->pm.dynpm_can_downclock = false;
 128                         } else {
 129                                 if (rdev->pm.active_crtc_count > 1) {
 130                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 131                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 132                                                         continue;
 133                                                 else if (i >= rdev->pm.current_power_state_index) {
 134                                                         rdev->pm.requested_power_state_index =
 135                                                                 rdev->pm.current_power_state_index;
 136                                                         break;
 137                                                 } else {
 138                                                         rdev->pm.requested_power_state_index = i;
 139                                                         break;
 140                                                 }
 141                                         }
 142                                 } else {
 143                                         if (rdev->pm.current_power_state_index == 0)
 144                                                 rdev->pm.requested_power_state_index =
 145                                                         rdev->pm.num_power_states - 1;
 146                                         else
 147                                                 rdev->pm.requested_power_state_index =
 148                                                         rdev->pm.current_power_state_index - 1;
 149                                 }
 150                         }
 151                         rdev->pm.requested_clock_mode_index = 0;
 152                         /* don't use the power state if crtcs are active and no display flag is set */
 153                         if ((rdev->pm.active_crtc_count > 0) &&
 154                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 155                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 156                              RADEON_PM_MODE_NO_DISPLAY)) {
 157                                 rdev->pm.requested_power_state_index++;
 158                         }
 159                         break;
 160                 case DYNPM_ACTION_UPCLOCK:
 161                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 162                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 163                                 rdev->pm.dynpm_can_upclock = false;
 164                         } else {
 165                                 if (rdev->pm.active_crtc_count > 1) {
 166                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 167                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 168                                                         continue;
 169                                                 else if (i <= rdev->pm.current_power_state_index) {
 170                                                         rdev->pm.requested_power_state_index =
 171                                                                 rdev->pm.current_power_state_index;
 172                                                         break;
 173                                                 } else {
 174                                                         rdev->pm.requested_power_state_index = i;
 175                                                         break;
 176                                                 }
 177                                         }
 178                                 } else
 179                                         rdev->pm.requested_power_state_index =
 180                                                 rdev->pm.current_power_state_index + 1;
 181                         }
 182                         rdev->pm.requested_clock_mode_index = 0;
 183                         break;
 184                 case DYNPM_ACTION_DEFAULT:
 185                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 186                         rdev->pm.requested_clock_mode_index = 0;
 187                         rdev->pm.dynpm_can_upclock = false;
 188                         break;
 189                 case DYNPM_ACTION_NONE:
 190                 default:
 191                         DRM_ERROR("Requested mode for not defined action\n");
 192                         return;
 193                 }
 194         } else {
 195                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 196                 /* for now just select the first power state and switch between clock modes */
 197                 /* power state array is low to high, default is first (0) */
 198                 if (rdev->pm.active_crtc_count > 1) {
 199                         rdev->pm.requested_power_state_index = -1;
 200                         /* start at 1 as we don't want the default mode */
 201                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 202                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 203                                         continue;
 204                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 205                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 206                                         rdev->pm.requested_power_state_index = i;
 207                                         break;
 208                                 }
 209                         }
 210                         /* if nothing selected, grab the default state. */
 211                         if (rdev->pm.requested_power_state_index == -1)
 212                                 rdev->pm.requested_power_state_index = 0;
 213                 } else
 214                         rdev->pm.requested_power_state_index = 1;
 215
 216                 switch (rdev->pm.dynpm_planned_action) {
 217                 case DYNPM_ACTION_MINIMUM:
 218                         rdev->pm.requested_clock_mode_index = 0;
 219                         rdev->pm.dynpm_can_downclock = false;
 220                         break;
 221                 case DYNPM_ACTION_DOWNCLOCK:
 222                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 223                                 if (rdev->pm.current_clock_mode_index == 0) {
 224                                         rdev->pm.requested_clock_mode_index = 0;
 225                                         rdev->pm.dynpm_can_downclock = false;
 226                                 } else
 227                                         rdev->pm.requested_clock_mode_index =
 228                                                 rdev->pm.current_clock_mode_index - 1;
 229                         } else {
 230                                 rdev->pm.requested_clock_mode_index = 0;
 231                                 rdev->pm.dynpm_can_downclock = false;
 232                         }
 233                         /* don't use the power state if crtcs are active and no display flag is set */
 234                         if ((rdev->pm.active_crtc_count > 0) &&
 235                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 236                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 237                              RADEON_PM_MODE_NO_DISPLAY)) {
 238                                 rdev->pm.requested_clock_mode_index++;
 239                         }
 240                         break;
 241                 case DYNPM_ACTION_UPCLOCK:
 242                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 243                                 if (rdev->pm.current_clock_mode_index ==
 244                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 245                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 246                                         rdev->pm.dynpm_can_upclock = false;
 247                                 } else
 248                                         rdev->pm.requested_clock_mode_index =
 249                                                 rdev->pm.current_clock_mode_index + 1;
 250                         } else {
 251                                 rdev->pm.requested_clock_mode_index =
 252                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 253                                 rdev->pm.dynpm_can_upclock = false;
 254                         }
 255                         break;
 256                 case DYNPM_ACTION_DEFAULT:
 257                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 258                         rdev->pm.requested_clock_mode_index = 0;
 259                         rdev->pm.dynpm_can_upclock = false;
 260                         break;
 261                 case DYNPM_ACTION_NONE:
 262                 default:
 263                         DRM_ERROR("Requested mode for not defined action\n");
 264                         return;
 265                 }
 266         }
 267
 268         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 269                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 270                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 271                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 272                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 273                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 274                   pcie_lanes);
 275 }
 276
 277 static int r600_pm_get_type_index(struct radeon_device *rdev,
 278                                   enum radeon_pm_state_type ps_type,
 279                                   int instance)
 280 {
 281         int i;
 282         int found_instance = -1;
 283
 284         for (i = 0; i < rdev->pm.num_power_states; i++) {
 285                 if (rdev->pm.power_state[i].type == ps_type) {
 286                         found_instance++;
 287                         if (found_instance == instance)
 288                                 return i;
 289                 }
 290         }
 291         /* return default if no match */
 292         return rdev->pm.default_power_state_index;
 293 }
 294
 295 void rs780_pm_init_profile(struct radeon_device *rdev)
 296 {
 297         if (rdev->pm.num_power_states == 2) {
 298                 /* default */
 299                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 300                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 301                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 303                 /* low sh */
 304                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 305                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 306                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 308                 /* mid sh */
 309                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 310                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 313                 /* high sh */
 314                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 316                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 318                 /* low mh */
 319                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 322                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 323                 /* mid mh */
 324                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 328                 /* high mh */
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 331                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 332                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 333         } else if (rdev->pm.num_power_states == 3) {
 334                 /* default */
 335                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 336                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 337                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 339                 /* low sh */
 340                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 341                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 342                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 343                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 344                 /* mid sh */
 345                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 346                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 348                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 349                 /* high sh */
 350                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 351                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 352                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 353                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 354                 /* low mh */
 355                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 356                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 357                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 358                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 359                 /* mid mh */
 360                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 361                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 362                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 363                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 364                 /* high mh */
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 366                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 367                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 368                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 369         } else {
 370                 /* default */
 371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 372                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 373                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 374                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 375                 /* low sh */
 376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 377                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 378                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 379                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 380                 /* mid sh */
 381                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 382                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 384                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 385                 /* high sh */
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 387                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 388                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 389                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 390                 /* low mh */
 391                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 392                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 393                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 394                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 395                 /* mid mh */
 396                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 397                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 398                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 399                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 400                 /* high mh */
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 402                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 403                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 404                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 405         }
 406 }
 407
 408 void r600_pm_init_profile(struct radeon_device *rdev)
 409 {
 410         if (rdev->family == CHIP_R600) {
 411                 /* XXX */
 412                 /* default */
 413                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 414                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 415                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 416                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 417                 /* low sh */
 418                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 419                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 421                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 422                 /* mid sh */
 423                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 426                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 427                 /* high sh */
 428                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 431                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 432                 /* low mh */
 433                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 436                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 437                 /* mid mh */
 438                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 441                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 442                 /* high mh */
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 446                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 447         } else {
 448                 if (rdev->pm.num_power_states < 4) {
 449                         /* default */
 450                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 451                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 452                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 453                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 454                         /* low sh */
 455                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 456                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 457                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 458                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 459                         /* mid sh */
 460                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 461                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 462                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 463                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 464                         /* high sh */
 465                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 467                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 468                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 469                         /* low mh */
 470                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 472                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 473                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 474                         /* low mh */
 475                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 476                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 477                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 478                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 479                         /* high mh */
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 482                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 483                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 484                 } else {
 485                         /* default */
 486                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 487                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 488                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 489                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 490                         /* low sh */
 491                         if (rdev->flags & RADEON_IS_MOBILITY) {
 492                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 493                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 494                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 495                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 496                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 497                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 498                         } else {
 499                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 500                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 501                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 502                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 503                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 504                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 505                         }
 506                         /* mid sh */
 507                         if (rdev->flags & RADEON_IS_MOBILITY) {
 508                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 509                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 510                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 511                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 512                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 513                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 514                         } else {
 515                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 516                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 517                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 518                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 519                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 520                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 521                         }
 522                         /* high sh */
 523                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 524                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 525                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 526                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 527                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 529                         /* low mh */
 530                         if (rdev->flags & RADEON_IS_MOBILITY) {
 531                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 532                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 533                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 534                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 535                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 536                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 537                         } else {
 538                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 539                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 540                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 541                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 542                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 543                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 544                         }
 545                         /* mid mh */
 546                         if (rdev->flags & RADEON_IS_MOBILITY) {
 547                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 548                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 549                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 550                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 551                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 552                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 553                         } else {
 554                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 555                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 556                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 557                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 558                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 559                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 560                         }
 561                         /* high mh */
 562                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 563                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 564                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 565                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 566                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 567                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 568                 }
 569         }
 570 }
 571
 572 void r600_pm_misc(struct radeon_device *rdev)
 573 {
 574         int req_ps_idx = rdev->pm.requested_power_state_index;
 575         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 576         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 577         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 578
 579         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 580                 if (voltage->voltage != rdev->pm.current_vddc) {
 581                         radeon_atom_set_voltage(rdev, voltage->voltage);
 582                         rdev->pm.current_vddc = voltage->voltage;
 583                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 584                 }
 585         }
 586 }
 587
 588 bool r600_gui_idle(struct radeon_device *rdev)
 589 {
 590         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 591                 return false;
 592         else
 593                 return true;
 594 }
 595
 596 /* hpd for digital panel detect/disconnect */
 597 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 598 {
 599         bool connected = false;
 600
 601         if (ASIC_IS_DCE3(rdev)) {
 602                 switch (hpd) {
 603                 case RADEON_HPD_1:
 604                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 605                                 connected = true;
 606                         break;
 607                 case RADEON_HPD_2:
 608                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 609                                 connected = true;
 610                         break;
 611                 case RADEON_HPD_3:
 612                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 613                                 connected = true;
 614                         break;
 615                 case RADEON_HPD_4:
 616                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 617                                 connected = true;
 618                         break;
 619                         /* DCE 3.2 */
 620                 case RADEON_HPD_5:
 621                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 622                                 connected = true;
 623                         break;
 624                 case RADEON_HPD_6:
 625                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 626                                 connected = true;
 627                         break;
 628                 default:
 629                         break;
 630                 }
 631         } else {
 632                 switch (hpd) {
 633                 case RADEON_HPD_1:
 634                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 635                                 connected = true;
 636                         break;
 637                 case RADEON_HPD_2:
 638                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 639                                 connected = true;
 640                         break;
 641                 case RADEON_HPD_3:
 642                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 643                                 connected = true;
 644                         break;
 645                 default:
 646                         break;
 647                 }
 648         }
 649         return connected;
 650 }
 651
 652 void r600_hpd_set_polarity(struct radeon_device *rdev,
 653                            enum radeon_hpd_id hpd)
 654 {
 655         u32 tmp;
 656         bool connected = r600_hpd_sense(rdev, hpd);
 657
 658         if (ASIC_IS_DCE3(rdev)) {
 659                 switch (hpd) {
 660                 case RADEON_HPD_1:
 661                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 662                         if (connected)
 663                                 tmp &= ~DC_HPDx_INT_POLARITY;
 664                         else
 665                                 tmp |= DC_HPDx_INT_POLARITY;
 666                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 667                         break;
 668                 case RADEON_HPD_2:
 669                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 670                         if (connected)
 671                                 tmp &= ~DC_HPDx_INT_POLARITY;
 672                         else
 673                                 tmp |= DC_HPDx_INT_POLARITY;
 674                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 675                         break;
 676                 case RADEON_HPD_3:
 677                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 678                         if (connected)
 679                                 tmp &= ~DC_HPDx_INT_POLARITY;
 680                         else
 681                                 tmp |= DC_HPDx_INT_POLARITY;
 682                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 683                         break;
 684                 case RADEON_HPD_4:
 685                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 686                         if (connected)
 687                                 tmp &= ~DC_HPDx_INT_POLARITY;
 688                         else
 689                                 tmp |= DC_HPDx_INT_POLARITY;
 690                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 691                         break;
 692                 case RADEON_HPD_5:
 693                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 694                         if (connected)
 695                                 tmp &= ~DC_HPDx_INT_POLARITY;
 696                         else
 697                                 tmp |= DC_HPDx_INT_POLARITY;
 698                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 699                         break;
 700                         /* DCE 3.2 */
 701                 case RADEON_HPD_6:
 702                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 703                         if (connected)
 704                                 tmp &= ~DC_HPDx_INT_POLARITY;
 705                         else
 706                                 tmp |= DC_HPDx_INT_POLARITY;
 707                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 708                         break;
 709                 default:
 710                         break;
 711                 }
 712         } else {
 713                 switch (hpd) {
 714                 case RADEON_HPD_1:
 715                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 716                         if (connected)
 717                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 718                         else
 719                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 720                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 721                         break;
 722                 case RADEON_HPD_2:
 723                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 724                         if (connected)
 725                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 726                         else
 727                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 728                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 729                         break;
 730                 case RADEON_HPD_3:
 731                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 732                         if (connected)
 733                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 734                         else
 735                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 736                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 737                         break;
 738                 default:
 739                         break;
 740                 }
 741         }
 742 }
 743
 744 void r600_hpd_init(struct radeon_device *rdev)
 745 {
 746         struct drm_device *dev = rdev->ddev;
 747         struct drm_connector *connector;
 748
 749         if (ASIC_IS_DCE3(rdev)) {
 750                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 751                 if (ASIC_IS_DCE32(rdev))
 752                         tmp |= DC_HPDx_EN;
 753
 754                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 755                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 756                         switch (radeon_connector->hpd.hpd) {
 757                         case RADEON_HPD_1:
 758                                 WREG32(DC_HPD1_CONTROL, tmp);
 759                                 rdev->irq.hpd[0] = true;
 760                                 break;
 761                         case RADEON_HPD_2:
 762                                 WREG32(DC_HPD2_CONTROL, tmp);
 763                                 rdev->irq.hpd[1] = true;
 764                                 break;
 765                         case RADEON_HPD_3:
 766                                 WREG32(DC_HPD3_CONTROL, tmp);
 767                                 rdev->irq.hpd[2] = true;
 768                                 break;
 769                         case RADEON_HPD_4:
 770                                 WREG32(DC_HPD4_CONTROL, tmp);
 771                                 rdev->irq.hpd[3] = true;
 772                                 break;
 773                                 /* DCE 3.2 */
 774                         case RADEON_HPD_5:
 775                                 WREG32(DC_HPD5_CONTROL, tmp);
 776                                 rdev->irq.hpd[4] = true;
 777                                 break;
 778                         case RADEON_HPD_6:
 779                                 WREG32(DC_HPD6_CONTROL, tmp);
 780                                 rdev->irq.hpd[5] = true;
 781                                 break;
 782                         default:
 783                                 break;
 784                         }
 785                 }
 786         } else {
 787                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 788                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 789                         switch (radeon_connector->hpd.hpd) {
 790                         case RADEON_HPD_1:
 791                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 792                                 rdev->irq.hpd[0] = true;
 793                                 break;
 794                         case RADEON_HPD_2:
 795                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 796                                 rdev->irq.hpd[1] = true;
 797                                 break;
 798                         case RADEON_HPD_3:
 799                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 800                                 rdev->irq.hpd[2] = true;
 801                                 break;
 802                         default:
 803                                 break;
 804                         }
 805                 }
 806         }
 807         if (rdev->irq.installed)
 808                 r600_irq_set(rdev);
 809 }
 810
 811 void r600_hpd_fini(struct radeon_device *rdev)
 812 {
 813         struct drm_device *dev = rdev->ddev;
 814         struct drm_connector *connector;
 815
 816         if (ASIC_IS_DCE3(rdev)) {
 817                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 818                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 819                         switch (radeon_connector->hpd.hpd) {
 820                         case RADEON_HPD_1:
 821                                 WREG32(DC_HPD1_CONTROL, 0);
 822                                 rdev->irq.hpd[0] = false;
 823                                 break;
 824                         case RADEON_HPD_2:
 825                                 WREG32(DC_HPD2_CONTROL, 0);
 826                                 rdev->irq.hpd[1] = false;
 827                                 break;
 828                         case RADEON_HPD_3:
 829                                 WREG32(DC_HPD3_CONTROL, 0);
 830                                 rdev->irq.hpd[2] = false;
 831                                 break;
 832                         case RADEON_HPD_4:
 833                                 WREG32(DC_HPD4_CONTROL, 0);
 834                                 rdev->irq.hpd[3] = false;
 835                                 break;
 836                                 /* DCE 3.2 */
 837                         case RADEON_HPD_5:
 838                                 WREG32(DC_HPD5_CONTROL, 0);
 839                                 rdev->irq.hpd[4] = false;
 840                                 break;
 841                         case RADEON_HPD_6:
 842                                 WREG32(DC_HPD6_CONTROL, 0);
 843                                 rdev->irq.hpd[5] = false;
 844                                 break;
 845                         default:
 846                                 break;
 847                         }
 848                 }
 849         } else {
 850                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 851                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 852                         switch (radeon_connector->hpd.hpd) {
 853                         case RADEON_HPD_1:
 854                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 855                                 rdev->irq.hpd[0] = false;
 856                                 break;
 857                         case RADEON_HPD_2:
 858                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 859                                 rdev->irq.hpd[1] = false;
 860                                 break;
 861                         case RADEON_HPD_3:
 862                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 863                                 rdev->irq.hpd[2] = false;
 864                                 break;
 865                         default:
 866                                 break;
 867                         }
 868                 }
 869         }
 870 }
 871
 872 /*
 873  * R600 PCIE GART
 874  */
 875 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 876 {
 877         unsigned i;
 878         u32 tmp;
 879
 880         /* flush hdp cache so updates hit vram */
 881         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
 882                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 883                 u32 tmp;
 884
 885                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 886                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 887                  */
 888                 WREG32(HDP_DEBUG1, 0);
 889                 tmp = readl((void __iomem *)ptr);
 890         } else
 891                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 892
 893         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 894         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 895         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 896         for (i = 0; i < rdev->usec_timeout; i++) {
 897                 /* read MC_STATUS */
 898                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 899                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 900                 if (tmp == 2) {
 901                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 902                         return;
 903                 }
 904                 if (tmp) {
 905                         return;
 906                 }
 907                 udelay(1);
 908         }
 909 }
 910
 911 int r600_pcie_gart_init(struct radeon_device *rdev)
 912 {
 913         int r;
 914
 915         if (rdev->gart.table.vram.robj) {
 916                 WARN(1, "R600 PCIE GART already initialized\n");
 917                 return 0;
 918         }
 919         /* Initialize common gart structure */
 920         r = radeon_gart_init(rdev);
 921         if (r)
 922                 return r;
 923         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 924         return radeon_gart_table_vram_alloc(rdev);
 925 }
 926
 927 int r600_pcie_gart_enable(struct radeon_device *rdev)
 928 {
 929         u32 tmp;
 930         int r, i;
 931
 932         if (rdev->gart.table.vram.robj == NULL) {
 933                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 934                 return -EINVAL;
 935         }
 936         r = radeon_gart_table_vram_pin(rdev);
 937         if (r)
 938                 return r;
 939         radeon_gart_restore(rdev);
 940
 941         /* Setup L2 cache */
 942         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 943                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 944                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 945         WREG32(VM_L2_CNTL2, 0);
 946         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 947         /* Setup TLB control */
 948         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 949                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 950                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 951                 ENABLE_WAIT_L2_QUERY;
 952         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 953         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 954         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 955         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 956         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 957         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 958         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 961         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 965         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 966         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 967         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 968         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 969         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 970                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 971         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 972                         (u32)(rdev->dummy_page.addr >> 12));
 973         for (i = 1; i < 7; i++)
 974                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 975
 976         r600_pcie_gart_tlb_flush(rdev);
 977         rdev->gart.ready = true;
 978         return 0;
 979 }
 980
 981 void r600_pcie_gart_disable(struct radeon_device *rdev)
 982 {
 983         u32 tmp;
 984         int i, r;
 985
 986         /* Disable all tables */
 987         for (i = 0; i < 7; i++)
 988                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 989
 990         /* Disable L2 cache */
 991         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 992                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 993         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 994         /* Setup L1 TLB control */
 995         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 996                 ENABLE_WAIT_L2_QUERY;
 997         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 998         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 999         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1000         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1001         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1002         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1003         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1011         if (rdev->gart.table.vram.robj) {
1012                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1013                 if (likely(r == 0)) {
1014                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1015                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1016                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1017                 }
1018         }
1019 }
1020
1021 void r600_pcie_gart_fini(struct radeon_device *rdev)
1022 {
1023         radeon_gart_fini(rdev);
1024         r600_pcie_gart_disable(rdev);
1025         radeon_gart_table_vram_free(rdev);
1026 }
1027
1028 void r600_agp_enable(struct radeon_device *rdev)
1029 {
1030         u32 tmp;
1031         int i;
1032
1033         /* Setup L2 cache */
1034         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1035                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1036                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1037         WREG32(VM_L2_CNTL2, 0);
1038         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1039         /* Setup TLB control */
1040         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1041                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1042                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1043                 ENABLE_WAIT_L2_QUERY;
1044         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1045         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1046         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1047         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1048         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1049         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1050         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1053         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1054         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1055         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1057         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1058         for (i = 0; i < 7; i++)
1059                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1060 }
1061
1062 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1063 {
1064         unsigned i;
1065         u32 tmp;
1066
1067         for (i = 0; i < rdev->usec_timeout; i++) {
1068                 /* read MC_STATUS */
1069                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1070                 if (!tmp)
1071                         return 0;
1072                 udelay(1);
1073         }
1074         return -1;
1075 }
1076
1077 static void r600_mc_program(struct radeon_device *rdev)
1078 {
1079         struct rv515_mc_save save;
1080         u32 tmp;
1081         int i, j;
1082
1083         /* Initialize HDP */
1084         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1085                 WREG32((0x2c14 + j), 0x00000000);
1086                 WREG32((0x2c18 + j), 0x00000000);
1087                 WREG32((0x2c1c + j), 0x00000000);
1088                 WREG32((0x2c20 + j), 0x00000000);
1089                 WREG32((0x2c24 + j), 0x00000000);
1090         }
1091         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1092
1093         rv515_mc_stop(rdev, &save);
1094         if (r600_mc_wait_for_idle(rdev)) {
1095                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1096         }
1097         /* Lockout access through VGA aperture (doesn't exist before R600) */
1098         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1099         /* Update configuration */
1100         if (rdev->flags & RADEON_IS_AGP) {
1101                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1102                         /* VRAM before AGP */
1103                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1104                                 rdev->mc.vram_start >> 12);
1105                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1106                                 rdev->mc.gtt_end >> 12);
1107                 } else {
1108                         /* VRAM after AGP */
1109                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1110                                 rdev->mc.gtt_start >> 12);
1111                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112                                 rdev->mc.vram_end >> 12);
1113                 }
1114         } else {
1115                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1116                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1117         }
1118         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1119         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1120         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1121         WREG32(MC_VM_FB_LOCATION, tmp);
1122         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1123         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1124         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1125         if (rdev->flags & RADEON_IS_AGP) {
1126                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1127                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1128                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1129         } else {
1130                 WREG32(MC_VM_AGP_BASE, 0);
1131                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1132                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1133         }
1134         if (r600_mc_wait_for_idle(rdev)) {
1135                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1136         }
1137         rv515_mc_resume(rdev, &save);
1138         /* we need to own VRAM, so turn off the VGA renderer here
1139          * to stop it overwriting our objects */
1140         rv515_vga_render_disable(rdev);
1141 }
1142
1143 /**
1144  * r600_vram_gtt_location - try to find VRAM & GTT location
1145  * @rdev: radeon device structure holding all necessary informations
1146  * @mc: memory controller structure holding memory informations
1147  *
1148  * Function will place try to place VRAM at same place as in CPU (PCI)
1149  * address space as some GPU seems to have issue when we reprogram at
1150  * different address space.
1151  *
1152  * If there is not enough space to fit the unvisible VRAM after the
1153  * aperture then we limit the VRAM size to the aperture.
1154  *
1155  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1156  * them to be in one from GPU point of view so that we can program GPU to
1157  * catch access outside them (weird GPU policy see ??).
1158  *
1159  * This function will never fails, worst case are limiting VRAM or GTT.
1160  *
1161  * Note: GTT start, end, size should be initialized before calling this
1162  * function on AGP platform.
1163  */
1164 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1165 {
1166         u64 size_bf, size_af;
1167
1168         if (mc->mc_vram_size > 0xE0000000) {
1169                 /* leave room for at least 512M GTT */
1170                 dev_warn(rdev->dev, "limiting VRAM\n");
1171                 mc->real_vram_size = 0xE0000000;
1172                 mc->mc_vram_size = 0xE0000000;
1173         }
1174         if (rdev->flags & RADEON_IS_AGP) {
1175                 size_bf = mc->gtt_start;
1176                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1177                 if (size_bf > size_af) {
1178                         if (mc->mc_vram_size > size_bf) {
1179                                 dev_warn(rdev->dev, "limiting VRAM\n");
1180                                 mc->real_vram_size = size_bf;
1181                                 mc->mc_vram_size = size_bf;
1182                         }
1183                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1184                 } else {
1185                         if (mc->mc_vram_size > size_af) {
1186                                 dev_warn(rdev->dev, "limiting VRAM\n");
1187                                 mc->real_vram_size = size_af;
1188                                 mc->mc_vram_size = size_af;
1189                         }
1190                         mc->vram_start = mc->gtt_end;
1191                 }
1192                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1193                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1194                                 mc->mc_vram_size >> 20, mc->vram_start,
1195                                 mc->vram_end, mc->real_vram_size >> 20);
1196         } else {
1197                 u64 base = 0;
1198                 if (rdev->flags & RADEON_IS_IGP)
1199                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1200                 radeon_vram_location(rdev, &rdev->mc, base);
1201                 rdev->mc.gtt_base_align = 0;
1202                 radeon_gtt_location(rdev, mc);
1203         }
1204 }
1205
1206 int r600_mc_init(struct radeon_device *rdev)
1207 {
1208         u32 tmp;
1209         int chansize, numchan;
1210
1211         /* Get VRAM informations */
1212         rdev->mc.vram_is_ddr = true;
1213         tmp = RREG32(RAMCFG);
1214         if (tmp & CHANSIZE_OVERRIDE) {
1215                 chansize = 16;
1216         } else if (tmp & CHANSIZE_MASK) {
1217                 chansize = 64;
1218         } else {
1219                 chansize = 32;
1220         }
1221         tmp = RREG32(CHMAP);
1222         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1223         case 0:
1224         default:
1225                 numchan = 1;
1226                 break;
1227         case 1:
1228                 numchan = 2;
1229                 break;
1230         case 2:
1231                 numchan = 4;
1232                 break;
1233         case 3:
1234                 numchan = 8;
1235                 break;
1236         }
1237         rdev->mc.vram_width = numchan * chansize;
1238         /* Could aper size report 0 ? */
1239         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1240         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1241         /* Setup GPU memory space */
1242         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1243         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1244         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1245         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1246         r600_vram_gtt_location(rdev, &rdev->mc);
1247
1248         if (rdev->flags & RADEON_IS_IGP) {
1249                 rs690_pm_info(rdev);
1250                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1251         }
1252         radeon_update_bandwidth_info(rdev);
1253         return 0;
1254 }
1255
1256 /* We doesn't check that the GPU really needs a reset we simply do the
1257  * reset, it's up to the caller to determine if the GPU needs one. We
1258  * might add an helper function to check that.
1259  */
1260 int r600_gpu_soft_reset(struct radeon_device *rdev)
1261 {
1262         struct rv515_mc_save save;
1263         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1264                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1265                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1266                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1267                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1268                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1269                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1270                                 S_008010_GUI_ACTIVE(1);
1271         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1272                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1273                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1274                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1275                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1276                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1277                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1278                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1279         u32 tmp;
1280
1281         dev_info(rdev->dev, "GPU softreset \n");
1282         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1283                 RREG32(R_008010_GRBM_STATUS));
1284         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1285                 RREG32(R_008014_GRBM_STATUS2));
1286         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1287                 RREG32(R_000E50_SRBM_STATUS));
1288         rv515_mc_stop(rdev, &save);
1289         if (r600_mc_wait_for_idle(rdev)) {
1290                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1291         }
1292         /* Disable CP parsing/prefetching */
1293         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1294         /* Check if any of the rendering block is busy and reset it */
1295         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1296             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1297                 tmp = S_008020_SOFT_RESET_CR(1) |
1298                         S_008020_SOFT_RESET_DB(1) |
1299                         S_008020_SOFT_RESET_CB(1) |
1300                         S_008020_SOFT_RESET_PA(1) |
1301                         S_008020_SOFT_RESET_SC(1) |
1302                         S_008020_SOFT_RESET_SMX(1) |
1303                         S_008020_SOFT_RESET_SPI(1) |
1304                         S_008020_SOFT_RESET_SX(1) |
1305                         S_008020_SOFT_RESET_SH(1) |
1306                         S_008020_SOFT_RESET_TC(1) |
1307                         S_008020_SOFT_RESET_TA(1) |
1308                         S_008020_SOFT_RESET_VC(1) |
1309                         S_008020_SOFT_RESET_VGT(1);
1310                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1311                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1312                 RREG32(R_008020_GRBM_SOFT_RESET);
1313                 mdelay(15);
1314                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1315         }
1316         /* Reset CP (we always reset CP) */
1317         tmp = S_008020_SOFT_RESET_CP(1);
1318         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1319         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1320         RREG32(R_008020_GRBM_SOFT_RESET);
1321         mdelay(15);
1322         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1323         /* Wait a little for things to settle down */
1324         mdelay(1);
1325         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1326                 RREG32(R_008010_GRBM_STATUS));
1327         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1328                 RREG32(R_008014_GRBM_STATUS2));
1329         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1330                 RREG32(R_000E50_SRBM_STATUS));
1331         rv515_mc_resume(rdev, &save);
1332         return 0;
1333 }
1334
1335 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1336 {
1337         u32 srbm_status;
1338         u32 grbm_status;
1339         u32 grbm_status2;
1340         int r;
1341
1342         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1343         grbm_status = RREG32(R_008010_GRBM_STATUS);
1344         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1345         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1346                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1347                 return false;
1348         }
1349         /* force CP activities */
1350         r = radeon_ring_lock(rdev, 2);
1351         if (!r) {
1352                 /* PACKET2 NOP */
1353                 radeon_ring_write(rdev, 0x80000000);
1354                 radeon_ring_write(rdev, 0x80000000);
1355                 radeon_ring_unlock_commit(rdev);
1356         }
1357         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1358         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1359 }
1360
1361 int r600_asic_reset(struct radeon_device *rdev)
1362 {
1363         return r600_gpu_soft_reset(rdev);
1364 }
1365
1366 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1367                                              u32 num_backends,
1368                                              u32 backend_disable_mask)
1369 {
1370         u32 backend_map = 0;
1371         u32 enabled_backends_mask;
1372         u32 enabled_backends_count;
1373         u32 cur_pipe;
1374         u32 swizzle_pipe[R6XX_MAX_PIPES];
1375         u32 cur_backend;
1376         u32 i;
1377
1378         if (num_tile_pipes > R6XX_MAX_PIPES)
1379                 num_tile_pipes = R6XX_MAX_PIPES;
1380         if (num_tile_pipes < 1)
1381                 num_tile_pipes = 1;
1382         if (num_backends > R6XX_MAX_BACKENDS)
1383                 num_backends = R6XX_MAX_BACKENDS;
1384         if (num_backends < 1)
1385                 num_backends = 1;
1386
1387         enabled_backends_mask = 0;
1388         enabled_backends_count = 0;
1389         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1390                 if (((backend_disable_mask >> i) & 1) == 0) {
1391                         enabled_backends_mask |= (1 << i);
1392                         ++enabled_backends_count;
1393                 }
1394                 if (enabled_backends_count == num_backends)
1395                         break;
1396         }
1397
1398         if (enabled_backends_count == 0) {
1399                 enabled_backends_mask = 1;
1400                 enabled_backends_count = 1;
1401         }
1402
1403         if (enabled_backends_count != num_backends)
1404                 num_backends = enabled_backends_count;
1405
1406         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1407         switch (num_tile_pipes) {
1408         case 1:
1409                 swizzle_pipe[0] = 0;
1410                 break;
1411         case 2:
1412                 swizzle_pipe[0] = 0;
1413                 swizzle_pipe[1] = 1;
1414                 break;
1415         case 3:
1416                 swizzle_pipe[0] = 0;
1417                 swizzle_pipe[1] = 1;
1418                 swizzle_pipe[2] = 2;
1419                 break;
1420         case 4:
1421                 swizzle_pipe[0] = 0;
1422                 swizzle_pipe[1] = 1;
1423                 swizzle_pipe[2] = 2;
1424                 swizzle_pipe[3] = 3;
1425                 break;
1426         case 5:
1427                 swizzle_pipe[0] = 0;
1428                 swizzle_pipe[1] = 1;
1429                 swizzle_pipe[2] = 2;
1430                 swizzle_pipe[3] = 3;
1431                 swizzle_pipe[4] = 4;
1432                 break;
1433         case 6:
1434                 swizzle_pipe[0] = 0;
1435                 swizzle_pipe[1] = 2;
1436                 swizzle_pipe[2] = 4;
1437                 swizzle_pipe[3] = 5;
1438                 swizzle_pipe[4] = 1;
1439                 swizzle_pipe[5] = 3;
1440                 break;
1441         case 7:
1442                 swizzle_pipe[0] = 0;
1443                 swizzle_pipe[1] = 2;
1444                 swizzle_pipe[2] = 4;
1445                 swizzle_pipe[3] = 6;
1446                 swizzle_pipe[4] = 1;
1447                 swizzle_pipe[5] = 3;
1448                 swizzle_pipe[6] = 5;
1449                 break;
1450         case 8:
1451                 swizzle_pipe[0] = 0;
1452                 swizzle_pipe[1] = 2;
1453                 swizzle_pipe[2] = 4;
1454                 swizzle_pipe[3] = 6;
1455                 swizzle_pipe[4] = 1;
1456                 swizzle_pipe[5] = 3;
1457                 swizzle_pipe[6] = 5;
1458                 swizzle_pipe[7] = 7;
1459                 break;
1460         }
1461
1462         cur_backend = 0;
1463         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1464                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1465                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1466
1467                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1468
1469                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1470         }
1471
1472         return backend_map;
1473 }
1474
1475 int r600_count_pipe_bits(uint32_t val)
1476 {
1477         int i, ret = 0;
1478
1479         for (i = 0; i < 32; i++) {
1480                 ret += val & 1;
1481                 val >>= 1;
1482         }
1483         return ret;
1484 }
1485
1486 void r600_gpu_init(struct radeon_device *rdev)
1487 {
1488         u32 tiling_config;
1489         u32 ramcfg;
1490         u32 backend_map;
1491         u32 cc_rb_backend_disable;
1492         u32 cc_gc_shader_pipe_config;
1493         u32 tmp;
1494         int i, j;
1495         u32 sq_config;
1496         u32 sq_gpr_resource_mgmt_1 = 0;
1497         u32 sq_gpr_resource_mgmt_2 = 0;
1498         u32 sq_thread_resource_mgmt = 0;
1499         u32 sq_stack_resource_mgmt_1 = 0;
1500         u32 sq_stack_resource_mgmt_2 = 0;
1501
1502         /* FIXME: implement */
1503         switch (rdev->family) {
1504         case CHIP_R600:
1505                 rdev->config.r600.max_pipes = 4;
1506                 rdev->config.r600.max_tile_pipes = 8;
1507                 rdev->config.r600.max_simds = 4;
1508                 rdev->config.r600.max_backends = 4;
1509                 rdev->config.r600.max_gprs = 256;
1510                 rdev->config.r600.max_threads = 192;
1511                 rdev->config.r600.max_stack_entries = 256;
1512                 rdev->config.r600.max_hw_contexts = 8;
1513                 rdev->config.r600.max_gs_threads = 16;
1514                 rdev->config.r600.sx_max_export_size = 128;
1515                 rdev->config.r600.sx_max_export_pos_size = 16;
1516                 rdev->config.r600.sx_max_export_smx_size = 128;
1517                 rdev->config.r600.sq_num_cf_insts = 2;
1518                 break;
1519         case CHIP_RV630:
1520         case CHIP_RV635:
1521                 rdev->config.r600.max_pipes = 2;
1522                 rdev->config.r600.max_tile_pipes = 2;
1523                 rdev->config.r600.max_simds = 3;
1524                 rdev->config.r600.max_backends = 1;
1525                 rdev->config.r600.max_gprs = 128;
1526                 rdev->config.r600.max_threads = 192;
1527                 rdev->config.r600.max_stack_entries = 128;
1528                 rdev->config.r600.max_hw_contexts = 8;
1529                 rdev->config.r600.max_gs_threads = 4;
1530                 rdev->config.r600.sx_max_export_size = 128;
1531                 rdev->config.r600.sx_max_export_pos_size = 16;
1532                 rdev->config.r600.sx_max_export_smx_size = 128;
1533                 rdev->config.r600.sq_num_cf_insts = 2;
1534                 break;
1535         case CHIP_RV610:
1536         case CHIP_RV620:
1537         case CHIP_RS780:
1538         case CHIP_RS880:
1539                 rdev->config.r600.max_pipes = 1;
1540                 rdev->config.r600.max_tile_pipes = 1;
1541                 rdev->config.r600.max_simds = 2;
1542                 rdev->config.r600.max_backends = 1;
1543                 rdev->config.r600.max_gprs = 128;
1544                 rdev->config.r600.max_threads = 192;
1545                 rdev->config.r600.max_stack_entries = 128;
1546                 rdev->config.r600.max_hw_contexts = 4;
1547                 rdev->config.r600.max_gs_threads = 4;
1548                 rdev->config.r600.sx_max_export_size = 128;
1549                 rdev->config.r600.sx_max_export_pos_size = 16;
1550                 rdev->config.r600.sx_max_export_smx_size = 128;
1551                 rdev->config.r600.sq_num_cf_insts = 1;
1552                 break;
1553         case CHIP_RV670:
1554                 rdev->config.r600.max_pipes = 4;
1555                 rdev->config.r600.max_tile_pipes = 4;
1556                 rdev->config.r600.max_simds = 4;
1557                 rdev->config.r600.max_backends = 4;
1558                 rdev->config.r600.max_gprs = 192;
1559                 rdev->config.r600.max_threads = 192;
1560                 rdev->config.r600.max_stack_entries = 256;
1561                 rdev->config.r600.max_hw_contexts = 8;
1562                 rdev->config.r600.max_gs_threads = 16;
1563                 rdev->config.r600.sx_max_export_size = 128;
1564                 rdev->config.r600.sx_max_export_pos_size = 16;
1565                 rdev->config.r600.sx_max_export_smx_size = 128;
1566                 rdev->config.r600.sq_num_cf_insts = 2;
1567                 break;
1568         default:
1569                 break;
1570         }
1571
1572         /* Initialize HDP */
1573         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1574                 WREG32((0x2c14 + j), 0x00000000);
1575                 WREG32((0x2c18 + j), 0x00000000);
1576                 WREG32((0x2c1c + j), 0x00000000);
1577                 WREG32((0x2c20 + j), 0x00000000);
1578                 WREG32((0x2c24 + j), 0x00000000);
1579         }
1580
1581         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1582
1583         /* Setup tiling */
1584         tiling_config = 0;
1585         ramcfg = RREG32(RAMCFG);
1586         switch (rdev->config.r600.max_tile_pipes) {
1587         case 1:
1588                 tiling_config |= PIPE_TILING(0);
1589                 break;
1590         case 2:
1591                 tiling_config |= PIPE_TILING(1);
1592                 break;
1593         case 4:
1594                 tiling_config |= PIPE_TILING(2);
1595                 break;
1596         case 8:
1597                 tiling_config |= PIPE_TILING(3);
1598                 break;
1599         default:
1600                 break;
1601         }
1602         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1603         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1604         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1605         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1606         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1607                 rdev->config.r600.tiling_group_size = 512;
1608         else
1609                 rdev->config.r600.tiling_group_size = 256;
1610         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1611         if (tmp > 3) {
1612                 tiling_config |= ROW_TILING(3);
1613                 tiling_config |= SAMPLE_SPLIT(3);
1614         } else {
1615                 tiling_config |= ROW_TILING(tmp);
1616                 tiling_config |= SAMPLE_SPLIT(tmp);
1617         }
1618         tiling_config |= BANK_SWAPS(1);
1619
1620         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1621         cc_rb_backend_disable |=
1622                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1623
1624         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1625         cc_gc_shader_pipe_config |=
1626                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1627         cc_gc_shader_pipe_config |=
1628                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1629
1630         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1631                                                         (R6XX_MAX_BACKENDS -
1632                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1633                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1634                                                         (cc_rb_backend_disable >> 16));
1635         rdev->config.r600.tile_config = tiling_config;
1636         tiling_config |= BACKEND_MAP(backend_map);
1637         WREG32(GB_TILING_CONFIG, tiling_config);
1638         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1639         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1640
1641         /* Setup pipes */
1642         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1643         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1644         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1645
1646         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1647         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1648         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1649
1650         /* Setup some CP states */
1651         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1652         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1653
1654         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1655                              SYNC_WALKER | SYNC_ALIGNER));
1656         /* Setup various GPU states */
1657         if (rdev->family == CHIP_RV670)
1658                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1659
1660         tmp = RREG32(SX_DEBUG_1);
1661         tmp |= SMX_EVENT_RELEASE;
1662         if ((rdev->family > CHIP_R600))
1663                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1664         WREG32(SX_DEBUG_1, tmp);
1665
1666         if (((rdev->family) == CHIP_R600) ||
1667             ((rdev->family) == CHIP_RV630) ||
1668             ((rdev->family) == CHIP_RV610) ||
1669             ((rdev->family) == CHIP_RV620) ||
1670             ((rdev->family) == CHIP_RS780) ||
1671             ((rdev->family) == CHIP_RS880)) {
1672                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1673         } else {
1674                 WREG32(DB_DEBUG, 0);
1675         }
1676         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1677                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1678
1679         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1680         WREG32(VGT_NUM_INSTANCES, 0);
1681
1682         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1683         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1684
1685         tmp = RREG32(SQ_MS_FIFO_SIZES);
1686         if (((rdev->family) == CHIP_RV610) ||
1687             ((rdev->family) == CHIP_RV620) ||
1688             ((rdev->family) == CHIP_RS780) ||
1689             ((rdev->family) == CHIP_RS880)) {
1690                 tmp = (CACHE_FIFO_SIZE(0xa) |
1691                        FETCH_FIFO_HIWATER(0xa) |
1692                        DONE_FIFO_HIWATER(0xe0) |
1693                        ALU_UPDATE_FIFO_HIWATER(0x8));
1694         } else if (((rdev->family) == CHIP_R600) ||
1695                    ((rdev->family) == CHIP_RV630)) {
1696                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1697                 tmp |= DONE_FIFO_HIWATER(0x4);
1698         }
1699         WREG32(SQ_MS_FIFO_SIZES, tmp);
1700
1701         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1702          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1703          */
1704         sq_config = RREG32(SQ_CONFIG);
1705         sq_config &= ~(PS_PRIO(3) |
1706                        VS_PRIO(3) |
1707                        GS_PRIO(3) |
1708                        ES_PRIO(3));
1709         sq_config |= (DX9_CONSTS |
1710                       VC_ENABLE |
1711                       PS_PRIO(0) |
1712                       VS_PRIO(1) |
1713                       GS_PRIO(2) |
1714                       ES_PRIO(3));
1715
1716         if ((rdev->family) == CHIP_R600) {
1717                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1718                                           NUM_VS_GPRS(124) |
1719                                           NUM_CLAUSE_TEMP_GPRS(4));
1720                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1721                                           NUM_ES_GPRS(0));
1722                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1723                                            NUM_VS_THREADS(48) |
1724                                            NUM_GS_THREADS(4) |
1725                                            NUM_ES_THREADS(4));
1726                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1727                                             NUM_VS_STACK_ENTRIES(128));
1728                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1729                                             NUM_ES_STACK_ENTRIES(0));
1730         } else if (((rdev->family) == CHIP_RV610) ||
1731                    ((rdev->family) == CHIP_RV620) ||
1732                    ((rdev->family) == CHIP_RS780) ||
1733                    ((rdev->family) == CHIP_RS880)) {
1734                 /* no vertex cache */
1735                 sq_config &= ~VC_ENABLE;
1736
1737                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1738                                           NUM_VS_GPRS(44) |
1739                                           NUM_CLAUSE_TEMP_GPRS(2));
1740                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1741                                           NUM_ES_GPRS(17));
1742                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1743                                            NUM_VS_THREADS(78) |
1744                                            NUM_GS_THREADS(4) |
1745                                            NUM_ES_THREADS(31));
1746                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1747                                             NUM_VS_STACK_ENTRIES(40));
1748                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1749                                             NUM_ES_STACK_ENTRIES(16));
1750         } else if (((rdev->family) == CHIP_RV630) ||
1751                    ((rdev->family) == CHIP_RV635)) {
1752                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1753                                           NUM_VS_GPRS(44) |
1754                                           NUM_CLAUSE_TEMP_GPRS(2));
1755                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1756                                           NUM_ES_GPRS(18));
1757                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1758                                            NUM_VS_THREADS(78) |
1759                                            NUM_GS_THREADS(4) |
1760                                            NUM_ES_THREADS(31));
1761                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1762                                             NUM_VS_STACK_ENTRIES(40));
1763                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1764                                             NUM_ES_STACK_ENTRIES(16));
1765         } else if ((rdev->family) == CHIP_RV670) {
1766                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1767                                           NUM_VS_GPRS(44) |
1768                                           NUM_CLAUSE_TEMP_GPRS(2));
1769                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1770                                           NUM_ES_GPRS(17));
1771                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1772                                            NUM_VS_THREADS(78) |
1773                                            NUM_GS_THREADS(4) |
1774                                            NUM_ES_THREADS(31));
1775                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1776                                             NUM_VS_STACK_ENTRIES(64));
1777                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1778                                             NUM_ES_STACK_ENTRIES(64));
1779         }
1780
1781         WREG32(SQ_CONFIG, sq_config);
1782         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1783         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1784         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1785         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1786         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1787
1788         if (((rdev->family) == CHIP_RV610) ||
1789             ((rdev->family) == CHIP_RV620) ||
1790             ((rdev->family) == CHIP_RS780) ||
1791             ((rdev->family) == CHIP_RS880)) {
1792                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1793         } else {
1794                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1795         }
1796
1797         /* More default values. 2D/3D driver should adjust as needed */
1798         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1799                                          S1_X(0x4) | S1_Y(0xc)));
1800         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1801                                          S1_X(0x2) | S1_Y(0x2) |
1802                                          S2_X(0xa) | S2_Y(0x6) |
1803                                          S3_X(0x6) | S3_Y(0xa)));
1804         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1805                                              S1_X(0x4) | S1_Y(0xc) |
1806                                              S2_X(0x1) | S2_Y(0x6) |
1807                                              S3_X(0xa) | S3_Y(0xe)));
1808         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1809                                              S5_X(0x0) | S5_Y(0x0) |
1810                                              S6_X(0xb) | S6_Y(0x4) |
1811                                              S7_X(0x7) | S7_Y(0x8)));
1812
1813         WREG32(VGT_STRMOUT_EN, 0);
1814         tmp = rdev->config.r600.max_pipes * 16;
1815         switch (rdev->family) {
1816         case CHIP_RV610:
1817         case CHIP_RV620:
1818         case CHIP_RS780:
1819         case CHIP_RS880:
1820                 tmp += 32;
1821                 break;
1822         case CHIP_RV670:
1823                 tmp += 128;
1824                 break;
1825         default:
1826                 break;
1827         }
1828         if (tmp > 256) {
1829                 tmp = 256;
1830         }
1831         WREG32(VGT_ES_PER_GS, 128);
1832         WREG32(VGT_GS_PER_ES, tmp);
1833         WREG32(VGT_GS_PER_VS, 2);
1834         WREG32(VGT_GS_VERTEX_REUSE, 16);
1835
1836         /* more default values. 2D/3D driver should adjust as needed */
1837         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1838         WREG32(VGT_STRMOUT_EN, 0);
1839         WREG32(SX_MISC, 0);
1840         WREG32(PA_SC_MODE_CNTL, 0);
1841         WREG32(PA_SC_AA_CONFIG, 0);
1842         WREG32(PA_SC_LINE_STIPPLE, 0);
1843         WREG32(SPI_INPUT_Z, 0);
1844         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1845         WREG32(CB_COLOR7_FRAG, 0);
1846
1847         /* Clear render buffer base addresses */
1848         WREG32(CB_COLOR0_BASE, 0);
1849         WREG32(CB_COLOR1_BASE, 0);
1850         WREG32(CB_COLOR2_BASE, 0);
1851         WREG32(CB_COLOR3_BASE, 0);
1852         WREG32(CB_COLOR4_BASE, 0);
1853         WREG32(CB_COLOR5_BASE, 0);
1854         WREG32(CB_COLOR6_BASE, 0);
1855         WREG32(CB_COLOR7_BASE, 0);
1856         WREG32(CB_COLOR7_FRAG, 0);
1857
1858         switch (rdev->family) {
1859         case CHIP_RV610:
1860         case CHIP_RV620:
1861         case CHIP_RS780:
1862         case CHIP_RS880:
1863                 tmp = TC_L2_SIZE(8);
1864                 break;
1865         case CHIP_RV630:
1866         case CHIP_RV635:
1867                 tmp = TC_L2_SIZE(4);
1868                 break;
1869         case CHIP_R600:
1870                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1871                 break;
1872         default:
1873                 tmp = TC_L2_SIZE(0);
1874                 break;
1875         }
1876         WREG32(TC_CNTL, tmp);
1877
1878         tmp = RREG32(HDP_HOST_PATH_CNTL);
1879         WREG32(HDP_HOST_PATH_CNTL, tmp);
1880
1881         tmp = RREG32(ARB_POP);
1882         tmp |= ENABLE_TC128;
1883         WREG32(ARB_POP, tmp);
1884
1885         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1886         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1887                                NUM_CLIP_SEQ(3)));
1888         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1889 }
1890
1891
1892 /*
1893  * Indirect registers accessor
1894  */
1895 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1896 {
1897         u32 r;
1898
1899         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1900         (void)RREG32(PCIE_PORT_INDEX);
1901         r = RREG32(PCIE_PORT_DATA);
1902         return r;
1903 }
1904
1905 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1906 {
1907         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1908         (void)RREG32(PCIE_PORT_INDEX);
1909         WREG32(PCIE_PORT_DATA, (v));
1910         (void)RREG32(PCIE_PORT_DATA);
1911 }
1912
1913 /*
1914  * CP & Ring
1915  */
1916 void r600_cp_stop(struct radeon_device *rdev)
1917 {
1918         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1919         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1920         WREG32(SCRATCH_UMSK, 0);
1921 }
1922
1923 int r600_init_microcode(struct radeon_device *rdev)
1924 {
1925         struct platform_device *pdev;
1926         const char *chip_name;
1927         const char *rlc_chip_name;
1928         size_t pfp_req_size, me_req_size, rlc_req_size;
1929         char fw_name[30];
1930         int err;
1931
1932         DRM_DEBUG("\n");
1933
1934         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1935         err = IS_ERR(pdev);
1936         if (err) {
1937                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1938                 return -EINVAL;
1939         }
1940
1941         switch (rdev->family) {
1942         case CHIP_R600:
1943                 chip_name = "R600";
1944                 rlc_chip_name = "R600";
1945                 break;
1946         case CHIP_RV610:
1947                 chip_name = "RV610";
1948                 rlc_chip_name = "R600";
1949                 break;
1950         case CHIP_RV630:
1951                 chip_name = "RV630";
1952                 rlc_chip_name = "R600";
1953                 break;
1954         case CHIP_RV620:
1955                 chip_name = "RV620";
1956                 rlc_chip_name = "R600";
1957                 break;
1958         case CHIP_RV635:
1959                 chip_name = "RV635";
1960                 rlc_chip_name = "R600";
1961                 break;
1962         case CHIP_RV670:
1963                 chip_name = "RV670";
1964                 rlc_chip_name = "R600";
1965                 break;
1966         case CHIP_RS780:
1967         case CHIP_RS880:
1968                 chip_name = "RS780";
1969                 rlc_chip_name = "R600";
1970                 break;
1971         case CHIP_RV770:
1972                 chip_name = "RV770";
1973                 rlc_chip_name = "R700";
1974                 break;
1975         case CHIP_RV730:
1976         case CHIP_RV740:
1977                 chip_name = "RV730";
1978                 rlc_chip_name = "R700";
1979                 break;
1980         case CHIP_RV710:
1981                 chip_name = "RV710";
1982                 rlc_chip_name = "R700";
1983                 break;
1984         case CHIP_CEDAR:
1985                 chip_name = "CEDAR";
1986                 rlc_chip_name = "CEDAR";
1987                 break;
1988         case CHIP_REDWOOD:
1989                 chip_name = "REDWOOD";
1990                 rlc_chip_name = "REDWOOD";
1991                 break;
1992         case CHIP_JUNIPER:
1993                 chip_name = "JUNIPER";
1994                 rlc_chip_name = "JUNIPER";
1995                 break;
1996         case CHIP_CYPRESS:
1997         case CHIP_HEMLOCK:
1998                 chip_name = "CYPRESS";
1999                 rlc_chip_name = "CYPRESS";
2000                 break;
2001         default: BUG();
2002         }
2003
2004         if (rdev->family >= CHIP_CEDAR) {
2005                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2006                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2007                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2008         } else if (rdev->family >= CHIP_RV770) {
2009                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2010                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2011                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2012         } else {
2013                 pfp_req_size = PFP_UCODE_SIZE * 4;
2014                 me_req_size = PM4_UCODE_SIZE * 12;
2015                 rlc_req_size = RLC_UCODE_SIZE * 4;
2016         }
2017
2018         DRM_INFO("Loading %s Microcode\n", chip_name);
2019
2020         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2021         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2022         if (err)
2023                 goto out;
2024         if (rdev->pfp_fw->size != pfp_req_size) {
2025                 printk(KERN_ERR
2026                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2027                        rdev->pfp_fw->size, fw_name);
2028                 err = -EINVAL;
2029                 goto out;
2030         }
2031
2032         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2033         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2034         if (err)
2035                 goto out;
2036         if (rdev->me_fw->size != me_req_size) {
2037                 printk(KERN_ERR
2038                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2039                        rdev->me_fw->size, fw_name);
2040                 err = -EINVAL;
2041         }
2042
2043         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2044         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2045         if (err)
2046                 goto out;
2047         if (rdev->rlc_fw->size != rlc_req_size) {
2048                 printk(KERN_ERR
2049                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2050                        rdev->rlc_fw->size, fw_name);
2051                 err = -EINVAL;
2052         }
2053
2054 out:
2055         platform_device_unregister(pdev);
2056
2057         if (err) {
2058                 if (err != -EINVAL)
2059                         printk(KERN_ERR
2060                                "r600_cp: Failed to load firmware \"%s\"\n",
2061                                fw_name);
2062                 release_firmware(rdev->pfp_fw);
2063                 rdev->pfp_fw = NULL;
2064                 release_firmware(rdev->me_fw);
2065                 rdev->me_fw = NULL;
2066                 release_firmware(rdev->rlc_fw);
2067                 rdev->rlc_fw = NULL;
2068         }
2069         return err;
2070 }
2071
2072 static int r600_cp_load_microcode(struct radeon_device *rdev)
2073 {
2074         const __be32 *fw_data;
2075         int i;
2076
2077         if (!rdev->me_fw || !rdev->pfp_fw)
2078                 return -EINVAL;
2079
2080         r600_cp_stop(rdev);
2081
2082         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2083
2084         /* Reset cp */
2085         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2086         RREG32(GRBM_SOFT_RESET);
2087         mdelay(15);
2088         WREG32(GRBM_SOFT_RESET, 0);
2089
2090         WREG32(CP_ME_RAM_WADDR, 0);
2091
2092         fw_data = (const __be32 *)rdev->me_fw->data;
2093         WREG32(CP_ME_RAM_WADDR, 0);
2094         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2095                 WREG32(CP_ME_RAM_DATA,
2096                        be32_to_cpup(fw_data++));
2097
2098         fw_data = (const __be32 *)rdev->pfp_fw->data;
2099         WREG32(CP_PFP_UCODE_ADDR, 0);
2100         for (i = 0; i < PFP_UCODE_SIZE; i++)
2101                 WREG32(CP_PFP_UCODE_DATA,
2102                        be32_to_cpup(fw_data++));
2103
2104         WREG32(CP_PFP_UCODE_ADDR, 0);
2105         WREG32(CP_ME_RAM_WADDR, 0);
2106         WREG32(CP_ME_RAM_RADDR, 0);
2107         return 0;
2108 }
2109
2110 int r600_cp_start(struct radeon_device *rdev)
2111 {
2112         int r;
2113         uint32_t cp_me;
2114
2115         r = radeon_ring_lock(rdev, 7);
2116         if (r) {
2117                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2118                 return r;
2119         }
2120         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2121         radeon_ring_write(rdev, 0x1);
2122         if (rdev->family >= CHIP_RV770) {
2123                 radeon_ring_write(rdev, 0x0);
2124                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2125         } else {
2126                 radeon_ring_write(rdev, 0x3);
2127                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2128         }
2129         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2130         radeon_ring_write(rdev, 0);
2131         radeon_ring_write(rdev, 0);
2132         radeon_ring_unlock_commit(rdev);
2133
2134         cp_me = 0xff;
2135         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2136         return 0;
2137 }
2138
2139 int r600_cp_resume(struct radeon_device *rdev)
2140 {
2141         u32 tmp;
2142         u32 rb_bufsz;
2143         int r;
2144
2145         /* Reset cp */
2146         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2147         RREG32(GRBM_SOFT_RESET);
2148         mdelay(15);
2149         WREG32(GRBM_SOFT_RESET, 0);
2150
2151         /* Set ring buffer size */
2152         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2153         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2154 #ifdef __BIG_ENDIAN
2155         tmp |= BUF_SWAP_32BIT;
2156 #endif
2157         WREG32(CP_RB_CNTL, tmp);
2158         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2159
2160         /* Set the write pointer delay */
2161         WREG32(CP_RB_WPTR_DELAY, 0);
2162
2163         /* Initialize the ring buffer's read and write pointers */
2164         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2165         WREG32(CP_RB_RPTR_WR, 0);
2166         WREG32(CP_RB_WPTR, 0);
2167
2168         /* set the wb address whether it's enabled or not */
2169         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2170         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2171         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2172
2173         if (rdev->wb.enabled)
2174                 WREG32(SCRATCH_UMSK, 0xff);
2175         else {
2176                 tmp |= RB_NO_UPDATE;
2177                 WREG32(SCRATCH_UMSK, 0);
2178         }
2179
2180         mdelay(1);
2181         WREG32(CP_RB_CNTL, tmp);
2182
2183         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2184         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2185
2186         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2187         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2188
2189         r600_cp_start(rdev);
2190         rdev->cp.ready = true;
2191         r = radeon_ring_test(rdev);
2192         if (r) {
2193                 rdev->cp.ready = false;
2194                 return r;
2195         }
2196         return 0;
2197 }
2198
2199 void r600_cp_commit(struct radeon_device *rdev)
2200 {
2201         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2202         (void)RREG32(CP_RB_WPTR);
2203 }
2204
2205 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2206 {
2207         u32 rb_bufsz;
2208
2209         /* Align ring size */
2210         rb_bufsz = drm_order(ring_size / 8);
2211         ring_size = (1 << (rb_bufsz + 1)) * 4;
2212         rdev->cp.ring_size = ring_size;
2213         rdev->cp.align_mask = 16 - 1;
2214 }
2215
2216 void r600_cp_fini(struct radeon_device *rdev)
2217 {
2218         r600_cp_stop(rdev);
2219         radeon_ring_fini(rdev);
2220 }
2221
2222
2223 /*
2224  * GPU scratch registers helpers function.
2225  */
2226 void r600_scratch_init(struct radeon_device *rdev)
2227 {
2228         int i;
2229
2230         rdev->scratch.num_reg = 7;
2231         rdev->scratch.reg_base = SCRATCH_REG0;
2232         for (i = 0; i < rdev->scratch.num_reg; i++) {
2233                 rdev->scratch.free[i] = true;
2234                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2235         }
2236 }
2237
2238 int r600_ring_test(struct radeon_device *rdev)
2239 {
2240         uint32_t scratch;
2241         uint32_t tmp = 0;
2242         unsigned i;
2243         int r;
2244
2245         r = radeon_scratch_get(rdev, &scratch);
2246         if (r) {
2247                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2248                 return r;
2249         }
2250         WREG32(scratch, 0xCAFEDEAD);
2251         r = radeon_ring_lock(rdev, 3);
2252         if (r) {
2253                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2254                 radeon_scratch_free(rdev, scratch);
2255                 return r;
2256         }
2257         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2258         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2259         radeon_ring_write(rdev, 0xDEADBEEF);
2260         radeon_ring_unlock_commit(rdev);
2261         for (i = 0; i < rdev->usec_timeout; i++) {
2262                 tmp = RREG32(scratch);
2263                 if (tmp == 0xDEADBEEF)
2264                         break;
2265                 DRM_UDELAY(1);
2266         }
2267         if (i < rdev->usec_timeout) {
2268                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2269         } else {
2270                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2271                           scratch, tmp);
2272                 r = -EINVAL;
2273         }
2274         radeon_scratch_free(rdev, scratch);
2275         return r;
2276 }
2277
2278 void r600_fence_ring_emit(struct radeon_device *rdev,
2279                           struct radeon_fence *fence)
2280 {
2281         if (rdev->wb.use_event) {
2282                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2283                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2284                 /* EVENT_WRITE_EOP - flush caches, send int */
2285                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2286                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2287                 radeon_ring_write(rdev, addr & 0xffffffff);
2288                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2289                 radeon_ring_write(rdev, fence->seq);
2290                 radeon_ring_write(rdev, 0);
2291         } else {
2292                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2293                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2294                 /* wait for 3D idle clean */
2295                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2296                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2297                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2298                 /* Emit fence sequence & fire IRQ */
2299                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2300                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2301                 radeon_ring_write(rdev, fence->seq);
2302                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2303                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2304                 radeon_ring_write(rdev, RB_INT_STAT);
2305         }
2306 }
2307
2308 int r600_copy_blit(struct radeon_device *rdev,
2309                    uint64_t src_offset, uint64_t dst_offset,
2310                    unsigned num_pages, struct radeon_fence *fence)
2311 {
2312         int r;
2313
2314         mutex_lock(&rdev->r600_blit.mutex);
2315         rdev->r600_blit.vb_ib = NULL;
2316         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2317         if (r) {
2318                 if (rdev->r600_blit.vb_ib)
2319                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2320                 mutex_unlock(&rdev->r600_blit.mutex);
2321                 return r;
2322         }
2323         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2324         r600_blit_done_copy(rdev, fence);
2325         mutex_unlock(&rdev->r600_blit.mutex);
2326         return 0;
2327 }
2328
2329 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2330                          uint32_t tiling_flags, uint32_t pitch,
2331                          uint32_t offset, uint32_t obj_size)
2332 {
2333         /* FIXME: implement */
2334         return 0;
2335 }
2336
2337 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2338 {
2339         /* FIXME: implement */
2340 }
2341
2342
2343 bool r600_card_posted(struct radeon_device *rdev)
2344 {
2345         uint32_t reg;
2346
2347         /* first check CRTCs */
2348         reg = RREG32(D1CRTC_CONTROL) |
2349                 RREG32(D2CRTC_CONTROL);
2350         if (reg & CRTC_EN)
2351                 return true;
2352
2353         /* then check MEM_SIZE, in case the crtcs are off */
2354         if (RREG32(CONFIG_MEMSIZE))
2355                 return true;
2356
2357         return false;
2358 }
2359
2360 int r600_startup(struct radeon_device *rdev)
2361 {
2362         int r;
2363
2364         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2365                 r = r600_init_microcode(rdev);
2366                 if (r) {
2367                         DRM_ERROR("Failed to load firmware!\n");
2368                         return r;
2369                 }
2370         }
2371
2372         r600_mc_program(rdev);
2373         if (rdev->flags & RADEON_IS_AGP) {
2374                 r600_agp_enable(rdev);
2375         } else {
2376                 r = r600_pcie_gart_enable(rdev);
2377                 if (r)
2378                         return r;
2379         }
2380         r600_gpu_init(rdev);
2381         r = r600_blit_init(rdev);
2382         if (r) {
2383                 r600_blit_fini(rdev);
2384                 rdev->asic->copy = NULL;
2385                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2386         }
2387
2388         /* allocate wb buffer */
2389         r = radeon_wb_init(rdev);
2390         if (r)
2391                 return r;
2392
2393         /* Enable IRQ */
2394         r = r600_irq_init(rdev);
2395         if (r) {
2396                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2397                 radeon_irq_kms_fini(rdev);
2398                 return r;
2399         }
2400         r600_irq_set(rdev);
2401
2402         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2403         if (r)
2404                 return r;
2405         r = r600_cp_load_microcode(rdev);
2406         if (r)
2407                 return r;
2408         r = r600_cp_resume(rdev);
2409         if (r)
2410                 return r;
2411
2412         return 0;
2413 }
2414
2415 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2416 {
2417         uint32_t temp;
2418
2419         temp = RREG32(CONFIG_CNTL);
2420         if (state == false) {
2421                 temp &= ~(1<<0);
2422                 temp |= (1<<1);
2423         } else {
2424                 temp &= ~(1<<1);
2425         }
2426         WREG32(CONFIG_CNTL, temp);
2427 }
2428
2429 int r600_resume(struct radeon_device *rdev)
2430 {
2431         int r;
2432
2433         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2434          * posting will perform necessary task to bring back GPU into good
2435          * shape.
2436          */
2437         /* post card */
2438         atom_asic_init(rdev->mode_info.atom_context);
2439
2440         r = r600_startup(rdev);
2441         if (r) {
2442                 DRM_ERROR("r600 startup failed on resume\n");
2443                 return r;
2444         }
2445
2446         r = r600_ib_test(rdev);
2447         if (r) {
2448                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2449                 return r;
2450         }
2451
2452         r = r600_audio_init(rdev);
2453         if (r) {
2454                 DRM_ERROR("radeon: audio resume failed\n");
2455                 return r;
2456         }
2457
2458         return r;
2459 }
2460
2461 int r600_suspend(struct radeon_device *rdev)
2462 {
2463         int r;
2464
2465         r600_audio_fini(rdev);
2466         /* FIXME: we should wait for ring to be empty */
2467         r600_cp_stop(rdev);
2468         rdev->cp.ready = false;
2469         r600_irq_suspend(rdev);
2470         radeon_wb_disable(rdev);
2471         r600_pcie_gart_disable(rdev);
2472         /* unpin shaders bo */
2473         if (rdev->r600_blit.shader_obj) {
2474                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2475                 if (!r) {
2476                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2477                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2478                 }
2479         }
2480         return 0;
2481 }
2482
2483 /* Plan is to move initialization in that function and use
2484  * helper function so that radeon_device_init pretty much
2485  * do nothing more than calling asic specific function. This
2486  * should also allow to remove a bunch of callback function
2487  * like vram_info.
2488  */
2489 int r600_init(struct radeon_device *rdev)
2490 {
2491         int r;
2492
2493         r = radeon_dummy_page_init(rdev);
2494         if (r)
2495                 return r;
2496         if (r600_debugfs_mc_info_init(rdev)) {
2497                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2498         }
2499         /* This don't do much */
2500         r = radeon_gem_init(rdev);
2501         if (r)
2502                 return r;
2503         /* Read BIOS */
2504         if (!radeon_get_bios(rdev)) {
2505                 if (ASIC_IS_AVIVO(rdev))
2506                         return -EINVAL;
2507         }
2508         /* Must be an ATOMBIOS */
2509         if (!rdev->is_atom_bios) {
2510                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2511                 return -EINVAL;
2512         }
2513         r = radeon_atombios_init(rdev);
2514         if (r)
2515                 return r;
2516         /* Post card if necessary */
2517         if (!r600_card_posted(rdev)) {
2518                 if (!rdev->bios) {
2519                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2520                         return -EINVAL;
2521                 }
2522                 DRM_INFO("GPU not posted. posting now...\n");
2523                 atom_asic_init(rdev->mode_info.atom_context);
2524         }
2525         /* Initialize scratch registers */
2526         r600_scratch_init(rdev);
2527         /* Initialize surface registers */
2528         radeon_surface_init(rdev);
2529         /* Initialize clocks */
2530         radeon_get_clock_info(rdev->ddev);
2531         /* Fence driver */
2532         r = radeon_fence_driver_init(rdev);
2533         if (r)
2534                 return r;
2535         if (rdev->flags & RADEON_IS_AGP) {
2536                 r = radeon_agp_init(rdev);
2537                 if (r)
2538                         radeon_agp_disable(rdev);
2539         }
2540         r = r600_mc_init(rdev);
2541         if (r)
2542                 return r;
2543         /* Memory manager */
2544         r = radeon_bo_init(rdev);
2545         if (r)
2546                 return r;
2547
2548         r = radeon_irq_kms_init(rdev);
2549         if (r)
2550                 return r;
2551
2552         rdev->cp.ring_obj = NULL;
2553         r600_ring_init(rdev, 1024 * 1024);
2554
2555         rdev->ih.ring_obj = NULL;
2556         r600_ih_ring_init(rdev, 64 * 1024);
2557
2558         r = r600_pcie_gart_init(rdev);
2559         if (r)
2560                 return r;
2561
2562         rdev->accel_working = true;
2563         r = r600_startup(rdev);
2564         if (r) {
2565                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2566                 r600_cp_fini(rdev);
2567                 r600_irq_fini(rdev);
2568                 radeon_wb_fini(rdev);
2569                 radeon_irq_kms_fini(rdev);
2570                 r600_pcie_gart_fini(rdev);
2571                 rdev->accel_working = false;
2572         }
2573         if (rdev->accel_working) {
2574                 r = radeon_ib_pool_init(rdev);
2575                 if (r) {
2576                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2577                         rdev->accel_working = false;
2578                 } else {
2579                         r = r600_ib_test(rdev);
2580                         if (r) {
2581                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2582                                 rdev->accel_working = false;
2583                         }
2584                 }
2585         }
2586
2587         r = r600_audio_init(rdev);
2588         if (r)
2589                 return r; /* TODO error handling */
2590         return 0;
2591 }
2592
2593 void r600_fini(struct radeon_device *rdev)
2594 {
2595         r600_audio_fini(rdev);
2596         r600_blit_fini(rdev);
2597         r600_cp_fini(rdev);
2598         r600_irq_fini(rdev);
2599         radeon_wb_fini(rdev);
2600         radeon_irq_kms_fini(rdev);
2601         r600_pcie_gart_fini(rdev);
2602         radeon_agp_fini(rdev);
2603         radeon_gem_fini(rdev);
2604         radeon_fence_driver_fini(rdev);
2605         radeon_bo_fini(rdev);
2606         radeon_atombios_fini(rdev);
2607         kfree(rdev->bios);
2608         rdev->bios = NULL;
2609         radeon_dummy_page_fini(rdev);
2610 }
2611
2612
2613 /*
2614  * CS stuff
2615  */
2616 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2617 {
2618         /* FIXME: implement */
2619         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2620         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2621         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2622         radeon_ring_write(rdev, ib->length_dw);
2623 }
2624
2625 int r600_ib_test(struct radeon_device *rdev)
2626 {
2627         struct radeon_ib *ib;
2628         uint32_t scratch;
2629         uint32_t tmp = 0;
2630         unsigned i;
2631         int r;
2632
2633         r = radeon_scratch_get(rdev, &scratch);
2634         if (r) {
2635                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2636                 return r;
2637         }
2638         WREG32(scratch, 0xCAFEDEAD);
2639         r = radeon_ib_get(rdev, &ib);
2640         if (r) {
2641                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2642                 return r;
2643         }
2644         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2645         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2646         ib->ptr[2] = 0xDEADBEEF;
2647         ib->ptr[3] = PACKET2(0);
2648         ib->ptr[4] = PACKET2(0);
2649         ib->ptr[5] = PACKET2(0);
2650         ib->ptr[6] = PACKET2(0);
2651         ib->ptr[7] = PACKET2(0);
2652         ib->ptr[8] = PACKET2(0);
2653         ib->ptr[9] = PACKET2(0);
2654         ib->ptr[10] = PACKET2(0);
2655         ib->ptr[11] = PACKET2(0);
2656         ib->ptr[12] = PACKET2(0);
2657         ib->ptr[13] = PACKET2(0);
2658         ib->ptr[14] = PACKET2(0);
2659         ib->ptr[15] = PACKET2(0);
2660         ib->length_dw = 16;
2661         r = radeon_ib_schedule(rdev, ib);
2662         if (r) {
2663                 radeon_scratch_free(rdev, scratch);
2664                 radeon_ib_free(rdev, &ib);
2665                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2666                 return r;
2667         }
2668         r = radeon_fence_wait(ib->fence, false);
2669         if (r) {
2670                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2671                 return r;
2672         }
2673         for (i = 0; i < rdev->usec_timeout; i++) {
2674                 tmp = RREG32(scratch);
2675                 if (tmp == 0xDEADBEEF)
2676                         break;
2677                 DRM_UDELAY(1);
2678         }
2679         if (i < rdev->usec_timeout) {
2680                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2681         } else {
2682                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2683                           scratch, tmp);
2684                 r = -EINVAL;
2685         }
2686         radeon_scratch_free(rdev, scratch);
2687         radeon_ib_free(rdev, &ib);
2688         return r;
2689 }
2690
2691 /*
2692  * Interrupts
2693  *
2694  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2695  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2696  * writing to the ring and the GPU consuming, the GPU writes to the ring
2697  * and host consumes.  As the host irq handler processes interrupts, it
2698  * increments the rptr.  When the rptr catches up with the wptr, all the
2699  * current interrupts have been processed.
2700  */
2701
2702 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2703 {
2704         u32 rb_bufsz;
2705
2706         /* Align ring size */
2707         rb_bufsz = drm_order(ring_size / 4);
2708         ring_size = (1 << rb_bufsz) * 4;
2709         rdev->ih.ring_size = ring_size;
2710         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2711         rdev->ih.rptr = 0;
2712 }
2713
2714 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2715 {
2716         int r;
2717
2718         /* Allocate ring buffer */
2719         if (rdev->ih.ring_obj == NULL) {
2720                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2721                                      true,
2722                                      RADEON_GEM_DOMAIN_GTT,
2723                                      &rdev->ih.ring_obj);
2724                 if (r) {
2725                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2726                         return r;
2727                 }
2728                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2729                 if (unlikely(r != 0))
2730                         return r;
2731                 r = radeon_bo_pin(rdev->ih.ring_obj,
2732                                   RADEON_GEM_DOMAIN_GTT,
2733                                   &rdev->ih.gpu_addr);
2734                 if (r) {
2735                         radeon_bo_unreserve(rdev->ih.ring_obj);
2736                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2737                         return r;
2738                 }
2739                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2740                                    (void **)&rdev->ih.ring);
2741                 radeon_bo_unreserve(rdev->ih.ring_obj);
2742                 if (r) {
2743                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2744                         return r;
2745                 }
2746         }
2747         return 0;
2748 }
2749
2750 static void r600_ih_ring_fini(struct radeon_device *rdev)
2751 {
2752         int r;
2753         if (rdev->ih.ring_obj) {
2754                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2755                 if (likely(r == 0)) {
2756                         radeon_bo_kunmap(rdev->ih.ring_obj);
2757                         radeon_bo_unpin(rdev->ih.ring_obj);
2758                         radeon_bo_unreserve(rdev->ih.ring_obj);
2759                 }
2760                 radeon_bo_unref(&rdev->ih.ring_obj);
2761                 rdev->ih.ring = NULL;
2762                 rdev->ih.ring_obj = NULL;
2763         }
2764 }
2765
2766 void r600_rlc_stop(struct radeon_device *rdev)
2767 {
2768
2769         if ((rdev->family >= CHIP_RV770) &&
2770             (rdev->family <= CHIP_RV740)) {
2771                 /* r7xx asics need to soft reset RLC before halting */
2772                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2773                 RREG32(SRBM_SOFT_RESET);
2774                 udelay(15000);
2775                 WREG32(SRBM_SOFT_RESET, 0);
2776                 RREG32(SRBM_SOFT_RESET);
2777         }
2778
2779         WREG32(RLC_CNTL, 0);
2780 }
2781
2782 static void r600_rlc_start(struct radeon_device *rdev)
2783 {
2784         WREG32(RLC_CNTL, RLC_ENABLE);
2785 }
2786
2787 static int r600_rlc_init(struct radeon_device *rdev)
2788 {
2789         u32 i;
2790         const __be32 *fw_data;
2791
2792         if (!rdev->rlc_fw)
2793                 return -EINVAL;
2794
2795         r600_rlc_stop(rdev);
2796
2797         WREG32(RLC_HB_BASE, 0);
2798         WREG32(RLC_HB_CNTL, 0);
2799         WREG32(RLC_HB_RPTR, 0);
2800         WREG32(RLC_HB_WPTR, 0);
2801         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2802         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2803         WREG32(RLC_MC_CNTL, 0);
2804         WREG32(RLC_UCODE_CNTL, 0);
2805
2806         fw_data = (const __be32 *)rdev->rlc_fw->data;
2807         if (rdev->family >= CHIP_CEDAR) {
2808                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2809                         WREG32(RLC_UCODE_ADDR, i);
2810                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2811                 }
2812         } else if (rdev->family >= CHIP_RV770) {
2813                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2814                         WREG32(RLC_UCODE_ADDR, i);
2815                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2816                 }
2817         } else {
2818                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2819                         WREG32(RLC_UCODE_ADDR, i);
2820                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2821                 }
2822         }
2823         WREG32(RLC_UCODE_ADDR, 0);
2824
2825         r600_rlc_start(rdev);
2826
2827         return 0;
2828 }
2829
2830 static void r600_enable_interrupts(struct radeon_device *rdev)
2831 {
2832         u32 ih_cntl = RREG32(IH_CNTL);
2833         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2834
2835         ih_cntl |= ENABLE_INTR;
2836         ih_rb_cntl |= IH_RB_ENABLE;
2837         WREG32(IH_CNTL, ih_cntl);
2838         WREG32(IH_RB_CNTL, ih_rb_cntl);
2839         rdev->ih.enabled = true;
2840 }
2841
2842 void r600_disable_interrupts(struct radeon_device *rdev)
2843 {
2844         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2845         u32 ih_cntl = RREG32(IH_CNTL);
2846
2847         ih_rb_cntl &= ~IH_RB_ENABLE;
2848         ih_cntl &= ~ENABLE_INTR;
2849         WREG32(IH_RB_CNTL, ih_rb_cntl);
2850         WREG32(IH_CNTL, ih_cntl);
2851         /* set rptr, wptr to 0 */
2852         WREG32(IH_RB_RPTR, 0);
2853         WREG32(IH_RB_WPTR, 0);
2854         rdev->ih.enabled = false;
2855         rdev->ih.wptr = 0;
2856         rdev->ih.rptr = 0;
2857 }
2858
2859 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2860 {
2861         u32 tmp;
2862
2863         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2864         WREG32(GRBM_INT_CNTL, 0);
2865         WREG32(DxMODE_INT_MASK, 0);
2866         if (ASIC_IS_DCE3(rdev)) {
2867                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2868                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2869                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2870                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2871                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2872                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2873                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2874                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2875                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2876                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2877                 if (ASIC_IS_DCE32(rdev)) {
2878                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2879                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2880                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2881                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2882                 }
2883         } else {
2884                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2885                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2886                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2887                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2888                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2889                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2890                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2891                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2892         }
2893 }
2894
2895 int r600_irq_init(struct radeon_device *rdev)
2896 {
2897         int ret = 0;
2898         int rb_bufsz;
2899         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2900
2901         /* allocate ring */
2902         ret = r600_ih_ring_alloc(rdev);
2903         if (ret)
2904                 return ret;
2905
2906         /* disable irqs */
2907         r600_disable_interrupts(rdev);
2908
2909         /* init rlc */
2910         ret = r600_rlc_init(rdev);
2911         if (ret) {
2912                 r600_ih_ring_fini(rdev);
2913                 return ret;
2914         }
2915
2916         /* setup interrupt control */
2917         /* set dummy read address to ring address */
2918         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2919         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2920         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2921          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2922          */
2923         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2924         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2925         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2926         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2927
2928         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2929         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2930
2931         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2932                       IH_WPTR_OVERFLOW_CLEAR |
2933                       (rb_bufsz << 1));
2934
2935         if (rdev->wb.enabled)
2936                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2937
2938         /* set the writeback address whether it's enabled or not */
2939         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2940         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2941
2942         WREG32(IH_RB_CNTL, ih_rb_cntl);
2943
2944         /* set rptr, wptr to 0 */
2945         WREG32(IH_RB_RPTR, 0);
2946         WREG32(IH_RB_WPTR, 0);
2947
2948         /* Default settings for IH_CNTL (disabled at first) */
2949         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2950         /* RPTR_REARM only works if msi's are enabled */
2951         if (rdev->msi_enabled)
2952                 ih_cntl |= RPTR_REARM;
2953
2954 #ifdef __BIG_ENDIAN
2955         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2956 #endif
2957         WREG32(IH_CNTL, ih_cntl);
2958
2959         /* force the active interrupt state to all disabled */
2960         if (rdev->family >= CHIP_CEDAR)
2961                 evergreen_disable_interrupt_state(rdev);
2962         else
2963                 r600_disable_interrupt_state(rdev);
2964
2965         /* enable irqs */
2966         r600_enable_interrupts(rdev);
2967
2968         return ret;
2969 }
2970
2971 void r600_irq_suspend(struct radeon_device *rdev)
2972 {
2973         r600_irq_disable(rdev);
2974         r600_rlc_stop(rdev);
2975 }
2976
2977 void r600_irq_fini(struct radeon_device *rdev)
2978 {
2979         r600_irq_suspend(rdev);
2980         r600_ih_ring_fini(rdev);
2981 }
2982
2983 int r600_irq_set(struct radeon_device *rdev)
2984 {
2985         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2986         u32 mode_int = 0;
2987         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2988         u32 grbm_int_cntl = 0;
2989         u32 hdmi1, hdmi2;
2990
2991         if (!rdev->irq.installed) {
2992                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2993                 return -EINVAL;
2994         }
2995         /* don't enable anything if the ih is disabled */
2996         if (!rdev->ih.enabled) {
2997                 r600_disable_interrupts(rdev);
2998                 /* force the active interrupt state to all disabled */
2999                 r600_disable_interrupt_state(rdev);
3000                 return 0;
3001         }
3002
3003         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3004         if (ASIC_IS_DCE3(rdev)) {
3005                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3006                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3007                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3008                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3009                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3010                 if (ASIC_IS_DCE32(rdev)) {
3011                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3012                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3013                 }
3014         } else {
3015                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3016                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3017                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3018                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3019         }
3020
3021         if (rdev->irq.sw_int) {
3022                 DRM_DEBUG("r600_irq_set: sw int\n");
3023                 cp_int_cntl |= RB_INT_ENABLE;
3024                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3025         }
3026         if (rdev->irq.crtc_vblank_int[0]) {
3027                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3028                 mode_int |= D1MODE_VBLANK_INT_MASK;
3029         }
3030         if (rdev->irq.crtc_vblank_int[1]) {
3031                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3032                 mode_int |= D2MODE_VBLANK_INT_MASK;
3033         }
3034         if (rdev->irq.hpd[0]) {
3035                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3036                 hpd1 |= DC_HPDx_INT_EN;
3037         }
3038         if (rdev->irq.hpd[1]) {
3039                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3040                 hpd2 |= DC_HPDx_INT_EN;
3041         }
3042         if (rdev->irq.hpd[2]) {
3043                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3044                 hpd3 |= DC_HPDx_INT_EN;
3045         }
3046         if (rdev->irq.hpd[3]) {
3047                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3048                 hpd4 |= DC_HPDx_INT_EN;
3049         }
3050         if (rdev->irq.hpd[4]) {
3051                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3052                 hpd5 |= DC_HPDx_INT_EN;
3053         }
3054         if (rdev->irq.hpd[5]) {
3055                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3056                 hpd6 |= DC_HPDx_INT_EN;
3057         }
3058         if (rdev->irq.hdmi[0]) {
3059                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3060                 hdmi1 |= R600_HDMI_INT_EN;
3061         }
3062         if (rdev->irq.hdmi[1]) {
3063                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3064                 hdmi2 |= R600_HDMI_INT_EN;
3065         }
3066         if (rdev->irq.gui_idle) {
3067                 DRM_DEBUG("gui idle\n");
3068                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3069         }
3070
3071         WREG32(CP_INT_CNTL, cp_int_cntl);
3072         WREG32(DxMODE_INT_MASK, mode_int);
3073         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3074         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3075         if (ASIC_IS_DCE3(rdev)) {
3076                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3077                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3078                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3079                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3080                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3081                 if (ASIC_IS_DCE32(rdev)) {
3082                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3083                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3084                 }
3085         } else {
3086                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3087                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3088                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3089                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3090         }
3091
3092         return 0;
3093 }
3094
3095 static inline void r600_irq_ack(struct radeon_device *rdev,
3096                                 u32 *disp_int,
3097                                 u32 *disp_int_cont,
3098                                 u32 *disp_int_cont2)
3099 {
3100         u32 tmp;
3101
3102         if (ASIC_IS_DCE3(rdev)) {
3103                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3104                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3105                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3106         } else {
3107                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3108                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3109                 *disp_int_cont2 = 0;
3110         }
3111
3112         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3113                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3114         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3115                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3116         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3117                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3118         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3119                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3120         if (*disp_int & DC_HPD1_INTERRUPT) {
3121                 if (ASIC_IS_DCE3(rdev)) {
3122                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3123                         tmp |= DC_HPDx_INT_ACK;
3124                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3125                 } else {
3126                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3127                         tmp |= DC_HPDx_INT_ACK;
3128                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3129                 }
3130         }
3131         if (*disp_int & DC_HPD2_INTERRUPT) {
3132                 if (ASIC_IS_DCE3(rdev)) {
3133                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3134                         tmp |= DC_HPDx_INT_ACK;
3135                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3136                 } else {
3137                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3138                         tmp |= DC_HPDx_INT_ACK;
3139                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3140                 }
3141         }
3142         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3143                 if (ASIC_IS_DCE3(rdev)) {
3144                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3145                         tmp |= DC_HPDx_INT_ACK;
3146                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3147                 } else {
3148                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3149                         tmp |= DC_HPDx_INT_ACK;
3150                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3151                 }
3152         }
3153         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3154                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3155                 tmp |= DC_HPDx_INT_ACK;
3156                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3157         }
3158         if (ASIC_IS_DCE32(rdev)) {
3159                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3160                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3161                         tmp |= DC_HPDx_INT_ACK;
3162                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3163                 }
3164                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3165                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3166                         tmp |= DC_HPDx_INT_ACK;
3167                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3168                 }
3169         }
3170         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3171                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3172         }
3173         if (ASIC_IS_DCE3(rdev)) {
3174                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3175                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3176                 }
3177         } else {
3178                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3179                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3180                 }
3181         }
3182 }
3183
3184 void r600_irq_disable(struct radeon_device *rdev)
3185 {
3186         u32 disp_int, disp_int_cont, disp_int_cont2;
3187
3188         r600_disable_interrupts(rdev);
3189         /* Wait and acknowledge irq */
3190         mdelay(1);
3191         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3192         r600_disable_interrupt_state(rdev);
3193 }
3194
3195 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3196 {
3197         u32 wptr, tmp;
3198
3199         if (rdev->wb.enabled)
3200                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3201         else
3202                 wptr = RREG32(IH_RB_WPTR);
3203
3204         if (wptr & RB_OVERFLOW) {
3205                 /* When a ring buffer overflow happen start parsing interrupt
3206                  * from the last not overwritten vector (wptr + 16). Hopefully
3207                  * this should allow us to catchup.
3208                  */
3209                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3210                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3211                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3212                 tmp = RREG32(IH_RB_CNTL);
3213                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3214                 WREG32(IH_RB_CNTL, tmp);
3215         }
3216         return (wptr & rdev->ih.ptr_mask);
3217 }
3218
3219 /*        r600 IV Ring
3220  * Each IV ring entry is 128 bits:
3221  * [7:0]    - interrupt source id
3222  * [31:8]   - reserved
3223  * [59:32]  - interrupt source data
3224  * [127:60]  - reserved
3225  *
3226  * The basic interrupt vector entries
3227  * are decoded as follows:
3228  * src_id  src_data  description
3229  *      1         0  D1 Vblank
3230  *      1         1  D1 Vline
3231  *      5         0  D2 Vblank
3232  *      5         1  D2 Vline
3233  *     19         0  FP Hot plug detection A
3234  *     19         1  FP Hot plug detection B
3235  *     19         2  DAC A auto-detection
3236  *     19         3  DAC B auto-detection
3237  *     21         4  HDMI block A
3238  *     21         5  HDMI block B
3239  *    176         -  CP_INT RB
3240  *    177         -  CP_INT IB1
3241  *    178         -  CP_INT IB2
3242  *    181         -  EOP Interrupt
3243  *    233         -  GUI Idle
3244  *
3245  * Note, these are based on r600 and may need to be
3246  * adjusted or added to on newer asics
3247  */
3248
3249 int r600_irq_process(struct radeon_device *rdev)
3250 {
3251         u32 wptr = r600_get_ih_wptr(rdev);
3252         u32 rptr = rdev->ih.rptr;
3253         u32 src_id, src_data;
3254         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3255         unsigned long flags;
3256         bool queue_hotplug = false;
3257
3258         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3259         if (!rdev->ih.enabled)
3260                 return IRQ_NONE;
3261
3262         spin_lock_irqsave(&rdev->ih.lock, flags);
3263
3264         if (rptr == wptr) {
3265                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3266                 return IRQ_NONE;
3267         }
3268         if (rdev->shutdown) {
3269                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3270                 return IRQ_NONE;
3271         }
3272
3273 restart_ih:
3274         /* display interrupts */
3275         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3276
3277         rdev->ih.wptr = wptr;
3278         while (rptr != wptr) {
3279                 /* wptr/rptr are in bytes! */
3280                 ring_index = rptr / 4;
3281                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3282                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3283
3284                 switch (src_id) {
3285                 case 1: /* D1 vblank/vline */
3286                         switch (src_data) {
3287                         case 0: /* D1 vblank */
3288                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3289                                         drm_handle_vblank(rdev->ddev, 0);
3290                                         rdev->pm.vblank_sync = true;
3291                                         wake_up(&rdev->irq.vblank_queue);
3292                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3293                                         DRM_DEBUG("IH: D1 vblank\n");
3294                                 }
3295                                 break;
3296                         case 1: /* D1 vline */
3297                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3298                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3299                                         DRM_DEBUG("IH: D1 vline\n");
3300                                 }
3301                                 break;
3302                         default:
3303                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3304                                 break;
3305                         }
3306                         break;
3307                 case 5: /* D2 vblank/vline */
3308                         switch (src_data) {
3309                         case 0: /* D2 vblank */
3310                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3311                                         drm_handle_vblank(rdev->ddev, 1);
3312                                         rdev->pm.vblank_sync = true;
3313                                         wake_up(&rdev->irq.vblank_queue);
3314                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3315                                         DRM_DEBUG("IH: D2 vblank\n");
3316                                 }
3317                                 break;
3318                         case 1: /* D1 vline */
3319                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3320                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3321                                         DRM_DEBUG("IH: D2 vline\n");
3322                                 }
3323                                 break;
3324                         default:
3325                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3326                                 break;
3327                         }
3328                         break;
3329                 case 19: /* HPD/DAC hotplug */
3330                         switch (src_data) {
3331                         case 0:
3332                                 if (disp_int & DC_HPD1_INTERRUPT) {
3333                                         disp_int &= ~DC_HPD1_INTERRUPT;
3334                                         queue_hotplug = true;
3335                                         DRM_DEBUG("IH: HPD1\n");
3336                                 }
3337                                 break;
3338                         case 1:
3339                                 if (disp_int & DC_HPD2_INTERRUPT) {
3340                                         disp_int &= ~DC_HPD2_INTERRUPT;
3341                                         queue_hotplug = true;
3342                                         DRM_DEBUG("IH: HPD2\n");
3343                                 }
3344                                 break;
3345                         case 4:
3346                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3347                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3348                                         queue_hotplug = true;
3349                                         DRM_DEBUG("IH: HPD3\n");
3350                                 }
3351                                 break;
3352                         case 5:
3353                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3354                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3355                                         queue_hotplug = true;
3356                                         DRM_DEBUG("IH: HPD4\n");
3357                                 }
3358                                 break;
3359                         case 10:
3360                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3361                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3362                                         queue_hotplug = true;
3363                                         DRM_DEBUG("IH: HPD5\n");
3364                                 }
3365                                 break;
3366                         case 12:
3367                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3368                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3369                                         queue_hotplug = true;
3370                                         DRM_DEBUG("IH: HPD6\n");
3371                                 }
3372                                 break;
3373                         default:
3374                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3375                                 break;
3376                         }
3377                         break;
3378                 case 21: /* HDMI */
3379                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3380                         r600_audio_schedule_polling(rdev);
3381                         break;
3382                 case 176: /* CP_INT in ring buffer */
3383                 case 177: /* CP_INT in IB1 */
3384                 case 178: /* CP_INT in IB2 */
3385                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3386                         radeon_fence_process(rdev);
3387                         break;
3388                 case 181: /* CP EOP event */
3389                         DRM_DEBUG("IH: CP EOP\n");
3390                         radeon_fence_process(rdev);
3391                         break;
3392                 case 233: /* GUI IDLE */
3393                         DRM_DEBUG("IH: CP EOP\n");
3394                         rdev->pm.gui_idle = true;
3395                         wake_up(&rdev->irq.idle_queue);
3396                         break;
3397                 default:
3398                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3399                         break;
3400                 }
3401
3402                 /* wptr/rptr are in bytes! */
3403                 rptr += 16;
3404                 rptr &= rdev->ih.ptr_mask;
3405         }
3406         /* make sure wptr hasn't changed while processing */
3407         wptr = r600_get_ih_wptr(rdev);
3408         if (wptr != rdev->ih.wptr)
3409                 goto restart_ih;
3410         if (queue_hotplug)
3411                 queue_work(rdev->wq, &rdev->hotplug_work);
3412         rdev->ih.rptr = rptr;
3413         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3414         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3415         return IRQ_HANDLED;
3416 }
3417
3418 /*
3419  * Debugfs info
3420  */
3421 #if defined(CONFIG_DEBUG_FS)
3422
3423 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3424 {
3425         struct drm_info_node *node = (struct drm_info_node *) m->private;
3426         struct drm_device *dev = node->minor->dev;
3427         struct radeon_device *rdev = dev->dev_private;
3428         unsigned count, i, j;
3429
3430         radeon_ring_free_size(rdev);
3431         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3432         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3433         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3434         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3435         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3436         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3437         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3438         seq_printf(m, "%u dwords in ring\n", count);
3439         i = rdev->cp.rptr;
3440         for (j = 0; j <= count; j++) {
3441                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3442                 i = (i + 1) & rdev->cp.ptr_mask;
3443         }
3444         return 0;
3445 }
3446
3447 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3448 {
3449         struct drm_info_node *node = (struct drm_info_node *) m->private;
3450         struct drm_device *dev = node->minor->dev;
3451         struct radeon_device *rdev = dev->dev_private;
3452
3453         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3454         DREG32_SYS(m, rdev, VM_L2_STATUS);
3455         return 0;
3456 }
3457
3458 static struct drm_info_list r600_mc_info_list[] = {
3459         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3460         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3461 };
3462 #endif
3463
3464 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3465 {
3466 #if defined(CONFIG_DEBUG_FS)
3467         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3468 #else
3469         return 0;
3470 #endif
3471 }
3472
3473 /**
3474  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3475  * rdev: radeon device structure
3476  * bo: buffer object struct which userspace is waiting for idle
3477  *
3478  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3479  * through ring buffer, this leads to corruption in rendering, see
3480  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3481  * directly perform HDP flush by writing register through MMIO.
3482  */
3483 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3484 {
3485         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3486          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3487          */
3488         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3489             rdev->vram_scratch.ptr) {
3490                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3491                 u32 tmp;
3492
3493                 WREG32(HDP_DEBUG1, 0);
3494                 tmp = readl((void __iomem *)ptr);
3495         } else
3496                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3497 }