Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[pandora-kernel.git] / drivers / gpu / drm / radeon / r420.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "r100d.h"
36 #include "r420d.h"
37 #include "r420_reg_safe.h"
38
39 void r420_pm_init_profile(struct radeon_device *rdev)
40 {
41         /* default */
42         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
46         /* low sh */
47         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
51         /* mid sh */
52         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
56         /* high sh */
57         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
61         /* low mh */
62         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
66         /* mid mh */
67         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
71         /* high mh */
72         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
76 }
77
78 static void r420_set_reg_safe(struct radeon_device *rdev)
79 {
80         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
82 }
83
84 void r420_pipes_init(struct radeon_device *rdev)
85 {
86         unsigned tmp;
87         unsigned gb_pipe_select;
88         unsigned num_pipes;
89
90         /* GA_ENHANCE workaround TCL deadlock issue */
91         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
92                (1 << 2) | (1 << 3));
93         /* add idle wait as per freedesktop.org bug 24041 */
94         if (r100_gui_wait_for_idle(rdev)) {
95                 printk(KERN_WARNING "Failed to wait GUI idle while "
96                        "programming pipes. Bad things might happen.\n");
97         }
98         /* get max number of pipes */
99         gb_pipe_select = RREG32(0x402C);
100         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
101
102         /* SE chips have 1 pipe */
103         if ((rdev->pdev->device == 0x5e4c) ||
104             (rdev->pdev->device == 0x5e4f))
105                 num_pipes = 1;
106
107         rdev->num_gb_pipes = num_pipes;
108         tmp = 0;
109         switch (num_pipes) {
110         default:
111                 /* force to 1 pipe */
112                 num_pipes = 1;
113         case 1:
114                 tmp = (0 << 1);
115                 break;
116         case 2:
117                 tmp = (3 << 1);
118                 break;
119         case 3:
120                 tmp = (6 << 1);
121                 break;
122         case 4:
123                 tmp = (7 << 1);
124                 break;
125         }
126         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
127         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
128         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
129         WREG32(R300_GB_TILE_CONFIG, tmp);
130         if (r100_gui_wait_for_idle(rdev)) {
131                 printk(KERN_WARNING "Failed to wait GUI idle while "
132                        "programming pipes. Bad things might happen.\n");
133         }
134
135         tmp = RREG32(R300_DST_PIPE_CONFIG);
136         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
137
138         WREG32(R300_RB2D_DSTCACHE_MODE,
139                RREG32(R300_RB2D_DSTCACHE_MODE) |
140                R300_DC_AUTOFLUSH_ENABLE |
141                R300_DC_DC_DISABLE_IGNORE_PE);
142
143         if (r100_gui_wait_for_idle(rdev)) {
144                 printk(KERN_WARNING "Failed to wait GUI idle while "
145                        "programming pipes. Bad things might happen.\n");
146         }
147
148         if (rdev->family == CHIP_RV530) {
149                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
150                 if ((tmp & 3) == 3)
151                         rdev->num_z_pipes = 2;
152                 else
153                         rdev->num_z_pipes = 1;
154         } else
155                 rdev->num_z_pipes = 1;
156
157         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
158                  rdev->num_gb_pipes, rdev->num_z_pipes);
159 }
160
161 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
162 {
163         u32 r;
164
165         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
166         r = RREG32(R_0001FC_MC_IND_DATA);
167         return r;
168 }
169
170 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
171 {
172         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
173                 S_0001F8_MC_IND_WR_EN(1));
174         WREG32(R_0001FC_MC_IND_DATA, v);
175 }
176
177 static void r420_debugfs(struct radeon_device *rdev)
178 {
179         if (r100_debugfs_rbbm_init(rdev)) {
180                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
181         }
182         if (r420_debugfs_pipes_info_init(rdev)) {
183                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
184         }
185 }
186
187 static void r420_clock_resume(struct radeon_device *rdev)
188 {
189         u32 sclk_cntl;
190
191         if (radeon_dynclks != -1 && radeon_dynclks)
192                 radeon_atom_set_clock_gating(rdev, 1);
193         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
194         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
195         if (rdev->family == CHIP_R420)
196                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
197         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
198 }
199
200 static void r420_cp_errata_init(struct radeon_device *rdev)
201 {
202         /* RV410 and R420 can lock up if CP DMA to host memory happens
203          * while the 2D engine is busy.
204          *
205          * The proper workaround is to queue a RESYNC at the beginning
206          * of the CP init, apparently.
207          */
208         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
209         radeon_ring_lock(rdev, 8);
210         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
211         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
212         radeon_ring_write(rdev, 0xDEADBEEF);
213         radeon_ring_unlock_commit(rdev);
214 }
215
216 static void r420_cp_errata_fini(struct radeon_device *rdev)
217 {
218         /* Catch the RESYNC we dispatched all the way back,
219          * at the very beginning of the CP init.
220          */
221         radeon_ring_lock(rdev, 8);
222         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
223         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
224         radeon_ring_unlock_commit(rdev);
225         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
226 }
227
228 static int r420_startup(struct radeon_device *rdev)
229 {
230         int r;
231
232         /* set common regs */
233         r100_set_common_regs(rdev);
234         /* program mc */
235         r300_mc_program(rdev);
236         /* Resume clock */
237         r420_clock_resume(rdev);
238         /* Initialize GART (initialize after TTM so we can allocate
239          * memory through TTM but finalize after TTM) */
240         if (rdev->flags & RADEON_IS_PCIE) {
241                 r = rv370_pcie_gart_enable(rdev);
242                 if (r)
243                         return r;
244         }
245         if (rdev->flags & RADEON_IS_PCI) {
246                 r = r100_pci_gart_enable(rdev);
247                 if (r)
248                         return r;
249         }
250         r420_pipes_init(rdev);
251
252         /* allocate wb buffer */
253         r = radeon_wb_init(rdev);
254         if (r)
255                 return r;
256
257         /* Enable IRQ */
258         r100_irq_set(rdev);
259         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
260         /* 1M ring buffer */
261         r = r100_cp_init(rdev, 1024 * 1024);
262         if (r) {
263                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
264                 return r;
265         }
266         r420_cp_errata_init(rdev);
267         r = r100_ib_init(rdev);
268         if (r) {
269                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
270                 return r;
271         }
272         return 0;
273 }
274
275 int r420_resume(struct radeon_device *rdev)
276 {
277         /* Make sur GART are not working */
278         if (rdev->flags & RADEON_IS_PCIE)
279                 rv370_pcie_gart_disable(rdev);
280         if (rdev->flags & RADEON_IS_PCI)
281                 r100_pci_gart_disable(rdev);
282         /* Resume clock before doing reset */
283         r420_clock_resume(rdev);
284         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
285         if (radeon_asic_reset(rdev)) {
286                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
287                         RREG32(R_000E40_RBBM_STATUS),
288                         RREG32(R_0007C0_CP_STAT));
289         }
290         /* check if cards are posted or not */
291         if (rdev->is_atom_bios) {
292                 atom_asic_init(rdev->mode_info.atom_context);
293         } else {
294                 radeon_combios_asic_init(rdev->ddev);
295         }
296         /* Resume clock after posting */
297         r420_clock_resume(rdev);
298         /* Initialize surface registers */
299         radeon_surface_init(rdev);
300         return r420_startup(rdev);
301 }
302
303 int r420_suspend(struct radeon_device *rdev)
304 {
305         r420_cp_errata_fini(rdev);
306         r100_cp_disable(rdev);
307         radeon_wb_disable(rdev);
308         r100_irq_disable(rdev);
309         if (rdev->flags & RADEON_IS_PCIE)
310                 rv370_pcie_gart_disable(rdev);
311         if (rdev->flags & RADEON_IS_PCI)
312                 r100_pci_gart_disable(rdev);
313         return 0;
314 }
315
316 void r420_fini(struct radeon_device *rdev)
317 {
318         r100_cp_fini(rdev);
319         radeon_wb_fini(rdev);
320         r100_ib_fini(rdev);
321         radeon_gem_fini(rdev);
322         if (rdev->flags & RADEON_IS_PCIE)
323                 rv370_pcie_gart_fini(rdev);
324         if (rdev->flags & RADEON_IS_PCI)
325                 r100_pci_gart_fini(rdev);
326         radeon_agp_fini(rdev);
327         radeon_irq_kms_fini(rdev);
328         radeon_fence_driver_fini(rdev);
329         radeon_bo_fini(rdev);
330         if (rdev->is_atom_bios) {
331                 radeon_atombios_fini(rdev);
332         } else {
333                 radeon_combios_fini(rdev);
334         }
335         kfree(rdev->bios);
336         rdev->bios = NULL;
337 }
338
339 int r420_init(struct radeon_device *rdev)
340 {
341         int r;
342
343         /* Initialize scratch registers */
344         radeon_scratch_init(rdev);
345         /* Initialize surface registers */
346         radeon_surface_init(rdev);
347         /* TODO: disable VGA need to use VGA request */
348         /* restore some register to sane defaults */
349         r100_restore_sanity(rdev);
350         /* BIOS*/
351         if (!radeon_get_bios(rdev)) {
352                 if (ASIC_IS_AVIVO(rdev))
353                         return -EINVAL;
354         }
355         if (rdev->is_atom_bios) {
356                 r = radeon_atombios_init(rdev);
357                 if (r) {
358                         return r;
359                 }
360         } else {
361                 r = radeon_combios_init(rdev);
362                 if (r) {
363                         return r;
364                 }
365         }
366         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
367         if (radeon_asic_reset(rdev)) {
368                 dev_warn(rdev->dev,
369                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
370                         RREG32(R_000E40_RBBM_STATUS),
371                         RREG32(R_0007C0_CP_STAT));
372         }
373         /* check if cards are posted or not */
374         if (radeon_boot_test_post_card(rdev) == false)
375                 return -EINVAL;
376
377         /* Initialize clocks */
378         radeon_get_clock_info(rdev->ddev);
379         /* initialize AGP */
380         if (rdev->flags & RADEON_IS_AGP) {
381                 r = radeon_agp_init(rdev);
382                 if (r) {
383                         radeon_agp_disable(rdev);
384                 }
385         }
386         /* initialize memory controller */
387         r300_mc_init(rdev);
388         r420_debugfs(rdev);
389         /* Fence driver */
390         r = radeon_fence_driver_init(rdev);
391         if (r) {
392                 return r;
393         }
394         r = radeon_irq_kms_init(rdev);
395         if (r) {
396                 return r;
397         }
398         /* Memory manager */
399         r = radeon_bo_init(rdev);
400         if (r) {
401                 return r;
402         }
403         if (rdev->family == CHIP_R420)
404                 r100_enable_bm(rdev);
405
406         if (rdev->flags & RADEON_IS_PCIE) {
407                 r = rv370_pcie_gart_init(rdev);
408                 if (r)
409                         return r;
410         }
411         if (rdev->flags & RADEON_IS_PCI) {
412                 r = r100_pci_gart_init(rdev);
413                 if (r)
414                         return r;
415         }
416         r420_set_reg_safe(rdev);
417         rdev->accel_working = true;
418         r = r420_startup(rdev);
419         if (r) {
420                 /* Somethings want wront with the accel init stop accel */
421                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
422                 r100_cp_fini(rdev);
423                 radeon_wb_fini(rdev);
424                 r100_ib_fini(rdev);
425                 radeon_irq_kms_fini(rdev);
426                 if (rdev->flags & RADEON_IS_PCIE)
427                         rv370_pcie_gart_fini(rdev);
428                 if (rdev->flags & RADEON_IS_PCI)
429                         r100_pci_gart_fini(rdev);
430                 radeon_agp_fini(rdev);
431                 rdev->accel_working = false;
432         }
433         return 0;
434 }
435
436 /*
437  * Debugfs info
438  */
439 #if defined(CONFIG_DEBUG_FS)
440 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
441 {
442         struct drm_info_node *node = (struct drm_info_node *) m->private;
443         struct drm_device *dev = node->minor->dev;
444         struct radeon_device *rdev = dev->dev_private;
445         uint32_t tmp;
446
447         tmp = RREG32(R400_GB_PIPE_SELECT);
448         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
449         tmp = RREG32(R300_GB_TILE_CONFIG);
450         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
451         tmp = RREG32(R300_DST_PIPE_CONFIG);
452         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
453         return 0;
454 }
455
456 static struct drm_info_list r420_pipes_info_list[] = {
457         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
458 };
459 #endif
460
461 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
462 {
463 #if defined(CONFIG_DEBUG_FS)
464         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
465 #else
466         return 0;
467 #endif
468 }