drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "radeon_drm.h"
  36 #include "r100_track.h"
  37 #include "r300d.h"
  38 #include "rv350d.h"
  39 #include "r300_reg_safe.h"
  40
  41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  42  *
  43  * GPU Errata:
  44  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  45  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  46  *   However, scheduling such write to the ring seems harmless, i suspect
  47  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  48  *   tell. (Jerome Glisse)
  49  */
  50
  51 /*
  52  * rv370,rv380 PCIE GART
  53  */
  54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  55
  56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  57 {
  58         uint32_t tmp;
  59         int i;
  60
  61         /* Workaround HW bug do flush 2 times */
  62         for (i = 0; i < 2; i++) {
  63                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  64                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  65                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  66                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  67         }
  68         mb();
  69 }
  70
  71 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  72 {
  73         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  74
  75         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  76                 return -EINVAL;
  77         }
  78         addr = (lower_32_bits(addr) >> 8) |
  79                ((upper_32_bits(addr) & 0xff) << 24) |
  80                0xc;
  81         /* on x86 we want this to be CPU endian, on powerpc
  82          * on powerpc without HW swappers, it'll get swapped on way
  83          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  84         writel(addr, ((void __iomem *)ptr) + (i * 4));
  85         return 0;
  86 }
  87
  88 int rv370_pcie_gart_init(struct radeon_device *rdev)
  89 {
  90         int r;
  91
  92         if (rdev->gart.table.vram.robj) {
  93                 WARN(1, "RV370 PCIE GART already initialized.\n");
  94                 return 0;
  95         }
  96         /* Initialize common gart structure */
  97         r = radeon_gart_init(rdev);
  98         if (r)
  99                 return r;
 100         r = rv370_debugfs_pcie_gart_info_init(rdev);
 101         if (r)
 102                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 103         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 104         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 105         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 106         return radeon_gart_table_vram_alloc(rdev);
 107 }
 108
 109 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 110 {
 111         uint32_t table_addr;
 112         uint32_t tmp;
 113         int r;
 114
 115         if (rdev->gart.table.vram.robj == NULL) {
 116                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 117                 return -EINVAL;
 118         }
 119         r = radeon_gart_table_vram_pin(rdev);
 120         if (r)
 121                 return r;
 122         radeon_gart_restore(rdev);
 123         /* discard memory request outside of configured range */
 124         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 125         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 126         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 127         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 128         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 129         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 130         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 131         table_addr = rdev->gart.table_addr;
 132         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 133         /* FIXME: setup default page */
 134         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 135         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 136         /* Clear error */
 137         WREG32_PCIE(0x18, 0);
 138         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 139         tmp |= RADEON_PCIE_TX_GART_EN;
 140         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 141         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 142         rv370_pcie_gart_tlb_flush(rdev);
 143         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
 144                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
 145         rdev->gart.ready = true;
 146         return 0;
 147 }
 148
 149 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 150 {
 151         u32 tmp;
 152         int r;
 153
 154         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 155         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 156         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 157         if (rdev->gart.table.vram.robj) {
 158                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 159                 if (likely(r == 0)) {
 160                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 161                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 162                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 163                 }
 164         }
 165 }
 166
 167 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 168 {
 169         radeon_gart_fini(rdev);
 170         rv370_pcie_gart_disable(rdev);
 171         radeon_gart_table_vram_free(rdev);
 172 }
 173
 174 void r300_fence_ring_emit(struct radeon_device *rdev,
 175                           struct radeon_fence *fence)
 176 {
 177         /* Who ever call radeon_fence_emit should call ring_lock and ask
 178          * for enough space (today caller are ib schedule and buffer move) */
 179         /* Write SC register so SC & US assert idle */
 180         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
 181         radeon_ring_write(rdev, 0);
 182         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
 183         radeon_ring_write(rdev, 0);
 184         /* Flush 3D cache */
 185         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 186         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
 187         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 188         radeon_ring_write(rdev, R300_ZC_FLUSH);
 189         /* Wait until IDLE & CLEAN */
 190         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 191         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
 192                                  RADEON_WAIT_2D_IDLECLEAN |
 193                                  RADEON_WAIT_DMA_GUI_IDLE));
 194         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 195         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
 196                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 197         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 198         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
 199         /* Emit fence sequence & fire IRQ */
 200         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 201         radeon_ring_write(rdev, fence->seq);
 202         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 203         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 204 }
 205
 206 void r300_ring_start(struct radeon_device *rdev)
 207 {
 208         unsigned gb_tile_config;
 209         int r;
 210
 211         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 212         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 213         switch(rdev->num_gb_pipes) {
 214         case 2:
 215                 gb_tile_config |= R300_PIPE_COUNT_R300;
 216                 break;
 217         case 3:
 218                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 219                 break;
 220         case 4:
 221                 gb_tile_config |= R300_PIPE_COUNT_R420;
 222                 break;
 223         case 1:
 224         default:
 225                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 226                 break;
 227         }
 228
 229         r = radeon_ring_lock(rdev, 64);
 230         if (r) {
 231                 return;
 232         }
 233         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 234         radeon_ring_write(rdev,
 235                           RADEON_ISYNC_ANY2D_IDLE3D |
 236                           RADEON_ISYNC_ANY3D_IDLE2D |
 237                           RADEON_ISYNC_WAIT_IDLEGUI |
 238                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 239         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
 240         radeon_ring_write(rdev, gb_tile_config);
 241         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 242         radeon_ring_write(rdev,
 243                           RADEON_WAIT_2D_IDLECLEAN |
 244                           RADEON_WAIT_3D_IDLECLEAN);
 245         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
 246         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
 247         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
 248         radeon_ring_write(rdev, 0);
 249         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
 250         radeon_ring_write(rdev, 0);
 251         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 252         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 253         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 254         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 255         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 256         radeon_ring_write(rdev,
 257                           RADEON_WAIT_2D_IDLECLEAN |
 258                           RADEON_WAIT_3D_IDLECLEAN);
 259         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
 260         radeon_ring_write(rdev, 0);
 261         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 262         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 263         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 264         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 265         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
 266         radeon_ring_write(rdev,
 267                           ((6 << R300_MS_X0_SHIFT) |
 268                            (6 << R300_MS_Y0_SHIFT) |
 269                            (6 << R300_MS_X1_SHIFT) |
 270                            (6 << R300_MS_Y1_SHIFT) |
 271                            (6 << R300_MS_X2_SHIFT) |
 272                            (6 << R300_MS_Y2_SHIFT) |
 273                            (6 << R300_MSBD0_Y_SHIFT) |
 274                            (6 << R300_MSBD0_X_SHIFT)));
 275         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
 276         radeon_ring_write(rdev,
 277                           ((6 << R300_MS_X3_SHIFT) |
 278                            (6 << R300_MS_Y3_SHIFT) |
 279                            (6 << R300_MS_X4_SHIFT) |
 280                            (6 << R300_MS_Y4_SHIFT) |
 281                            (6 << R300_MS_X5_SHIFT) |
 282                            (6 << R300_MS_Y5_SHIFT) |
 283                            (6 << R300_MSBD1_SHIFT)));
 284         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
 285         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 286         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
 287         radeon_ring_write(rdev,
 288                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 289         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
 290         radeon_ring_write(rdev,
 291                           R300_GEOMETRY_ROUND_NEAREST |
 292                           R300_COLOR_ROUND_NEAREST);
 293         radeon_ring_unlock_commit(rdev);
 294 }
 295
 296 void r300_errata(struct radeon_device *rdev)
 297 {
 298         rdev->pll_errata = 0;
 299
 300         if (rdev->family == CHIP_R300 &&
 301             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 302                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 303         }
 304 }
 305
 306 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 307 {
 308         unsigned i;
 309         uint32_t tmp;
 310
 311         for (i = 0; i < rdev->usec_timeout; i++) {
 312                 /* read MC_STATUS */
 313                 tmp = RREG32(RADEON_MC_STATUS);
 314                 if (tmp & R300_MC_IDLE) {
 315                         return 0;
 316                 }
 317                 DRM_UDELAY(1);
 318         }
 319         return -1;
 320 }
 321
 322 void r300_gpu_init(struct radeon_device *rdev)
 323 {
 324         uint32_t gb_tile_config, tmp;
 325
 326         r100_hdp_reset(rdev);
 327         /* FIXME: rv380 one pipes ? */
 328         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 329             (rdev->family == CHIP_R350)) {
 330                 /* r300,r350 */
 331                 rdev->num_gb_pipes = 2;
 332         } else {
 333                 /* rv350,rv370,rv380,r300 AD */
 334                 rdev->num_gb_pipes = 1;
 335         }
 336         rdev->num_z_pipes = 1;
 337         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 338         switch (rdev->num_gb_pipes) {
 339         case 2:
 340                 gb_tile_config |= R300_PIPE_COUNT_R300;
 341                 break;
 342         case 3:
 343                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 344                 break;
 345         case 4:
 346                 gb_tile_config |= R300_PIPE_COUNT_R420;
 347                 break;
 348         default:
 349         case 1:
 350                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 351                 break;
 352         }
 353         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 354
 355         if (r100_gui_wait_for_idle(rdev)) {
 356                 printk(KERN_WARNING "Failed to wait GUI idle while "
 357                        "programming pipes. Bad things might happen.\n");
 358         }
 359
 360         tmp = RREG32(R300_DST_PIPE_CONFIG);
 361         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 362
 363         WREG32(R300_RB2D_DSTCACHE_MODE,
 364                R300_DC_AUTOFLUSH_ENABLE |
 365                R300_DC_DC_DISABLE_IGNORE_PE);
 366
 367         if (r100_gui_wait_for_idle(rdev)) {
 368                 printk(KERN_WARNING "Failed to wait GUI idle while "
 369                        "programming pipes. Bad things might happen.\n");
 370         }
 371         if (r300_mc_wait_for_idle(rdev)) {
 372                 printk(KERN_WARNING "Failed to wait MC idle while "
 373                        "programming pipes. Bad things might happen.\n");
 374         }
 375         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 376                  rdev->num_gb_pipes, rdev->num_z_pipes);
 377 }
 378
 379 int r300_ga_reset(struct radeon_device *rdev)
 380 {
 381         uint32_t tmp;
 382         bool reinit_cp;
 383         int i;
 384
 385         reinit_cp = rdev->cp.ready;
 386         rdev->cp.ready = false;
 387         for (i = 0; i < rdev->usec_timeout; i++) {
 388                 WREG32(RADEON_CP_CSQ_MODE, 0);
 389                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 390                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
 391                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
 392                 udelay(200);
 393                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 394                 /* Wait to prevent race in RBBM_STATUS */
 395                 mdelay(1);
 396                 tmp = RREG32(RADEON_RBBM_STATUS);
 397                 if (tmp & ((1 << 20) | (1 << 26))) {
 398                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
 399                         /* GA still busy soft reset it */
 400                         WREG32(0x429C, 0x200);
 401                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 402                         WREG32(R300_RE_SCISSORS_TL, 0);
 403                         WREG32(R300_RE_SCISSORS_BR, 0);
 404                         WREG32(0x24AC, 0);
 405                 }
 406                 /* Wait to prevent race in RBBM_STATUS */
 407                 mdelay(1);
 408                 tmp = RREG32(RADEON_RBBM_STATUS);
 409                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 410                         break;
 411                 }
 412         }
 413         for (i = 0; i < rdev->usec_timeout; i++) {
 414                 tmp = RREG32(RADEON_RBBM_STATUS);
 415                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 416                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 417                                  tmp);
 418                         if (reinit_cp) {
 419                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 420                         }
 421                         return 0;
 422                 }
 423                 DRM_UDELAY(1);
 424         }
 425         tmp = RREG32(RADEON_RBBM_STATUS);
 426         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 427         return -1;
 428 }
 429
 430 int r300_gpu_reset(struct radeon_device *rdev)
 431 {
 432         uint32_t status;
 433
 434         /* reset order likely matter */
 435         status = RREG32(RADEON_RBBM_STATUS);
 436         /* reset HDP */
 437         r100_hdp_reset(rdev);
 438         /* reset rb2d */
 439         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 440                 r100_rb2d_reset(rdev);
 441         }
 442         /* reset GA */
 443         if (status & ((1 << 20) | (1 << 26))) {
 444                 r300_ga_reset(rdev);
 445         }
 446         /* reset CP */
 447         status = RREG32(RADEON_RBBM_STATUS);
 448         if (status & (1 << 16)) {
 449                 r100_cp_reset(rdev);
 450         }
 451         /* Check if GPU is idle */
 452         status = RREG32(RADEON_RBBM_STATUS);
 453         if (status & RADEON_RBBM_ACTIVE) {
 454                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 455                 return -1;
 456         }
 457         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 458         return 0;
 459 }
 460
 461
 462 /*
 463  * r300,r350,rv350,rv380 VRAM info
 464  */
 465 void r300_mc_init(struct radeon_device *rdev)
 466 {
 467         u64 base;
 468         u32 tmp;
 469
 470         /* DDR for all card after R300 & IGP */
 471         rdev->mc.vram_is_ddr = true;
 472         tmp = RREG32(RADEON_MEM_CNTL);
 473         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 474         switch (tmp) {
 475         case 0: rdev->mc.vram_width = 64; break;
 476         case 1: rdev->mc.vram_width = 128; break;
 477         case 2: rdev->mc.vram_width = 256; break;
 478         default:  rdev->mc.vram_width = 128; break;
 479         }
 480         r100_vram_init_sizes(rdev);
 481         base = rdev->mc.aper_base;
 482         if (rdev->flags & RADEON_IS_IGP)
 483                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 484         radeon_vram_location(rdev, &rdev->mc, base);
 485         if (!(rdev->flags & RADEON_IS_AGP))
 486                 radeon_gtt_location(rdev, &rdev->mc);
 487         radeon_update_bandwidth_info(rdev);
 488 }
 489
 490 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 491 {
 492         uint32_t link_width_cntl, mask;
 493
 494         if (rdev->flags & RADEON_IS_IGP)
 495                 return;
 496
 497         if (!(rdev->flags & RADEON_IS_PCIE))
 498                 return;
 499
 500         /* FIXME wait for idle */
 501
 502         switch (lanes) {
 503         case 0:
 504                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 505                 break;
 506         case 1:
 507                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 508                 break;
 509         case 2:
 510                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 511                 break;
 512         case 4:
 513                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 514                 break;
 515         case 8:
 516                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 517                 break;
 518         case 12:
 519                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 520                 break;
 521         case 16:
 522         default:
 523                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 524                 break;
 525         }
 526
 527         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 528
 529         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 530             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 531                 return;
 532
 533         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 534                              RADEON_PCIE_LC_RECONFIG_NOW |
 535                              RADEON_PCIE_LC_RECONFIG_LATER |
 536                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 537         link_width_cntl |= mask;
 538         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 539         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 540                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 541
 542         /* wait for lane set to complete */
 543         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 544         while (link_width_cntl == 0xffffffff)
 545                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 546
 547 }
 548
 549 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 550 {
 551         u32 link_width_cntl;
 552
 553         if (rdev->flags & RADEON_IS_IGP)
 554                 return 0;
 555
 556         if (!(rdev->flags & RADEON_IS_PCIE))
 557                 return 0;
 558
 559         /* FIXME wait for idle */
 560
 561         if (rdev->family < CHIP_R600)
 562                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 563         else
 564                 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 565
 566         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 567         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 568                 return 0;
 569         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 570                 return 1;
 571         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 572                 return 2;
 573         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 574                 return 4;
 575         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 576                 return 8;
 577         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 578         default:
 579                 return 16;
 580         }
 581 }
 582
 583 #if defined(CONFIG_DEBUG_FS)
 584 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 585 {
 586         struct drm_info_node *node = (struct drm_info_node *) m->private;
 587         struct drm_device *dev = node->minor->dev;
 588         struct radeon_device *rdev = dev->dev_private;
 589         uint32_t tmp;
 590
 591         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 592         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 593         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 594         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 595         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 596         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 597         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 598         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 599         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 600         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 601         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 602         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 603         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 604         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 605         return 0;
 606 }
 607
 608 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 609         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 610 };
 611 #endif
 612
 613 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 614 {
 615 #if defined(CONFIG_DEBUG_FS)
 616         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 617 #else
 618         return 0;
 619 #endif
 620 }
 621
 622 static int r300_packet0_check(struct radeon_cs_parser *p,
 623                 struct radeon_cs_packet *pkt,
 624                 unsigned idx, unsigned reg)
 625 {
 626         struct radeon_cs_reloc *reloc;
 627         struct r100_cs_track *track;
 628         volatile uint32_t *ib;
 629         uint32_t tmp, tile_flags = 0;
 630         unsigned i;
 631         int r;
 632         u32 idx_value;
 633
 634         ib = p->ib->ptr;
 635         track = (struct r100_cs_track *)p->track;
 636         idx_value = radeon_get_ib_value(p, idx);
 637
 638         switch(reg) {
 639         case AVIVO_D1MODE_VLINE_START_END:
 640         case RADEON_CRTC_GUI_TRIG_VLINE:
 641                 r = r100_cs_packet_parse_vline(p);
 642                 if (r) {
 643                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 644                                         idx, reg);
 645                         r100_cs_dump_packet(p, pkt);
 646                         return r;
 647                 }
 648                 break;
 649         case RADEON_DST_PITCH_OFFSET:
 650         case RADEON_SRC_PITCH_OFFSET:
 651                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 652                 if (r)
 653                         return r;
 654                 break;
 655         case R300_RB3D_COLOROFFSET0:
 656         case R300_RB3D_COLOROFFSET1:
 657         case R300_RB3D_COLOROFFSET2:
 658         case R300_RB3D_COLOROFFSET3:
 659                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 660                 r = r100_cs_packet_next_reloc(p, &reloc);
 661                 if (r) {
 662                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 663                                         idx, reg);
 664                         r100_cs_dump_packet(p, pkt);
 665                         return r;
 666                 }
 667                 track->cb[i].robj = reloc->robj;
 668                 track->cb[i].offset = idx_value;
 669                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 670                 break;
 671         case R300_ZB_DEPTHOFFSET:
 672                 r = r100_cs_packet_next_reloc(p, &reloc);
 673                 if (r) {
 674                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 675                                         idx, reg);
 676                         r100_cs_dump_packet(p, pkt);
 677                         return r;
 678                 }
 679                 track->zb.robj = reloc->robj;
 680                 track->zb.offset = idx_value;
 681                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 682                 break;
 683         case R300_TX_OFFSET_0:
 684         case R300_TX_OFFSET_0+4:
 685         case R300_TX_OFFSET_0+8:
 686         case R300_TX_OFFSET_0+12:
 687         case R300_TX_OFFSET_0+16:
 688         case R300_TX_OFFSET_0+20:
 689         case R300_TX_OFFSET_0+24:
 690         case R300_TX_OFFSET_0+28:
 691         case R300_TX_OFFSET_0+32:
 692         case R300_TX_OFFSET_0+36:
 693         case R300_TX_OFFSET_0+40:
 694         case R300_TX_OFFSET_0+44:
 695         case R300_TX_OFFSET_0+48:
 696         case R300_TX_OFFSET_0+52:
 697         case R300_TX_OFFSET_0+56:
 698         case R300_TX_OFFSET_0+60:
 699                 i = (reg - R300_TX_OFFSET_0) >> 2;
 700                 r = r100_cs_packet_next_reloc(p, &reloc);
 701                 if (r) {
 702                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 703                                         idx, reg);
 704                         r100_cs_dump_packet(p, pkt);
 705                         return r;
 706                 }
 707
 708                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 709                         tile_flags |= R300_TXO_MACRO_TILE;
 710                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 711                         tile_flags |= R300_TXO_MICRO_TILE;
 712                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 713                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 714
 715                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
 716                 tmp |= tile_flags;
 717                 ib[idx] = tmp;
 718                 track->textures[i].robj = reloc->robj;
 719                 break;
 720         /* Tracked registers */
 721         case 0x2084:
 722                 /* VAP_VF_CNTL */
 723                 track->vap_vf_cntl = idx_value;
 724                 break;
 725         case 0x20B4:
 726                 /* VAP_VTX_SIZE */
 727                 track->vtx_size = idx_value & 0x7F;
 728                 break;
 729         case 0x2134:
 730                 /* VAP_VF_MAX_VTX_INDX */
 731                 track->max_indx = idx_value & 0x00FFFFFFUL;
 732                 break;
 733         case 0x2088:
 734                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 735                 if (p->rdev->family < CHIP_RV515)
 736                         goto fail;
 737                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 738                 break;
 739         case 0x43E4:
 740                 /* SC_SCISSOR1 */
 741                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 742                 if (p->rdev->family < CHIP_RV515) {
 743                         track->maxy -= 1440;
 744                 }
 745                 break;
 746         case 0x4E00:
 747                 /* RB3D_CCTL */
 748                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 749                 break;
 750         case 0x4E38:
 751         case 0x4E3C:
 752         case 0x4E40:
 753         case 0x4E44:
 754                 /* RB3D_COLORPITCH0 */
 755                 /* RB3D_COLORPITCH1 */
 756                 /* RB3D_COLORPITCH2 */
 757                 /* RB3D_COLORPITCH3 */
 758                 r = r100_cs_packet_next_reloc(p, &reloc);
 759                 if (r) {
 760                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 761                                   idx, reg);
 762                         r100_cs_dump_packet(p, pkt);
 763                         return r;
 764                 }
 765
 766                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 767                         tile_flags |= R300_COLOR_TILE_ENABLE;
 768                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 769                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 770                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 771                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 772
 773                 tmp = idx_value & ~(0x7 << 16);
 774                 tmp |= tile_flags;
 775                 ib[idx] = tmp;
 776                 i = (reg - 0x4E38) >> 2;
 777                 track->cb[i].pitch = idx_value & 0x3FFE;
 778                 switch (((idx_value >> 21) & 0xF)) {
 779                 case 9:
 780                 case 11:
 781                 case 12:
 782                         track->cb[i].cpp = 1;
 783                         break;
 784                 case 3:
 785                 case 4:
 786                 case 13:
 787                 case 15:
 788                         track->cb[i].cpp = 2;
 789                         break;
 790                 case 6:
 791                         track->cb[i].cpp = 4;
 792                         break;
 793                 case 10:
 794                         track->cb[i].cpp = 8;
 795                         break;
 796                 case 7:
 797                         track->cb[i].cpp = 16;
 798                         break;
 799                 default:
 800                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 801                                   ((idx_value >> 21) & 0xF));
 802                         return -EINVAL;
 803                 }
 804                 break;
 805         case 0x4F00:
 806                 /* ZB_CNTL */
 807                 if (idx_value & 2) {
 808                         track->z_enabled = true;
 809                 } else {
 810                         track->z_enabled = false;
 811                 }
 812                 break;
 813         case 0x4F10:
 814                 /* ZB_FORMAT */
 815                 switch ((idx_value & 0xF)) {
 816                 case 0:
 817                 case 1:
 818                         track->zb.cpp = 2;
 819                         break;
 820                 case 2:
 821                         track->zb.cpp = 4;
 822                         break;
 823                 default:
 824                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 825                                   (idx_value & 0xF));
 826                         return -EINVAL;
 827                 }
 828                 break;
 829         case 0x4F24:
 830                 /* ZB_DEPTHPITCH */
 831                 r = r100_cs_packet_next_reloc(p, &reloc);
 832                 if (r) {
 833                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 834                                   idx, reg);
 835                         r100_cs_dump_packet(p, pkt);
 836                         return r;
 837                 }
 838
 839                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 840                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 841                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 842                         tile_flags |= R300_DEPTHMICROTILE_TILED;
 843                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 844                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 845
 846                 tmp = idx_value & ~(0x7 << 16);
 847                 tmp |= tile_flags;
 848                 ib[idx] = tmp;
 849
 850                 track->zb.pitch = idx_value & 0x3FFC;
 851                 break;
 852         case 0x4104:
 853                 for (i = 0; i < 16; i++) {
 854                         bool enabled;
 855
 856                         enabled = !!(idx_value & (1 << i));
 857                         track->textures[i].enabled = enabled;
 858                 }
 859                 break;
 860         case 0x44C0:
 861         case 0x44C4:
 862         case 0x44C8:
 863         case 0x44CC:
 864         case 0x44D0:
 865         case 0x44D4:
 866         case 0x44D8:
 867         case 0x44DC:
 868         case 0x44E0:
 869         case 0x44E4:
 870         case 0x44E8:
 871         case 0x44EC:
 872         case 0x44F0:
 873         case 0x44F4:
 874         case 0x44F8:
 875         case 0x44FC:
 876                 /* TX_FORMAT1_[0-15] */
 877                 i = (reg - 0x44C0) >> 2;
 878                 tmp = (idx_value >> 25) & 0x3;
 879                 track->textures[i].tex_coord_type = tmp;
 880                 switch ((idx_value & 0x1F)) {
 881                 case R300_TX_FORMAT_X8:
 882                 case R300_TX_FORMAT_Y4X4:
 883                 case R300_TX_FORMAT_Z3Y3X2:
 884                         track->textures[i].cpp = 1;
 885                         break;
 886                 case R300_TX_FORMAT_X16:
 887                 case R300_TX_FORMAT_Y8X8:
 888                 case R300_TX_FORMAT_Z5Y6X5:
 889                 case R300_TX_FORMAT_Z6Y5X5:
 890                 case R300_TX_FORMAT_W4Z4Y4X4:
 891                 case R300_TX_FORMAT_W1Z5Y5X5:
 892                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 893                 case R300_TX_FORMAT_B8G8_B8G8:
 894                 case R300_TX_FORMAT_G8R8_G8B8:
 895                         track->textures[i].cpp = 2;
 896                         break;
 897                 case R300_TX_FORMAT_Y16X16:
 898                 case R300_TX_FORMAT_Z11Y11X10:
 899                 case R300_TX_FORMAT_Z10Y11X11:
 900                 case R300_TX_FORMAT_W8Z8Y8X8:
 901                 case R300_TX_FORMAT_W2Z10Y10X10:
 902                 case 0x17:
 903                 case R300_TX_FORMAT_FL_I32:
 904                 case 0x1e:
 905                         track->textures[i].cpp = 4;
 906                         break;
 907                 case R300_TX_FORMAT_W16Z16Y16X16:
 908                 case R300_TX_FORMAT_FL_R16G16B16A16:
 909                 case R300_TX_FORMAT_FL_I32A32:
 910                         track->textures[i].cpp = 8;
 911                         break;
 912                 case R300_TX_FORMAT_FL_R32G32B32A32:
 913                         track->textures[i].cpp = 16;
 914                         break;
 915                 case R300_TX_FORMAT_DXT1:
 916                         track->textures[i].cpp = 1;
 917                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 918                         break;
 919                 case R300_TX_FORMAT_ATI2N:
 920                         if (p->rdev->family < CHIP_R420) {
 921                                 DRM_ERROR("Invalid texture format %u\n",
 922                                           (idx_value & 0x1F));
 923                                 return -EINVAL;
 924                         }
 925                         /* The same rules apply as for DXT3/5. */
 926                         /* Pass through. */
 927                 case R300_TX_FORMAT_DXT3:
 928                 case R300_TX_FORMAT_DXT5:
 929                         track->textures[i].cpp = 1;
 930                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 931                         break;
 932                 default:
 933                         DRM_ERROR("Invalid texture format %u\n",
 934                                   (idx_value & 0x1F));
 935                         return -EINVAL;
 936                         break;
 937                 }
 938                 break;
 939         case 0x4400:
 940         case 0x4404:
 941         case 0x4408:
 942         case 0x440C:
 943         case 0x4410:
 944         case 0x4414:
 945         case 0x4418:
 946         case 0x441C:
 947         case 0x4420:
 948         case 0x4424:
 949         case 0x4428:
 950         case 0x442C:
 951         case 0x4430:
 952         case 0x4434:
 953         case 0x4438:
 954         case 0x443C:
 955                 /* TX_FILTER0_[0-15] */
 956                 i = (reg - 0x4400) >> 2;
 957                 tmp = idx_value & 0x7;
 958                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 959                         track->textures[i].roundup_w = false;
 960                 }
 961                 tmp = (idx_value >> 3) & 0x7;
 962                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 963                         track->textures[i].roundup_h = false;
 964                 }
 965                 break;
 966         case 0x4500:
 967         case 0x4504:
 968         case 0x4508:
 969         case 0x450C:
 970         case 0x4510:
 971         case 0x4514:
 972         case 0x4518:
 973         case 0x451C:
 974         case 0x4520:
 975         case 0x4524:
 976         case 0x4528:
 977         case 0x452C:
 978         case 0x4530:
 979         case 0x4534:
 980         case 0x4538:
 981         case 0x453C:
 982                 /* TX_FORMAT2_[0-15] */
 983                 i = (reg - 0x4500) >> 2;
 984                 tmp = idx_value & 0x3FFF;
 985                 track->textures[i].pitch = tmp + 1;
 986                 if (p->rdev->family >= CHIP_RV515) {
 987                         tmp = ((idx_value >> 15) & 1) << 11;
 988                         track->textures[i].width_11 = tmp;
 989                         tmp = ((idx_value >> 16) & 1) << 11;
 990                         track->textures[i].height_11 = tmp;
 991
 992                         /* ATI1N */
 993                         if (idx_value & (1 << 14)) {
 994                                 /* The same rules apply as for DXT1. */
 995                                 track->textures[i].compress_format =
 996                                         R100_TRACK_COMP_DXT1;
 997                         }
 998                 } else if (idx_value & (1 << 14)) {
 999                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1000                         return -EINVAL;
1001                 }
1002                 break;
1003         case 0x4480:
1004         case 0x4484:
1005         case 0x4488:
1006         case 0x448C:
1007         case 0x4490:
1008         case 0x4494:
1009         case 0x4498:
1010         case 0x449C:
1011         case 0x44A0:
1012         case 0x44A4:
1013         case 0x44A8:
1014         case 0x44AC:
1015         case 0x44B0:
1016         case 0x44B4:
1017         case 0x44B8:
1018         case 0x44BC:
1019                 /* TX_FORMAT0_[0-15] */
1020                 i = (reg - 0x4480) >> 2;
1021                 tmp = idx_value & 0x7FF;
1022                 track->textures[i].width = tmp + 1;
1023                 tmp = (idx_value >> 11) & 0x7FF;
1024                 track->textures[i].height = tmp + 1;
1025                 tmp = (idx_value >> 26) & 0xF;
1026                 track->textures[i].num_levels = tmp;
1027                 tmp = idx_value & (1 << 31);
1028                 track->textures[i].use_pitch = !!tmp;
1029                 tmp = (idx_value >> 22) & 0xF;
1030                 track->textures[i].txdepth = tmp;
1031                 break;
1032         case R300_ZB_ZPASS_ADDR:
1033                 r = r100_cs_packet_next_reloc(p, &reloc);
1034                 if (r) {
1035                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1036                                         idx, reg);
1037                         r100_cs_dump_packet(p, pkt);
1038                         return r;
1039                 }
1040                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1041                 break;
1042         case 0x4e0c:
1043                 /* RB3D_COLOR_CHANNEL_MASK */
1044                 track->color_channel_mask = idx_value;
1045                 break;
1046         case 0x4d1c:
1047                 /* ZB_BW_CNTL */
1048                 track->fastfill = !!(idx_value & (1 << 2));
1049                 break;
1050         case 0x4e04:
1051                 /* RB3D_BLENDCNTL */
1052                 track->blend_read_enable = !!(idx_value & (1 << 2));
1053                 break;
1054         case 0x4be8:
1055                 /* valid register only on RV530 */
1056                 if (p->rdev->family == CHIP_RV530)
1057                         break;
1058                 /* fallthrough do not move */
1059         default:
1060                 goto fail;
1061         }
1062         return 0;
1063 fail:
1064         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1065                reg, idx);
1066         return -EINVAL;
1067 }
1068
1069 static int r300_packet3_check(struct radeon_cs_parser *p,
1070                               struct radeon_cs_packet *pkt)
1071 {
1072         struct radeon_cs_reloc *reloc;
1073         struct r100_cs_track *track;
1074         volatile uint32_t *ib;
1075         unsigned idx;
1076         int r;
1077
1078         ib = p->ib->ptr;
1079         idx = pkt->idx + 1;
1080         track = (struct r100_cs_track *)p->track;
1081         switch(pkt->opcode) {
1082         case PACKET3_3D_LOAD_VBPNTR:
1083                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1084                 if (r)
1085                         return r;
1086                 break;
1087         case PACKET3_INDX_BUFFER:
1088                 r = r100_cs_packet_next_reloc(p, &reloc);
1089                 if (r) {
1090                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1091                         r100_cs_dump_packet(p, pkt);
1092                         return r;
1093                 }
1094                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1095                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1096                 if (r) {
1097                         return r;
1098                 }
1099                 break;
1100         /* Draw packet */
1101         case PACKET3_3D_DRAW_IMMD:
1102                 /* Number of dwords is vtx_size * (num_vertices - 1)
1103                  * PRIM_WALK must be equal to 3 vertex data in embedded
1104                  * in cmd stream */
1105                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1106                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1107                         return -EINVAL;
1108                 }
1109                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1110                 track->immd_dwords = pkt->count - 1;
1111                 r = r100_cs_track_check(p->rdev, track);
1112                 if (r) {
1113                         return r;
1114                 }
1115                 break;
1116         case PACKET3_3D_DRAW_IMMD_2:
1117                 /* Number of dwords is vtx_size * (num_vertices - 1)
1118                  * PRIM_WALK must be equal to 3 vertex data in embedded
1119                  * in cmd stream */
1120                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1121                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1122                         return -EINVAL;
1123                 }
1124                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1125                 track->immd_dwords = pkt->count;
1126                 r = r100_cs_track_check(p->rdev, track);
1127                 if (r) {
1128                         return r;
1129                 }
1130                 break;
1131         case PACKET3_3D_DRAW_VBUF:
1132                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1133                 r = r100_cs_track_check(p->rdev, track);
1134                 if (r) {
1135                         return r;
1136                 }
1137                 break;
1138         case PACKET3_3D_DRAW_VBUF_2:
1139                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1140                 r = r100_cs_track_check(p->rdev, track);
1141                 if (r) {
1142                         return r;
1143                 }
1144                 break;
1145         case PACKET3_3D_DRAW_INDX:
1146                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1147                 r = r100_cs_track_check(p->rdev, track);
1148                 if (r) {
1149                         return r;
1150                 }
1151                 break;
1152         case PACKET3_3D_DRAW_INDX_2:
1153                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1154                 r = r100_cs_track_check(p->rdev, track);
1155                 if (r) {
1156                         return r;
1157                 }
1158                 break;
1159         case PACKET3_NOP:
1160                 break;
1161         default:
1162                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1163                 return -EINVAL;
1164         }
1165         return 0;
1166 }
1167
1168 int r300_cs_parse(struct radeon_cs_parser *p)
1169 {
1170         struct radeon_cs_packet pkt;
1171         struct r100_cs_track *track;
1172         int r;
1173
1174         track = kzalloc(sizeof(*track), GFP_KERNEL);
1175         r100_cs_track_clear(p->rdev, track);
1176         p->track = track;
1177         do {
1178                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1179                 if (r) {
1180                         return r;
1181                 }
1182                 p->idx += pkt.count + 2;
1183                 switch (pkt.type) {
1184                 case PACKET_TYPE0:
1185                         r = r100_cs_parse_packet0(p, &pkt,
1186                                                   p->rdev->config.r300.reg_safe_bm,
1187                                                   p->rdev->config.r300.reg_safe_bm_size,
1188                                                   &r300_packet0_check);
1189                         break;
1190                 case PACKET_TYPE2:
1191                         break;
1192                 case PACKET_TYPE3:
1193                         r = r300_packet3_check(p, &pkt);
1194                         break;
1195                 default:
1196                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1197                         return -EINVAL;
1198                 }
1199                 if (r) {
1200                         return r;
1201                 }
1202         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1203         return 0;
1204 }
1205
1206 void r300_set_reg_safe(struct radeon_device *rdev)
1207 {
1208         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1209         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1210 }
1211
1212 void r300_mc_program(struct radeon_device *rdev)
1213 {
1214         struct r100_mc_save save;
1215         int r;
1216
1217         r = r100_debugfs_mc_info_init(rdev);
1218         if (r) {
1219                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1220         }
1221
1222         /* Stops all mc clients */
1223         r100_mc_stop(rdev, &save);
1224         if (rdev->flags & RADEON_IS_AGP) {
1225                 WREG32(R_00014C_MC_AGP_LOCATION,
1226                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1227                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1228                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1229                 WREG32(R_00015C_AGP_BASE_2,
1230                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1231         } else {
1232                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1233                 WREG32(R_000170_AGP_BASE, 0);
1234                 WREG32(R_00015C_AGP_BASE_2, 0);
1235         }
1236         /* Wait for mc idle */
1237         if (r300_mc_wait_for_idle(rdev))
1238                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1239         /* Program MC, should be a 32bits limited address space */
1240         WREG32(R_000148_MC_FB_LOCATION,
1241                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1242                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1243         r100_mc_resume(rdev, &save);
1244 }
1245
1246 void r300_clock_startup(struct radeon_device *rdev)
1247 {
1248         u32 tmp;
1249
1250         if (radeon_dynclks != -1 && radeon_dynclks)
1251                 radeon_legacy_set_clock_gating(rdev, 1);
1252         /* We need to force on some of the block */
1253         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1254         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1255         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1256                 tmp |= S_00000D_FORCE_VAP(1);
1257         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1258 }
1259
1260 static int r300_startup(struct radeon_device *rdev)
1261 {
1262         int r;
1263
1264         /* set common regs */
1265         r100_set_common_regs(rdev);
1266         /* program mc */
1267         r300_mc_program(rdev);
1268         /* Resume clock */
1269         r300_clock_startup(rdev);
1270         /* Initialize GPU configuration (# pipes, ...) */
1271         r300_gpu_init(rdev);
1272         /* Initialize GART (initialize after TTM so we can allocate
1273          * memory through TTM but finalize after TTM) */
1274         if (rdev->flags & RADEON_IS_PCIE) {
1275                 r = rv370_pcie_gart_enable(rdev);
1276                 if (r)
1277                         return r;
1278         }
1279
1280         if (rdev->family == CHIP_R300 ||
1281             rdev->family == CHIP_R350 ||
1282             rdev->family == CHIP_RV350)
1283                 r100_enable_bm(rdev);
1284
1285         if (rdev->flags & RADEON_IS_PCI) {
1286                 r = r100_pci_gart_enable(rdev);
1287                 if (r)
1288                         return r;
1289         }
1290         /* Enable IRQ */
1291         r100_irq_set(rdev);
1292         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1293         /* 1M ring buffer */
1294         r = r100_cp_init(rdev, 1024 * 1024);
1295         if (r) {
1296                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1297                 return r;
1298         }
1299         r = r100_wb_init(rdev);
1300         if (r)
1301                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1302         r = r100_ib_init(rdev);
1303         if (r) {
1304                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1305                 return r;
1306         }
1307         return 0;
1308 }
1309
1310 int r300_resume(struct radeon_device *rdev)
1311 {
1312         /* Make sur GART are not working */
1313         if (rdev->flags & RADEON_IS_PCIE)
1314                 rv370_pcie_gart_disable(rdev);
1315         if (rdev->flags & RADEON_IS_PCI)
1316                 r100_pci_gart_disable(rdev);
1317         /* Resume clock before doing reset */
1318         r300_clock_startup(rdev);
1319         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1320         if (radeon_gpu_reset(rdev)) {
1321                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1322                         RREG32(R_000E40_RBBM_STATUS),
1323                         RREG32(R_0007C0_CP_STAT));
1324         }
1325         /* post */
1326         radeon_combios_asic_init(rdev->ddev);
1327         /* Resume clock after posting */
1328         r300_clock_startup(rdev);
1329         /* Initialize surface registers */
1330         radeon_surface_init(rdev);
1331         return r300_startup(rdev);
1332 }
1333
1334 int r300_suspend(struct radeon_device *rdev)
1335 {
1336         r100_cp_disable(rdev);
1337         r100_wb_disable(rdev);
1338         r100_irq_disable(rdev);
1339         if (rdev->flags & RADEON_IS_PCIE)
1340                 rv370_pcie_gart_disable(rdev);
1341         if (rdev->flags & RADEON_IS_PCI)
1342                 r100_pci_gart_disable(rdev);
1343         return 0;
1344 }
1345
1346 void r300_fini(struct radeon_device *rdev)
1347 {
1348         radeon_pm_fini(rdev);
1349         r100_cp_fini(rdev);
1350         r100_wb_fini(rdev);
1351         r100_ib_fini(rdev);
1352         radeon_gem_fini(rdev);
1353         if (rdev->flags & RADEON_IS_PCIE)
1354                 rv370_pcie_gart_fini(rdev);
1355         if (rdev->flags & RADEON_IS_PCI)
1356                 r100_pci_gart_fini(rdev);
1357         radeon_agp_fini(rdev);
1358         radeon_irq_kms_fini(rdev);
1359         radeon_fence_driver_fini(rdev);
1360         radeon_bo_fini(rdev);
1361         radeon_atombios_fini(rdev);
1362         kfree(rdev->bios);
1363         rdev->bios = NULL;
1364 }
1365
1366 int r300_init(struct radeon_device *rdev)
1367 {
1368         int r;
1369
1370         /* Disable VGA */
1371         r100_vga_render_disable(rdev);
1372         /* Initialize scratch registers */
1373         radeon_scratch_init(rdev);
1374         /* Initialize surface registers */
1375         radeon_surface_init(rdev);
1376         /* TODO: disable VGA need to use VGA request */
1377         /* BIOS*/
1378         if (!radeon_get_bios(rdev)) {
1379                 if (ASIC_IS_AVIVO(rdev))
1380                         return -EINVAL;
1381         }
1382         if (rdev->is_atom_bios) {
1383                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1384                 return -EINVAL;
1385         } else {
1386                 r = radeon_combios_init(rdev);
1387                 if (r)
1388                         return r;
1389         }
1390         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1391         if (radeon_gpu_reset(rdev)) {
1392                 dev_warn(rdev->dev,
1393                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1394                         RREG32(R_000E40_RBBM_STATUS),
1395                         RREG32(R_0007C0_CP_STAT));
1396         }
1397         /* check if cards are posted or not */
1398         if (radeon_boot_test_post_card(rdev) == false)
1399                 return -EINVAL;
1400         /* Set asic errata */
1401         r300_errata(rdev);
1402         /* Initialize clocks */
1403         radeon_get_clock_info(rdev->ddev);
1404         /* Initialize power management */
1405         radeon_pm_init(rdev);
1406         /* initialize AGP */
1407         if (rdev->flags & RADEON_IS_AGP) {
1408                 r = radeon_agp_init(rdev);
1409                 if (r) {
1410                         radeon_agp_disable(rdev);
1411                 }
1412         }
1413         /* initialize memory controller */
1414         r300_mc_init(rdev);
1415         /* Fence driver */
1416         r = radeon_fence_driver_init(rdev);
1417         if (r)
1418                 return r;
1419         r = radeon_irq_kms_init(rdev);
1420         if (r)
1421                 return r;
1422         /* Memory manager */
1423         r = radeon_bo_init(rdev);
1424         if (r)
1425                 return r;
1426         if (rdev->flags & RADEON_IS_PCIE) {
1427                 r = rv370_pcie_gart_init(rdev);
1428                 if (r)
1429                         return r;
1430         }
1431         if (rdev->flags & RADEON_IS_PCI) {
1432                 r = r100_pci_gart_init(rdev);
1433                 if (r)
1434                         return r;
1435         }
1436         r300_set_reg_safe(rdev);
1437         rdev->accel_working = true;
1438         r = r300_startup(rdev);
1439         if (r) {
1440                 /* Somethings want wront with the accel init stop accel */
1441                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1442                 r100_cp_fini(rdev);
1443                 r100_wb_fini(rdev);
1444                 r100_ib_fini(rdev);
1445                 radeon_irq_kms_fini(rdev);
1446                 if (rdev->flags & RADEON_IS_PCIE)
1447                         rv370_pcie_gart_fini(rdev);
1448                 if (rdev->flags & RADEON_IS_PCI)
1449                         r100_pci_gart_fini(rdev);
1450                 radeon_agp_fini(rdev);
1451                 rdev->accel_working = false;
1452         }
1453         return 0;
1454 }