drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
  72                             struct radeon_cs_packet *pkt,
  73                             unsigned idx,
  74                             unsigned reg)
  75 {
  76         int r;
  77         u32 tile_flags = 0;
  78         u32 tmp;
  79         struct radeon_cs_reloc *reloc;
  80         u32 value;
  81
  82         r = r100_cs_packet_next_reloc(p, &reloc);
  83         if (r) {
  84                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  85                           idx, reg);
  86                 r100_cs_dump_packet(p, pkt);
  87                 return r;
  88         }
  89         value = radeon_get_ib_value(p, idx);
  90         tmp = value & 0x003fffff;
  91         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
  92
  93         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  94                 tile_flags |= RADEON_DST_TILE_MACRO;
  95         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
  96                 if (reg == RADEON_SRC_PITCH_OFFSET) {
  97                         DRM_ERROR("Cannot src blit from microtiled surface\n");
  98                         r100_cs_dump_packet(p, pkt);
  99                         return -EINVAL;
 100                 }
 101                 tile_flags |= RADEON_DST_TILE_MICRO;
 102         }
 103
 104         tmp |= tile_flags;
 105         p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
 106         return 0;
 107 }
 108
 109 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
 110                              struct radeon_cs_packet *pkt,
 111                              int idx)
 112 {
 113         unsigned c, i;
 114         struct radeon_cs_reloc *reloc;
 115         struct r100_cs_track *track;
 116         int r = 0;
 117         volatile uint32_t *ib;
 118         u32 idx_value;
 119
 120         ib = p->ib->ptr;
 121         track = (struct r100_cs_track *)p->track;
 122         c = radeon_get_ib_value(p, idx++) & 0x1F;
 123         if (c > 16) {
 124             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
 125                       pkt->opcode);
 126             r100_cs_dump_packet(p, pkt);
 127             return -EINVAL;
 128         }
 129         track->num_arrays = c;
 130         for (i = 0; i < (c - 1); i+=2, idx+=3) {
 131                 r = r100_cs_packet_next_reloc(p, &reloc);
 132                 if (r) {
 133                         DRM_ERROR("No reloc for packet3 %d\n",
 134                                   pkt->opcode);
 135                         r100_cs_dump_packet(p, pkt);
 136                         return r;
 137                 }
 138                 idx_value = radeon_get_ib_value(p, idx);
 139                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 140
 141                 track->arrays[i + 0].esize = idx_value >> 8;
 142                 track->arrays[i + 0].robj = reloc->robj;
 143                 track->arrays[i + 0].esize &= 0x7F;
 144                 r = r100_cs_packet_next_reloc(p, &reloc);
 145                 if (r) {
 146                         DRM_ERROR("No reloc for packet3 %d\n",
 147                                   pkt->opcode);
 148                         r100_cs_dump_packet(p, pkt);
 149                         return r;
 150                 }
 151                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
 152                 track->arrays[i + 1].robj = reloc->robj;
 153                 track->arrays[i + 1].esize = idx_value >> 24;
 154                 track->arrays[i + 1].esize &= 0x7F;
 155         }
 156         if (c & 1) {
 157                 r = r100_cs_packet_next_reloc(p, &reloc);
 158                 if (r) {
 159                         DRM_ERROR("No reloc for packet3 %d\n",
 160                                           pkt->opcode);
 161                         r100_cs_dump_packet(p, pkt);
 162                         return r;
 163                 }
 164                 idx_value = radeon_get_ib_value(p, idx);
 165                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 166                 track->arrays[i + 0].robj = reloc->robj;
 167                 track->arrays[i + 0].esize = idx_value >> 8;
 168                 track->arrays[i + 0].esize &= 0x7F;
 169         }
 170         return r;
 171 }
 172
 173 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 174 {
 175         /* enable the pflip int */
 176         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 177 }
 178
 179 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
 180 {
 181         /* disable the pflip int */
 182         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 183 }
 184
 185 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 186 {
 187         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 188         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 189
 190         /* Lock the graphics update lock */
 191         /* update the scanout addresses */
 192         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 193
 194         /* Wait for update_pending to go high. */
 195         while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
 196         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 197
 198         /* Unlock the lock, so double-buffering can take place inside vblank */
 199         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 200         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 201
 202         /* Return current update_pending status: */
 203         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 204 }
 205
 206 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 207 {
 208         int i;
 209         rdev->pm.dynpm_can_upclock = true;
 210         rdev->pm.dynpm_can_downclock = true;
 211
 212         switch (rdev->pm.dynpm_planned_action) {
 213         case DYNPM_ACTION_MINIMUM:
 214                 rdev->pm.requested_power_state_index = 0;
 215                 rdev->pm.dynpm_can_downclock = false;
 216                 break;
 217         case DYNPM_ACTION_DOWNCLOCK:
 218                 if (rdev->pm.current_power_state_index == 0) {
 219                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 220                         rdev->pm.dynpm_can_downclock = false;
 221                 } else {
 222                         if (rdev->pm.active_crtc_count > 1) {
 223                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 224                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 225                                                 continue;
 226                                         else if (i >= rdev->pm.current_power_state_index) {
 227                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 228                                                 break;
 229                                         } else {
 230                                                 rdev->pm.requested_power_state_index = i;
 231                                                 break;
 232                                         }
 233                                 }
 234                         } else
 235                                 rdev->pm.requested_power_state_index =
 236                                         rdev->pm.current_power_state_index - 1;
 237                 }
 238                 /* don't use the power state if crtcs are active and no display flag is set */
 239                 if ((rdev->pm.active_crtc_count > 0) &&
 240                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 241                      RADEON_PM_MODE_NO_DISPLAY)) {
 242                         rdev->pm.requested_power_state_index++;
 243                 }
 244                 break;
 245         case DYNPM_ACTION_UPCLOCK:
 246                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 247                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 248                         rdev->pm.dynpm_can_upclock = false;
 249                 } else {
 250                         if (rdev->pm.active_crtc_count > 1) {
 251                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 252                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 253                                                 continue;
 254                                         else if (i <= rdev->pm.current_power_state_index) {
 255                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 256                                                 break;
 257                                         } else {
 258                                                 rdev->pm.requested_power_state_index = i;
 259                                                 break;
 260                                         }
 261                                 }
 262                         } else
 263                                 rdev->pm.requested_power_state_index =
 264                                         rdev->pm.current_power_state_index + 1;
 265                 }
 266                 break;
 267         case DYNPM_ACTION_DEFAULT:
 268                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 269                 rdev->pm.dynpm_can_upclock = false;
 270                 break;
 271         case DYNPM_ACTION_NONE:
 272         default:
 273                 DRM_ERROR("Requested mode for not defined action\n");
 274                 return;
 275         }
 276         /* only one clock mode per power state */
 277         rdev->pm.requested_clock_mode_index = 0;
 278
 279         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 280                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 281                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 282                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 283                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 284                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 285                   pcie_lanes);
 286 }
 287
 288 void r100_pm_init_profile(struct radeon_device *rdev)
 289 {
 290         /* default */
 291         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 292         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 293         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 294         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 295         /* low sh */
 296         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 297         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 298         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 299         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 300         /* mid sh */
 301         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 303         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 304         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 305         /* high sh */
 306         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 308         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 309         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 310         /* low mh */
 311         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 312         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 313         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 314         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 315         /* mid mh */
 316         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 317         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 318         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 319         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 320         /* high mh */
 321         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 322         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 323         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 324         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 325 }
 326
 327 void r100_pm_misc(struct radeon_device *rdev)
 328 {
 329         int requested_index = rdev->pm.requested_power_state_index;
 330         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 331         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 332         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 333
 334         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 335                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 336                         tmp = RREG32(voltage->gpio.reg);
 337                         if (voltage->active_high)
 338                                 tmp |= voltage->gpio.mask;
 339                         else
 340                                 tmp &= ~(voltage->gpio.mask);
 341                         WREG32(voltage->gpio.reg, tmp);
 342                         if (voltage->delay)
 343                                 udelay(voltage->delay);
 344                 } else {
 345                         tmp = RREG32(voltage->gpio.reg);
 346                         if (voltage->active_high)
 347                                 tmp &= ~voltage->gpio.mask;
 348                         else
 349                                 tmp |= voltage->gpio.mask;
 350                         WREG32(voltage->gpio.reg, tmp);
 351                         if (voltage->delay)
 352                                 udelay(voltage->delay);
 353                 }
 354         }
 355
 356         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 357         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 358         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 359         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 360         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 361         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 362                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 363                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 364                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 365                 else
 366                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 367                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 368                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 369                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 370                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 371         } else
 372                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 373
 374         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 375                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 376                 if (voltage->delay) {
 377                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 378                         switch (voltage->delay) {
 379                         case 33:
 380                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 381                                 break;
 382                         case 66:
 383                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 384                                 break;
 385                         case 99:
 386                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 387                                 break;
 388                         case 132:
 389                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 390                                 break;
 391                         }
 392                 } else
 393                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 394         } else
 395                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 396
 397         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 398                 sclk_cntl &= ~FORCE_HDP;
 399         else
 400                 sclk_cntl |= FORCE_HDP;
 401
 402         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 403         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 404         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 405
 406         /* set pcie lanes */
 407         if ((rdev->flags & RADEON_IS_PCIE) &&
 408             !(rdev->flags & RADEON_IS_IGP) &&
 409             rdev->asic->set_pcie_lanes &&
 410             (ps->pcie_lanes !=
 411              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 412                 radeon_set_pcie_lanes(rdev,
 413                                       ps->pcie_lanes);
 414                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 415         }
 416 }
 417
 418 void r100_pm_prepare(struct radeon_device *rdev)
 419 {
 420         struct drm_device *ddev = rdev->ddev;
 421         struct drm_crtc *crtc;
 422         struct radeon_crtc *radeon_crtc;
 423         u32 tmp;
 424
 425         /* disable any active CRTCs */
 426         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 427                 radeon_crtc = to_radeon_crtc(crtc);
 428                 if (radeon_crtc->enabled) {
 429                         if (radeon_crtc->crtc_id) {
 430                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 431                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 432                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 433                         } else {
 434                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 435                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 436                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 437                         }
 438                 }
 439         }
 440 }
 441
 442 void r100_pm_finish(struct radeon_device *rdev)
 443 {
 444         struct drm_device *ddev = rdev->ddev;
 445         struct drm_crtc *crtc;
 446         struct radeon_crtc *radeon_crtc;
 447         u32 tmp;
 448
 449         /* enable any active CRTCs */
 450         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 451                 radeon_crtc = to_radeon_crtc(crtc);
 452                 if (radeon_crtc->enabled) {
 453                         if (radeon_crtc->crtc_id) {
 454                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 455                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 456                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 457                         } else {
 458                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 459                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 460                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 461                         }
 462                 }
 463         }
 464 }
 465
 466 bool r100_gui_idle(struct radeon_device *rdev)
 467 {
 468         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 469                 return false;
 470         else
 471                 return true;
 472 }
 473
 474 /* hpd for digital panel detect/disconnect */
 475 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 476 {
 477         bool connected = false;
 478
 479         switch (hpd) {
 480         case RADEON_HPD_1:
 481                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 482                         connected = true;
 483                 break;
 484         case RADEON_HPD_2:
 485                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 486                         connected = true;
 487                 break;
 488         default:
 489                 break;
 490         }
 491         return connected;
 492 }
 493
 494 void r100_hpd_set_polarity(struct radeon_device *rdev,
 495                            enum radeon_hpd_id hpd)
 496 {
 497         u32 tmp;
 498         bool connected = r100_hpd_sense(rdev, hpd);
 499
 500         switch (hpd) {
 501         case RADEON_HPD_1:
 502                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 503                 if (connected)
 504                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 505                 else
 506                         tmp |= RADEON_FP_DETECT_INT_POL;
 507                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 508                 break;
 509         case RADEON_HPD_2:
 510                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 511                 if (connected)
 512                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 513                 else
 514                         tmp |= RADEON_FP2_DETECT_INT_POL;
 515                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 516                 break;
 517         default:
 518                 break;
 519         }
 520 }
 521
 522 void r100_hpd_init(struct radeon_device *rdev)
 523 {
 524         struct drm_device *dev = rdev->ddev;
 525         struct drm_connector *connector;
 526
 527         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 528                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 529                 switch (radeon_connector->hpd.hpd) {
 530                 case RADEON_HPD_1:
 531                         rdev->irq.hpd[0] = true;
 532                         break;
 533                 case RADEON_HPD_2:
 534                         rdev->irq.hpd[1] = true;
 535                         break;
 536                 default:
 537                         break;
 538                 }
 539         }
 540         if (rdev->irq.installed)
 541                 r100_irq_set(rdev);
 542 }
 543
 544 void r100_hpd_fini(struct radeon_device *rdev)
 545 {
 546         struct drm_device *dev = rdev->ddev;
 547         struct drm_connector *connector;
 548
 549         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 550                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 551                 switch (radeon_connector->hpd.hpd) {
 552                 case RADEON_HPD_1:
 553                         rdev->irq.hpd[0] = false;
 554                         break;
 555                 case RADEON_HPD_2:
 556                         rdev->irq.hpd[1] = false;
 557                         break;
 558                 default:
 559                         break;
 560                 }
 561         }
 562 }
 563
 564 /*
 565  * PCI GART
 566  */
 567 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 568 {
 569         /* TODO: can we do somethings here ? */
 570         /* It seems hw only cache one entry so we should discard this
 571          * entry otherwise if first GPU GART read hit this entry it
 572          * could end up in wrong address. */
 573 }
 574
 575 int r100_pci_gart_init(struct radeon_device *rdev)
 576 {
 577         int r;
 578
 579         if (rdev->gart.table.ram.ptr) {
 580                 WARN(1, "R100 PCI GART already initialized\n");
 581                 return 0;
 582         }
 583         /* Initialize common gart structure */
 584         r = radeon_gart_init(rdev);
 585         if (r)
 586                 return r;
 587         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 588         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 589         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 590         return radeon_gart_table_ram_alloc(rdev);
 591 }
 592
 593 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 594 void r100_enable_bm(struct radeon_device *rdev)
 595 {
 596         uint32_t tmp;
 597         /* Enable bus mastering */
 598         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 599         WREG32(RADEON_BUS_CNTL, tmp);
 600 }
 601
 602 int r100_pci_gart_enable(struct radeon_device *rdev)
 603 {
 604         uint32_t tmp;
 605
 606         radeon_gart_restore(rdev);
 607         /* discard memory request outside of configured range */
 608         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 609         WREG32(RADEON_AIC_CNTL, tmp);
 610         /* set address range for PCI address translate */
 611         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 612         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 613         /* set PCI GART page-table base address */
 614         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 615         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 616         WREG32(RADEON_AIC_CNTL, tmp);
 617         r100_pci_gart_tlb_flush(rdev);
 618         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 619                  (unsigned)(rdev->mc.gtt_size >> 20),
 620                  (unsigned long long)rdev->gart.table_addr);
 621         rdev->gart.ready = true;
 622         return 0;
 623 }
 624
 625 void r100_pci_gart_disable(struct radeon_device *rdev)
 626 {
 627         uint32_t tmp;
 628
 629         /* discard memory request outside of configured range */
 630         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 631         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 632         WREG32(RADEON_AIC_LO_ADDR, 0);
 633         WREG32(RADEON_AIC_HI_ADDR, 0);
 634 }
 635
 636 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 637 {
 638         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 639                 return -EINVAL;
 640         }
 641         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 642         return 0;
 643 }
 644
 645 void r100_pci_gart_fini(struct radeon_device *rdev)
 646 {
 647         radeon_gart_fini(rdev);
 648         r100_pci_gart_disable(rdev);
 649         radeon_gart_table_ram_free(rdev);
 650 }
 651
 652 int r100_irq_set(struct radeon_device *rdev)
 653 {
 654         uint32_t tmp = 0;
 655
 656         if (!rdev->irq.installed) {
 657                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 658                 WREG32(R_000040_GEN_INT_CNTL, 0);
 659                 return -EINVAL;
 660         }
 661         if (rdev->irq.sw_int) {
 662                 tmp |= RADEON_SW_INT_ENABLE;
 663         }
 664         if (rdev->irq.gui_idle) {
 665                 tmp |= RADEON_GUI_IDLE_MASK;
 666         }
 667         if (rdev->irq.crtc_vblank_int[0] ||
 668             rdev->irq.pflip[0]) {
 669                 tmp |= RADEON_CRTC_VBLANK_MASK;
 670         }
 671         if (rdev->irq.crtc_vblank_int[1] ||
 672             rdev->irq.pflip[1]) {
 673                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 674         }
 675         if (rdev->irq.hpd[0]) {
 676                 tmp |= RADEON_FP_DETECT_MASK;
 677         }
 678         if (rdev->irq.hpd[1]) {
 679                 tmp |= RADEON_FP2_DETECT_MASK;
 680         }
 681         WREG32(RADEON_GEN_INT_CNTL, tmp);
 682         return 0;
 683 }
 684
 685 void r100_irq_disable(struct radeon_device *rdev)
 686 {
 687         u32 tmp;
 688
 689         WREG32(R_000040_GEN_INT_CNTL, 0);
 690         /* Wait and acknowledge irq */
 691         mdelay(1);
 692         tmp = RREG32(R_000044_GEN_INT_STATUS);
 693         WREG32(R_000044_GEN_INT_STATUS, tmp);
 694 }
 695
 696 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 697 {
 698         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 699         uint32_t irq_mask = RADEON_SW_INT_TEST |
 700                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 701                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 702
 703         /* the interrupt works, but the status bit is permanently asserted */
 704         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 705                 if (!rdev->irq.gui_idle_acked)
 706                         irq_mask |= RADEON_GUI_IDLE_STAT;
 707         }
 708
 709         if (irqs) {
 710                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 711         }
 712         return irqs & irq_mask;
 713 }
 714
 715 int r100_irq_process(struct radeon_device *rdev)
 716 {
 717         uint32_t status, msi_rearm;
 718         bool queue_hotplug = false;
 719
 720         /* reset gui idle ack.  the status bit is broken */
 721         rdev->irq.gui_idle_acked = false;
 722
 723         status = r100_irq_ack(rdev);
 724         if (!status) {
 725                 return IRQ_NONE;
 726         }
 727         if (rdev->shutdown) {
 728                 return IRQ_NONE;
 729         }
 730         while (status) {
 731                 /* SW interrupt */
 732                 if (status & RADEON_SW_INT_TEST) {
 733                         radeon_fence_process(rdev);
 734                 }
 735                 /* gui idle interrupt */
 736                 if (status & RADEON_GUI_IDLE_STAT) {
 737                         rdev->irq.gui_idle_acked = true;
 738                         rdev->pm.gui_idle = true;
 739                         wake_up(&rdev->irq.idle_queue);
 740                 }
 741                 /* Vertical blank interrupts */
 742                 if (status & RADEON_CRTC_VBLANK_STAT) {
 743                         if (rdev->irq.crtc_vblank_int[0]) {
 744                                 drm_handle_vblank(rdev->ddev, 0);
 745                                 rdev->pm.vblank_sync = true;
 746                                 wake_up(&rdev->irq.vblank_queue);
 747                         }
 748                         if (rdev->irq.pflip[0])
 749                                 radeon_crtc_handle_flip(rdev, 0);
 750                 }
 751                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 752                         if (rdev->irq.crtc_vblank_int[1]) {
 753                                 drm_handle_vblank(rdev->ddev, 1);
 754                                 rdev->pm.vblank_sync = true;
 755                                 wake_up(&rdev->irq.vblank_queue);
 756                         }
 757                         if (rdev->irq.pflip[1])
 758                                 radeon_crtc_handle_flip(rdev, 1);
 759                 }
 760                 if (status & RADEON_FP_DETECT_STAT) {
 761                         queue_hotplug = true;
 762                         DRM_DEBUG("HPD1\n");
 763                 }
 764                 if (status & RADEON_FP2_DETECT_STAT) {
 765                         queue_hotplug = true;
 766                         DRM_DEBUG("HPD2\n");
 767                 }
 768                 status = r100_irq_ack(rdev);
 769         }
 770         /* reset gui idle ack.  the status bit is broken */
 771         rdev->irq.gui_idle_acked = false;
 772         if (queue_hotplug)
 773                 schedule_work(&rdev->hotplug_work);
 774         if (rdev->msi_enabled) {
 775                 switch (rdev->family) {
 776                 case CHIP_RS400:
 777                 case CHIP_RS480:
 778                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 779                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 780                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 781                         break;
 782                 default:
 783                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 784                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 785                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 786                         break;
 787                 }
 788         }
 789         return IRQ_HANDLED;
 790 }
 791
 792 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 793 {
 794         if (crtc == 0)
 795                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 796         else
 797                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 798 }
 799
 800 /* Who ever call radeon_fence_emit should call ring_lock and ask
 801  * for enough space (today caller are ib schedule and buffer move) */
 802 void r100_fence_ring_emit(struct radeon_device *rdev,
 803                           struct radeon_fence *fence)
 804 {
 805         /* We have to make sure that caches are flushed before
 806          * CPU might read something from VRAM. */
 807         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 808         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 809         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 810         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 811         /* Wait until IDLE & CLEAN */
 812         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 813         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 814         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 815         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 816                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 817         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 818         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 819         /* Emit fence sequence & fire IRQ */
 820         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 821         radeon_ring_write(rdev, fence->seq);
 822         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 823         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 824 }
 825
 826 int r100_copy_blit(struct radeon_device *rdev,
 827                    uint64_t src_offset,
 828                    uint64_t dst_offset,
 829                    unsigned num_gpu_pages,
 830                    struct radeon_fence *fence)
 831 {
 832         uint32_t cur_pages;
 833         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 834         uint32_t pitch;
 835         uint32_t stride_pixels;
 836         unsigned ndw;
 837         int num_loops;
 838         int r = 0;
 839
 840         /* radeon limited to 16k stride */
 841         stride_bytes &= 0x3fff;
 842         /* radeon pitch is /64 */
 843         pitch = stride_bytes / 64;
 844         stride_pixels = stride_bytes / 4;
 845         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 846
 847         /* Ask for enough room for blit + flush + fence */
 848         ndw = 64 + (10 * num_loops);
 849         r = radeon_ring_lock(rdev, ndw);
 850         if (r) {
 851                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 852                 return -EINVAL;
 853         }
 854         while (num_gpu_pages > 0) {
 855                 cur_pages = num_gpu_pages;
 856                 if (cur_pages > 8191) {
 857                         cur_pages = 8191;
 858                 }
 859                 num_gpu_pages -= cur_pages;
 860
 861                 /* pages are in Y direction - height
 862                    page width in X direction - width */
 863                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 864                 radeon_ring_write(rdev,
 865                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 866                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 867                                   RADEON_GMC_SRC_CLIPPING |
 868                                   RADEON_GMC_DST_CLIPPING |
 869                                   RADEON_GMC_BRUSH_NONE |
 870                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 871                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 872                                   RADEON_ROP3_S |
 873                                   RADEON_DP_SRC_SOURCE_MEMORY |
 874                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 875                                   RADEON_GMC_WR_MSK_DIS);
 876                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 877                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 878                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 879                 radeon_ring_write(rdev, 0);
 880                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 881                 radeon_ring_write(rdev, num_gpu_pages);
 882                 radeon_ring_write(rdev, num_gpu_pages);
 883                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 884         }
 885         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 886         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 887         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 888         radeon_ring_write(rdev,
 889                           RADEON_WAIT_2D_IDLECLEAN |
 890                           RADEON_WAIT_HOST_IDLECLEAN |
 891                           RADEON_WAIT_DMA_GUI_IDLE);
 892         if (fence) {
 893                 r = radeon_fence_emit(rdev, fence);
 894         }
 895         radeon_ring_unlock_commit(rdev);
 896         return r;
 897 }
 898
 899 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 900 {
 901         unsigned i;
 902         u32 tmp;
 903
 904         for (i = 0; i < rdev->usec_timeout; i++) {
 905                 tmp = RREG32(R_000E40_RBBM_STATUS);
 906                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 907                         return 0;
 908                 }
 909                 udelay(1);
 910         }
 911         return -1;
 912 }
 913
 914 void r100_ring_start(struct radeon_device *rdev)
 915 {
 916         int r;
 917
 918         r = radeon_ring_lock(rdev, 2);
 919         if (r) {
 920                 return;
 921         }
 922         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 923         radeon_ring_write(rdev,
 924                           RADEON_ISYNC_ANY2D_IDLE3D |
 925                           RADEON_ISYNC_ANY3D_IDLE2D |
 926                           RADEON_ISYNC_WAIT_IDLEGUI |
 927                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 928         radeon_ring_unlock_commit(rdev);
 929 }
 930
 931
 932 /* Load the microcode for the CP */
 933 static int r100_cp_init_microcode(struct radeon_device *rdev)
 934 {
 935         struct platform_device *pdev;
 936         const char *fw_name = NULL;
 937         int err;
 938
 939         DRM_DEBUG_KMS("\n");
 940
 941         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 942         err = IS_ERR(pdev);
 943         if (err) {
 944                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 945                 return -EINVAL;
 946         }
 947         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 948             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 949             (rdev->family == CHIP_RS200)) {
 950                 DRM_INFO("Loading R100 Microcode\n");
 951                 fw_name = FIRMWARE_R100;
 952         } else if ((rdev->family == CHIP_R200) ||
 953                    (rdev->family == CHIP_RV250) ||
 954                    (rdev->family == CHIP_RV280) ||
 955                    (rdev->family == CHIP_RS300)) {
 956                 DRM_INFO("Loading R200 Microcode\n");
 957                 fw_name = FIRMWARE_R200;
 958         } else if ((rdev->family == CHIP_R300) ||
 959                    (rdev->family == CHIP_R350) ||
 960                    (rdev->family == CHIP_RV350) ||
 961                    (rdev->family == CHIP_RV380) ||
 962                    (rdev->family == CHIP_RS400) ||
 963                    (rdev->family == CHIP_RS480)) {
 964                 DRM_INFO("Loading R300 Microcode\n");
 965                 fw_name = FIRMWARE_R300;
 966         } else if ((rdev->family == CHIP_R420) ||
 967                    (rdev->family == CHIP_R423) ||
 968                    (rdev->family == CHIP_RV410)) {
 969                 DRM_INFO("Loading R400 Microcode\n");
 970                 fw_name = FIRMWARE_R420;
 971         } else if ((rdev->family == CHIP_RS690) ||
 972                    (rdev->family == CHIP_RS740)) {
 973                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 974                 fw_name = FIRMWARE_RS690;
 975         } else if (rdev->family == CHIP_RS600) {
 976                 DRM_INFO("Loading RS600 Microcode\n");
 977                 fw_name = FIRMWARE_RS600;
 978         } else if ((rdev->family == CHIP_RV515) ||
 979                    (rdev->family == CHIP_R520) ||
 980                    (rdev->family == CHIP_RV530) ||
 981                    (rdev->family == CHIP_R580) ||
 982                    (rdev->family == CHIP_RV560) ||
 983                    (rdev->family == CHIP_RV570)) {
 984                 DRM_INFO("Loading R500 Microcode\n");
 985                 fw_name = FIRMWARE_R520;
 986         }
 987
 988         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 989         platform_device_unregister(pdev);
 990         if (err) {
 991                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 992                        fw_name);
 993         } else if (rdev->me_fw->size % 8) {
 994                 printk(KERN_ERR
 995                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 996                        rdev->me_fw->size, fw_name);
 997                 err = -EINVAL;
 998                 release_firmware(rdev->me_fw);
 999                 rdev->me_fw = NULL;
1000         }
1001         return err;
1002 }
1003
1004 static void r100_cp_load_microcode(struct radeon_device *rdev)
1005 {
1006         const __be32 *fw_data;
1007         int i, size;
1008
1009         if (r100_gui_wait_for_idle(rdev)) {
1010                 printk(KERN_WARNING "Failed to wait GUI idle while "
1011                        "programming pipes. Bad things might happen.\n");
1012         }
1013
1014         if (rdev->me_fw) {
1015                 size = rdev->me_fw->size / 4;
1016                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1017                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1018                 for (i = 0; i < size; i += 2) {
1019                         WREG32(RADEON_CP_ME_RAM_DATAH,
1020                                be32_to_cpup(&fw_data[i]));
1021                         WREG32(RADEON_CP_ME_RAM_DATAL,
1022                                be32_to_cpup(&fw_data[i + 1]));
1023                 }
1024         }
1025 }
1026
1027 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1028 {
1029         unsigned rb_bufsz;
1030         unsigned rb_blksz;
1031         unsigned max_fetch;
1032         unsigned pre_write_timer;
1033         unsigned pre_write_limit;
1034         unsigned indirect2_start;
1035         unsigned indirect1_start;
1036         uint32_t tmp;
1037         int r;
1038
1039         if (r100_debugfs_cp_init(rdev)) {
1040                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1041         }
1042         if (!rdev->me_fw) {
1043                 r = r100_cp_init_microcode(rdev);
1044                 if (r) {
1045                         DRM_ERROR("Failed to load firmware!\n");
1046                         return r;
1047                 }
1048         }
1049
1050         /* Align ring size */
1051         rb_bufsz = drm_order(ring_size / 8);
1052         ring_size = (1 << (rb_bufsz + 1)) * 4;
1053         r100_cp_load_microcode(rdev);
1054         r = radeon_ring_init(rdev, ring_size);
1055         if (r) {
1056                 return r;
1057         }
1058         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1059          * the rptr copy in system ram */
1060         rb_blksz = 9;
1061         /* cp will read 128bytes at a time (4 dwords) */
1062         max_fetch = 1;
1063         rdev->cp.align_mask = 16 - 1;
1064         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1065         pre_write_timer = 64;
1066         /* Force CP_RB_WPTR write if written more than one time before the
1067          * delay expire
1068          */
1069         pre_write_limit = 0;
1070         /* Setup the cp cache like this (cache size is 96 dwords) :
1071          *      RING            0  to 15
1072          *      INDIRECT1       16 to 79
1073          *      INDIRECT2       80 to 95
1074          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1075          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1076          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1077          * Idea being that most of the gpu cmd will be through indirect1 buffer
1078          * so it gets the bigger cache.
1079          */
1080         indirect2_start = 80;
1081         indirect1_start = 16;
1082         /* cp setup */
1083         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1084         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1085                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1086                REG_SET(RADEON_MAX_FETCH, max_fetch));
1087 #ifdef __BIG_ENDIAN
1088         tmp |= RADEON_BUF_SWAP_32BIT;
1089 #endif
1090         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1091
1092         /* Set ring address */
1093         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1094         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1095         /* Force read & write ptr to 0 */
1096         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1097         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1098         rdev->cp.wptr = 0;
1099         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1100
1101         /* set the wb address whether it's enabled or not */
1102         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1103                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1104         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1105
1106         if (rdev->wb.enabled)
1107                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1108         else {
1109                 tmp |= RADEON_RB_NO_UPDATE;
1110                 WREG32(R_000770_SCRATCH_UMSK, 0);
1111         }
1112
1113         WREG32(RADEON_CP_RB_CNTL, tmp);
1114         udelay(10);
1115         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1116         /* Set cp mode to bus mastering & enable cp*/
1117         WREG32(RADEON_CP_CSQ_MODE,
1118                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1119                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1120         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1121         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1122         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1123         radeon_ring_start(rdev);
1124         r = radeon_ring_test(rdev);
1125         if (r) {
1126                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1127                 return r;
1128         }
1129         rdev->cp.ready = true;
1130         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1131         return 0;
1132 }
1133
1134 void r100_cp_fini(struct radeon_device *rdev)
1135 {
1136         if (r100_cp_wait_for_idle(rdev)) {
1137                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1138         }
1139         /* Disable ring */
1140         r100_cp_disable(rdev);
1141         radeon_ring_fini(rdev);
1142         DRM_INFO("radeon: cp finalized\n");
1143 }
1144
1145 void r100_cp_disable(struct radeon_device *rdev)
1146 {
1147         /* Disable ring */
1148         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1149         rdev->cp.ready = false;
1150         WREG32(RADEON_CP_CSQ_MODE, 0);
1151         WREG32(RADEON_CP_CSQ_CNTL, 0);
1152         WREG32(R_000770_SCRATCH_UMSK, 0);
1153         if (r100_gui_wait_for_idle(rdev)) {
1154                 printk(KERN_WARNING "Failed to wait GUI idle while "
1155                        "programming pipes. Bad things might happen.\n");
1156         }
1157 }
1158
1159 void r100_cp_commit(struct radeon_device *rdev)
1160 {
1161         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1162         (void)RREG32(RADEON_CP_RB_WPTR);
1163 }
1164
1165
1166 /*
1167  * CS functions
1168  */
1169 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1170                           struct radeon_cs_packet *pkt,
1171                           const unsigned *auth, unsigned n,
1172                           radeon_packet0_check_t check)
1173 {
1174         unsigned reg;
1175         unsigned i, j, m;
1176         unsigned idx;
1177         int r;
1178
1179         idx = pkt->idx + 1;
1180         reg = pkt->reg;
1181         /* Check that register fall into register range
1182          * determined by the number of entry (n) in the
1183          * safe register bitmap.
1184          */
1185         if (pkt->one_reg_wr) {
1186                 if ((reg >> 7) > n) {
1187                         return -EINVAL;
1188                 }
1189         } else {
1190                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1191                         return -EINVAL;
1192                 }
1193         }
1194         for (i = 0; i <= pkt->count; i++, idx++) {
1195                 j = (reg >> 7);
1196                 m = 1 << ((reg >> 2) & 31);
1197                 if (auth[j] & m) {
1198                         r = check(p, pkt, idx, reg);
1199                         if (r) {
1200                                 return r;
1201                         }
1202                 }
1203                 if (pkt->one_reg_wr) {
1204                         if (!(auth[j] & m)) {
1205                                 break;
1206                         }
1207                 } else {
1208                         reg += 4;
1209                 }
1210         }
1211         return 0;
1212 }
1213
1214 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1215                          struct radeon_cs_packet *pkt)
1216 {
1217         volatile uint32_t *ib;
1218         unsigned i;
1219         unsigned idx;
1220
1221         ib = p->ib->ptr;
1222         idx = pkt->idx;
1223         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1224                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1225         }
1226 }
1227
1228 /**
1229  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1230  * @parser:     parser structure holding parsing context.
1231  * @pkt:        where to store packet informations
1232  *
1233  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1234  * if packet is bigger than remaining ib size. or if packets is unknown.
1235  **/
1236 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1237                          struct radeon_cs_packet *pkt,
1238                          unsigned idx)
1239 {
1240         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1241         uint32_t header;
1242
1243         if (idx >= ib_chunk->length_dw) {
1244                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1245                           idx, ib_chunk->length_dw);
1246                 return -EINVAL;
1247         }
1248         header = radeon_get_ib_value(p, idx);
1249         pkt->idx = idx;
1250         pkt->type = CP_PACKET_GET_TYPE(header);
1251         pkt->count = CP_PACKET_GET_COUNT(header);
1252         switch (pkt->type) {
1253         case PACKET_TYPE0:
1254                 pkt->reg = CP_PACKET0_GET_REG(header);
1255                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1256                 break;
1257         case PACKET_TYPE3:
1258                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1259                 break;
1260         case PACKET_TYPE2:
1261                 pkt->count = -1;
1262                 break;
1263         default:
1264                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1265                 return -EINVAL;
1266         }
1267         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1268                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1269                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1270                 return -EINVAL;
1271         }
1272         return 0;
1273 }
1274
1275 /**
1276  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1277  * @parser:             parser structure holding parsing context.
1278  *
1279  * Userspace sends a special sequence for VLINE waits.
1280  * PACKET0 - VLINE_START_END + value
1281  * PACKET0 - WAIT_UNTIL +_value
1282  * RELOC (P3) - crtc_id in reloc.
1283  *
1284  * This function parses this and relocates the VLINE START END
1285  * and WAIT UNTIL packets to the correct crtc.
1286  * It also detects a switched off crtc and nulls out the
1287  * wait in that case.
1288  */
1289 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1290 {
1291         struct drm_mode_object *obj;
1292         struct drm_crtc *crtc;
1293         struct radeon_crtc *radeon_crtc;
1294         struct radeon_cs_packet p3reloc, waitreloc;
1295         int crtc_id;
1296         int r;
1297         uint32_t header, h_idx, reg;
1298         volatile uint32_t *ib;
1299
1300         ib = p->ib->ptr;
1301
1302         /* parse the wait until */
1303         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1304         if (r)
1305                 return r;
1306
1307         /* check its a wait until and only 1 count */
1308         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1309             waitreloc.count != 0) {
1310                 DRM_ERROR("vline wait had illegal wait until segment\n");
1311                 return -EINVAL;
1312         }
1313
1314         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1315                 DRM_ERROR("vline wait had illegal wait until\n");
1316                 return -EINVAL;
1317         }
1318
1319         /* jump over the NOP */
1320         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1321         if (r)
1322                 return r;
1323
1324         h_idx = p->idx - 2;
1325         p->idx += waitreloc.count + 2;
1326         p->idx += p3reloc.count + 2;
1327
1328         header = radeon_get_ib_value(p, h_idx);
1329         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1330         reg = CP_PACKET0_GET_REG(header);
1331         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1332         if (!obj) {
1333                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1334                 return -EINVAL;
1335         }
1336         crtc = obj_to_crtc(obj);
1337         radeon_crtc = to_radeon_crtc(crtc);
1338         crtc_id = radeon_crtc->crtc_id;
1339
1340         if (!crtc->enabled) {
1341                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1342                 ib[h_idx + 2] = PACKET2(0);
1343                 ib[h_idx + 3] = PACKET2(0);
1344         } else if (crtc_id == 1) {
1345                 switch (reg) {
1346                 case AVIVO_D1MODE_VLINE_START_END:
1347                         header &= ~R300_CP_PACKET0_REG_MASK;
1348                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1349                         break;
1350                 case RADEON_CRTC_GUI_TRIG_VLINE:
1351                         header &= ~R300_CP_PACKET0_REG_MASK;
1352                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1353                         break;
1354                 default:
1355                         DRM_ERROR("unknown crtc reloc\n");
1356                         return -EINVAL;
1357                 }
1358                 ib[h_idx] = header;
1359                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1360         }
1361
1362         return 0;
1363 }
1364
1365 /**
1366  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1367  * @parser:             parser structure holding parsing context.
1368  * @data:               pointer to relocation data
1369  * @offset_start:       starting offset
1370  * @offset_mask:        offset mask (to align start offset on)
1371  * @reloc:              reloc informations
1372  *
1373  * Check next packet is relocation packet3, do bo validation and compute
1374  * GPU offset using the provided start.
1375  **/
1376 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1377                               struct radeon_cs_reloc **cs_reloc)
1378 {
1379         struct radeon_cs_chunk *relocs_chunk;
1380         struct radeon_cs_packet p3reloc;
1381         unsigned idx;
1382         int r;
1383
1384         if (p->chunk_relocs_idx == -1) {
1385                 DRM_ERROR("No relocation chunk !\n");
1386                 return -EINVAL;
1387         }
1388         *cs_reloc = NULL;
1389         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1390         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1391         if (r) {
1392                 return r;
1393         }
1394         p->idx += p3reloc.count + 2;
1395         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1396                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1397                           p3reloc.idx);
1398                 r100_cs_dump_packet(p, &p3reloc);
1399                 return -EINVAL;
1400         }
1401         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1402         if (idx >= relocs_chunk->length_dw) {
1403                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1404                           idx, relocs_chunk->length_dw);
1405                 r100_cs_dump_packet(p, &p3reloc);
1406                 return -EINVAL;
1407         }
1408         /* FIXME: we assume reloc size is 4 dwords */
1409         *cs_reloc = p->relocs_ptr[(idx / 4)];
1410         return 0;
1411 }
1412
1413 static int r100_get_vtx_size(uint32_t vtx_fmt)
1414 {
1415         int vtx_size;
1416         vtx_size = 2;
1417         /* ordered according to bits in spec */
1418         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1419                 vtx_size++;
1420         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1421                 vtx_size += 3;
1422         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1423                 vtx_size++;
1424         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1425                 vtx_size++;
1426         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1427                 vtx_size += 3;
1428         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1429                 vtx_size++;
1430         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1431                 vtx_size++;
1432         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1433                 vtx_size += 2;
1434         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1435                 vtx_size += 2;
1436         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1437                 vtx_size++;
1438         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1439                 vtx_size += 2;
1440         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1441                 vtx_size++;
1442         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1443                 vtx_size += 2;
1444         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1445                 vtx_size++;
1446         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1447                 vtx_size++;
1448         /* blend weight */
1449         if (vtx_fmt & (0x7 << 15))
1450                 vtx_size += (vtx_fmt >> 15) & 0x7;
1451         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1452                 vtx_size += 3;
1453         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1454                 vtx_size += 2;
1455         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1456                 vtx_size++;
1457         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1458                 vtx_size++;
1459         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1460                 vtx_size++;
1461         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1462                 vtx_size++;
1463         return vtx_size;
1464 }
1465
1466 static int r100_packet0_check(struct radeon_cs_parser *p,
1467                               struct radeon_cs_packet *pkt,
1468                               unsigned idx, unsigned reg)
1469 {
1470         struct radeon_cs_reloc *reloc;
1471         struct r100_cs_track *track;
1472         volatile uint32_t *ib;
1473         uint32_t tmp;
1474         int r;
1475         int i, face;
1476         u32 tile_flags = 0;
1477         u32 idx_value;
1478
1479         ib = p->ib->ptr;
1480         track = (struct r100_cs_track *)p->track;
1481
1482         idx_value = radeon_get_ib_value(p, idx);
1483
1484         switch (reg) {
1485         case RADEON_CRTC_GUI_TRIG_VLINE:
1486                 r = r100_cs_packet_parse_vline(p);
1487                 if (r) {
1488                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1489                                   idx, reg);
1490                         r100_cs_dump_packet(p, pkt);
1491                         return r;
1492                 }
1493                 break;
1494                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1495                  * range access */
1496         case RADEON_DST_PITCH_OFFSET:
1497         case RADEON_SRC_PITCH_OFFSET:
1498                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1499                 if (r)
1500                         return r;
1501                 break;
1502         case RADEON_RB3D_DEPTHOFFSET:
1503                 r = r100_cs_packet_next_reloc(p, &reloc);
1504                 if (r) {
1505                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1506                                   idx, reg);
1507                         r100_cs_dump_packet(p, pkt);
1508                         return r;
1509                 }
1510                 track->zb.robj = reloc->robj;
1511                 track->zb.offset = idx_value;
1512                 track->zb_dirty = true;
1513                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1514                 break;
1515         case RADEON_RB3D_COLOROFFSET:
1516                 r = r100_cs_packet_next_reloc(p, &reloc);
1517                 if (r) {
1518                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1519                                   idx, reg);
1520                         r100_cs_dump_packet(p, pkt);
1521                         return r;
1522                 }
1523                 track->cb[0].robj = reloc->robj;
1524                 track->cb[0].offset = idx_value;
1525                 track->cb_dirty = true;
1526                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1527                 break;
1528         case RADEON_PP_TXOFFSET_0:
1529         case RADEON_PP_TXOFFSET_1:
1530         case RADEON_PP_TXOFFSET_2:
1531                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1532                 r = r100_cs_packet_next_reloc(p, &reloc);
1533                 if (r) {
1534                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1535                                   idx, reg);
1536                         r100_cs_dump_packet(p, pkt);
1537                         return r;
1538                 }
1539                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1540                 track->textures[i].robj = reloc->robj;
1541                 track->tex_dirty = true;
1542                 break;
1543         case RADEON_PP_CUBIC_OFFSET_T0_0:
1544         case RADEON_PP_CUBIC_OFFSET_T0_1:
1545         case RADEON_PP_CUBIC_OFFSET_T0_2:
1546         case RADEON_PP_CUBIC_OFFSET_T0_3:
1547         case RADEON_PP_CUBIC_OFFSET_T0_4:
1548                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1549                 r = r100_cs_packet_next_reloc(p, &reloc);
1550                 if (r) {
1551                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1552                                   idx, reg);
1553                         r100_cs_dump_packet(p, pkt);
1554                         return r;
1555                 }
1556                 track->textures[0].cube_info[i].offset = idx_value;
1557                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1558                 track->textures[0].cube_info[i].robj = reloc->robj;
1559                 track->tex_dirty = true;
1560                 break;
1561         case RADEON_PP_CUBIC_OFFSET_T1_0:
1562         case RADEON_PP_CUBIC_OFFSET_T1_1:
1563         case RADEON_PP_CUBIC_OFFSET_T1_2:
1564         case RADEON_PP_CUBIC_OFFSET_T1_3:
1565         case RADEON_PP_CUBIC_OFFSET_T1_4:
1566                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1567                 r = r100_cs_packet_next_reloc(p, &reloc);
1568                 if (r) {
1569                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1570                                   idx, reg);
1571                         r100_cs_dump_packet(p, pkt);
1572                         return r;
1573                 }
1574                 track->textures[1].cube_info[i].offset = idx_value;
1575                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1576                 track->textures[1].cube_info[i].robj = reloc->robj;
1577                 track->tex_dirty = true;
1578                 break;
1579         case RADEON_PP_CUBIC_OFFSET_T2_0:
1580         case RADEON_PP_CUBIC_OFFSET_T2_1:
1581         case RADEON_PP_CUBIC_OFFSET_T2_2:
1582         case RADEON_PP_CUBIC_OFFSET_T2_3:
1583         case RADEON_PP_CUBIC_OFFSET_T2_4:
1584                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1585                 r = r100_cs_packet_next_reloc(p, &reloc);
1586                 if (r) {
1587                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1588                                   idx, reg);
1589                         r100_cs_dump_packet(p, pkt);
1590                         return r;
1591                 }
1592                 track->textures[2].cube_info[i].offset = idx_value;
1593                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1594                 track->textures[2].cube_info[i].robj = reloc->robj;
1595                 track->tex_dirty = true;
1596                 break;
1597         case RADEON_RE_WIDTH_HEIGHT:
1598                 track->maxy = ((idx_value >> 16) & 0x7FF);
1599                 track->cb_dirty = true;
1600                 track->zb_dirty = true;
1601                 break;
1602         case RADEON_RB3D_COLORPITCH:
1603                 r = r100_cs_packet_next_reloc(p, &reloc);
1604                 if (r) {
1605                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1606                                   idx, reg);
1607                         r100_cs_dump_packet(p, pkt);
1608                         return r;
1609                 }
1610
1611                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1612                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1613                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1614                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1615
1616                 tmp = idx_value & ~(0x7 << 16);
1617                 tmp |= tile_flags;
1618                 ib[idx] = tmp;
1619
1620                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1621                 track->cb_dirty = true;
1622                 break;
1623         case RADEON_RB3D_DEPTHPITCH:
1624                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1625                 track->zb_dirty = true;
1626                 break;
1627         case RADEON_RB3D_CNTL:
1628                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1629                 case 7:
1630                 case 8:
1631                 case 9:
1632                 case 11:
1633                 case 12:
1634                         track->cb[0].cpp = 1;
1635                         break;
1636                 case 3:
1637                 case 4:
1638                 case 15:
1639                         track->cb[0].cpp = 2;
1640                         break;
1641                 case 6:
1642                         track->cb[0].cpp = 4;
1643                         break;
1644                 default:
1645                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1646                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1647                         return -EINVAL;
1648                 }
1649                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1650                 track->cb_dirty = true;
1651                 track->zb_dirty = true;
1652                 break;
1653         case RADEON_RB3D_ZSTENCILCNTL:
1654                 switch (idx_value & 0xf) {
1655                 case 0:
1656                         track->zb.cpp = 2;
1657                         break;
1658                 case 2:
1659                 case 3:
1660                 case 4:
1661                 case 5:
1662                 case 9:
1663                 case 11:
1664                         track->zb.cpp = 4;
1665                         break;
1666                 default:
1667                         break;
1668                 }
1669                 track->zb_dirty = true;
1670                 break;
1671         case RADEON_RB3D_ZPASS_ADDR:
1672                 r = r100_cs_packet_next_reloc(p, &reloc);
1673                 if (r) {
1674                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1675                                   idx, reg);
1676                         r100_cs_dump_packet(p, pkt);
1677                         return r;
1678                 }
1679                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1680                 break;
1681         case RADEON_PP_CNTL:
1682                 {
1683                         uint32_t temp = idx_value >> 4;
1684                         for (i = 0; i < track->num_texture; i++)
1685                                 track->textures[i].enabled = !!(temp & (1 << i));
1686                         track->tex_dirty = true;
1687                 }
1688                 break;
1689         case RADEON_SE_VF_CNTL:
1690                 track->vap_vf_cntl = idx_value;
1691                 break;
1692         case RADEON_SE_VTX_FMT:
1693                 track->vtx_size = r100_get_vtx_size(idx_value);
1694                 break;
1695         case RADEON_PP_TEX_SIZE_0:
1696         case RADEON_PP_TEX_SIZE_1:
1697         case RADEON_PP_TEX_SIZE_2:
1698                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1699                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1700                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1701                 track->tex_dirty = true;
1702                 break;
1703         case RADEON_PP_TEX_PITCH_0:
1704         case RADEON_PP_TEX_PITCH_1:
1705         case RADEON_PP_TEX_PITCH_2:
1706                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1707                 track->textures[i].pitch = idx_value + 32;
1708                 track->tex_dirty = true;
1709                 break;
1710         case RADEON_PP_TXFILTER_0:
1711         case RADEON_PP_TXFILTER_1:
1712         case RADEON_PP_TXFILTER_2:
1713                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1714                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1715                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1716                 tmp = (idx_value >> 23) & 0x7;
1717                 if (tmp == 2 || tmp == 6)
1718                         track->textures[i].roundup_w = false;
1719                 tmp = (idx_value >> 27) & 0x7;
1720                 if (tmp == 2 || tmp == 6)
1721                         track->textures[i].roundup_h = false;
1722                 track->tex_dirty = true;
1723                 break;
1724         case RADEON_PP_TXFORMAT_0:
1725         case RADEON_PP_TXFORMAT_1:
1726         case RADEON_PP_TXFORMAT_2:
1727                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1728                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1729                         track->textures[i].use_pitch = 1;
1730                 } else {
1731                         track->textures[i].use_pitch = 0;
1732                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1733                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1734                 }
1735                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1736                         track->textures[i].tex_coord_type = 2;
1737                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1738                 case RADEON_TXFORMAT_I8:
1739                 case RADEON_TXFORMAT_RGB332:
1740                 case RADEON_TXFORMAT_Y8:
1741                         track->textures[i].cpp = 1;
1742                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1743                         break;
1744                 case RADEON_TXFORMAT_AI88:
1745                 case RADEON_TXFORMAT_ARGB1555:
1746                 case RADEON_TXFORMAT_RGB565:
1747                 case RADEON_TXFORMAT_ARGB4444:
1748                 case RADEON_TXFORMAT_VYUY422:
1749                 case RADEON_TXFORMAT_YVYU422:
1750                 case RADEON_TXFORMAT_SHADOW16:
1751                 case RADEON_TXFORMAT_LDUDV655:
1752                 case RADEON_TXFORMAT_DUDV88:
1753                         track->textures[i].cpp = 2;
1754                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1755                         break;
1756                 case RADEON_TXFORMAT_ARGB8888:
1757                 case RADEON_TXFORMAT_RGBA8888:
1758                 case RADEON_TXFORMAT_SHADOW32:
1759                 case RADEON_TXFORMAT_LDUDUV8888:
1760                         track->textures[i].cpp = 4;
1761                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1762                         break;
1763                 case RADEON_TXFORMAT_DXT1:
1764                         track->textures[i].cpp = 1;
1765                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1766                         break;
1767                 case RADEON_TXFORMAT_DXT23:
1768                 case RADEON_TXFORMAT_DXT45:
1769                         track->textures[i].cpp = 1;
1770                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1771                         break;
1772                 }
1773                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1774                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1775                 track->tex_dirty = true;
1776                 break;
1777         case RADEON_PP_CUBIC_FACES_0:
1778         case RADEON_PP_CUBIC_FACES_1:
1779         case RADEON_PP_CUBIC_FACES_2:
1780                 tmp = idx_value;
1781                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1782                 for (face = 0; face < 4; face++) {
1783                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1784                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1785                 }
1786                 track->tex_dirty = true;
1787                 break;
1788         default:
1789                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1790                        reg, idx);
1791                 return -EINVAL;
1792         }
1793         return 0;
1794 }
1795
1796 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1797                                          struct radeon_cs_packet *pkt,
1798                                          struct radeon_bo *robj)
1799 {
1800         unsigned idx;
1801         u32 value;
1802         idx = pkt->idx + 1;
1803         value = radeon_get_ib_value(p, idx + 2);
1804         if ((value + 1) > radeon_bo_size(robj)) {
1805                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1806                           "(need %u have %lu) !\n",
1807                           value + 1,
1808                           radeon_bo_size(robj));
1809                 return -EINVAL;
1810         }
1811         return 0;
1812 }
1813
1814 static int r100_packet3_check(struct radeon_cs_parser *p,
1815                               struct radeon_cs_packet *pkt)
1816 {
1817         struct radeon_cs_reloc *reloc;
1818         struct r100_cs_track *track;
1819         unsigned idx;
1820         volatile uint32_t *ib;
1821         int r;
1822
1823         ib = p->ib->ptr;
1824         idx = pkt->idx + 1;
1825         track = (struct r100_cs_track *)p->track;
1826         switch (pkt->opcode) {
1827         case PACKET3_3D_LOAD_VBPNTR:
1828                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1829                 if (r)
1830                         return r;
1831                 break;
1832         case PACKET3_INDX_BUFFER:
1833                 r = r100_cs_packet_next_reloc(p, &reloc);
1834                 if (r) {
1835                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1836                         r100_cs_dump_packet(p, pkt);
1837                         return r;
1838                 }
1839                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1840                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1841                 if (r) {
1842                         return r;
1843                 }
1844                 break;
1845         case 0x23:
1846                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1847                 r = r100_cs_packet_next_reloc(p, &reloc);
1848                 if (r) {
1849                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1850                         r100_cs_dump_packet(p, pkt);
1851                         return r;
1852                 }
1853                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1854                 track->num_arrays = 1;
1855                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1856
1857                 track->arrays[0].robj = reloc->robj;
1858                 track->arrays[0].esize = track->vtx_size;
1859
1860                 track->max_indx = radeon_get_ib_value(p, idx+1);
1861
1862                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1863                 track->immd_dwords = pkt->count - 1;
1864                 r = r100_cs_track_check(p->rdev, track);
1865                 if (r)
1866                         return r;
1867                 break;
1868         case PACKET3_3D_DRAW_IMMD:
1869                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1870                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1871                         return -EINVAL;
1872                 }
1873                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1874                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1875                 track->immd_dwords = pkt->count - 1;
1876                 r = r100_cs_track_check(p->rdev, track);
1877                 if (r)
1878                         return r;
1879                 break;
1880                 /* triggers drawing using in-packet vertex data */
1881         case PACKET3_3D_DRAW_IMMD_2:
1882                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1883                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1884                         return -EINVAL;
1885                 }
1886                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1887                 track->immd_dwords = pkt->count;
1888                 r = r100_cs_track_check(p->rdev, track);
1889                 if (r)
1890                         return r;
1891                 break;
1892                 /* triggers drawing using in-packet vertex data */
1893         case PACKET3_3D_DRAW_VBUF_2:
1894                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1895                 r = r100_cs_track_check(p->rdev, track);
1896                 if (r)
1897                         return r;
1898                 break;
1899                 /* triggers drawing of vertex buffers setup elsewhere */
1900         case PACKET3_3D_DRAW_INDX_2:
1901                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1902                 r = r100_cs_track_check(p->rdev, track);
1903                 if (r)
1904                         return r;
1905                 break;
1906                 /* triggers drawing using indices to vertex buffer */
1907         case PACKET3_3D_DRAW_VBUF:
1908                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1909                 r = r100_cs_track_check(p->rdev, track);
1910                 if (r)
1911                         return r;
1912                 break;
1913                 /* triggers drawing of vertex buffers setup elsewhere */
1914         case PACKET3_3D_DRAW_INDX:
1915                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1916                 r = r100_cs_track_check(p->rdev, track);
1917                 if (r)
1918                         return r;
1919                 break;
1920                 /* triggers drawing using indices to vertex buffer */
1921         case PACKET3_3D_CLEAR_HIZ:
1922         case PACKET3_3D_CLEAR_ZMASK:
1923                 if (p->rdev->hyperz_filp != p->filp)
1924                         return -EINVAL;
1925                 break;
1926         case PACKET3_NOP:
1927                 break;
1928         default:
1929                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1930                 return -EINVAL;
1931         }
1932         return 0;
1933 }
1934
1935 int r100_cs_parse(struct radeon_cs_parser *p)
1936 {
1937         struct radeon_cs_packet pkt;
1938         struct r100_cs_track *track;
1939         int r;
1940
1941         track = kzalloc(sizeof(*track), GFP_KERNEL);
1942         r100_cs_track_clear(p->rdev, track);
1943         p->track = track;
1944         do {
1945                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1946                 if (r) {
1947                         return r;
1948                 }
1949                 p->idx += pkt.count + 2;
1950                 switch (pkt.type) {
1951                         case PACKET_TYPE0:
1952                                 if (p->rdev->family >= CHIP_R200)
1953                                         r = r100_cs_parse_packet0(p, &pkt,
1954                                                                   p->rdev->config.r100.reg_safe_bm,
1955                                                                   p->rdev->config.r100.reg_safe_bm_size,
1956                                                                   &r200_packet0_check);
1957                                 else
1958                                         r = r100_cs_parse_packet0(p, &pkt,
1959                                                                   p->rdev->config.r100.reg_safe_bm,
1960                                                                   p->rdev->config.r100.reg_safe_bm_size,
1961                                                                   &r100_packet0_check);
1962                                 break;
1963                         case PACKET_TYPE2:
1964                                 break;
1965                         case PACKET_TYPE3:
1966                                 r = r100_packet3_check(p, &pkt);
1967                                 break;
1968                         default:
1969                                 DRM_ERROR("Unknown packet type %d !\n",
1970                                           pkt.type);
1971                                 return -EINVAL;
1972                 }
1973                 if (r) {
1974                         return r;
1975                 }
1976         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1977         return 0;
1978 }
1979
1980
1981 /*
1982  * Global GPU functions
1983  */
1984 void r100_errata(struct radeon_device *rdev)
1985 {
1986         rdev->pll_errata = 0;
1987
1988         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1989                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1990         }
1991
1992         if (rdev->family == CHIP_RV100 ||
1993             rdev->family == CHIP_RS100 ||
1994             rdev->family == CHIP_RS200) {
1995                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1996         }
1997 }
1998
1999 /* Wait for vertical sync on primary CRTC */
2000 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2001 {
2002         uint32_t crtc_gen_cntl, tmp;
2003         int i;
2004
2005         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2006         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2007             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2008                 return;
2009         }
2010         /* Clear the CRTC_VBLANK_SAVE bit */
2011         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2012         for (i = 0; i < rdev->usec_timeout; i++) {
2013                 tmp = RREG32(RADEON_CRTC_STATUS);
2014                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2015                         return;
2016                 }
2017                 DRM_UDELAY(1);
2018         }
2019 }
2020
2021 /* Wait for vertical sync on secondary CRTC */
2022 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2023 {
2024         uint32_t crtc2_gen_cntl, tmp;
2025         int i;
2026
2027         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2028         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2029             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2030                 return;
2031
2032         /* Clear the CRTC_VBLANK_SAVE bit */
2033         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2034         for (i = 0; i < rdev->usec_timeout; i++) {
2035                 tmp = RREG32(RADEON_CRTC2_STATUS);
2036                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2037                         return;
2038                 }
2039                 DRM_UDELAY(1);
2040         }
2041 }
2042
2043 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2044 {
2045         unsigned i;
2046         uint32_t tmp;
2047
2048         for (i = 0; i < rdev->usec_timeout; i++) {
2049                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2050                 if (tmp >= n) {
2051                         return 0;
2052                 }
2053                 DRM_UDELAY(1);
2054         }
2055         return -1;
2056 }
2057
2058 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2059 {
2060         unsigned i;
2061         uint32_t tmp;
2062
2063         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2064                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2065                        " Bad things might happen.\n");
2066         }
2067         for (i = 0; i < rdev->usec_timeout; i++) {
2068                 tmp = RREG32(RADEON_RBBM_STATUS);
2069                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2070                         return 0;
2071                 }
2072                 DRM_UDELAY(1);
2073         }
2074         return -1;
2075 }
2076
2077 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2078 {
2079         unsigned i;
2080         uint32_t tmp;
2081
2082         for (i = 0; i < rdev->usec_timeout; i++) {
2083                 /* read MC_STATUS */
2084                 tmp = RREG32(RADEON_MC_STATUS);
2085                 if (tmp & RADEON_MC_IDLE) {
2086                         return 0;
2087                 }
2088                 DRM_UDELAY(1);
2089         }
2090         return -1;
2091 }
2092
2093 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2094 {
2095         lockup->last_cp_rptr = cp->rptr;
2096         lockup->last_jiffies = jiffies;
2097 }
2098
2099 /**
2100  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2101  * @rdev:       radeon device structure
2102  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2103  * @cp:         radeon_cp structure holding CP information
2104  *
2105  * We don't need to initialize the lockup tracking information as we will either
2106  * have CP rptr to a different value of jiffies wrap around which will force
2107  * initialization of the lockup tracking informations.
2108  *
2109  * A possible false positivie is if we get call after while and last_cp_rptr ==
2110  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2111  * if the elapsed time since last call is bigger than 2 second than we return
2112  * false and update the tracking information. Due to this the caller must call
2113  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2114  * the fencing code should be cautious about that.
2115  *
2116  * Caller should write to the ring to force CP to do something so we don't get
2117  * false positive when CP is just gived nothing to do.
2118  *
2119  **/
2120 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2121 {
2122         unsigned long cjiffies, elapsed;
2123
2124         cjiffies = jiffies;
2125         if (!time_after(cjiffies, lockup->last_jiffies)) {
2126                 /* likely a wrap around */
2127                 lockup->last_cp_rptr = cp->rptr;
2128                 lockup->last_jiffies = jiffies;
2129                 return false;
2130         }
2131         if (cp->rptr != lockup->last_cp_rptr) {
2132                 /* CP is still working no lockup */
2133                 lockup->last_cp_rptr = cp->rptr;
2134                 lockup->last_jiffies = jiffies;
2135                 return false;
2136         }
2137         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2138         if (elapsed >= 10000) {
2139                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2140                 return true;
2141         }
2142         /* give a chance to the GPU ... */
2143         return false;
2144 }
2145
2146 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2147 {
2148         u32 rbbm_status;
2149         int r;
2150
2151         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2152         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2153                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2154                 return false;
2155         }
2156         /* force CP activities */
2157         r = radeon_ring_lock(rdev, 2);
2158         if (!r) {
2159                 /* PACKET2 NOP */
2160                 radeon_ring_write(rdev, 0x80000000);
2161                 radeon_ring_write(rdev, 0x80000000);
2162                 radeon_ring_unlock_commit(rdev);
2163         }
2164         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2165         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2166 }
2167
2168 void r100_bm_disable(struct radeon_device *rdev)
2169 {
2170         u32 tmp;
2171
2172         /* disable bus mastering */
2173         tmp = RREG32(R_000030_BUS_CNTL);
2174         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2175         mdelay(1);
2176         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2177         mdelay(1);
2178         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2179         tmp = RREG32(RADEON_BUS_CNTL);
2180         mdelay(1);
2181         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2182         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2183         mdelay(1);
2184 }
2185
2186 int r100_asic_reset(struct radeon_device *rdev)
2187 {
2188         struct r100_mc_save save;
2189         u32 status, tmp;
2190         int ret = 0;
2191
2192         status = RREG32(R_000E40_RBBM_STATUS);
2193         if (!G_000E40_GUI_ACTIVE(status)) {
2194                 return 0;
2195         }
2196         r100_mc_stop(rdev, &save);
2197         status = RREG32(R_000E40_RBBM_STATUS);
2198         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2199         /* stop CP */
2200         WREG32(RADEON_CP_CSQ_CNTL, 0);
2201         tmp = RREG32(RADEON_CP_RB_CNTL);
2202         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2203         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2204         WREG32(RADEON_CP_RB_WPTR, 0);
2205         WREG32(RADEON_CP_RB_CNTL, tmp);
2206         /* save PCI state */
2207         pci_save_state(rdev->pdev);
2208         /* disable bus mastering */
2209         r100_bm_disable(rdev);
2210         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2211                                         S_0000F0_SOFT_RESET_RE(1) |
2212                                         S_0000F0_SOFT_RESET_PP(1) |
2213                                         S_0000F0_SOFT_RESET_RB(1));
2214         RREG32(R_0000F0_RBBM_SOFT_RESET);
2215         mdelay(500);
2216         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2217         mdelay(1);
2218         status = RREG32(R_000E40_RBBM_STATUS);
2219         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2220         /* reset CP */
2221         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2222         RREG32(R_0000F0_RBBM_SOFT_RESET);
2223         mdelay(500);
2224         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2225         mdelay(1);
2226         status = RREG32(R_000E40_RBBM_STATUS);
2227         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2228         /* restore PCI & busmastering */
2229         pci_restore_state(rdev->pdev);
2230         r100_enable_bm(rdev);
2231         /* Check if GPU is idle */
2232         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2233                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2234                 dev_err(rdev->dev, "failed to reset GPU\n");
2235                 rdev->gpu_lockup = true;
2236                 ret = -1;
2237         } else
2238                 dev_info(rdev->dev, "GPU reset succeed\n");
2239         r100_mc_resume(rdev, &save);
2240         return ret;
2241 }
2242
2243 void r100_set_common_regs(struct radeon_device *rdev)
2244 {
2245         struct drm_device *dev = rdev->ddev;
2246         bool force_dac2 = false;
2247         u32 tmp;
2248
2249         /* set these so they don't interfere with anything */
2250         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2251         WREG32(RADEON_SUBPIC_CNTL, 0);
2252         WREG32(RADEON_VIPH_CONTROL, 0);
2253         WREG32(RADEON_I2C_CNTL_1, 0);
2254         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2255         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2256         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2257
2258         /* always set up dac2 on rn50 and some rv100 as lots
2259          * of servers seem to wire it up to a VGA port but
2260          * don't report it in the bios connector
2261          * table.
2262          */
2263         switch (dev->pdev->device) {
2264                 /* RN50 */
2265         case 0x515e:
2266         case 0x5969:
2267                 force_dac2 = true;
2268                 break;
2269                 /* RV100*/
2270         case 0x5159:
2271         case 0x515a:
2272                 /* DELL triple head servers */
2273                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2274                     ((dev->pdev->subsystem_device == 0x016c) ||
2275                      (dev->pdev->subsystem_device == 0x016d) ||
2276                      (dev->pdev->subsystem_device == 0x016e) ||
2277                      (dev->pdev->subsystem_device == 0x016f) ||
2278                      (dev->pdev->subsystem_device == 0x0170) ||
2279                      (dev->pdev->subsystem_device == 0x017d) ||
2280                      (dev->pdev->subsystem_device == 0x017e) ||
2281                      (dev->pdev->subsystem_device == 0x0183) ||
2282                      (dev->pdev->subsystem_device == 0x018a) ||
2283                      (dev->pdev->subsystem_device == 0x019a)))
2284                         force_dac2 = true;
2285                 break;
2286         }
2287
2288         if (force_dac2) {
2289                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2290                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2291                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2292
2293                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2294                    enable it, even it's detected.
2295                 */
2296
2297                 /* force it to crtc0 */
2298                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2299                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2300                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2301
2302                 /* set up the TV DAC */
2303                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2304                                  RADEON_TV_DAC_STD_MASK |
2305                                  RADEON_TV_DAC_RDACPD |
2306                                  RADEON_TV_DAC_GDACPD |
2307                                  RADEON_TV_DAC_BDACPD |
2308                                  RADEON_TV_DAC_BGADJ_MASK |
2309                                  RADEON_TV_DAC_DACADJ_MASK);
2310                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2311                                 RADEON_TV_DAC_NHOLD |
2312                                 RADEON_TV_DAC_STD_PS2 |
2313                                 (0x58 << 16));
2314
2315                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2316                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2317                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2318         }
2319
2320         /* switch PM block to ACPI mode */
2321         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2322         tmp &= ~RADEON_PM_MODE_SEL;
2323         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2324
2325 }
2326
2327 /*
2328  * VRAM info
2329  */
2330 static void r100_vram_get_type(struct radeon_device *rdev)
2331 {
2332         uint32_t tmp;
2333
2334         rdev->mc.vram_is_ddr = false;
2335         if (rdev->flags & RADEON_IS_IGP)
2336                 rdev->mc.vram_is_ddr = true;
2337         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2338                 rdev->mc.vram_is_ddr = true;
2339         if ((rdev->family == CHIP_RV100) ||
2340             (rdev->family == CHIP_RS100) ||
2341             (rdev->family == CHIP_RS200)) {
2342                 tmp = RREG32(RADEON_MEM_CNTL);
2343                 if (tmp & RV100_HALF_MODE) {
2344                         rdev->mc.vram_width = 32;
2345                 } else {
2346                         rdev->mc.vram_width = 64;
2347                 }
2348                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2349                         rdev->mc.vram_width /= 4;
2350                         rdev->mc.vram_is_ddr = true;
2351                 }
2352         } else if (rdev->family <= CHIP_RV280) {
2353                 tmp = RREG32(RADEON_MEM_CNTL);
2354                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2355                         rdev->mc.vram_width = 128;
2356                 } else {
2357                         rdev->mc.vram_width = 64;
2358                 }
2359         } else {
2360                 /* newer IGPs */
2361                 rdev->mc.vram_width = 128;
2362         }
2363 }
2364
2365 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2366 {
2367         u32 aper_size;
2368         u8 byte;
2369
2370         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2371
2372         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2373          * that is has the 2nd generation multifunction PCI interface
2374          */
2375         if (rdev->family == CHIP_RV280 ||
2376             rdev->family >= CHIP_RV350) {
2377                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2378                        ~RADEON_HDP_APER_CNTL);
2379                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2380                 return aper_size * 2;
2381         }
2382
2383         /* Older cards have all sorts of funny issues to deal with. First
2384          * check if it's a multifunction card by reading the PCI config
2385          * header type... Limit those to one aperture size
2386          */
2387         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2388         if (byte & 0x80) {
2389                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2390                 DRM_INFO("Limiting VRAM to one aperture\n");
2391                 return aper_size;
2392         }
2393
2394         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2395          * have set it up. We don't write this as it's broken on some ASICs but
2396          * we expect the BIOS to have done the right thing (might be too optimistic...)
2397          */
2398         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2399                 return aper_size * 2;
2400         return aper_size;
2401 }
2402
2403 void r100_vram_init_sizes(struct radeon_device *rdev)
2404 {
2405         u64 config_aper_size;
2406
2407         /* work out accessible VRAM */
2408         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2409         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2410         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2411         /* FIXME we don't use the second aperture yet when we could use it */
2412         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2413                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2414         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2415         if (rdev->flags & RADEON_IS_IGP) {
2416                 uint32_t tom;
2417                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2418                 tom = RREG32(RADEON_NB_TOM);
2419                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2420                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2421                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2422         } else {
2423                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2424                 /* Some production boards of m6 will report 0
2425                  * if it's 8 MB
2426                  */
2427                 if (rdev->mc.real_vram_size == 0) {
2428                         rdev->mc.real_vram_size = 8192 * 1024;
2429                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2430                 }
2431                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2432                  * Novell bug 204882 + along with lots of ubuntu ones
2433                  */
2434                 if (rdev->mc.aper_size > config_aper_size)
2435                         config_aper_size = rdev->mc.aper_size;
2436
2437                 if (config_aper_size > rdev->mc.real_vram_size)
2438                         rdev->mc.mc_vram_size = config_aper_size;
2439                 else
2440                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2441         }
2442 }
2443
2444 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2445 {
2446         uint32_t temp;
2447
2448         temp = RREG32(RADEON_CONFIG_CNTL);
2449         if (state == false) {
2450                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2451                 temp |= RADEON_CFG_VGA_IO_DIS;
2452         } else {
2453                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2454         }
2455         WREG32(RADEON_CONFIG_CNTL, temp);
2456 }
2457
2458 void r100_mc_init(struct radeon_device *rdev)
2459 {
2460         u64 base;
2461
2462         r100_vram_get_type(rdev);
2463         r100_vram_init_sizes(rdev);
2464         base = rdev->mc.aper_base;
2465         if (rdev->flags & RADEON_IS_IGP)
2466                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2467         radeon_vram_location(rdev, &rdev->mc, base);
2468         rdev->mc.gtt_base_align = 0;
2469         if (!(rdev->flags & RADEON_IS_AGP))
2470                 radeon_gtt_location(rdev, &rdev->mc);
2471         radeon_update_bandwidth_info(rdev);
2472 }
2473
2474
2475 /*
2476  * Indirect registers accessor
2477  */
2478 void r100_pll_errata_after_index(struct radeon_device *rdev)
2479 {
2480         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2481                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2482                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2483         }
2484 }
2485
2486 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2487 {
2488         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2489          * or the chip could hang on a subsequent access
2490          */
2491         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2492                 udelay(5000);
2493         }
2494
2495         /* This function is required to workaround a hardware bug in some (all?)
2496          * revisions of the R300.  This workaround should be called after every
2497          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2498          * may not be correct.
2499          */
2500         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2501                 uint32_t save, tmp;
2502
2503                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2504                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2505                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2506                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2507                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2508         }
2509 }
2510
2511 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2512 {
2513         uint32_t data;
2514
2515         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2516         r100_pll_errata_after_index(rdev);
2517         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2518         r100_pll_errata_after_data(rdev);
2519         return data;
2520 }
2521
2522 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2523 {
2524         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2525         r100_pll_errata_after_index(rdev);
2526         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2527         r100_pll_errata_after_data(rdev);
2528 }
2529
2530 void r100_set_safe_registers(struct radeon_device *rdev)
2531 {
2532         if (ASIC_IS_RN50(rdev)) {
2533                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2534                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2535         } else if (rdev->family < CHIP_R200) {
2536                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2537                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2538         } else {
2539                 r200_set_safe_registers(rdev);
2540         }
2541 }
2542
2543 /*
2544  * Debugfs info
2545  */
2546 #if defined(CONFIG_DEBUG_FS)
2547 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2548 {
2549         struct drm_info_node *node = (struct drm_info_node *) m->private;
2550         struct drm_device *dev = node->minor->dev;
2551         struct radeon_device *rdev = dev->dev_private;
2552         uint32_t reg, value;
2553         unsigned i;
2554
2555         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2556         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2557         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2558         for (i = 0; i < 64; i++) {
2559                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2560                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2561                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2562                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2563                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2564         }
2565         return 0;
2566 }
2567
2568 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2569 {
2570         struct drm_info_node *node = (struct drm_info_node *) m->private;
2571         struct drm_device *dev = node->minor->dev;
2572         struct radeon_device *rdev = dev->dev_private;
2573         uint32_t rdp, wdp;
2574         unsigned count, i, j;
2575
2576         radeon_ring_free_size(rdev);
2577         rdp = RREG32(RADEON_CP_RB_RPTR);
2578         wdp = RREG32(RADEON_CP_RB_WPTR);
2579         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2580         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2581         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2582         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2583         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2584         seq_printf(m, "%u dwords in ring\n", count);
2585         for (j = 0; j <= count; j++) {
2586                 i = (rdp + j) & rdev->cp.ptr_mask;
2587                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2588         }
2589         return 0;
2590 }
2591
2592
2593 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2594 {
2595         struct drm_info_node *node = (struct drm_info_node *) m->private;
2596         struct drm_device *dev = node->minor->dev;
2597         struct radeon_device *rdev = dev->dev_private;
2598         uint32_t csq_stat, csq2_stat, tmp;
2599         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2600         unsigned i;
2601
2602         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2603         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2604         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2605         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2606         r_rptr = (csq_stat >> 0) & 0x3ff;
2607         r_wptr = (csq_stat >> 10) & 0x3ff;
2608         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2609         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2610         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2611         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2612         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2613         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2614         seq_printf(m, "Ring rptr %u\n", r_rptr);
2615         seq_printf(m, "Ring wptr %u\n", r_wptr);
2616         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2617         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2618         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2619         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2620         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2621          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2622         seq_printf(m, "Ring fifo:\n");
2623         for (i = 0; i < 256; i++) {
2624                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2625                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2626                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2627         }
2628         seq_printf(m, "Indirect1 fifo:\n");
2629         for (i = 256; i <= 512; i++) {
2630                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2631                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2632                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2633         }
2634         seq_printf(m, "Indirect2 fifo:\n");
2635         for (i = 640; i < ib1_wptr; i++) {
2636                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2637                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2638                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2639         }
2640         return 0;
2641 }
2642
2643 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2644 {
2645         struct drm_info_node *node = (struct drm_info_node *) m->private;
2646         struct drm_device *dev = node->minor->dev;
2647         struct radeon_device *rdev = dev->dev_private;
2648         uint32_t tmp;
2649
2650         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2651         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2652         tmp = RREG32(RADEON_MC_FB_LOCATION);
2653         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2654         tmp = RREG32(RADEON_BUS_CNTL);
2655         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2656         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2657         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2658         tmp = RREG32(RADEON_AGP_BASE);
2659         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2660         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2661         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2662         tmp = RREG32(0x01D0);
2663         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2664         tmp = RREG32(RADEON_AIC_LO_ADDR);
2665         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2666         tmp = RREG32(RADEON_AIC_HI_ADDR);
2667         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2668         tmp = RREG32(0x01E4);
2669         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2670         return 0;
2671 }
2672
2673 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2674         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2675 };
2676
2677 static struct drm_info_list r100_debugfs_cp_list[] = {
2678         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2679         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2680 };
2681
2682 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2683         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2684 };
2685 #endif
2686
2687 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2688 {
2689 #if defined(CONFIG_DEBUG_FS)
2690         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2691 #else
2692         return 0;
2693 #endif
2694 }
2695
2696 int r100_debugfs_cp_init(struct radeon_device *rdev)
2697 {
2698 #if defined(CONFIG_DEBUG_FS)
2699         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2700 #else
2701         return 0;
2702 #endif
2703 }
2704
2705 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2706 {
2707 #if defined(CONFIG_DEBUG_FS)
2708         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2709 #else
2710         return 0;
2711 #endif
2712 }
2713
2714 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2715                          uint32_t tiling_flags, uint32_t pitch,
2716                          uint32_t offset, uint32_t obj_size)
2717 {
2718         int surf_index = reg * 16;
2719         int flags = 0;
2720
2721         if (rdev->family <= CHIP_RS200) {
2722                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2723                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2724                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2725                 if (tiling_flags & RADEON_TILING_MACRO)
2726                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2727         } else if (rdev->family <= CHIP_RV280) {
2728                 if (tiling_flags & (RADEON_TILING_MACRO))
2729                         flags |= R200_SURF_TILE_COLOR_MACRO;
2730                 if (tiling_flags & RADEON_TILING_MICRO)
2731                         flags |= R200_SURF_TILE_COLOR_MICRO;
2732         } else {
2733                 if (tiling_flags & RADEON_TILING_MACRO)
2734                         flags |= R300_SURF_TILE_MACRO;
2735                 if (tiling_flags & RADEON_TILING_MICRO)
2736                         flags |= R300_SURF_TILE_MICRO;
2737         }
2738
2739         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2740                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2741         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2742                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2743
2744         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2745         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2746                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2747                         if (ASIC_IS_RN50(rdev))
2748                                 pitch /= 16;
2749         }
2750
2751         /* r100/r200 divide by 16 */
2752         if (rdev->family < CHIP_R300)
2753                 flags |= pitch / 16;
2754         else
2755                 flags |= pitch / 8;
2756
2757
2758         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2759         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2760         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2761         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2762         return 0;
2763 }
2764
2765 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2766 {
2767         int surf_index = reg * 16;
2768         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2769 }
2770
2771 void r100_bandwidth_update(struct radeon_device *rdev)
2772 {
2773         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2774         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2775         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2776         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2777         fixed20_12 memtcas_ff[8] = {
2778                 dfixed_init(1),
2779                 dfixed_init(2),
2780                 dfixed_init(3),
2781                 dfixed_init(0),
2782                 dfixed_init_half(1),
2783                 dfixed_init_half(2),
2784                 dfixed_init(0),
2785         };
2786         fixed20_12 memtcas_rs480_ff[8] = {
2787                 dfixed_init(0),
2788                 dfixed_init(1),
2789                 dfixed_init(2),
2790                 dfixed_init(3),
2791                 dfixed_init(0),
2792                 dfixed_init_half(1),
2793                 dfixed_init_half(2),
2794                 dfixed_init_half(3),
2795         };
2796         fixed20_12 memtcas2_ff[8] = {
2797                 dfixed_init(0),
2798                 dfixed_init(1),
2799                 dfixed_init(2),
2800                 dfixed_init(3),
2801                 dfixed_init(4),
2802                 dfixed_init(5),
2803                 dfixed_init(6),
2804                 dfixed_init(7),
2805         };
2806         fixed20_12 memtrbs[8] = {
2807                 dfixed_init(1),
2808                 dfixed_init_half(1),
2809                 dfixed_init(2),
2810                 dfixed_init_half(2),
2811                 dfixed_init(3),
2812                 dfixed_init_half(3),
2813                 dfixed_init(4),
2814                 dfixed_init_half(4)
2815         };
2816         fixed20_12 memtrbs_r4xx[8] = {
2817                 dfixed_init(4),
2818                 dfixed_init(5),
2819                 dfixed_init(6),
2820                 dfixed_init(7),
2821                 dfixed_init(8),
2822                 dfixed_init(9),
2823                 dfixed_init(10),
2824                 dfixed_init(11)
2825         };
2826         fixed20_12 min_mem_eff;
2827         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2828         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2829         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2830                 disp_drain_rate2, read_return_rate;
2831         fixed20_12 time_disp1_drop_priority;
2832         int c;
2833         int cur_size = 16;       /* in octawords */
2834         int critical_point = 0, critical_point2;
2835 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2836         int stop_req, max_stop_req;
2837         struct drm_display_mode *mode1 = NULL;
2838         struct drm_display_mode *mode2 = NULL;
2839         uint32_t pixel_bytes1 = 0;
2840         uint32_t pixel_bytes2 = 0;
2841
2842         radeon_update_display_priority(rdev);
2843
2844         if (rdev->mode_info.crtcs[0]->base.enabled) {
2845                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2846                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2847         }
2848         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2849                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2850                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2851                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2852                 }
2853         }
2854
2855         min_mem_eff.full = dfixed_const_8(0);
2856         /* get modes */
2857         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2858                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2859                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2860                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2861                 /* check crtc enables */
2862                 if (mode2)
2863                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2864                 if (mode1)
2865                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2866                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2867         }
2868
2869         /*
2870          * determine is there is enough bw for current mode
2871          */
2872         sclk_ff = rdev->pm.sclk;
2873         mclk_ff = rdev->pm.mclk;
2874
2875         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2876         temp_ff.full = dfixed_const(temp);
2877         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2878
2879         pix_clk.full = 0;
2880         pix_clk2.full = 0;
2881         peak_disp_bw.full = 0;
2882         if (mode1) {
2883                 temp_ff.full = dfixed_const(1000);
2884                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2885                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2886                 temp_ff.full = dfixed_const(pixel_bytes1);
2887                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2888         }
2889         if (mode2) {
2890                 temp_ff.full = dfixed_const(1000);
2891                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2892                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2893                 temp_ff.full = dfixed_const(pixel_bytes2);
2894                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2895         }
2896
2897         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2898         if (peak_disp_bw.full >= mem_bw.full) {
2899                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2900                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2901         }
2902
2903         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2904         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2905         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2906                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2907                 mem_trp  = ((temp & 0x3)) + 1;
2908                 mem_tras = ((temp & 0x70) >> 4) + 1;
2909         } else if (rdev->family == CHIP_R300 ||
2910                    rdev->family == CHIP_R350) { /* r300, r350 */
2911                 mem_trcd = (temp & 0x7) + 1;
2912                 mem_trp = ((temp >> 8) & 0x7) + 1;
2913                 mem_tras = ((temp >> 11) & 0xf) + 4;
2914         } else if (rdev->family == CHIP_RV350 ||
2915                    rdev->family <= CHIP_RV380) {
2916                 /* rv3x0 */
2917                 mem_trcd = (temp & 0x7) + 3;
2918                 mem_trp = ((temp >> 8) & 0x7) + 3;
2919                 mem_tras = ((temp >> 11) & 0xf) + 6;
2920         } else if (rdev->family == CHIP_R420 ||
2921                    rdev->family == CHIP_R423 ||
2922                    rdev->family == CHIP_RV410) {
2923                 /* r4xx */
2924                 mem_trcd = (temp & 0xf) + 3;
2925                 if (mem_trcd > 15)
2926                         mem_trcd = 15;
2927                 mem_trp = ((temp >> 8) & 0xf) + 3;
2928                 if (mem_trp > 15)
2929                         mem_trp = 15;
2930                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2931                 if (mem_tras > 31)
2932                         mem_tras = 31;
2933         } else { /* RV200, R200 */
2934                 mem_trcd = (temp & 0x7) + 1;
2935                 mem_trp = ((temp >> 8) & 0x7) + 1;
2936                 mem_tras = ((temp >> 12) & 0xf) + 4;
2937         }
2938         /* convert to FF */
2939         trcd_ff.full = dfixed_const(mem_trcd);
2940         trp_ff.full = dfixed_const(mem_trp);
2941         tras_ff.full = dfixed_const(mem_tras);
2942
2943         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2944         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2945         data = (temp & (7 << 20)) >> 20;
2946         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2947                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2948                         tcas_ff = memtcas_rs480_ff[data];
2949                 else
2950                         tcas_ff = memtcas_ff[data];
2951         } else
2952                 tcas_ff = memtcas2_ff[data];
2953
2954         if (rdev->family == CHIP_RS400 ||
2955             rdev->family == CHIP_RS480) {
2956                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2957                 data = (temp >> 23) & 0x7;
2958                 if (data < 5)
2959                         tcas_ff.full += dfixed_const(data);
2960         }
2961
2962         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2963                 /* on the R300, Tcas is included in Trbs.
2964                  */
2965                 temp = RREG32(RADEON_MEM_CNTL);
2966                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2967                 if (data == 1) {
2968                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2969                                 temp = RREG32(R300_MC_IND_INDEX);
2970                                 temp &= ~R300_MC_IND_ADDR_MASK;
2971                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2972                                 WREG32(R300_MC_IND_INDEX, temp);
2973                                 temp = RREG32(R300_MC_IND_DATA);
2974                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2975                         } else {
2976                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2977                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2978                         }
2979                 } else {
2980                         temp = RREG32(R300_MC_READ_CNTL_AB);
2981                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2982                 }
2983                 if (rdev->family == CHIP_RV410 ||
2984                     rdev->family == CHIP_R420 ||
2985                     rdev->family == CHIP_R423)
2986                         trbs_ff = memtrbs_r4xx[data];
2987                 else
2988                         trbs_ff = memtrbs[data];
2989                 tcas_ff.full += trbs_ff.full;
2990         }
2991
2992         sclk_eff_ff.full = sclk_ff.full;
2993
2994         if (rdev->flags & RADEON_IS_AGP) {
2995                 fixed20_12 agpmode_ff;
2996                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2997                 temp_ff.full = dfixed_const_666(16);
2998                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2999         }
3000         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3001
3002         if (ASIC_IS_R300(rdev)) {
3003                 sclk_delay_ff.full = dfixed_const(250);
3004         } else {
3005                 if ((rdev->family == CHIP_RV100) ||
3006                     rdev->flags & RADEON_IS_IGP) {
3007                         if (rdev->mc.vram_is_ddr)
3008                                 sclk_delay_ff.full = dfixed_const(41);
3009                         else
3010                                 sclk_delay_ff.full = dfixed_const(33);
3011                 } else {
3012                         if (rdev->mc.vram_width == 128)
3013                                 sclk_delay_ff.full = dfixed_const(57);
3014                         else
3015                                 sclk_delay_ff.full = dfixed_const(41);
3016                 }
3017         }
3018
3019         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3020
3021         if (rdev->mc.vram_is_ddr) {
3022                 if (rdev->mc.vram_width == 32) {
3023                         k1.full = dfixed_const(40);
3024                         c  = 3;
3025                 } else {
3026                         k1.full = dfixed_const(20);
3027                         c  = 1;
3028                 }
3029         } else {
3030                 k1.full = dfixed_const(40);
3031                 c  = 3;
3032         }
3033
3034         temp_ff.full = dfixed_const(2);
3035         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3036         temp_ff.full = dfixed_const(c);
3037         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3038         temp_ff.full = dfixed_const(4);
3039         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3040         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3041         mc_latency_mclk.full += k1.full;
3042
3043         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3044         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3045
3046         /*
3047           HW cursor time assuming worst case of full size colour cursor.
3048         */
3049         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3050         temp_ff.full += trcd_ff.full;
3051         if (temp_ff.full < tras_ff.full)
3052                 temp_ff.full = tras_ff.full;
3053         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3054
3055         temp_ff.full = dfixed_const(cur_size);
3056         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3057         /*
3058           Find the total latency for the display data.
3059         */
3060         disp_latency_overhead.full = dfixed_const(8);
3061         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3062         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3063         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3064
3065         if (mc_latency_mclk.full > mc_latency_sclk.full)
3066                 disp_latency.full = mc_latency_mclk.full;
3067         else
3068                 disp_latency.full = mc_latency_sclk.full;
3069
3070         /* setup Max GRPH_STOP_REQ default value */
3071         if (ASIC_IS_RV100(rdev))
3072                 max_stop_req = 0x5c;
3073         else
3074                 max_stop_req = 0x7c;
3075
3076         if (mode1) {
3077                 /*  CRTC1
3078                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3079                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3080                 */
3081                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3082
3083                 if (stop_req > max_stop_req)
3084                         stop_req = max_stop_req;
3085
3086                 /*
3087                   Find the drain rate of the display buffer.
3088                 */
3089                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3090                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3091
3092                 /*
3093                   Find the critical point of the display buffer.
3094                 */
3095                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3096                 crit_point_ff.full += dfixed_const_half(0);
3097
3098                 critical_point = dfixed_trunc(crit_point_ff);
3099
3100                 if (rdev->disp_priority == 2) {
3101                         critical_point = 0;
3102                 }
3103
3104                 /*
3105                   The critical point should never be above max_stop_req-4.  Setting
3106                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3107                 */
3108                 if (max_stop_req - critical_point < 4)
3109                         critical_point = 0;
3110
3111                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3112                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3113                         critical_point = 0x10;
3114                 }
3115
3116                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3117                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3118                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3119                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3120                 if ((rdev->family == CHIP_R350) &&
3121                     (stop_req > 0x15)) {
3122                         stop_req -= 0x10;
3123                 }
3124                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3125                 temp |= RADEON_GRPH_BUFFER_SIZE;
3126                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3127                           RADEON_GRPH_CRITICAL_AT_SOF |
3128                           RADEON_GRPH_STOP_CNTL);
3129                 /*
3130                   Write the result into the register.
3131                 */
3132                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3133                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3134
3135 #if 0
3136                 if ((rdev->family == CHIP_RS400) ||
3137                     (rdev->family == CHIP_RS480)) {
3138                         /* attempt to program RS400 disp regs correctly ??? */
3139                         temp = RREG32(RS400_DISP1_REG_CNTL);
3140                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3141                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3142                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3143                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3144                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3145                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3146                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3147                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3148                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3149                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3150                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3151                 }
3152 #endif
3153
3154                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3155                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3156                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3157         }
3158
3159         if (mode2) {
3160                 u32 grph2_cntl;
3161                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3162
3163                 if (stop_req > max_stop_req)
3164                         stop_req = max_stop_req;
3165
3166                 /*
3167                   Find the drain rate of the display buffer.
3168                 */
3169                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3170                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3171
3172                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3173                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3174                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3175                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3176                 if ((rdev->family == CHIP_R350) &&
3177                     (stop_req > 0x15)) {
3178                         stop_req -= 0x10;
3179                 }
3180                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3181                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3182                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3183                           RADEON_GRPH_CRITICAL_AT_SOF |
3184                           RADEON_GRPH_STOP_CNTL);
3185
3186                 if ((rdev->family == CHIP_RS100) ||
3187                     (rdev->family == CHIP_RS200))
3188                         critical_point2 = 0;
3189                 else {
3190                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3191                         temp_ff.full = dfixed_const(temp);
3192                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3193                         if (sclk_ff.full < temp_ff.full)
3194                                 temp_ff.full = sclk_ff.full;
3195
3196                         read_return_rate.full = temp_ff.full;
3197
3198                         if (mode1) {
3199                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3200                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3201                         } else {
3202                                 time_disp1_drop_priority.full = 0;
3203                         }
3204                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3205                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3206                         crit_point_ff.full += dfixed_const_half(0);
3207
3208                         critical_point2 = dfixed_trunc(crit_point_ff);
3209
3210                         if (rdev->disp_priority == 2) {
3211                                 critical_point2 = 0;
3212                         }
3213
3214                         if (max_stop_req - critical_point2 < 4)
3215                                 critical_point2 = 0;
3216
3217                 }
3218
3219                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3220                         /* some R300 cards have problem with this set to 0 */
3221                         critical_point2 = 0x10;
3222                 }
3223
3224                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3225                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3226
3227                 if ((rdev->family == CHIP_RS400) ||
3228                     (rdev->family == CHIP_RS480)) {
3229 #if 0
3230                         /* attempt to program RS400 disp2 regs correctly ??? */
3231                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3232                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3233                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3234                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3235                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3236                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3237                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3238                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3239                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3240                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3241                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3242                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3243 #endif
3244                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3245                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3246                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3247                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3248                 }
3249
3250                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3251                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3252         }
3253 }
3254
3255 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3256 {
3257         DRM_ERROR("pitch                      %d\n", t->pitch);
3258         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3259         DRM_ERROR("width                      %d\n", t->width);
3260         DRM_ERROR("width_11                   %d\n", t->width_11);
3261         DRM_ERROR("height                     %d\n", t->height);
3262         DRM_ERROR("height_11                  %d\n", t->height_11);
3263         DRM_ERROR("num levels                 %d\n", t->num_levels);
3264         DRM_ERROR("depth                      %d\n", t->txdepth);
3265         DRM_ERROR("bpp                        %d\n", t->cpp);
3266         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3267         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3268         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3269         DRM_ERROR("compress format            %d\n", t->compress_format);
3270 }
3271
3272 static int r100_track_compress_size(int compress_format, int w, int h)
3273 {
3274         int block_width, block_height, block_bytes;
3275         int wblocks, hblocks;
3276         int min_wblocks;
3277         int sz;
3278
3279         block_width = 4;
3280         block_height = 4;
3281
3282         switch (compress_format) {
3283         case R100_TRACK_COMP_DXT1:
3284                 block_bytes = 8;
3285                 min_wblocks = 4;
3286                 break;
3287         default:
3288         case R100_TRACK_COMP_DXT35:
3289                 block_bytes = 16;
3290                 min_wblocks = 2;
3291                 break;
3292         }
3293
3294         hblocks = (h + block_height - 1) / block_height;
3295         wblocks = (w + block_width - 1) / block_width;
3296         if (wblocks < min_wblocks)
3297                 wblocks = min_wblocks;
3298         sz = wblocks * hblocks * block_bytes;
3299         return sz;
3300 }
3301
3302 static int r100_cs_track_cube(struct radeon_device *rdev,
3303                               struct r100_cs_track *track, unsigned idx)
3304 {
3305         unsigned face, w, h;
3306         struct radeon_bo *cube_robj;
3307         unsigned long size;
3308         unsigned compress_format = track->textures[idx].compress_format;
3309
3310         for (face = 0; face < 5; face++) {
3311                 cube_robj = track->textures[idx].cube_info[face].robj;
3312                 w = track->textures[idx].cube_info[face].width;
3313                 h = track->textures[idx].cube_info[face].height;
3314
3315                 if (compress_format) {
3316                         size = r100_track_compress_size(compress_format, w, h);
3317                 } else
3318                         size = w * h;
3319                 size *= track->textures[idx].cpp;
3320
3321                 size += track->textures[idx].cube_info[face].offset;
3322
3323                 if (size > radeon_bo_size(cube_robj)) {
3324                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3325                                   size, radeon_bo_size(cube_robj));
3326                         r100_cs_track_texture_print(&track->textures[idx]);
3327                         return -1;
3328                 }
3329         }
3330         return 0;
3331 }
3332
3333 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3334                                        struct r100_cs_track *track)
3335 {
3336         struct radeon_bo *robj;
3337         unsigned long size;
3338         unsigned u, i, w, h, d;
3339         int ret;
3340
3341         for (u = 0; u < track->num_texture; u++) {
3342                 if (!track->textures[u].enabled)
3343                         continue;
3344                 if (track->textures[u].lookup_disable)
3345                         continue;
3346                 robj = track->textures[u].robj;
3347                 if (robj == NULL) {
3348                         DRM_ERROR("No texture bound to unit %u\n", u);
3349                         return -EINVAL;
3350                 }
3351                 size = 0;
3352                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3353                         if (track->textures[u].use_pitch) {
3354                                 if (rdev->family < CHIP_R300)
3355                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3356                                 else
3357                                         w = track->textures[u].pitch / (1 << i);
3358                         } else {
3359                                 w = track->textures[u].width;
3360                                 if (rdev->family >= CHIP_RV515)
3361                                         w |= track->textures[u].width_11;
3362                                 w = w / (1 << i);
3363                                 if (track->textures[u].roundup_w)
3364                                         w = roundup_pow_of_two(w);
3365                         }
3366                         h = track->textures[u].height;
3367                         if (rdev->family >= CHIP_RV515)
3368                                 h |= track->textures[u].height_11;
3369                         h = h / (1 << i);
3370                         if (track->textures[u].roundup_h)
3371                                 h = roundup_pow_of_two(h);
3372                         if (track->textures[u].tex_coord_type == 1) {
3373                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3374                                 if (!d)
3375                                         d = 1;
3376                         } else {
3377                                 d = 1;
3378                         }
3379                         if (track->textures[u].compress_format) {
3380
3381                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3382                                 /* compressed textures are block based */
3383                         } else
3384                                 size += w * h * d;
3385                 }
3386                 size *= track->textures[u].cpp;
3387
3388                 switch (track->textures[u].tex_coord_type) {
3389                 case 0:
3390                 case 1:
3391                         break;
3392                 case 2:
3393                         if (track->separate_cube) {
3394                                 ret = r100_cs_track_cube(rdev, track, u);
3395                                 if (ret)
3396                                         return ret;
3397                         } else
3398                                 size *= 6;
3399                         break;
3400                 default:
3401                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3402                                   "%u\n", track->textures[u].tex_coord_type, u);
3403                         return -EINVAL;
3404                 }
3405                 if (size > radeon_bo_size(robj)) {
3406                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3407                                   "%lu\n", u, size, radeon_bo_size(robj));
3408                         r100_cs_track_texture_print(&track->textures[u]);
3409                         return -EINVAL;
3410                 }
3411         }
3412         return 0;
3413 }
3414
3415 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3416 {
3417         unsigned i;
3418         unsigned long size;
3419         unsigned prim_walk;
3420         unsigned nverts;
3421         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3422
3423         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3424             !track->blend_read_enable)
3425                 num_cb = 0;
3426
3427         for (i = 0; i < num_cb; i++) {
3428                 if (track->cb[i].robj == NULL) {
3429                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3430                         return -EINVAL;
3431                 }
3432                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3433                 size += track->cb[i].offset;
3434                 if (size > radeon_bo_size(track->cb[i].robj)) {
3435                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3436                                   "(need %lu have %lu) !\n", i, size,
3437                                   radeon_bo_size(track->cb[i].robj));
3438                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3439                                   i, track->cb[i].pitch, track->cb[i].cpp,
3440                                   track->cb[i].offset, track->maxy);
3441                         return -EINVAL;
3442                 }
3443         }
3444         track->cb_dirty = false;
3445
3446         if (track->zb_dirty && track->z_enabled) {
3447                 if (track->zb.robj == NULL) {
3448                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3449                         return -EINVAL;
3450                 }
3451                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3452                 size += track->zb.offset;
3453                 if (size > radeon_bo_size(track->zb.robj)) {
3454                         DRM_ERROR("[drm] Buffer too small for z buffer "
3455                                   "(need %lu have %lu) !\n", size,
3456                                   radeon_bo_size(track->zb.robj));
3457                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3458                                   track->zb.pitch, track->zb.cpp,
3459                                   track->zb.offset, track->maxy);
3460                         return -EINVAL;
3461                 }
3462         }
3463         track->zb_dirty = false;
3464
3465         if (track->aa_dirty && track->aaresolve) {
3466                 if (track->aa.robj == NULL) {
3467                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3468                         return -EINVAL;
3469                 }
3470                 /* I believe the format comes from colorbuffer0. */
3471                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3472                 size += track->aa.offset;
3473                 if (size > radeon_bo_size(track->aa.robj)) {
3474                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3475                                   "(need %lu have %lu) !\n", i, size,
3476                                   radeon_bo_size(track->aa.robj));
3477                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3478                                   i, track->aa.pitch, track->cb[0].cpp,
3479                                   track->aa.offset, track->maxy);
3480                         return -EINVAL;
3481                 }
3482         }
3483         track->aa_dirty = false;
3484
3485         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3486         if (track->vap_vf_cntl & (1 << 14)) {
3487                 nverts = track->vap_alt_nverts;
3488         } else {
3489                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3490         }
3491         switch (prim_walk) {
3492         case 1:
3493                 for (i = 0; i < track->num_arrays; i++) {
3494                         size = track->arrays[i].esize * track->max_indx * 4;
3495                         if (track->arrays[i].robj == NULL) {
3496                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3497                                           "bound\n", prim_walk, i);
3498                                 return -EINVAL;
3499                         }
3500                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3501                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3502                                         "need %lu dwords have %lu dwords\n",
3503                                         prim_walk, i, size >> 2,
3504                                         radeon_bo_size(track->arrays[i].robj)
3505                                         >> 2);
3506                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3507                                 return -EINVAL;
3508                         }
3509                 }
3510                 break;
3511         case 2:
3512                 for (i = 0; i < track->num_arrays; i++) {
3513                         size = track->arrays[i].esize * (nverts - 1) * 4;
3514                         if (track->arrays[i].robj == NULL) {
3515                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3516                                           "bound\n", prim_walk, i);
3517                                 return -EINVAL;
3518                         }
3519                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3520                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3521                                         "need %lu dwords have %lu dwords\n",
3522                                         prim_walk, i, size >> 2,
3523                                         radeon_bo_size(track->arrays[i].robj)
3524                                         >> 2);
3525                                 return -EINVAL;
3526                         }
3527                 }
3528                 break;
3529         case 3:
3530                 size = track->vtx_size * nverts;
3531                 if (size != track->immd_dwords) {
3532                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3533                                   track->immd_dwords, size);
3534                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3535                                   nverts, track->vtx_size);
3536                         return -EINVAL;
3537                 }
3538                 break;
3539         default:
3540                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3541                           prim_walk);
3542                 return -EINVAL;
3543         }
3544
3545         if (track->tex_dirty) {
3546                 track->tex_dirty = false;
3547                 return r100_cs_track_texture_check(rdev, track);
3548         }
3549         return 0;
3550 }
3551
3552 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3553 {
3554         unsigned i, face;
3555
3556         track->cb_dirty = true;
3557         track->zb_dirty = true;
3558         track->tex_dirty = true;
3559         track->aa_dirty = true;
3560
3561         if (rdev->family < CHIP_R300) {
3562                 track->num_cb = 1;
3563                 if (rdev->family <= CHIP_RS200)
3564                         track->num_texture = 3;
3565                 else
3566                         track->num_texture = 6;
3567                 track->maxy = 2048;
3568                 track->separate_cube = 1;
3569         } else {
3570                 track->num_cb = 4;
3571                 track->num_texture = 16;
3572                 track->maxy = 4096;
3573                 track->separate_cube = 0;
3574                 track->aaresolve = false;
3575                 track->aa.robj = NULL;
3576         }
3577
3578         for (i = 0; i < track->num_cb; i++) {
3579                 track->cb[i].robj = NULL;
3580                 track->cb[i].pitch = 8192;
3581                 track->cb[i].cpp = 16;
3582                 track->cb[i].offset = 0;
3583         }
3584         track->z_enabled = true;
3585         track->zb.robj = NULL;
3586         track->zb.pitch = 8192;
3587         track->zb.cpp = 4;
3588         track->zb.offset = 0;
3589         track->vtx_size = 0x7F;
3590         track->immd_dwords = 0xFFFFFFFFUL;
3591         track->num_arrays = 11;
3592         track->max_indx = 0x00FFFFFFUL;
3593         for (i = 0; i < track->num_arrays; i++) {
3594                 track->arrays[i].robj = NULL;
3595                 track->arrays[i].esize = 0x7F;
3596         }
3597         for (i = 0; i < track->num_texture; i++) {
3598                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3599                 track->textures[i].pitch = 16536;
3600                 track->textures[i].width = 16536;
3601                 track->textures[i].height = 16536;
3602                 track->textures[i].width_11 = 1 << 11;
3603                 track->textures[i].height_11 = 1 << 11;
3604                 track->textures[i].num_levels = 12;
3605                 if (rdev->family <= CHIP_RS200) {
3606                         track->textures[i].tex_coord_type = 0;
3607                         track->textures[i].txdepth = 0;
3608                 } else {
3609                         track->textures[i].txdepth = 16;
3610                         track->textures[i].tex_coord_type = 1;
3611                 }
3612                 track->textures[i].cpp = 64;
3613                 track->textures[i].robj = NULL;
3614                 /* CS IB emission code makes sure texture unit are disabled */
3615                 track->textures[i].enabled = false;
3616                 track->textures[i].lookup_disable = false;
3617                 track->textures[i].roundup_w = true;
3618                 track->textures[i].roundup_h = true;
3619                 if (track->separate_cube)
3620                         for (face = 0; face < 5; face++) {
3621                                 track->textures[i].cube_info[face].robj = NULL;
3622                                 track->textures[i].cube_info[face].width = 16536;
3623                                 track->textures[i].cube_info[face].height = 16536;
3624                                 track->textures[i].cube_info[face].offset = 0;
3625                         }
3626         }
3627 }
3628
3629 int r100_ring_test(struct radeon_device *rdev)
3630 {
3631         uint32_t scratch;
3632         uint32_t tmp = 0;
3633         unsigned i;
3634         int r;
3635
3636         r = radeon_scratch_get(rdev, &scratch);
3637         if (r) {
3638                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3639                 return r;
3640         }
3641         WREG32(scratch, 0xCAFEDEAD);
3642         r = radeon_ring_lock(rdev, 2);
3643         if (r) {
3644                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3645                 radeon_scratch_free(rdev, scratch);
3646                 return r;
3647         }
3648         radeon_ring_write(rdev, PACKET0(scratch, 0));
3649         radeon_ring_write(rdev, 0xDEADBEEF);
3650         radeon_ring_unlock_commit(rdev);
3651         for (i = 0; i < rdev->usec_timeout; i++) {
3652                 tmp = RREG32(scratch);
3653                 if (tmp == 0xDEADBEEF) {
3654                         break;
3655                 }
3656                 DRM_UDELAY(1);
3657         }
3658         if (i < rdev->usec_timeout) {
3659                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3660         } else {
3661                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3662                           scratch, tmp);
3663                 r = -EINVAL;
3664         }
3665         radeon_scratch_free(rdev, scratch);
3666         return r;
3667 }
3668
3669 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3670 {
3671         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3672         radeon_ring_write(rdev, ib->gpu_addr);
3673         radeon_ring_write(rdev, ib->length_dw);
3674 }
3675
3676 int r100_ib_test(struct radeon_device *rdev)
3677 {
3678         struct radeon_ib *ib;
3679         uint32_t scratch;
3680         uint32_t tmp = 0;
3681         unsigned i;
3682         int r;
3683
3684         r = radeon_scratch_get(rdev, &scratch);
3685         if (r) {
3686                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3687                 return r;
3688         }
3689         WREG32(scratch, 0xCAFEDEAD);
3690         r = radeon_ib_get(rdev, &ib);
3691         if (r) {
3692                 return r;
3693         }
3694         ib->ptr[0] = PACKET0(scratch, 0);
3695         ib->ptr[1] = 0xDEADBEEF;
3696         ib->ptr[2] = PACKET2(0);
3697         ib->ptr[3] = PACKET2(0);
3698         ib->ptr[4] = PACKET2(0);
3699         ib->ptr[5] = PACKET2(0);
3700         ib->ptr[6] = PACKET2(0);
3701         ib->ptr[7] = PACKET2(0);
3702         ib->length_dw = 8;
3703         r = radeon_ib_schedule(rdev, ib);
3704         if (r) {
3705                 radeon_scratch_free(rdev, scratch);
3706                 radeon_ib_free(rdev, &ib);
3707                 return r;
3708         }
3709         r = radeon_fence_wait(ib->fence, false);
3710         if (r) {
3711                 return r;
3712         }
3713         for (i = 0; i < rdev->usec_timeout; i++) {
3714                 tmp = RREG32(scratch);
3715                 if (tmp == 0xDEADBEEF) {
3716                         break;
3717                 }
3718                 DRM_UDELAY(1);
3719         }
3720         if (i < rdev->usec_timeout) {
3721                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3722         } else {
3723                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3724                           scratch, tmp);
3725                 r = -EINVAL;
3726         }
3727         radeon_scratch_free(rdev, scratch);
3728         radeon_ib_free(rdev, &ib);
3729         return r;
3730 }
3731
3732 void r100_ib_fini(struct radeon_device *rdev)
3733 {
3734         radeon_ib_pool_fini(rdev);
3735 }
3736
3737 int r100_ib_init(struct radeon_device *rdev)
3738 {
3739         int r;
3740
3741         r = radeon_ib_pool_init(rdev);
3742         if (r) {
3743                 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3744                 r100_ib_fini(rdev);
3745                 return r;
3746         }
3747         r = r100_ib_test(rdev);
3748         if (r) {
3749                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3750                 r100_ib_fini(rdev);
3751                 return r;
3752         }
3753         return 0;
3754 }
3755
3756 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3757 {
3758         /* Shutdown CP we shouldn't need to do that but better be safe than
3759          * sorry
3760          */
3761         rdev->cp.ready = false;
3762         WREG32(R_000740_CP_CSQ_CNTL, 0);
3763
3764         /* Save few CRTC registers */
3765         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3766         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3767         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3768         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3769         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3770                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3771                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3772         }
3773
3774         /* Disable VGA aperture access */
3775         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3776         /* Disable cursor, overlay, crtc */
3777         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3778         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3779                                         S_000054_CRTC_DISPLAY_DIS(1));
3780         WREG32(R_000050_CRTC_GEN_CNTL,
3781                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3782                         S_000050_CRTC_DISP_REQ_EN_B(1));
3783         WREG32(R_000420_OV0_SCALE_CNTL,
3784                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3785         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3786         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3787                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3788                                                 S_000360_CUR2_LOCK(1));
3789                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3790                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3791                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3792                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3793                 WREG32(R_000360_CUR2_OFFSET,
3794                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3795         }
3796 }
3797
3798 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3799 {
3800         /* Update base address for crtc */
3801         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3802         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3803                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3804         }
3805         /* Restore CRTC registers */
3806         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3807         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3808         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3809         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3810                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3811         }
3812 }
3813
3814 void r100_vga_render_disable(struct radeon_device *rdev)
3815 {
3816         u32 tmp;
3817
3818         tmp = RREG8(R_0003C2_GENMO_WT);
3819         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3820 }
3821
3822 static void r100_debugfs(struct radeon_device *rdev)
3823 {
3824         int r;
3825
3826         r = r100_debugfs_mc_info_init(rdev);
3827         if (r)
3828                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3829 }
3830
3831 static void r100_mc_program(struct radeon_device *rdev)
3832 {
3833         struct r100_mc_save save;
3834
3835         /* Stops all mc clients */
3836         r100_mc_stop(rdev, &save);
3837         if (rdev->flags & RADEON_IS_AGP) {
3838                 WREG32(R_00014C_MC_AGP_LOCATION,
3839                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3840                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3841                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3842                 if (rdev->family > CHIP_RV200)
3843                         WREG32(R_00015C_AGP_BASE_2,
3844                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3845         } else {
3846                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3847                 WREG32(R_000170_AGP_BASE, 0);
3848                 if (rdev->family > CHIP_RV200)
3849                         WREG32(R_00015C_AGP_BASE_2, 0);
3850         }
3851         /* Wait for mc idle */
3852         if (r100_mc_wait_for_idle(rdev))
3853                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3854         /* Program MC, should be a 32bits limited address space */
3855         WREG32(R_000148_MC_FB_LOCATION,
3856                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3857                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3858         r100_mc_resume(rdev, &save);
3859 }
3860
3861 void r100_clock_startup(struct radeon_device *rdev)
3862 {
3863         u32 tmp;
3864
3865         if (radeon_dynclks != -1 && radeon_dynclks)
3866                 radeon_legacy_set_clock_gating(rdev, 1);
3867         /* We need to force on some of the block */
3868         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3869         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3870         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3871                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3872         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3873 }
3874
3875 static int r100_startup(struct radeon_device *rdev)
3876 {
3877         int r;
3878
3879         /* set common regs */
3880         r100_set_common_regs(rdev);
3881         /* program mc */
3882         r100_mc_program(rdev);
3883         /* Resume clock */
3884         r100_clock_startup(rdev);
3885         /* Initialize GART (initialize after TTM so we can allocate
3886          * memory through TTM but finalize after TTM) */
3887         r100_enable_bm(rdev);
3888         if (rdev->flags & RADEON_IS_PCI) {
3889                 r = r100_pci_gart_enable(rdev);
3890                 if (r)
3891                         return r;
3892         }
3893
3894         /* allocate wb buffer */
3895         r = radeon_wb_init(rdev);
3896         if (r)
3897                 return r;
3898
3899         /* Enable IRQ */
3900         r100_irq_set(rdev);
3901         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3902         /* 1M ring buffer */
3903         r = r100_cp_init(rdev, 1024 * 1024);
3904         if (r) {
3905                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3906                 return r;
3907         }
3908         r = r100_ib_init(rdev);
3909         if (r) {
3910                 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3911                 return r;
3912         }
3913         return 0;
3914 }
3915
3916 int r100_resume(struct radeon_device *rdev)
3917 {
3918         /* Make sur GART are not working */
3919         if (rdev->flags & RADEON_IS_PCI)
3920                 r100_pci_gart_disable(rdev);
3921         /* Resume clock before doing reset */
3922         r100_clock_startup(rdev);
3923         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3924         if (radeon_asic_reset(rdev)) {
3925                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3926                         RREG32(R_000E40_RBBM_STATUS),
3927                         RREG32(R_0007C0_CP_STAT));
3928         }
3929         /* post */
3930         radeon_combios_asic_init(rdev->ddev);
3931         /* Resume clock after posting */
3932         r100_clock_startup(rdev);
3933         /* Initialize surface registers */
3934         radeon_surface_init(rdev);
3935         return r100_startup(rdev);
3936 }
3937
3938 int r100_suspend(struct radeon_device *rdev)
3939 {
3940         r100_cp_disable(rdev);
3941         radeon_wb_disable(rdev);
3942         r100_irq_disable(rdev);
3943         if (rdev->flags & RADEON_IS_PCI)
3944                 r100_pci_gart_disable(rdev);
3945         return 0;
3946 }
3947
3948 void r100_fini(struct radeon_device *rdev)
3949 {
3950         r100_cp_fini(rdev);
3951         radeon_wb_fini(rdev);
3952         r100_ib_fini(rdev);
3953         radeon_gem_fini(rdev);
3954         if (rdev->flags & RADEON_IS_PCI)
3955                 r100_pci_gart_fini(rdev);
3956         radeon_agp_fini(rdev);
3957         radeon_irq_kms_fini(rdev);
3958         radeon_fence_driver_fini(rdev);
3959         radeon_bo_fini(rdev);
3960         radeon_atombios_fini(rdev);
3961         kfree(rdev->bios);
3962         rdev->bios = NULL;
3963 }
3964
3965 /*
3966  * Due to how kexec works, it can leave the hw fully initialised when it
3967  * boots the new kernel. However doing our init sequence with the CP and
3968  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3969  * do some quick sanity checks and restore sane values to avoid this
3970  * problem.
3971  */
3972 void r100_restore_sanity(struct radeon_device *rdev)
3973 {
3974         u32 tmp;
3975
3976         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3977         if (tmp) {
3978                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3979         }
3980         tmp = RREG32(RADEON_CP_RB_CNTL);
3981         if (tmp) {
3982                 WREG32(RADEON_CP_RB_CNTL, 0);
3983         }
3984         tmp = RREG32(RADEON_SCRATCH_UMSK);
3985         if (tmp) {
3986                 WREG32(RADEON_SCRATCH_UMSK, 0);
3987         }
3988 }
3989
3990 int r100_init(struct radeon_device *rdev)
3991 {
3992         int r;
3993
3994         /* Register debugfs file specific to this group of asics */
3995         r100_debugfs(rdev);
3996         /* Disable VGA */
3997         r100_vga_render_disable(rdev);
3998         /* Initialize scratch registers */
3999         radeon_scratch_init(rdev);
4000         /* Initialize surface registers */
4001         radeon_surface_init(rdev);
4002         /* sanity check some register to avoid hangs like after kexec */
4003         r100_restore_sanity(rdev);
4004         /* TODO: disable VGA need to use VGA request */
4005         /* BIOS*/
4006         if (!radeon_get_bios(rdev)) {
4007                 if (ASIC_IS_AVIVO(rdev))
4008                         return -EINVAL;
4009         }
4010         if (rdev->is_atom_bios) {
4011                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4012                 return -EINVAL;
4013         } else {
4014                 r = radeon_combios_init(rdev);
4015                 if (r)
4016                         return r;
4017         }
4018         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4019         if (radeon_asic_reset(rdev)) {
4020                 dev_warn(rdev->dev,
4021                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4022                         RREG32(R_000E40_RBBM_STATUS),
4023                         RREG32(R_0007C0_CP_STAT));
4024         }
4025         /* check if cards are posted or not */
4026         if (radeon_boot_test_post_card(rdev) == false)
4027                 return -EINVAL;
4028         /* Set asic errata */
4029         r100_errata(rdev);
4030         /* Initialize clocks */
4031         radeon_get_clock_info(rdev->ddev);
4032         /* initialize AGP */
4033         if (rdev->flags & RADEON_IS_AGP) {
4034                 r = radeon_agp_init(rdev);
4035                 if (r) {
4036                         radeon_agp_disable(rdev);
4037                 }
4038         }
4039         /* initialize VRAM */
4040         r100_mc_init(rdev);
4041         /* Fence driver */
4042         r = radeon_fence_driver_init(rdev);
4043         if (r)
4044                 return r;
4045         r = radeon_irq_kms_init(rdev);
4046         if (r)
4047                 return r;
4048         /* Memory manager */
4049         r = radeon_bo_init(rdev);
4050         if (r)
4051                 return r;
4052         if (rdev->flags & RADEON_IS_PCI) {
4053                 r = r100_pci_gart_init(rdev);
4054                 if (r)
4055                         return r;
4056         }
4057         r100_set_safe_registers(rdev);
4058         rdev->accel_working = true;
4059         r = r100_startup(rdev);
4060         if (r) {
4061                 /* Somethings want wront with the accel init stop accel */
4062                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4063                 r100_cp_fini(rdev);
4064                 radeon_wb_fini(rdev);
4065                 r100_ib_fini(rdev);
4066                 radeon_irq_kms_fini(rdev);
4067                 if (rdev->flags & RADEON_IS_PCI)
4068                         r100_pci_gart_fini(rdev);
4069                 rdev->accel_working = false;
4070         }
4071         return 0;
4072 }
4073
4074 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4075 {
4076         if (reg < rdev->rmmio_size)
4077                 return readl(((void __iomem *)rdev->rmmio) + reg);
4078         else {
4079                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4080                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4081         }
4082 }
4083
4084 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4085 {
4086         if (reg < rdev->rmmio_size)
4087                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4088         else {
4089                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4090                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4091         }
4092 }
4093
4094 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4095 {
4096         if (reg < rdev->rio_mem_size)
4097                 return ioread32(rdev->rio_mem + reg);
4098         else {
4099                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4100                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4101         }
4102 }
4103
4104 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4105 {
4106         if (reg < rdev->rio_mem_size)
4107                 iowrite32(v, rdev->rio_mem + reg);
4108         else {
4109                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4110                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4111         }
4112 }