drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40
  41 #include <linux/firmware.h>
  42 #include <linux/platform_device.h>
  43
  44 #include "r100_reg_safe.h"
  45 #include "rn50_reg_safe.h"
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  49 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  50 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  51 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  52 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  53 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  54 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  55
  56 MODULE_FIRMWARE(FIRMWARE_R100);
  57 MODULE_FIRMWARE(FIRMWARE_R200);
  58 MODULE_FIRMWARE(FIRMWARE_R300);
  59 MODULE_FIRMWARE(FIRMWARE_R420);
  60 MODULE_FIRMWARE(FIRMWARE_RS690);
  61 MODULE_FIRMWARE(FIRMWARE_RS600);
  62 MODULE_FIRMWARE(FIRMWARE_R520);
  63
  64 #include "r100_track.h"
  65
  66 /* This files gather functions specifics to:
  67  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  68  */
  69
  70 /* hpd for digital panel detect/disconnect */
  71 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  72 {
  73         bool connected = false;
  74
  75         switch (hpd) {
  76         case RADEON_HPD_1:
  77                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  78                         connected = true;
  79                 break;
  80         case RADEON_HPD_2:
  81                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  82                         connected = true;
  83                 break;
  84         default:
  85                 break;
  86         }
  87         return connected;
  88 }
  89
  90 void r100_hpd_set_polarity(struct radeon_device *rdev,
  91                            enum radeon_hpd_id hpd)
  92 {
  93         u32 tmp;
  94         bool connected = r100_hpd_sense(rdev, hpd);
  95
  96         switch (hpd) {
  97         case RADEON_HPD_1:
  98                 tmp = RREG32(RADEON_FP_GEN_CNTL);
  99                 if (connected)
 100                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 101                 else
 102                         tmp |= RADEON_FP_DETECT_INT_POL;
 103                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 104                 break;
 105         case RADEON_HPD_2:
 106                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 107                 if (connected)
 108                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 109                 else
 110                         tmp |= RADEON_FP2_DETECT_INT_POL;
 111                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 112                 break;
 113         default:
 114                 break;
 115         }
 116 }
 117
 118 void r100_hpd_init(struct radeon_device *rdev)
 119 {
 120         struct drm_device *dev = rdev->ddev;
 121         struct drm_connector *connector;
 122
 123         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 124                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 125                 switch (radeon_connector->hpd.hpd) {
 126                 case RADEON_HPD_1:
 127                         rdev->irq.hpd[0] = true;
 128                         break;
 129                 case RADEON_HPD_2:
 130                         rdev->irq.hpd[1] = true;
 131                         break;
 132                 default:
 133                         break;
 134                 }
 135         }
 136         if (rdev->irq.installed)
 137                 r100_irq_set(rdev);
 138 }
 139
 140 void r100_hpd_fini(struct radeon_device *rdev)
 141 {
 142         struct drm_device *dev = rdev->ddev;
 143         struct drm_connector *connector;
 144
 145         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 146                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 147                 switch (radeon_connector->hpd.hpd) {
 148                 case RADEON_HPD_1:
 149                         rdev->irq.hpd[0] = false;
 150                         break;
 151                 case RADEON_HPD_2:
 152                         rdev->irq.hpd[1] = false;
 153                         break;
 154                 default:
 155                         break;
 156                 }
 157         }
 158 }
 159
 160 /*
 161  * PCI GART
 162  */
 163 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 164 {
 165         /* TODO: can we do somethings here ? */
 166         /* It seems hw only cache one entry so we should discard this
 167          * entry otherwise if first GPU GART read hit this entry it
 168          * could end up in wrong address. */
 169 }
 170
 171 int r100_pci_gart_init(struct radeon_device *rdev)
 172 {
 173         int r;
 174
 175         if (rdev->gart.table.ram.ptr) {
 176                 WARN(1, "R100 PCI GART already initialized.\n");
 177                 return 0;
 178         }
 179         /* Initialize common gart structure */
 180         r = radeon_gart_init(rdev);
 181         if (r)
 182                 return r;
 183         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 184         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 185         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 186         return radeon_gart_table_ram_alloc(rdev);
 187 }
 188
 189 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 190 void r100_enable_bm(struct radeon_device *rdev)
 191 {
 192         uint32_t tmp;
 193         /* Enable bus mastering */
 194         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 195         WREG32(RADEON_BUS_CNTL, tmp);
 196 }
 197
 198 int r100_pci_gart_enable(struct radeon_device *rdev)
 199 {
 200         uint32_t tmp;
 201
 202         radeon_gart_restore(rdev);
 203         /* discard memory request outside of configured range */
 204         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 205         WREG32(RADEON_AIC_CNTL, tmp);
 206         /* set address range for PCI address translate */
 207         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 208         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 209         /* set PCI GART page-table base address */
 210         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 211         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 212         WREG32(RADEON_AIC_CNTL, tmp);
 213         r100_pci_gart_tlb_flush(rdev);
 214         rdev->gart.ready = true;
 215         return 0;
 216 }
 217
 218 void r100_pci_gart_disable(struct radeon_device *rdev)
 219 {
 220         uint32_t tmp;
 221
 222         /* discard memory request outside of configured range */
 223         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 224         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 225         WREG32(RADEON_AIC_LO_ADDR, 0);
 226         WREG32(RADEON_AIC_HI_ADDR, 0);
 227 }
 228
 229 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 230 {
 231         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 232                 return -EINVAL;
 233         }
 234         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 235         return 0;
 236 }
 237
 238 void r100_pci_gart_fini(struct radeon_device *rdev)
 239 {
 240         radeon_gart_fini(rdev);
 241         r100_pci_gart_disable(rdev);
 242         radeon_gart_table_ram_free(rdev);
 243 }
 244
 245 int r100_irq_set(struct radeon_device *rdev)
 246 {
 247         uint32_t tmp = 0;
 248
 249         if (!rdev->irq.installed) {
 250                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 251                 WREG32(R_000040_GEN_INT_CNTL, 0);
 252                 return -EINVAL;
 253         }
 254         if (rdev->irq.sw_int) {
 255                 tmp |= RADEON_SW_INT_ENABLE;
 256         }
 257         if (rdev->irq.crtc_vblank_int[0]) {
 258                 tmp |= RADEON_CRTC_VBLANK_MASK;
 259         }
 260         if (rdev->irq.crtc_vblank_int[1]) {
 261                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 262         }
 263         if (rdev->irq.hpd[0]) {
 264                 tmp |= RADEON_FP_DETECT_MASK;
 265         }
 266         if (rdev->irq.hpd[1]) {
 267                 tmp |= RADEON_FP2_DETECT_MASK;
 268         }
 269         WREG32(RADEON_GEN_INT_CNTL, tmp);
 270         return 0;
 271 }
 272
 273 void r100_irq_disable(struct radeon_device *rdev)
 274 {
 275         u32 tmp;
 276
 277         WREG32(R_000040_GEN_INT_CNTL, 0);
 278         /* Wait and acknowledge irq */
 279         mdelay(1);
 280         tmp = RREG32(R_000044_GEN_INT_STATUS);
 281         WREG32(R_000044_GEN_INT_STATUS, tmp);
 282 }
 283
 284 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 285 {
 286         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 287         uint32_t irq_mask = RADEON_SW_INT_TEST |
 288                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 289                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 290
 291         if (irqs) {
 292                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 293         }
 294         return irqs & irq_mask;
 295 }
 296
 297 int r100_irq_process(struct radeon_device *rdev)
 298 {
 299         uint32_t status, msi_rearm;
 300         bool queue_hotplug = false;
 301
 302         status = r100_irq_ack(rdev);
 303         if (!status) {
 304                 return IRQ_NONE;
 305         }
 306         if (rdev->shutdown) {
 307                 return IRQ_NONE;
 308         }
 309         while (status) {
 310                 /* SW interrupt */
 311                 if (status & RADEON_SW_INT_TEST) {
 312                         radeon_fence_process(rdev);
 313                 }
 314                 /* Vertical blank interrupts */
 315                 if (status & RADEON_CRTC_VBLANK_STAT) {
 316                         drm_handle_vblank(rdev->ddev, 0);
 317                         rdev->pm.vblank_sync = true;
 318                         wake_up(&rdev->irq.vblank_queue);
 319                 }
 320                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 321                         drm_handle_vblank(rdev->ddev, 1);
 322                         rdev->pm.vblank_sync = true;
 323                         wake_up(&rdev->irq.vblank_queue);
 324                 }
 325                 if (status & RADEON_FP_DETECT_STAT) {
 326                         queue_hotplug = true;
 327                         DRM_DEBUG("HPD1\n");
 328                 }
 329                 if (status & RADEON_FP2_DETECT_STAT) {
 330                         queue_hotplug = true;
 331                         DRM_DEBUG("HPD2\n");
 332                 }
 333                 status = r100_irq_ack(rdev);
 334         }
 335         if (queue_hotplug)
 336                 queue_work(rdev->wq, &rdev->hotplug_work);
 337         if (rdev->msi_enabled) {
 338                 switch (rdev->family) {
 339                 case CHIP_RS400:
 340                 case CHIP_RS480:
 341                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 342                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 343                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 344                         break;
 345                 default:
 346                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 347                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 348                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 349                         break;
 350                 }
 351         }
 352         return IRQ_HANDLED;
 353 }
 354
 355 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 356 {
 357         if (crtc == 0)
 358                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 359         else
 360                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 361 }
 362
 363 /* Who ever call radeon_fence_emit should call ring_lock and ask
 364  * for enough space (today caller are ib schedule and buffer move) */
 365 void r100_fence_ring_emit(struct radeon_device *rdev,
 366                           struct radeon_fence *fence)
 367 {
 368         /* We have to make sure that caches are flushed before
 369          * CPU might read something from VRAM. */
 370         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 371         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 372         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 373         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 374         /* Wait until IDLE & CLEAN */
 375         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 376         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 377         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 378         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 379                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 380         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 381         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 382         /* Emit fence sequence & fire IRQ */
 383         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 384         radeon_ring_write(rdev, fence->seq);
 385         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 386         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 387 }
 388
 389 int r100_wb_init(struct radeon_device *rdev)
 390 {
 391         int r;
 392
 393         if (rdev->wb.wb_obj == NULL) {
 394                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 395                                         RADEON_GEM_DOMAIN_GTT,
 396                                         &rdev->wb.wb_obj);
 397                 if (r) {
 398                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 399                         return r;
 400                 }
 401                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 402                 if (unlikely(r != 0))
 403                         return r;
 404                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 405                                         &rdev->wb.gpu_addr);
 406                 if (r) {
 407                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 408                         radeon_bo_unreserve(rdev->wb.wb_obj);
 409                         return r;
 410                 }
 411                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 412                 radeon_bo_unreserve(rdev->wb.wb_obj);
 413                 if (r) {
 414                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 415                         return r;
 416                 }
 417         }
 418         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 419         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 420                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 421         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 422         return 0;
 423 }
 424
 425 void r100_wb_disable(struct radeon_device *rdev)
 426 {
 427         WREG32(R_000770_SCRATCH_UMSK, 0);
 428 }
 429
 430 void r100_wb_fini(struct radeon_device *rdev)
 431 {
 432         int r;
 433
 434         r100_wb_disable(rdev);
 435         if (rdev->wb.wb_obj) {
 436                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 437                 if (unlikely(r != 0)) {
 438                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 439                         return;
 440                 }
 441                 radeon_bo_kunmap(rdev->wb.wb_obj);
 442                 radeon_bo_unpin(rdev->wb.wb_obj);
 443                 radeon_bo_unreserve(rdev->wb.wb_obj);
 444                 radeon_bo_unref(&rdev->wb.wb_obj);
 445                 rdev->wb.wb = NULL;
 446                 rdev->wb.wb_obj = NULL;
 447         }
 448 }
 449
 450 int r100_copy_blit(struct radeon_device *rdev,
 451                    uint64_t src_offset,
 452                    uint64_t dst_offset,
 453                    unsigned num_pages,
 454                    struct radeon_fence *fence)
 455 {
 456         uint32_t cur_pages;
 457         uint32_t stride_bytes = PAGE_SIZE;
 458         uint32_t pitch;
 459         uint32_t stride_pixels;
 460         unsigned ndw;
 461         int num_loops;
 462         int r = 0;
 463
 464         /* radeon limited to 16k stride */
 465         stride_bytes &= 0x3fff;
 466         /* radeon pitch is /64 */
 467         pitch = stride_bytes / 64;
 468         stride_pixels = stride_bytes / 4;
 469         num_loops = DIV_ROUND_UP(num_pages, 8191);
 470
 471         /* Ask for enough room for blit + flush + fence */
 472         ndw = 64 + (10 * num_loops);
 473         r = radeon_ring_lock(rdev, ndw);
 474         if (r) {
 475                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 476                 return -EINVAL;
 477         }
 478         while (num_pages > 0) {
 479                 cur_pages = num_pages;
 480                 if (cur_pages > 8191) {
 481                         cur_pages = 8191;
 482                 }
 483                 num_pages -= cur_pages;
 484
 485                 /* pages are in Y direction - height
 486                    page width in X direction - width */
 487                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 488                 radeon_ring_write(rdev,
 489                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 490                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 491                                   RADEON_GMC_SRC_CLIPPING |
 492                                   RADEON_GMC_DST_CLIPPING |
 493                                   RADEON_GMC_BRUSH_NONE |
 494                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 495                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 496                                   RADEON_ROP3_S |
 497                                   RADEON_DP_SRC_SOURCE_MEMORY |
 498                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 499                                   RADEON_GMC_WR_MSK_DIS);
 500                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 501                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 502                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 503                 radeon_ring_write(rdev, 0);
 504                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 505                 radeon_ring_write(rdev, num_pages);
 506                 radeon_ring_write(rdev, num_pages);
 507                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 508         }
 509         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 510         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 511         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 512         radeon_ring_write(rdev,
 513                           RADEON_WAIT_2D_IDLECLEAN |
 514                           RADEON_WAIT_HOST_IDLECLEAN |
 515                           RADEON_WAIT_DMA_GUI_IDLE);
 516         if (fence) {
 517                 r = radeon_fence_emit(rdev, fence);
 518         }
 519         radeon_ring_unlock_commit(rdev);
 520         return r;
 521 }
 522
 523 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 524 {
 525         unsigned i;
 526         u32 tmp;
 527
 528         for (i = 0; i < rdev->usec_timeout; i++) {
 529                 tmp = RREG32(R_000E40_RBBM_STATUS);
 530                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 531                         return 0;
 532                 }
 533                 udelay(1);
 534         }
 535         return -1;
 536 }
 537
 538 void r100_ring_start(struct radeon_device *rdev)
 539 {
 540         int r;
 541
 542         r = radeon_ring_lock(rdev, 2);
 543         if (r) {
 544                 return;
 545         }
 546         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 547         radeon_ring_write(rdev,
 548                           RADEON_ISYNC_ANY2D_IDLE3D |
 549                           RADEON_ISYNC_ANY3D_IDLE2D |
 550                           RADEON_ISYNC_WAIT_IDLEGUI |
 551                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 552         radeon_ring_unlock_commit(rdev);
 553 }
 554
 555
 556 /* Load the microcode for the CP */
 557 static int r100_cp_init_microcode(struct radeon_device *rdev)
 558 {
 559         struct platform_device *pdev;
 560         const char *fw_name = NULL;
 561         int err;
 562
 563         DRM_DEBUG("\n");
 564
 565         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 566         err = IS_ERR(pdev);
 567         if (err) {
 568                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 569                 return -EINVAL;
 570         }
 571         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 572             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 573             (rdev->family == CHIP_RS200)) {
 574                 DRM_INFO("Loading R100 Microcode\n");
 575                 fw_name = FIRMWARE_R100;
 576         } else if ((rdev->family == CHIP_R200) ||
 577                    (rdev->family == CHIP_RV250) ||
 578                    (rdev->family == CHIP_RV280) ||
 579                    (rdev->family == CHIP_RS300)) {
 580                 DRM_INFO("Loading R200 Microcode\n");
 581                 fw_name = FIRMWARE_R200;
 582         } else if ((rdev->family == CHIP_R300) ||
 583                    (rdev->family == CHIP_R350) ||
 584                    (rdev->family == CHIP_RV350) ||
 585                    (rdev->family == CHIP_RV380) ||
 586                    (rdev->family == CHIP_RS400) ||
 587                    (rdev->family == CHIP_RS480)) {
 588                 DRM_INFO("Loading R300 Microcode\n");
 589                 fw_name = FIRMWARE_R300;
 590         } else if ((rdev->family == CHIP_R420) ||
 591                    (rdev->family == CHIP_R423) ||
 592                    (rdev->family == CHIP_RV410)) {
 593                 DRM_INFO("Loading R400 Microcode\n");
 594                 fw_name = FIRMWARE_R420;
 595         } else if ((rdev->family == CHIP_RS690) ||
 596                    (rdev->family == CHIP_RS740)) {
 597                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 598                 fw_name = FIRMWARE_RS690;
 599         } else if (rdev->family == CHIP_RS600) {
 600                 DRM_INFO("Loading RS600 Microcode\n");
 601                 fw_name = FIRMWARE_RS600;
 602         } else if ((rdev->family == CHIP_RV515) ||
 603                    (rdev->family == CHIP_R520) ||
 604                    (rdev->family == CHIP_RV530) ||
 605                    (rdev->family == CHIP_R580) ||
 606                    (rdev->family == CHIP_RV560) ||
 607                    (rdev->family == CHIP_RV570)) {
 608                 DRM_INFO("Loading R500 Microcode\n");
 609                 fw_name = FIRMWARE_R520;
 610         }
 611
 612         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 613         platform_device_unregister(pdev);
 614         if (err) {
 615                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 616                        fw_name);
 617         } else if (rdev->me_fw->size % 8) {
 618                 printk(KERN_ERR
 619                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 620                        rdev->me_fw->size, fw_name);
 621                 err = -EINVAL;
 622                 release_firmware(rdev->me_fw);
 623                 rdev->me_fw = NULL;
 624         }
 625         return err;
 626 }
 627
 628 static void r100_cp_load_microcode(struct radeon_device *rdev)
 629 {
 630         const __be32 *fw_data;
 631         int i, size;
 632
 633         if (r100_gui_wait_for_idle(rdev)) {
 634                 printk(KERN_WARNING "Failed to wait GUI idle while "
 635                        "programming pipes. Bad things might happen.\n");
 636         }
 637
 638         if (rdev->me_fw) {
 639                 size = rdev->me_fw->size / 4;
 640                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 641                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 642                 for (i = 0; i < size; i += 2) {
 643                         WREG32(RADEON_CP_ME_RAM_DATAH,
 644                                be32_to_cpup(&fw_data[i]));
 645                         WREG32(RADEON_CP_ME_RAM_DATAL,
 646                                be32_to_cpup(&fw_data[i + 1]));
 647                 }
 648         }
 649 }
 650
 651 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 652 {
 653         unsigned rb_bufsz;
 654         unsigned rb_blksz;
 655         unsigned max_fetch;
 656         unsigned pre_write_timer;
 657         unsigned pre_write_limit;
 658         unsigned indirect2_start;
 659         unsigned indirect1_start;
 660         uint32_t tmp;
 661         int r;
 662
 663         if (r100_debugfs_cp_init(rdev)) {
 664                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 665         }
 666         /* Reset CP */
 667         tmp = RREG32(RADEON_CP_CSQ_STAT);
 668         if ((tmp & (1 << 31))) {
 669                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 670                 WREG32(RADEON_CP_CSQ_MODE, 0);
 671                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 672                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 673                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 674                 mdelay(2);
 675                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 676                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 677                 mdelay(2);
 678                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 679                 if ((tmp & (1 << 31))) {
 680                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 681                 }
 682         } else {
 683                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 684         }
 685
 686         if (!rdev->me_fw) {
 687                 r = r100_cp_init_microcode(rdev);
 688                 if (r) {
 689                         DRM_ERROR("Failed to load firmware!\n");
 690                         return r;
 691                 }
 692         }
 693
 694         /* Align ring size */
 695         rb_bufsz = drm_order(ring_size / 8);
 696         ring_size = (1 << (rb_bufsz + 1)) * 4;
 697         r100_cp_load_microcode(rdev);
 698         r = radeon_ring_init(rdev, ring_size);
 699         if (r) {
 700                 return r;
 701         }
 702         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 703          * the rptr copy in system ram */
 704         rb_blksz = 9;
 705         /* cp will read 128bytes at a time (4 dwords) */
 706         max_fetch = 1;
 707         rdev->cp.align_mask = 16 - 1;
 708         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 709         pre_write_timer = 64;
 710         /* Force CP_RB_WPTR write if written more than one time before the
 711          * delay expire
 712          */
 713         pre_write_limit = 0;
 714         /* Setup the cp cache like this (cache size is 96 dwords) :
 715          *      RING            0  to 15
 716          *      INDIRECT1       16 to 79
 717          *      INDIRECT2       80 to 95
 718          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 719          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 720          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 721          * Idea being that most of the gpu cmd will be through indirect1 buffer
 722          * so it gets the bigger cache.
 723          */
 724         indirect2_start = 80;
 725         indirect1_start = 16;
 726         /* cp setup */
 727         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 728         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 729                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 730                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 731                RADEON_RB_NO_UPDATE);
 732 #ifdef __BIG_ENDIAN
 733         tmp |= RADEON_BUF_SWAP_32BIT;
 734 #endif
 735         WREG32(RADEON_CP_RB_CNTL, tmp);
 736
 737         /* Set ring address */
 738         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 739         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 740         /* Force read & write ptr to 0 */
 741         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 742         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 743         WREG32(RADEON_CP_RB_WPTR, 0);
 744         WREG32(RADEON_CP_RB_CNTL, tmp);
 745         udelay(10);
 746         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 747         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 748         /* protect against crazy HW on resume */
 749         rdev->cp.wptr &= rdev->cp.ptr_mask;
 750         /* Set cp mode to bus mastering & enable cp*/
 751         WREG32(RADEON_CP_CSQ_MODE,
 752                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 753                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 754         WREG32(0x718, 0);
 755         WREG32(0x744, 0x00004D4D);
 756         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 757         radeon_ring_start(rdev);
 758         r = radeon_ring_test(rdev);
 759         if (r) {
 760                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 761                 return r;
 762         }
 763         rdev->cp.ready = true;
 764         return 0;
 765 }
 766
 767 void r100_cp_fini(struct radeon_device *rdev)
 768 {
 769         if (r100_cp_wait_for_idle(rdev)) {
 770                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 771         }
 772         /* Disable ring */
 773         r100_cp_disable(rdev);
 774         radeon_ring_fini(rdev);
 775         DRM_INFO("radeon: cp finalized\n");
 776 }
 777
 778 void r100_cp_disable(struct radeon_device *rdev)
 779 {
 780         /* Disable ring */
 781         rdev->cp.ready = false;
 782         WREG32(RADEON_CP_CSQ_MODE, 0);
 783         WREG32(RADEON_CP_CSQ_CNTL, 0);
 784         if (r100_gui_wait_for_idle(rdev)) {
 785                 printk(KERN_WARNING "Failed to wait GUI idle while "
 786                        "programming pipes. Bad things might happen.\n");
 787         }
 788 }
 789
 790 int r100_cp_reset(struct radeon_device *rdev)
 791 {
 792         uint32_t tmp;
 793         bool reinit_cp;
 794         int i;
 795
 796         reinit_cp = rdev->cp.ready;
 797         rdev->cp.ready = false;
 798         WREG32(RADEON_CP_CSQ_MODE, 0);
 799         WREG32(RADEON_CP_CSQ_CNTL, 0);
 800         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 801         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 802         udelay(200);
 803         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 804         /* Wait to prevent race in RBBM_STATUS */
 805         mdelay(1);
 806         for (i = 0; i < rdev->usec_timeout; i++) {
 807                 tmp = RREG32(RADEON_RBBM_STATUS);
 808                 if (!(tmp & (1 << 16))) {
 809                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 810                                  tmp);
 811                         if (reinit_cp) {
 812                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 813                         }
 814                         return 0;
 815                 }
 816                 DRM_UDELAY(1);
 817         }
 818         tmp = RREG32(RADEON_RBBM_STATUS);
 819         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 820         return -1;
 821 }
 822
 823 void r100_cp_commit(struct radeon_device *rdev)
 824 {
 825         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 826         (void)RREG32(RADEON_CP_RB_WPTR);
 827 }
 828
 829
 830 /*
 831  * CS functions
 832  */
 833 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 834                           struct radeon_cs_packet *pkt,
 835                           const unsigned *auth, unsigned n,
 836                           radeon_packet0_check_t check)
 837 {
 838         unsigned reg;
 839         unsigned i, j, m;
 840         unsigned idx;
 841         int r;
 842
 843         idx = pkt->idx + 1;
 844         reg = pkt->reg;
 845         /* Check that register fall into register range
 846          * determined by the number of entry (n) in the
 847          * safe register bitmap.
 848          */
 849         if (pkt->one_reg_wr) {
 850                 if ((reg >> 7) > n) {
 851                         return -EINVAL;
 852                 }
 853         } else {
 854                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 855                         return -EINVAL;
 856                 }
 857         }
 858         for (i = 0; i <= pkt->count; i++, idx++) {
 859                 j = (reg >> 7);
 860                 m = 1 << ((reg >> 2) & 31);
 861                 if (auth[j] & m) {
 862                         r = check(p, pkt, idx, reg);
 863                         if (r) {
 864                                 return r;
 865                         }
 866                 }
 867                 if (pkt->one_reg_wr) {
 868                         if (!(auth[j] & m)) {
 869                                 break;
 870                         }
 871                 } else {
 872                         reg += 4;
 873                 }
 874         }
 875         return 0;
 876 }
 877
 878 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 879                          struct radeon_cs_packet *pkt)
 880 {
 881         volatile uint32_t *ib;
 882         unsigned i;
 883         unsigned idx;
 884
 885         ib = p->ib->ptr;
 886         idx = pkt->idx;
 887         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 888                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 889         }
 890 }
 891
 892 /**
 893  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 894  * @parser:     parser structure holding parsing context.
 895  * @pkt:        where to store packet informations
 896  *
 897  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 898  * if packet is bigger than remaining ib size. or if packets is unknown.
 899  **/
 900 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 901                          struct radeon_cs_packet *pkt,
 902                          unsigned idx)
 903 {
 904         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 905         uint32_t header;
 906
 907         if (idx >= ib_chunk->length_dw) {
 908                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 909                           idx, ib_chunk->length_dw);
 910                 return -EINVAL;
 911         }
 912         header = radeon_get_ib_value(p, idx);
 913         pkt->idx = idx;
 914         pkt->type = CP_PACKET_GET_TYPE(header);
 915         pkt->count = CP_PACKET_GET_COUNT(header);
 916         switch (pkt->type) {
 917         case PACKET_TYPE0:
 918                 pkt->reg = CP_PACKET0_GET_REG(header);
 919                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 920                 break;
 921         case PACKET_TYPE3:
 922                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 923                 break;
 924         case PACKET_TYPE2:
 925                 pkt->count = -1;
 926                 break;
 927         default:
 928                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 929                 return -EINVAL;
 930         }
 931         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 932                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 933                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 934                 return -EINVAL;
 935         }
 936         return 0;
 937 }
 938
 939 /**
 940  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 941  * @parser:             parser structure holding parsing context.
 942  *
 943  * Userspace sends a special sequence for VLINE waits.
 944  * PACKET0 - VLINE_START_END + value
 945  * PACKET0 - WAIT_UNTIL +_value
 946  * RELOC (P3) - crtc_id in reloc.
 947  *
 948  * This function parses this and relocates the VLINE START END
 949  * and WAIT UNTIL packets to the correct crtc.
 950  * It also detects a switched off crtc and nulls out the
 951  * wait in that case.
 952  */
 953 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 954 {
 955         struct drm_mode_object *obj;
 956         struct drm_crtc *crtc;
 957         struct radeon_crtc *radeon_crtc;
 958         struct radeon_cs_packet p3reloc, waitreloc;
 959         int crtc_id;
 960         int r;
 961         uint32_t header, h_idx, reg;
 962         volatile uint32_t *ib;
 963
 964         ib = p->ib->ptr;
 965
 966         /* parse the wait until */
 967         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 968         if (r)
 969                 return r;
 970
 971         /* check its a wait until and only 1 count */
 972         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 973             waitreloc.count != 0) {
 974                 DRM_ERROR("vline wait had illegal wait until segment\n");
 975                 r = -EINVAL;
 976                 return r;
 977         }
 978
 979         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
 980                 DRM_ERROR("vline wait had illegal wait until\n");
 981                 r = -EINVAL;
 982                 return r;
 983         }
 984
 985         /* jump over the NOP */
 986         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
 987         if (r)
 988                 return r;
 989
 990         h_idx = p->idx - 2;
 991         p->idx += waitreloc.count + 2;
 992         p->idx += p3reloc.count + 2;
 993
 994         header = radeon_get_ib_value(p, h_idx);
 995         crtc_id = radeon_get_ib_value(p, h_idx + 5);
 996         reg = CP_PACKET0_GET_REG(header);
 997         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 998         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 999         if (!obj) {
1000                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1001                 r = -EINVAL;
1002                 goto out;
1003         }
1004         crtc = obj_to_crtc(obj);
1005         radeon_crtc = to_radeon_crtc(crtc);
1006         crtc_id = radeon_crtc->crtc_id;
1007
1008         if (!crtc->enabled) {
1009                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1010                 ib[h_idx + 2] = PACKET2(0);
1011                 ib[h_idx + 3] = PACKET2(0);
1012         } else if (crtc_id == 1) {
1013                 switch (reg) {
1014                 case AVIVO_D1MODE_VLINE_START_END:
1015                         header &= ~R300_CP_PACKET0_REG_MASK;
1016                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1017                         break;
1018                 case RADEON_CRTC_GUI_TRIG_VLINE:
1019                         header &= ~R300_CP_PACKET0_REG_MASK;
1020                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1021                         break;
1022                 default:
1023                         DRM_ERROR("unknown crtc reloc\n");
1024                         r = -EINVAL;
1025                         goto out;
1026                 }
1027                 ib[h_idx] = header;
1028                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1029         }
1030 out:
1031         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1032         return r;
1033 }
1034
1035 /**
1036  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1037  * @parser:             parser structure holding parsing context.
1038  * @data:               pointer to relocation data
1039  * @offset_start:       starting offset
1040  * @offset_mask:        offset mask (to align start offset on)
1041  * @reloc:              reloc informations
1042  *
1043  * Check next packet is relocation packet3, do bo validation and compute
1044  * GPU offset using the provided start.
1045  **/
1046 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1047                               struct radeon_cs_reloc **cs_reloc)
1048 {
1049         struct radeon_cs_chunk *relocs_chunk;
1050         struct radeon_cs_packet p3reloc;
1051         unsigned idx;
1052         int r;
1053
1054         if (p->chunk_relocs_idx == -1) {
1055                 DRM_ERROR("No relocation chunk !\n");
1056                 return -EINVAL;
1057         }
1058         *cs_reloc = NULL;
1059         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1060         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1061         if (r) {
1062                 return r;
1063         }
1064         p->idx += p3reloc.count + 2;
1065         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1066                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1067                           p3reloc.idx);
1068                 r100_cs_dump_packet(p, &p3reloc);
1069                 return -EINVAL;
1070         }
1071         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1072         if (idx >= relocs_chunk->length_dw) {
1073                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1074                           idx, relocs_chunk->length_dw);
1075                 r100_cs_dump_packet(p, &p3reloc);
1076                 return -EINVAL;
1077         }
1078         /* FIXME: we assume reloc size is 4 dwords */
1079         *cs_reloc = p->relocs_ptr[(idx / 4)];
1080         return 0;
1081 }
1082
1083 static int r100_get_vtx_size(uint32_t vtx_fmt)
1084 {
1085         int vtx_size;
1086         vtx_size = 2;
1087         /* ordered according to bits in spec */
1088         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1089                 vtx_size++;
1090         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1091                 vtx_size += 3;
1092         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1093                 vtx_size++;
1094         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1095                 vtx_size++;
1096         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1097                 vtx_size += 3;
1098         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1099                 vtx_size++;
1100         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1101                 vtx_size++;
1102         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1103                 vtx_size += 2;
1104         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1105                 vtx_size += 2;
1106         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1107                 vtx_size++;
1108         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1109                 vtx_size += 2;
1110         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1111                 vtx_size++;
1112         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1113                 vtx_size += 2;
1114         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1115                 vtx_size++;
1116         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1117                 vtx_size++;
1118         /* blend weight */
1119         if (vtx_fmt & (0x7 << 15))
1120                 vtx_size += (vtx_fmt >> 15) & 0x7;
1121         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1122                 vtx_size += 3;
1123         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1124                 vtx_size += 2;
1125         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1126                 vtx_size++;
1127         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1128                 vtx_size++;
1129         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1130                 vtx_size++;
1131         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1132                 vtx_size++;
1133         return vtx_size;
1134 }
1135
1136 static int r100_packet0_check(struct radeon_cs_parser *p,
1137                               struct radeon_cs_packet *pkt,
1138                               unsigned idx, unsigned reg)
1139 {
1140         struct radeon_cs_reloc *reloc;
1141         struct r100_cs_track *track;
1142         volatile uint32_t *ib;
1143         uint32_t tmp;
1144         int r;
1145         int i, face;
1146         u32 tile_flags = 0;
1147         u32 idx_value;
1148
1149         ib = p->ib->ptr;
1150         track = (struct r100_cs_track *)p->track;
1151
1152         idx_value = radeon_get_ib_value(p, idx);
1153
1154         switch (reg) {
1155         case RADEON_CRTC_GUI_TRIG_VLINE:
1156                 r = r100_cs_packet_parse_vline(p);
1157                 if (r) {
1158                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1159                                   idx, reg);
1160                         r100_cs_dump_packet(p, pkt);
1161                         return r;
1162                 }
1163                 break;
1164                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1165                  * range access */
1166         case RADEON_DST_PITCH_OFFSET:
1167         case RADEON_SRC_PITCH_OFFSET:
1168                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1169                 if (r)
1170                         return r;
1171                 break;
1172         case RADEON_RB3D_DEPTHOFFSET:
1173                 r = r100_cs_packet_next_reloc(p, &reloc);
1174                 if (r) {
1175                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1176                                   idx, reg);
1177                         r100_cs_dump_packet(p, pkt);
1178                         return r;
1179                 }
1180                 track->zb.robj = reloc->robj;
1181                 track->zb.offset = idx_value;
1182                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1183                 break;
1184         case RADEON_RB3D_COLOROFFSET:
1185                 r = r100_cs_packet_next_reloc(p, &reloc);
1186                 if (r) {
1187                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1188                                   idx, reg);
1189                         r100_cs_dump_packet(p, pkt);
1190                         return r;
1191                 }
1192                 track->cb[0].robj = reloc->robj;
1193                 track->cb[0].offset = idx_value;
1194                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1195                 break;
1196         case RADEON_PP_TXOFFSET_0:
1197         case RADEON_PP_TXOFFSET_1:
1198         case RADEON_PP_TXOFFSET_2:
1199                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1200                 r = r100_cs_packet_next_reloc(p, &reloc);
1201                 if (r) {
1202                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1203                                   idx, reg);
1204                         r100_cs_dump_packet(p, pkt);
1205                         return r;
1206                 }
1207                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1208                 track->textures[i].robj = reloc->robj;
1209                 break;
1210         case RADEON_PP_CUBIC_OFFSET_T0_0:
1211         case RADEON_PP_CUBIC_OFFSET_T0_1:
1212         case RADEON_PP_CUBIC_OFFSET_T0_2:
1213         case RADEON_PP_CUBIC_OFFSET_T0_3:
1214         case RADEON_PP_CUBIC_OFFSET_T0_4:
1215                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1216                 r = r100_cs_packet_next_reloc(p, &reloc);
1217                 if (r) {
1218                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1219                                   idx, reg);
1220                         r100_cs_dump_packet(p, pkt);
1221                         return r;
1222                 }
1223                 track->textures[0].cube_info[i].offset = idx_value;
1224                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1225                 track->textures[0].cube_info[i].robj = reloc->robj;
1226                 break;
1227         case RADEON_PP_CUBIC_OFFSET_T1_0:
1228         case RADEON_PP_CUBIC_OFFSET_T1_1:
1229         case RADEON_PP_CUBIC_OFFSET_T1_2:
1230         case RADEON_PP_CUBIC_OFFSET_T1_3:
1231         case RADEON_PP_CUBIC_OFFSET_T1_4:
1232                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1233                 r = r100_cs_packet_next_reloc(p, &reloc);
1234                 if (r) {
1235                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1236                                   idx, reg);
1237                         r100_cs_dump_packet(p, pkt);
1238                         return r;
1239                 }
1240                 track->textures[1].cube_info[i].offset = idx_value;
1241                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1242                 track->textures[1].cube_info[i].robj = reloc->robj;
1243                 break;
1244         case RADEON_PP_CUBIC_OFFSET_T2_0:
1245         case RADEON_PP_CUBIC_OFFSET_T2_1:
1246         case RADEON_PP_CUBIC_OFFSET_T2_2:
1247         case RADEON_PP_CUBIC_OFFSET_T2_3:
1248         case RADEON_PP_CUBIC_OFFSET_T2_4:
1249                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1250                 r = r100_cs_packet_next_reloc(p, &reloc);
1251                 if (r) {
1252                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1253                                   idx, reg);
1254                         r100_cs_dump_packet(p, pkt);
1255                         return r;
1256                 }
1257                 track->textures[2].cube_info[i].offset = idx_value;
1258                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1259                 track->textures[2].cube_info[i].robj = reloc->robj;
1260                 break;
1261         case RADEON_RE_WIDTH_HEIGHT:
1262                 track->maxy = ((idx_value >> 16) & 0x7FF);
1263                 break;
1264         case RADEON_RB3D_COLORPITCH:
1265                 r = r100_cs_packet_next_reloc(p, &reloc);
1266                 if (r) {
1267                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1268                                   idx, reg);
1269                         r100_cs_dump_packet(p, pkt);
1270                         return r;
1271                 }
1272
1273                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1274                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1275                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1276                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1277
1278                 tmp = idx_value & ~(0x7 << 16);
1279                 tmp |= tile_flags;
1280                 ib[idx] = tmp;
1281
1282                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1283                 break;
1284         case RADEON_RB3D_DEPTHPITCH:
1285                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1286                 break;
1287         case RADEON_RB3D_CNTL:
1288                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1289                 case 7:
1290                 case 8:
1291                 case 9:
1292                 case 11:
1293                 case 12:
1294                         track->cb[0].cpp = 1;
1295                         break;
1296                 case 3:
1297                 case 4:
1298                 case 15:
1299                         track->cb[0].cpp = 2;
1300                         break;
1301                 case 6:
1302                         track->cb[0].cpp = 4;
1303                         break;
1304                 default:
1305                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1306                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1307                         return -EINVAL;
1308                 }
1309                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1310                 break;
1311         case RADEON_RB3D_ZSTENCILCNTL:
1312                 switch (idx_value & 0xf) {
1313                 case 0:
1314                         track->zb.cpp = 2;
1315                         break;
1316                 case 2:
1317                 case 3:
1318                 case 4:
1319                 case 5:
1320                 case 9:
1321                 case 11:
1322                         track->zb.cpp = 4;
1323                         break;
1324                 default:
1325                         break;
1326                 }
1327                 break;
1328         case RADEON_RB3D_ZPASS_ADDR:
1329                 r = r100_cs_packet_next_reloc(p, &reloc);
1330                 if (r) {
1331                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1332                                   idx, reg);
1333                         r100_cs_dump_packet(p, pkt);
1334                         return r;
1335                 }
1336                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1337                 break;
1338         case RADEON_PP_CNTL:
1339                 {
1340                         uint32_t temp = idx_value >> 4;
1341                         for (i = 0; i < track->num_texture; i++)
1342                                 track->textures[i].enabled = !!(temp & (1 << i));
1343                 }
1344                 break;
1345         case RADEON_SE_VF_CNTL:
1346                 track->vap_vf_cntl = idx_value;
1347                 break;
1348         case RADEON_SE_VTX_FMT:
1349                 track->vtx_size = r100_get_vtx_size(idx_value);
1350                 break;
1351         case RADEON_PP_TEX_SIZE_0:
1352         case RADEON_PP_TEX_SIZE_1:
1353         case RADEON_PP_TEX_SIZE_2:
1354                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1355                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1356                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1357                 break;
1358         case RADEON_PP_TEX_PITCH_0:
1359         case RADEON_PP_TEX_PITCH_1:
1360         case RADEON_PP_TEX_PITCH_2:
1361                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1362                 track->textures[i].pitch = idx_value + 32;
1363                 break;
1364         case RADEON_PP_TXFILTER_0:
1365         case RADEON_PP_TXFILTER_1:
1366         case RADEON_PP_TXFILTER_2:
1367                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1368                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1369                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1370                 tmp = (idx_value >> 23) & 0x7;
1371                 if (tmp == 2 || tmp == 6)
1372                         track->textures[i].roundup_w = false;
1373                 tmp = (idx_value >> 27) & 0x7;
1374                 if (tmp == 2 || tmp == 6)
1375                         track->textures[i].roundup_h = false;
1376                 break;
1377         case RADEON_PP_TXFORMAT_0:
1378         case RADEON_PP_TXFORMAT_1:
1379         case RADEON_PP_TXFORMAT_2:
1380                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1381                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1382                         track->textures[i].use_pitch = 1;
1383                 } else {
1384                         track->textures[i].use_pitch = 0;
1385                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1386                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1387                 }
1388                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1389                         track->textures[i].tex_coord_type = 2;
1390                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1391                 case RADEON_TXFORMAT_I8:
1392                 case RADEON_TXFORMAT_RGB332:
1393                 case RADEON_TXFORMAT_Y8:
1394                         track->textures[i].cpp = 1;
1395                         break;
1396                 case RADEON_TXFORMAT_AI88:
1397                 case RADEON_TXFORMAT_ARGB1555:
1398                 case RADEON_TXFORMAT_RGB565:
1399                 case RADEON_TXFORMAT_ARGB4444:
1400                 case RADEON_TXFORMAT_VYUY422:
1401                 case RADEON_TXFORMAT_YVYU422:
1402                 case RADEON_TXFORMAT_SHADOW16:
1403                 case RADEON_TXFORMAT_LDUDV655:
1404                 case RADEON_TXFORMAT_DUDV88:
1405                         track->textures[i].cpp = 2;
1406                         break;
1407                 case RADEON_TXFORMAT_ARGB8888:
1408                 case RADEON_TXFORMAT_RGBA8888:
1409                 case RADEON_TXFORMAT_SHADOW32:
1410                 case RADEON_TXFORMAT_LDUDUV8888:
1411                         track->textures[i].cpp = 4;
1412                         break;
1413                 case RADEON_TXFORMAT_DXT1:
1414                         track->textures[i].cpp = 1;
1415                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1416                         break;
1417                 case RADEON_TXFORMAT_DXT23:
1418                 case RADEON_TXFORMAT_DXT45:
1419                         track->textures[i].cpp = 1;
1420                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1421                         break;
1422                 }
1423                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1424                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1425                 break;
1426         case RADEON_PP_CUBIC_FACES_0:
1427         case RADEON_PP_CUBIC_FACES_1:
1428         case RADEON_PP_CUBIC_FACES_2:
1429                 tmp = idx_value;
1430                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1431                 for (face = 0; face < 4; face++) {
1432                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1433                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1434                 }
1435                 break;
1436         default:
1437                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1438                        reg, idx);
1439                 return -EINVAL;
1440         }
1441         return 0;
1442 }
1443
1444 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1445                                          struct radeon_cs_packet *pkt,
1446                                          struct radeon_bo *robj)
1447 {
1448         unsigned idx;
1449         u32 value;
1450         idx = pkt->idx + 1;
1451         value = radeon_get_ib_value(p, idx + 2);
1452         if ((value + 1) > radeon_bo_size(robj)) {
1453                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1454                           "(need %u have %lu) !\n",
1455                           value + 1,
1456                           radeon_bo_size(robj));
1457                 return -EINVAL;
1458         }
1459         return 0;
1460 }
1461
1462 static int r100_packet3_check(struct radeon_cs_parser *p,
1463                               struct radeon_cs_packet *pkt)
1464 {
1465         struct radeon_cs_reloc *reloc;
1466         struct r100_cs_track *track;
1467         unsigned idx;
1468         volatile uint32_t *ib;
1469         int r;
1470
1471         ib = p->ib->ptr;
1472         idx = pkt->idx + 1;
1473         track = (struct r100_cs_track *)p->track;
1474         switch (pkt->opcode) {
1475         case PACKET3_3D_LOAD_VBPNTR:
1476                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1477                 if (r)
1478                         return r;
1479                 break;
1480         case PACKET3_INDX_BUFFER:
1481                 r = r100_cs_packet_next_reloc(p, &reloc);
1482                 if (r) {
1483                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1484                         r100_cs_dump_packet(p, pkt);
1485                         return r;
1486                 }
1487                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1488                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1489                 if (r) {
1490                         return r;
1491                 }
1492                 break;
1493         case 0x23:
1494                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1495                 r = r100_cs_packet_next_reloc(p, &reloc);
1496                 if (r) {
1497                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1498                         r100_cs_dump_packet(p, pkt);
1499                         return r;
1500                 }
1501                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1502                 track->num_arrays = 1;
1503                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1504
1505                 track->arrays[0].robj = reloc->robj;
1506                 track->arrays[0].esize = track->vtx_size;
1507
1508                 track->max_indx = radeon_get_ib_value(p, idx+1);
1509
1510                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1511                 track->immd_dwords = pkt->count - 1;
1512                 r = r100_cs_track_check(p->rdev, track);
1513                 if (r)
1514                         return r;
1515                 break;
1516         case PACKET3_3D_DRAW_IMMD:
1517                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1518                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1519                         return -EINVAL;
1520                 }
1521                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1522                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1523                 track->immd_dwords = pkt->count - 1;
1524                 r = r100_cs_track_check(p->rdev, track);
1525                 if (r)
1526                         return r;
1527                 break;
1528                 /* triggers drawing using in-packet vertex data */
1529         case PACKET3_3D_DRAW_IMMD_2:
1530                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1531                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1532                         return -EINVAL;
1533                 }
1534                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1535                 track->immd_dwords = pkt->count;
1536                 r = r100_cs_track_check(p->rdev, track);
1537                 if (r)
1538                         return r;
1539                 break;
1540                 /* triggers drawing using in-packet vertex data */
1541         case PACKET3_3D_DRAW_VBUF_2:
1542                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1543                 r = r100_cs_track_check(p->rdev, track);
1544                 if (r)
1545                         return r;
1546                 break;
1547                 /* triggers drawing of vertex buffers setup elsewhere */
1548         case PACKET3_3D_DRAW_INDX_2:
1549                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1550                 r = r100_cs_track_check(p->rdev, track);
1551                 if (r)
1552                         return r;
1553                 break;
1554                 /* triggers drawing using indices to vertex buffer */
1555         case PACKET3_3D_DRAW_VBUF:
1556                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1557                 r = r100_cs_track_check(p->rdev, track);
1558                 if (r)
1559                         return r;
1560                 break;
1561                 /* triggers drawing of vertex buffers setup elsewhere */
1562         case PACKET3_3D_DRAW_INDX:
1563                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1564                 r = r100_cs_track_check(p->rdev, track);
1565                 if (r)
1566                         return r;
1567                 break;
1568                 /* triggers drawing using indices to vertex buffer */
1569         case PACKET3_NOP:
1570                 break;
1571         default:
1572                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1573                 return -EINVAL;
1574         }
1575         return 0;
1576 }
1577
1578 int r100_cs_parse(struct radeon_cs_parser *p)
1579 {
1580         struct radeon_cs_packet pkt;
1581         struct r100_cs_track *track;
1582         int r;
1583
1584         track = kzalloc(sizeof(*track), GFP_KERNEL);
1585         r100_cs_track_clear(p->rdev, track);
1586         p->track = track;
1587         do {
1588                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1589                 if (r) {
1590                         return r;
1591                 }
1592                 p->idx += pkt.count + 2;
1593                 switch (pkt.type) {
1594                         case PACKET_TYPE0:
1595                                 if (p->rdev->family >= CHIP_R200)
1596                                         r = r100_cs_parse_packet0(p, &pkt,
1597                                                                   p->rdev->config.r100.reg_safe_bm,
1598                                                                   p->rdev->config.r100.reg_safe_bm_size,
1599                                                                   &r200_packet0_check);
1600                                 else
1601                                         r = r100_cs_parse_packet0(p, &pkt,
1602                                                                   p->rdev->config.r100.reg_safe_bm,
1603                                                                   p->rdev->config.r100.reg_safe_bm_size,
1604                                                                   &r100_packet0_check);
1605                                 break;
1606                         case PACKET_TYPE2:
1607                                 break;
1608                         case PACKET_TYPE3:
1609                                 r = r100_packet3_check(p, &pkt);
1610                                 break;
1611                         default:
1612                                 DRM_ERROR("Unknown packet type %d !\n",
1613                                           pkt.type);
1614                                 return -EINVAL;
1615                 }
1616                 if (r) {
1617                         return r;
1618                 }
1619         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1620         return 0;
1621 }
1622
1623
1624 /*
1625  * Global GPU functions
1626  */
1627 void r100_errata(struct radeon_device *rdev)
1628 {
1629         rdev->pll_errata = 0;
1630
1631         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1632                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1633         }
1634
1635         if (rdev->family == CHIP_RV100 ||
1636             rdev->family == CHIP_RS100 ||
1637             rdev->family == CHIP_RS200) {
1638                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1639         }
1640 }
1641
1642 /* Wait for vertical sync on primary CRTC */
1643 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1644 {
1645         uint32_t crtc_gen_cntl, tmp;
1646         int i;
1647
1648         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1649         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1650             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1651                 return;
1652         }
1653         /* Clear the CRTC_VBLANK_SAVE bit */
1654         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1655         for (i = 0; i < rdev->usec_timeout; i++) {
1656                 tmp = RREG32(RADEON_CRTC_STATUS);
1657                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1658                         return;
1659                 }
1660                 DRM_UDELAY(1);
1661         }
1662 }
1663
1664 /* Wait for vertical sync on secondary CRTC */
1665 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1666 {
1667         uint32_t crtc2_gen_cntl, tmp;
1668         int i;
1669
1670         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1671         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1672             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1673                 return;
1674
1675         /* Clear the CRTC_VBLANK_SAVE bit */
1676         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1677         for (i = 0; i < rdev->usec_timeout; i++) {
1678                 tmp = RREG32(RADEON_CRTC2_STATUS);
1679                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1680                         return;
1681                 }
1682                 DRM_UDELAY(1);
1683         }
1684 }
1685
1686 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1687 {
1688         unsigned i;
1689         uint32_t tmp;
1690
1691         for (i = 0; i < rdev->usec_timeout; i++) {
1692                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1693                 if (tmp >= n) {
1694                         return 0;
1695                 }
1696                 DRM_UDELAY(1);
1697         }
1698         return -1;
1699 }
1700
1701 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1702 {
1703         unsigned i;
1704         uint32_t tmp;
1705
1706         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1707                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1708                        " Bad things might happen.\n");
1709         }
1710         for (i = 0; i < rdev->usec_timeout; i++) {
1711                 tmp = RREG32(RADEON_RBBM_STATUS);
1712                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1713                         return 0;
1714                 }
1715                 DRM_UDELAY(1);
1716         }
1717         return -1;
1718 }
1719
1720 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1721 {
1722         unsigned i;
1723         uint32_t tmp;
1724
1725         for (i = 0; i < rdev->usec_timeout; i++) {
1726                 /* read MC_STATUS */
1727                 tmp = RREG32(RADEON_MC_STATUS);
1728                 if (tmp & RADEON_MC_IDLE) {
1729                         return 0;
1730                 }
1731                 DRM_UDELAY(1);
1732         }
1733         return -1;
1734 }
1735
1736 void r100_gpu_init(struct radeon_device *rdev)
1737 {
1738         /* TODO: anythings to do here ? pipes ? */
1739         r100_hdp_reset(rdev);
1740 }
1741
1742 void r100_hdp_reset(struct radeon_device *rdev)
1743 {
1744         uint32_t tmp;
1745
1746         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1747         tmp |= (7 << 28);
1748         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1749         (void)RREG32(RADEON_HOST_PATH_CNTL);
1750         udelay(200);
1751         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1752         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1753         (void)RREG32(RADEON_HOST_PATH_CNTL);
1754 }
1755
1756 int r100_rb2d_reset(struct radeon_device *rdev)
1757 {
1758         uint32_t tmp;
1759         int i;
1760
1761         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1762         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1763         udelay(200);
1764         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1765         /* Wait to prevent race in RBBM_STATUS */
1766         mdelay(1);
1767         for (i = 0; i < rdev->usec_timeout; i++) {
1768                 tmp = RREG32(RADEON_RBBM_STATUS);
1769                 if (!(tmp & (1 << 26))) {
1770                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1771                                  tmp);
1772                         return 0;
1773                 }
1774                 DRM_UDELAY(1);
1775         }
1776         tmp = RREG32(RADEON_RBBM_STATUS);
1777         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1778         return -1;
1779 }
1780
1781 int r100_gpu_reset(struct radeon_device *rdev)
1782 {
1783         uint32_t status;
1784
1785         /* reset order likely matter */
1786         status = RREG32(RADEON_RBBM_STATUS);
1787         /* reset HDP */
1788         r100_hdp_reset(rdev);
1789         /* reset rb2d */
1790         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1791                 r100_rb2d_reset(rdev);
1792         }
1793         /* TODO: reset 3D engine */
1794         /* reset CP */
1795         status = RREG32(RADEON_RBBM_STATUS);
1796         if (status & (1 << 16)) {
1797                 r100_cp_reset(rdev);
1798         }
1799         /* Check if GPU is idle */
1800         status = RREG32(RADEON_RBBM_STATUS);
1801         if (status & RADEON_RBBM_ACTIVE) {
1802                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1803                 return -1;
1804         }
1805         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1806         return 0;
1807 }
1808
1809 void r100_set_common_regs(struct radeon_device *rdev)
1810 {
1811         struct drm_device *dev = rdev->ddev;
1812         bool force_dac2 = false;
1813         u32 tmp;
1814
1815         /* set these so they don't interfere with anything */
1816         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1817         WREG32(RADEON_SUBPIC_CNTL, 0);
1818         WREG32(RADEON_VIPH_CONTROL, 0);
1819         WREG32(RADEON_I2C_CNTL_1, 0);
1820         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1821         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1822         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1823
1824         /* always set up dac2 on rn50 and some rv100 as lots
1825          * of servers seem to wire it up to a VGA port but
1826          * don't report it in the bios connector
1827          * table.
1828          */
1829         switch (dev->pdev->device) {
1830                 /* RN50 */
1831         case 0x515e:
1832         case 0x5969:
1833                 force_dac2 = true;
1834                 break;
1835                 /* RV100*/
1836         case 0x5159:
1837         case 0x515a:
1838                 /* DELL triple head servers */
1839                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1840                     ((dev->pdev->subsystem_device == 0x016c) ||
1841                      (dev->pdev->subsystem_device == 0x016d) ||
1842                      (dev->pdev->subsystem_device == 0x016e) ||
1843                      (dev->pdev->subsystem_device == 0x016f) ||
1844                      (dev->pdev->subsystem_device == 0x0170) ||
1845                      (dev->pdev->subsystem_device == 0x017d) ||
1846                      (dev->pdev->subsystem_device == 0x017e) ||
1847                      (dev->pdev->subsystem_device == 0x0183) ||
1848                      (dev->pdev->subsystem_device == 0x018a) ||
1849                      (dev->pdev->subsystem_device == 0x019a)))
1850                         force_dac2 = true;
1851                 break;
1852         }
1853
1854         if (force_dac2) {
1855                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1856                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1857                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1858
1859                 /* For CRT on DAC2, don't turn it on if BIOS didn't
1860                    enable it, even it's detected.
1861                 */
1862
1863                 /* force it to crtc0 */
1864                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1865                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1866                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1867
1868                 /* set up the TV DAC */
1869                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1870                                  RADEON_TV_DAC_STD_MASK |
1871                                  RADEON_TV_DAC_RDACPD |
1872                                  RADEON_TV_DAC_GDACPD |
1873                                  RADEON_TV_DAC_BDACPD |
1874                                  RADEON_TV_DAC_BGADJ_MASK |
1875                                  RADEON_TV_DAC_DACADJ_MASK);
1876                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1877                                 RADEON_TV_DAC_NHOLD |
1878                                 RADEON_TV_DAC_STD_PS2 |
1879                                 (0x58 << 16));
1880
1881                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1882                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1883                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1884         }
1885
1886         /* switch PM block to ACPI mode */
1887         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1888         tmp &= ~RADEON_PM_MODE_SEL;
1889         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1890
1891 }
1892
1893 /*
1894  * VRAM info
1895  */
1896 static void r100_vram_get_type(struct radeon_device *rdev)
1897 {
1898         uint32_t tmp;
1899
1900         rdev->mc.vram_is_ddr = false;
1901         if (rdev->flags & RADEON_IS_IGP)
1902                 rdev->mc.vram_is_ddr = true;
1903         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1904                 rdev->mc.vram_is_ddr = true;
1905         if ((rdev->family == CHIP_RV100) ||
1906             (rdev->family == CHIP_RS100) ||
1907             (rdev->family == CHIP_RS200)) {
1908                 tmp = RREG32(RADEON_MEM_CNTL);
1909                 if (tmp & RV100_HALF_MODE) {
1910                         rdev->mc.vram_width = 32;
1911                 } else {
1912                         rdev->mc.vram_width = 64;
1913                 }
1914                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1915                         rdev->mc.vram_width /= 4;
1916                         rdev->mc.vram_is_ddr = true;
1917                 }
1918         } else if (rdev->family <= CHIP_RV280) {
1919                 tmp = RREG32(RADEON_MEM_CNTL);
1920                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1921                         rdev->mc.vram_width = 128;
1922                 } else {
1923                         rdev->mc.vram_width = 64;
1924                 }
1925         } else {
1926                 /* newer IGPs */
1927                 rdev->mc.vram_width = 128;
1928         }
1929 }
1930
1931 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1932 {
1933         u32 aper_size;
1934         u8 byte;
1935
1936         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1937
1938         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1939          * that is has the 2nd generation multifunction PCI interface
1940          */
1941         if (rdev->family == CHIP_RV280 ||
1942             rdev->family >= CHIP_RV350) {
1943                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1944                        ~RADEON_HDP_APER_CNTL);
1945                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1946                 return aper_size * 2;
1947         }
1948
1949         /* Older cards have all sorts of funny issues to deal with. First
1950          * check if it's a multifunction card by reading the PCI config
1951          * header type... Limit those to one aperture size
1952          */
1953         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1954         if (byte & 0x80) {
1955                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1956                 DRM_INFO("Limiting VRAM to one aperture\n");
1957                 return aper_size;
1958         }
1959
1960         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1961          * have set it up. We don't write this as it's broken on some ASICs but
1962          * we expect the BIOS to have done the right thing (might be too optimistic...)
1963          */
1964         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1965                 return aper_size * 2;
1966         return aper_size;
1967 }
1968
1969 void r100_vram_init_sizes(struct radeon_device *rdev)
1970 {
1971         u64 config_aper_size;
1972
1973         /* work out accessible VRAM */
1974         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1975         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1976         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1977         /* FIXME we don't use the second aperture yet when we could use it */
1978         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1979                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1980         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1981         if (rdev->flags & RADEON_IS_IGP) {
1982                 uint32_t tom;
1983                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1984                 tom = RREG32(RADEON_NB_TOM);
1985                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1986                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1987                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1988         } else {
1989                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1990                 /* Some production boards of m6 will report 0
1991                  * if it's 8 MB
1992                  */
1993                 if (rdev->mc.real_vram_size == 0) {
1994                         rdev->mc.real_vram_size = 8192 * 1024;
1995                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1996                 }
1997                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1998                  * Novell bug 204882 + along with lots of ubuntu ones
1999                  */
2000                 if (config_aper_size > rdev->mc.real_vram_size)
2001                         rdev->mc.mc_vram_size = config_aper_size;
2002                 else
2003                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2004         }
2005         /* FIXME remove this once we support unmappable VRAM */
2006         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
2007                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
2008                 rdev->mc.real_vram_size = rdev->mc.aper_size;
2009         }
2010 }
2011
2012 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2013 {
2014         uint32_t temp;
2015
2016         temp = RREG32(RADEON_CONFIG_CNTL);
2017         if (state == false) {
2018                 temp &= ~(1<<8);
2019                 temp |= (1<<9);
2020         } else {
2021                 temp &= ~(1<<9);
2022         }
2023         WREG32(RADEON_CONFIG_CNTL, temp);
2024 }
2025
2026 void r100_mc_init(struct radeon_device *rdev)
2027 {
2028         u64 base;
2029
2030         r100_vram_get_type(rdev);
2031         r100_vram_init_sizes(rdev);
2032         base = rdev->mc.aper_base;
2033         if (rdev->flags & RADEON_IS_IGP)
2034                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2035         radeon_vram_location(rdev, &rdev->mc, base);
2036         if (!(rdev->flags & RADEON_IS_AGP))
2037                 radeon_gtt_location(rdev, &rdev->mc);
2038         radeon_update_bandwidth_info(rdev);
2039 }
2040
2041
2042 /*
2043  * Indirect registers accessor
2044  */
2045 void r100_pll_errata_after_index(struct radeon_device *rdev)
2046 {
2047         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2048                 return;
2049         }
2050         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2051         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2052 }
2053
2054 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2055 {
2056         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2057          * or the chip could hang on a subsequent access
2058          */
2059         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2060                 udelay(5000);
2061         }
2062
2063         /* This function is required to workaround a hardware bug in some (all?)
2064          * revisions of the R300.  This workaround should be called after every
2065          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2066          * may not be correct.
2067          */
2068         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2069                 uint32_t save, tmp;
2070
2071                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2072                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2073                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2074                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2075                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2076         }
2077 }
2078
2079 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2080 {
2081         uint32_t data;
2082
2083         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2084         r100_pll_errata_after_index(rdev);
2085         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2086         r100_pll_errata_after_data(rdev);
2087         return data;
2088 }
2089
2090 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2091 {
2092         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2093         r100_pll_errata_after_index(rdev);
2094         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2095         r100_pll_errata_after_data(rdev);
2096 }
2097
2098 void r100_set_safe_registers(struct radeon_device *rdev)
2099 {
2100         if (ASIC_IS_RN50(rdev)) {
2101                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2102                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2103         } else if (rdev->family < CHIP_R200) {
2104                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2105                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2106         } else {
2107                 r200_set_safe_registers(rdev);
2108         }
2109 }
2110
2111 /*
2112  * Debugfs info
2113  */
2114 #if defined(CONFIG_DEBUG_FS)
2115 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2116 {
2117         struct drm_info_node *node = (struct drm_info_node *) m->private;
2118         struct drm_device *dev = node->minor->dev;
2119         struct radeon_device *rdev = dev->dev_private;
2120         uint32_t reg, value;
2121         unsigned i;
2122
2123         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2124         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2125         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2126         for (i = 0; i < 64; i++) {
2127                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2128                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2129                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2130                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2131                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2132         }
2133         return 0;
2134 }
2135
2136 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2137 {
2138         struct drm_info_node *node = (struct drm_info_node *) m->private;
2139         struct drm_device *dev = node->minor->dev;
2140         struct radeon_device *rdev = dev->dev_private;
2141         uint32_t rdp, wdp;
2142         unsigned count, i, j;
2143
2144         radeon_ring_free_size(rdev);
2145         rdp = RREG32(RADEON_CP_RB_RPTR);
2146         wdp = RREG32(RADEON_CP_RB_WPTR);
2147         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2148         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2149         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2150         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2151         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2152         seq_printf(m, "%u dwords in ring\n", count);
2153         for (j = 0; j <= count; j++) {
2154                 i = (rdp + j) & rdev->cp.ptr_mask;
2155                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2156         }
2157         return 0;
2158 }
2159
2160
2161 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2162 {
2163         struct drm_info_node *node = (struct drm_info_node *) m->private;
2164         struct drm_device *dev = node->minor->dev;
2165         struct radeon_device *rdev = dev->dev_private;
2166         uint32_t csq_stat, csq2_stat, tmp;
2167         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2168         unsigned i;
2169
2170         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2171         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2172         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2173         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2174         r_rptr = (csq_stat >> 0) & 0x3ff;
2175         r_wptr = (csq_stat >> 10) & 0x3ff;
2176         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2177         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2178         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2179         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2180         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2181         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2182         seq_printf(m, "Ring rptr %u\n", r_rptr);
2183         seq_printf(m, "Ring wptr %u\n", r_wptr);
2184         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2185         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2186         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2187         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2188         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2189          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2190         seq_printf(m, "Ring fifo:\n");
2191         for (i = 0; i < 256; i++) {
2192                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2193                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2194                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2195         }
2196         seq_printf(m, "Indirect1 fifo:\n");
2197         for (i = 256; i <= 512; i++) {
2198                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2199                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2200                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2201         }
2202         seq_printf(m, "Indirect2 fifo:\n");
2203         for (i = 640; i < ib1_wptr; i++) {
2204                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2205                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2206                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2207         }
2208         return 0;
2209 }
2210
2211 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2212 {
2213         struct drm_info_node *node = (struct drm_info_node *) m->private;
2214         struct drm_device *dev = node->minor->dev;
2215         struct radeon_device *rdev = dev->dev_private;
2216         uint32_t tmp;
2217
2218         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2219         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2220         tmp = RREG32(RADEON_MC_FB_LOCATION);
2221         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2222         tmp = RREG32(RADEON_BUS_CNTL);
2223         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2224         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2225         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2226         tmp = RREG32(RADEON_AGP_BASE);
2227         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2228         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2229         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2230         tmp = RREG32(0x01D0);
2231         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2232         tmp = RREG32(RADEON_AIC_LO_ADDR);
2233         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2234         tmp = RREG32(RADEON_AIC_HI_ADDR);
2235         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2236         tmp = RREG32(0x01E4);
2237         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2238         return 0;
2239 }
2240
2241 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2242         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2243 };
2244
2245 static struct drm_info_list r100_debugfs_cp_list[] = {
2246         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2247         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2248 };
2249
2250 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2251         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2252 };
2253 #endif
2254
2255 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2256 {
2257 #if defined(CONFIG_DEBUG_FS)
2258         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2259 #else
2260         return 0;
2261 #endif
2262 }
2263
2264 int r100_debugfs_cp_init(struct radeon_device *rdev)
2265 {
2266 #if defined(CONFIG_DEBUG_FS)
2267         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2268 #else
2269         return 0;
2270 #endif
2271 }
2272
2273 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2274 {
2275 #if defined(CONFIG_DEBUG_FS)
2276         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2277 #else
2278         return 0;
2279 #endif
2280 }
2281
2282 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2283                          uint32_t tiling_flags, uint32_t pitch,
2284                          uint32_t offset, uint32_t obj_size)
2285 {
2286         int surf_index = reg * 16;
2287         int flags = 0;
2288
2289         /* r100/r200 divide by 16 */
2290         if (rdev->family < CHIP_R300)
2291                 flags = pitch / 16;
2292         else
2293                 flags = pitch / 8;
2294
2295         if (rdev->family <= CHIP_RS200) {
2296                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2297                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2298                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2299                 if (tiling_flags & RADEON_TILING_MACRO)
2300                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2301         } else if (rdev->family <= CHIP_RV280) {
2302                 if (tiling_flags & (RADEON_TILING_MACRO))
2303                         flags |= R200_SURF_TILE_COLOR_MACRO;
2304                 if (tiling_flags & RADEON_TILING_MICRO)
2305                         flags |= R200_SURF_TILE_COLOR_MICRO;
2306         } else {
2307                 if (tiling_flags & RADEON_TILING_MACRO)
2308                         flags |= R300_SURF_TILE_MACRO;
2309                 if (tiling_flags & RADEON_TILING_MICRO)
2310                         flags |= R300_SURF_TILE_MICRO;
2311         }
2312
2313         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2314                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2315         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2316                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2317
2318         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2319         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2320         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2321         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2322         return 0;
2323 }
2324
2325 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2326 {
2327         int surf_index = reg * 16;
2328         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2329 }
2330
2331 void r100_bandwidth_update(struct radeon_device *rdev)
2332 {
2333         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2334         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2335         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2336         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2337         fixed20_12 memtcas_ff[8] = {
2338                 fixed_init(1),
2339                 fixed_init(2),
2340                 fixed_init(3),
2341                 fixed_init(0),
2342                 fixed_init_half(1),
2343                 fixed_init_half(2),
2344                 fixed_init(0),
2345         };
2346         fixed20_12 memtcas_rs480_ff[8] = {
2347                 fixed_init(0),
2348                 fixed_init(1),
2349                 fixed_init(2),
2350                 fixed_init(3),
2351                 fixed_init(0),
2352                 fixed_init_half(1),
2353                 fixed_init_half(2),
2354                 fixed_init_half(3),
2355         };
2356         fixed20_12 memtcas2_ff[8] = {
2357                 fixed_init(0),
2358                 fixed_init(1),
2359                 fixed_init(2),
2360                 fixed_init(3),
2361                 fixed_init(4),
2362                 fixed_init(5),
2363                 fixed_init(6),
2364                 fixed_init(7),
2365         };
2366         fixed20_12 memtrbs[8] = {
2367                 fixed_init(1),
2368                 fixed_init_half(1),
2369                 fixed_init(2),
2370                 fixed_init_half(2),
2371                 fixed_init(3),
2372                 fixed_init_half(3),
2373                 fixed_init(4),
2374                 fixed_init_half(4)
2375         };
2376         fixed20_12 memtrbs_r4xx[8] = {
2377                 fixed_init(4),
2378                 fixed_init(5),
2379                 fixed_init(6),
2380                 fixed_init(7),
2381                 fixed_init(8),
2382                 fixed_init(9),
2383                 fixed_init(10),
2384                 fixed_init(11)
2385         };
2386         fixed20_12 min_mem_eff;
2387         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2388         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2389         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2390                 disp_drain_rate2, read_return_rate;
2391         fixed20_12 time_disp1_drop_priority;
2392         int c;
2393         int cur_size = 16;       /* in octawords */
2394         int critical_point = 0, critical_point2;
2395 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2396         int stop_req, max_stop_req;
2397         struct drm_display_mode *mode1 = NULL;
2398         struct drm_display_mode *mode2 = NULL;
2399         uint32_t pixel_bytes1 = 0;
2400         uint32_t pixel_bytes2 = 0;
2401
2402         radeon_update_display_priority(rdev);
2403
2404         if (rdev->mode_info.crtcs[0]->base.enabled) {
2405                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2406                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2407         }
2408         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2409                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2410                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2411                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2412                 }
2413         }
2414
2415         min_mem_eff.full = rfixed_const_8(0);
2416         /* get modes */
2417         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2418                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2419                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2420                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2421                 /* check crtc enables */
2422                 if (mode2)
2423                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2424                 if (mode1)
2425                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2426                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2427         }
2428
2429         /*
2430          * determine is there is enough bw for current mode
2431          */
2432         sclk_ff = rdev->pm.sclk;
2433         mclk_ff = rdev->pm.mclk;
2434
2435         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2436         temp_ff.full = rfixed_const(temp);
2437         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2438
2439         pix_clk.full = 0;
2440         pix_clk2.full = 0;
2441         peak_disp_bw.full = 0;
2442         if (mode1) {
2443                 temp_ff.full = rfixed_const(1000);
2444                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2445                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2446                 temp_ff.full = rfixed_const(pixel_bytes1);
2447                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2448         }
2449         if (mode2) {
2450                 temp_ff.full = rfixed_const(1000);
2451                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2452                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2453                 temp_ff.full = rfixed_const(pixel_bytes2);
2454                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2455         }
2456
2457         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2458         if (peak_disp_bw.full >= mem_bw.full) {
2459                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2460                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2461         }
2462
2463         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2464         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2465         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2466                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2467                 mem_trp  = ((temp & 0x3)) + 1;
2468                 mem_tras = ((temp & 0x70) >> 4) + 1;
2469         } else if (rdev->family == CHIP_R300 ||
2470                    rdev->family == CHIP_R350) { /* r300, r350 */
2471                 mem_trcd = (temp & 0x7) + 1;
2472                 mem_trp = ((temp >> 8) & 0x7) + 1;
2473                 mem_tras = ((temp >> 11) & 0xf) + 4;
2474         } else if (rdev->family == CHIP_RV350 ||
2475                    rdev->family <= CHIP_RV380) {
2476                 /* rv3x0 */
2477                 mem_trcd = (temp & 0x7) + 3;
2478                 mem_trp = ((temp >> 8) & 0x7) + 3;
2479                 mem_tras = ((temp >> 11) & 0xf) + 6;
2480         } else if (rdev->family == CHIP_R420 ||
2481                    rdev->family == CHIP_R423 ||
2482                    rdev->family == CHIP_RV410) {
2483                 /* r4xx */
2484                 mem_trcd = (temp & 0xf) + 3;
2485                 if (mem_trcd > 15)
2486                         mem_trcd = 15;
2487                 mem_trp = ((temp >> 8) & 0xf) + 3;
2488                 if (mem_trp > 15)
2489                         mem_trp = 15;
2490                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2491                 if (mem_tras > 31)
2492                         mem_tras = 31;
2493         } else { /* RV200, R200 */
2494                 mem_trcd = (temp & 0x7) + 1;
2495                 mem_trp = ((temp >> 8) & 0x7) + 1;
2496                 mem_tras = ((temp >> 12) & 0xf) + 4;
2497         }
2498         /* convert to FF */
2499         trcd_ff.full = rfixed_const(mem_trcd);
2500         trp_ff.full = rfixed_const(mem_trp);
2501         tras_ff.full = rfixed_const(mem_tras);
2502
2503         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2504         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2505         data = (temp & (7 << 20)) >> 20;
2506         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2507                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2508                         tcas_ff = memtcas_rs480_ff[data];
2509                 else
2510                         tcas_ff = memtcas_ff[data];
2511         } else
2512                 tcas_ff = memtcas2_ff[data];
2513
2514         if (rdev->family == CHIP_RS400 ||
2515             rdev->family == CHIP_RS480) {
2516                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2517                 data = (temp >> 23) & 0x7;
2518                 if (data < 5)
2519                         tcas_ff.full += rfixed_const(data);
2520         }
2521
2522         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2523                 /* on the R300, Tcas is included in Trbs.
2524                  */
2525                 temp = RREG32(RADEON_MEM_CNTL);
2526                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2527                 if (data == 1) {
2528                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2529                                 temp = RREG32(R300_MC_IND_INDEX);
2530                                 temp &= ~R300_MC_IND_ADDR_MASK;
2531                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2532                                 WREG32(R300_MC_IND_INDEX, temp);
2533                                 temp = RREG32(R300_MC_IND_DATA);
2534                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2535                         } else {
2536                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2537                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2538                         }
2539                 } else {
2540                         temp = RREG32(R300_MC_READ_CNTL_AB);
2541                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2542                 }
2543                 if (rdev->family == CHIP_RV410 ||
2544                     rdev->family == CHIP_R420 ||
2545                     rdev->family == CHIP_R423)
2546                         trbs_ff = memtrbs_r4xx[data];
2547                 else
2548                         trbs_ff = memtrbs[data];
2549                 tcas_ff.full += trbs_ff.full;
2550         }
2551
2552         sclk_eff_ff.full = sclk_ff.full;
2553
2554         if (rdev->flags & RADEON_IS_AGP) {
2555                 fixed20_12 agpmode_ff;
2556                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2557                 temp_ff.full = rfixed_const_666(16);
2558                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2559         }
2560         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2561
2562         if (ASIC_IS_R300(rdev)) {
2563                 sclk_delay_ff.full = rfixed_const(250);
2564         } else {
2565                 if ((rdev->family == CHIP_RV100) ||
2566                     rdev->flags & RADEON_IS_IGP) {
2567                         if (rdev->mc.vram_is_ddr)
2568                                 sclk_delay_ff.full = rfixed_const(41);
2569                         else
2570                                 sclk_delay_ff.full = rfixed_const(33);
2571                 } else {
2572                         if (rdev->mc.vram_width == 128)
2573                                 sclk_delay_ff.full = rfixed_const(57);
2574                         else
2575                                 sclk_delay_ff.full = rfixed_const(41);
2576                 }
2577         }
2578
2579         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2580
2581         if (rdev->mc.vram_is_ddr) {
2582                 if (rdev->mc.vram_width == 32) {
2583                         k1.full = rfixed_const(40);
2584                         c  = 3;
2585                 } else {
2586                         k1.full = rfixed_const(20);
2587                         c  = 1;
2588                 }
2589         } else {
2590                 k1.full = rfixed_const(40);
2591                 c  = 3;
2592         }
2593
2594         temp_ff.full = rfixed_const(2);
2595         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2596         temp_ff.full = rfixed_const(c);
2597         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2598         temp_ff.full = rfixed_const(4);
2599         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2600         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2601         mc_latency_mclk.full += k1.full;
2602
2603         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2604         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2605
2606         /*
2607           HW cursor time assuming worst case of full size colour cursor.
2608         */
2609         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2610         temp_ff.full += trcd_ff.full;
2611         if (temp_ff.full < tras_ff.full)
2612                 temp_ff.full = tras_ff.full;
2613         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2614
2615         temp_ff.full = rfixed_const(cur_size);
2616         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2617         /*
2618           Find the total latency for the display data.
2619         */
2620         disp_latency_overhead.full = rfixed_const(8);
2621         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2622         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2623         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2624
2625         if (mc_latency_mclk.full > mc_latency_sclk.full)
2626                 disp_latency.full = mc_latency_mclk.full;
2627         else
2628                 disp_latency.full = mc_latency_sclk.full;
2629
2630         /* setup Max GRPH_STOP_REQ default value */
2631         if (ASIC_IS_RV100(rdev))
2632                 max_stop_req = 0x5c;
2633         else
2634                 max_stop_req = 0x7c;
2635
2636         if (mode1) {
2637                 /*  CRTC1
2638                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2639                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2640                 */
2641                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2642
2643                 if (stop_req > max_stop_req)
2644                         stop_req = max_stop_req;
2645
2646                 /*
2647                   Find the drain rate of the display buffer.
2648                 */
2649                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2650                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2651
2652                 /*
2653                   Find the critical point of the display buffer.
2654                 */
2655                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2656                 crit_point_ff.full += rfixed_const_half(0);
2657
2658                 critical_point = rfixed_trunc(crit_point_ff);
2659
2660                 if (rdev->disp_priority == 2) {
2661                         critical_point = 0;
2662                 }
2663
2664                 /*
2665                   The critical point should never be above max_stop_req-4.  Setting
2666                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2667                 */
2668                 if (max_stop_req - critical_point < 4)
2669                         critical_point = 0;
2670
2671                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2672                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2673                         critical_point = 0x10;
2674                 }
2675
2676                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2677                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2678                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2679                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2680                 if ((rdev->family == CHIP_R350) &&
2681                     (stop_req > 0x15)) {
2682                         stop_req -= 0x10;
2683                 }
2684                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2685                 temp |= RADEON_GRPH_BUFFER_SIZE;
2686                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2687                           RADEON_GRPH_CRITICAL_AT_SOF |
2688                           RADEON_GRPH_STOP_CNTL);
2689                 /*
2690                   Write the result into the register.
2691                 */
2692                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2693                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2694
2695 #if 0
2696                 if ((rdev->family == CHIP_RS400) ||
2697                     (rdev->family == CHIP_RS480)) {
2698                         /* attempt to program RS400 disp regs correctly ??? */
2699                         temp = RREG32(RS400_DISP1_REG_CNTL);
2700                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2701                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2702                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2703                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2704                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2705                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2706                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2707                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2708                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2709                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2710                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2711                 }
2712 #endif
2713
2714                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2715                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2716                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2717         }
2718
2719         if (mode2) {
2720                 u32 grph2_cntl;
2721                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2722
2723                 if (stop_req > max_stop_req)
2724                         stop_req = max_stop_req;
2725
2726                 /*
2727                   Find the drain rate of the display buffer.
2728                 */
2729                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2730                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2731
2732                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2733                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2734                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2735                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2736                 if ((rdev->family == CHIP_R350) &&
2737                     (stop_req > 0x15)) {
2738                         stop_req -= 0x10;
2739                 }
2740                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2741                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2742                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2743                           RADEON_GRPH_CRITICAL_AT_SOF |
2744                           RADEON_GRPH_STOP_CNTL);
2745
2746                 if ((rdev->family == CHIP_RS100) ||
2747                     (rdev->family == CHIP_RS200))
2748                         critical_point2 = 0;
2749                 else {
2750                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2751                         temp_ff.full = rfixed_const(temp);
2752                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2753                         if (sclk_ff.full < temp_ff.full)
2754                                 temp_ff.full = sclk_ff.full;
2755
2756                         read_return_rate.full = temp_ff.full;
2757
2758                         if (mode1) {
2759                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2760                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2761                         } else {
2762                                 time_disp1_drop_priority.full = 0;
2763                         }
2764                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2765                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2766                         crit_point_ff.full += rfixed_const_half(0);
2767
2768                         critical_point2 = rfixed_trunc(crit_point_ff);
2769
2770                         if (rdev->disp_priority == 2) {
2771                                 critical_point2 = 0;
2772                         }
2773
2774                         if (max_stop_req - critical_point2 < 4)
2775                                 critical_point2 = 0;
2776
2777                 }
2778
2779                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2780                         /* some R300 cards have problem with this set to 0 */
2781                         critical_point2 = 0x10;
2782                 }
2783
2784                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2785                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2786
2787                 if ((rdev->family == CHIP_RS400) ||
2788                     (rdev->family == CHIP_RS480)) {
2789 #if 0
2790                         /* attempt to program RS400 disp2 regs correctly ??? */
2791                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2792                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2793                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2794                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2795                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2796                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2797                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2798                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2799                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2800                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2801                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2802                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2803 #endif
2804                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2805                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2806                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2807                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2808                 }
2809
2810                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2811                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2812         }
2813 }
2814
2815 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2816 {
2817         DRM_ERROR("pitch                      %d\n", t->pitch);
2818         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2819         DRM_ERROR("width                      %d\n", t->width);
2820         DRM_ERROR("width_11                   %d\n", t->width_11);
2821         DRM_ERROR("height                     %d\n", t->height);
2822         DRM_ERROR("height_11                  %d\n", t->height_11);
2823         DRM_ERROR("num levels                 %d\n", t->num_levels);
2824         DRM_ERROR("depth                      %d\n", t->txdepth);
2825         DRM_ERROR("bpp                        %d\n", t->cpp);
2826         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2827         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2828         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2829         DRM_ERROR("compress format            %d\n", t->compress_format);
2830 }
2831
2832 static int r100_cs_track_cube(struct radeon_device *rdev,
2833                               struct r100_cs_track *track, unsigned idx)
2834 {
2835         unsigned face, w, h;
2836         struct radeon_bo *cube_robj;
2837         unsigned long size;
2838
2839         for (face = 0; face < 5; face++) {
2840                 cube_robj = track->textures[idx].cube_info[face].robj;
2841                 w = track->textures[idx].cube_info[face].width;
2842                 h = track->textures[idx].cube_info[face].height;
2843
2844                 size = w * h;
2845                 size *= track->textures[idx].cpp;
2846
2847                 size += track->textures[idx].cube_info[face].offset;
2848
2849                 if (size > radeon_bo_size(cube_robj)) {
2850                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2851                                   size, radeon_bo_size(cube_robj));
2852                         r100_cs_track_texture_print(&track->textures[idx]);
2853                         return -1;
2854                 }
2855         }
2856         return 0;
2857 }
2858
2859 static int r100_track_compress_size(int compress_format, int w, int h)
2860 {
2861         int block_width, block_height, block_bytes;
2862         int wblocks, hblocks;
2863         int min_wblocks;
2864         int sz;
2865
2866         block_width = 4;
2867         block_height = 4;
2868
2869         switch (compress_format) {
2870         case R100_TRACK_COMP_DXT1:
2871                 block_bytes = 8;
2872                 min_wblocks = 4;
2873                 break;
2874         default:
2875         case R100_TRACK_COMP_DXT35:
2876                 block_bytes = 16;
2877                 min_wblocks = 2;
2878                 break;
2879         }
2880
2881         hblocks = (h + block_height - 1) / block_height;
2882         wblocks = (w + block_width - 1) / block_width;
2883         if (wblocks < min_wblocks)
2884                 wblocks = min_wblocks;
2885         sz = wblocks * hblocks * block_bytes;
2886         return sz;
2887 }
2888
2889 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2890                                        struct r100_cs_track *track)
2891 {
2892         struct radeon_bo *robj;
2893         unsigned long size;
2894         unsigned u, i, w, h, d;
2895         int ret;
2896
2897         for (u = 0; u < track->num_texture; u++) {
2898                 if (!track->textures[u].enabled)
2899                         continue;
2900                 robj = track->textures[u].robj;
2901                 if (robj == NULL) {
2902                         DRM_ERROR("No texture bound to unit %u\n", u);
2903                         return -EINVAL;
2904                 }
2905                 size = 0;
2906                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2907                         if (track->textures[u].use_pitch) {
2908                                 if (rdev->family < CHIP_R300)
2909                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2910                                 else
2911                                         w = track->textures[u].pitch / (1 << i);
2912                         } else {
2913                                 w = track->textures[u].width;
2914                                 if (rdev->family >= CHIP_RV515)
2915                                         w |= track->textures[u].width_11;
2916                                 w = w / (1 << i);
2917                                 if (track->textures[u].roundup_w)
2918                                         w = roundup_pow_of_two(w);
2919                         }
2920                         h = track->textures[u].height;
2921                         if (rdev->family >= CHIP_RV515)
2922                                 h |= track->textures[u].height_11;
2923                         h = h / (1 << i);
2924                         if (track->textures[u].roundup_h)
2925                                 h = roundup_pow_of_two(h);
2926                         if (track->textures[u].tex_coord_type == 1) {
2927                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2928                                 if (!d)
2929                                         d = 1;
2930                         } else {
2931                                 d = 1;
2932                         }
2933                         if (track->textures[u].compress_format) {
2934
2935                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2936                                 /* compressed textures are block based */
2937                         } else
2938                                 size += w * h * d;
2939                 }
2940                 size *= track->textures[u].cpp;
2941
2942                 switch (track->textures[u].tex_coord_type) {
2943                 case 0:
2944                 case 1:
2945                         break;
2946                 case 2:
2947                         if (track->separate_cube) {
2948                                 ret = r100_cs_track_cube(rdev, track, u);
2949                                 if (ret)
2950                                         return ret;
2951                         } else
2952                                 size *= 6;
2953                         break;
2954                 default:
2955                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2956                                   "%u\n", track->textures[u].tex_coord_type, u);
2957                         return -EINVAL;
2958                 }
2959                 if (size > radeon_bo_size(robj)) {
2960                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2961                                   "%lu\n", u, size, radeon_bo_size(robj));
2962                         r100_cs_track_texture_print(&track->textures[u]);
2963                         return -EINVAL;
2964                 }
2965         }
2966         return 0;
2967 }
2968
2969 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2970 {
2971         unsigned i;
2972         unsigned long size;
2973         unsigned prim_walk;
2974         unsigned nverts;
2975
2976         for (i = 0; i < track->num_cb; i++) {
2977                 if (track->cb[i].robj == NULL) {
2978                         if (!(track->fastfill || track->color_channel_mask ||
2979                               track->blend_read_enable)) {
2980                                 continue;
2981                         }
2982                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2983                         return -EINVAL;
2984                 }
2985                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2986                 size += track->cb[i].offset;
2987                 if (size > radeon_bo_size(track->cb[i].robj)) {
2988                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2989                                   "(need %lu have %lu) !\n", i, size,
2990                                   radeon_bo_size(track->cb[i].robj));
2991                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2992                                   i, track->cb[i].pitch, track->cb[i].cpp,
2993                                   track->cb[i].offset, track->maxy);
2994                         return -EINVAL;
2995                 }
2996         }
2997         if (track->z_enabled) {
2998                 if (track->zb.robj == NULL) {
2999                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3000                         return -EINVAL;
3001                 }
3002                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3003                 size += track->zb.offset;
3004                 if (size > radeon_bo_size(track->zb.robj)) {
3005                         DRM_ERROR("[drm] Buffer too small for z buffer "
3006                                   "(need %lu have %lu) !\n", size,
3007                                   radeon_bo_size(track->zb.robj));
3008                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3009                                   track->zb.pitch, track->zb.cpp,
3010                                   track->zb.offset, track->maxy);
3011                         return -EINVAL;
3012                 }
3013         }
3014         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3015         if (track->vap_vf_cntl & (1 << 14)) {
3016                 nverts = track->vap_alt_nverts;
3017         } else {
3018                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3019         }
3020         switch (prim_walk) {
3021         case 1:
3022                 for (i = 0; i < track->num_arrays; i++) {
3023                         size = track->arrays[i].esize * track->max_indx * 4;
3024                         if (track->arrays[i].robj == NULL) {
3025                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3026                                           "bound\n", prim_walk, i);
3027                                 return -EINVAL;
3028                         }
3029                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3030                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3031                                         "need %lu dwords have %lu dwords\n",
3032                                         prim_walk, i, size >> 2,
3033                                         radeon_bo_size(track->arrays[i].robj)
3034                                         >> 2);
3035                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3036                                 return -EINVAL;
3037                         }
3038                 }
3039                 break;
3040         case 2:
3041                 for (i = 0; i < track->num_arrays; i++) {
3042                         size = track->arrays[i].esize * (nverts - 1) * 4;
3043                         if (track->arrays[i].robj == NULL) {
3044                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3045                                           "bound\n", prim_walk, i);
3046                                 return -EINVAL;
3047                         }
3048                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3049                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3050                                         "need %lu dwords have %lu dwords\n",
3051                                         prim_walk, i, size >> 2,
3052                                         radeon_bo_size(track->arrays[i].robj)
3053                                         >> 2);
3054                                 return -EINVAL;
3055                         }
3056                 }
3057                 break;
3058         case 3:
3059                 size = track->vtx_size * nverts;
3060                 if (size != track->immd_dwords) {
3061                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3062                                   track->immd_dwords, size);
3063                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3064                                   nverts, track->vtx_size);
3065                         return -EINVAL;
3066                 }
3067                 break;
3068         default:
3069                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3070                           prim_walk);
3071                 return -EINVAL;
3072         }
3073         return r100_cs_track_texture_check(rdev, track);
3074 }
3075
3076 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3077 {
3078         unsigned i, face;
3079
3080         if (rdev->family < CHIP_R300) {
3081                 track->num_cb = 1;
3082                 if (rdev->family <= CHIP_RS200)
3083                         track->num_texture = 3;
3084                 else
3085                         track->num_texture = 6;
3086                 track->maxy = 2048;
3087                 track->separate_cube = 1;
3088         } else {
3089                 track->num_cb = 4;
3090                 track->num_texture = 16;
3091                 track->maxy = 4096;
3092                 track->separate_cube = 0;
3093         }
3094
3095         for (i = 0; i < track->num_cb; i++) {
3096                 track->cb[i].robj = NULL;
3097                 track->cb[i].pitch = 8192;
3098                 track->cb[i].cpp = 16;
3099                 track->cb[i].offset = 0;
3100         }
3101         track->z_enabled = true;
3102         track->zb.robj = NULL;
3103         track->zb.pitch = 8192;
3104         track->zb.cpp = 4;
3105         track->zb.offset = 0;
3106         track->vtx_size = 0x7F;
3107         track->immd_dwords = 0xFFFFFFFFUL;
3108         track->num_arrays = 11;
3109         track->max_indx = 0x00FFFFFFUL;
3110         for (i = 0; i < track->num_arrays; i++) {
3111                 track->arrays[i].robj = NULL;
3112                 track->arrays[i].esize = 0x7F;
3113         }
3114         for (i = 0; i < track->num_texture; i++) {
3115                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3116                 track->textures[i].pitch = 16536;
3117                 track->textures[i].width = 16536;
3118                 track->textures[i].height = 16536;
3119                 track->textures[i].width_11 = 1 << 11;
3120                 track->textures[i].height_11 = 1 << 11;
3121                 track->textures[i].num_levels = 12;
3122                 if (rdev->family <= CHIP_RS200) {
3123                         track->textures[i].tex_coord_type = 0;
3124                         track->textures[i].txdepth = 0;
3125                 } else {
3126                         track->textures[i].txdepth = 16;
3127                         track->textures[i].tex_coord_type = 1;
3128                 }
3129                 track->textures[i].cpp = 64;
3130                 track->textures[i].robj = NULL;
3131                 /* CS IB emission code makes sure texture unit are disabled */
3132                 track->textures[i].enabled = false;
3133                 track->textures[i].roundup_w = true;
3134                 track->textures[i].roundup_h = true;
3135                 if (track->separate_cube)
3136                         for (face = 0; face < 5; face++) {
3137                                 track->textures[i].cube_info[face].robj = NULL;
3138                                 track->textures[i].cube_info[face].width = 16536;
3139                                 track->textures[i].cube_info[face].height = 16536;
3140                                 track->textures[i].cube_info[face].offset = 0;
3141                         }
3142         }
3143 }
3144
3145 int r100_ring_test(struct radeon_device *rdev)
3146 {
3147         uint32_t scratch;
3148         uint32_t tmp = 0;
3149         unsigned i;
3150         int r;
3151
3152         r = radeon_scratch_get(rdev, &scratch);
3153         if (r) {
3154                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3155                 return r;
3156         }
3157         WREG32(scratch, 0xCAFEDEAD);
3158         r = radeon_ring_lock(rdev, 2);
3159         if (r) {
3160                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3161                 radeon_scratch_free(rdev, scratch);
3162                 return r;
3163         }
3164         radeon_ring_write(rdev, PACKET0(scratch, 0));
3165         radeon_ring_write(rdev, 0xDEADBEEF);
3166         radeon_ring_unlock_commit(rdev);
3167         for (i = 0; i < rdev->usec_timeout; i++) {
3168                 tmp = RREG32(scratch);
3169                 if (tmp == 0xDEADBEEF) {
3170                         break;
3171                 }
3172                 DRM_UDELAY(1);
3173         }
3174         if (i < rdev->usec_timeout) {
3175                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3176         } else {
3177                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3178                           scratch, tmp);
3179                 r = -EINVAL;
3180         }
3181         radeon_scratch_free(rdev, scratch);
3182         return r;
3183 }
3184
3185 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3186 {
3187         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3188         radeon_ring_write(rdev, ib->gpu_addr);
3189         radeon_ring_write(rdev, ib->length_dw);
3190 }
3191
3192 int r100_ib_test(struct radeon_device *rdev)
3193 {
3194         struct radeon_ib *ib;
3195         uint32_t scratch;
3196         uint32_t tmp = 0;
3197         unsigned i;
3198         int r;
3199
3200         r = radeon_scratch_get(rdev, &scratch);
3201         if (r) {
3202                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3203                 return r;
3204         }
3205         WREG32(scratch, 0xCAFEDEAD);
3206         r = radeon_ib_get(rdev, &ib);
3207         if (r) {
3208                 return r;
3209         }
3210         ib->ptr[0] = PACKET0(scratch, 0);
3211         ib->ptr[1] = 0xDEADBEEF;
3212         ib->ptr[2] = PACKET2(0);
3213         ib->ptr[3] = PACKET2(0);
3214         ib->ptr[4] = PACKET2(0);
3215         ib->ptr[5] = PACKET2(0);
3216         ib->ptr[6] = PACKET2(0);
3217         ib->ptr[7] = PACKET2(0);
3218         ib->length_dw = 8;
3219         r = radeon_ib_schedule(rdev, ib);
3220         if (r) {
3221                 radeon_scratch_free(rdev, scratch);
3222                 radeon_ib_free(rdev, &ib);
3223                 return r;
3224         }
3225         r = radeon_fence_wait(ib->fence, false);
3226         if (r) {
3227                 return r;
3228         }
3229         for (i = 0; i < rdev->usec_timeout; i++) {
3230                 tmp = RREG32(scratch);
3231                 if (tmp == 0xDEADBEEF) {
3232                         break;
3233                 }
3234                 DRM_UDELAY(1);
3235         }
3236         if (i < rdev->usec_timeout) {
3237                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3238         } else {
3239                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3240                           scratch, tmp);
3241                 r = -EINVAL;
3242         }
3243         radeon_scratch_free(rdev, scratch);
3244         radeon_ib_free(rdev, &ib);
3245         return r;
3246 }
3247
3248 void r100_ib_fini(struct radeon_device *rdev)
3249 {
3250         radeon_ib_pool_fini(rdev);
3251 }
3252
3253 int r100_ib_init(struct radeon_device *rdev)
3254 {
3255         int r;
3256
3257         r = radeon_ib_pool_init(rdev);
3258         if (r) {
3259                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3260                 r100_ib_fini(rdev);
3261                 return r;
3262         }
3263         r = r100_ib_test(rdev);
3264         if (r) {
3265                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3266                 r100_ib_fini(rdev);
3267                 return r;
3268         }
3269         return 0;
3270 }
3271
3272 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3273 {
3274         /* Shutdown CP we shouldn't need to do that but better be safe than
3275          * sorry
3276          */
3277         rdev->cp.ready = false;
3278         WREG32(R_000740_CP_CSQ_CNTL, 0);
3279
3280         /* Save few CRTC registers */
3281         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3282         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3283         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3284         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3285         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3286                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3287                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3288         }
3289
3290         /* Disable VGA aperture access */
3291         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3292         /* Disable cursor, overlay, crtc */
3293         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3294         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3295                                         S_000054_CRTC_DISPLAY_DIS(1));
3296         WREG32(R_000050_CRTC_GEN_CNTL,
3297                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3298                         S_000050_CRTC_DISP_REQ_EN_B(1));
3299         WREG32(R_000420_OV0_SCALE_CNTL,
3300                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3301         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3302         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3303                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3304                                                 S_000360_CUR2_LOCK(1));
3305                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3306                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3307                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3308                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3309                 WREG32(R_000360_CUR2_OFFSET,
3310                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3311         }
3312 }
3313
3314 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3315 {
3316         /* Update base address for crtc */
3317         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3318         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3319                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3320         }
3321         /* Restore CRTC registers */
3322         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3323         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3324         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3325         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3326                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3327         }
3328 }
3329
3330 void r100_vga_render_disable(struct radeon_device *rdev)
3331 {
3332         u32 tmp;
3333
3334         tmp = RREG8(R_0003C2_GENMO_WT);
3335         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3336 }
3337
3338 static void r100_debugfs(struct radeon_device *rdev)
3339 {
3340         int r;
3341
3342         r = r100_debugfs_mc_info_init(rdev);
3343         if (r)
3344                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3345 }
3346
3347 static void r100_mc_program(struct radeon_device *rdev)
3348 {
3349         struct r100_mc_save save;
3350
3351         /* Stops all mc clients */
3352         r100_mc_stop(rdev, &save);
3353         if (rdev->flags & RADEON_IS_AGP) {
3354                 WREG32(R_00014C_MC_AGP_LOCATION,
3355                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3356                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3357                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3358                 if (rdev->family > CHIP_RV200)
3359                         WREG32(R_00015C_AGP_BASE_2,
3360                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3361         } else {
3362                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3363                 WREG32(R_000170_AGP_BASE, 0);
3364                 if (rdev->family > CHIP_RV200)
3365                         WREG32(R_00015C_AGP_BASE_2, 0);
3366         }
3367         /* Wait for mc idle */
3368         if (r100_mc_wait_for_idle(rdev))
3369                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3370         /* Program MC, should be a 32bits limited address space */
3371         WREG32(R_000148_MC_FB_LOCATION,
3372                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3373                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3374         r100_mc_resume(rdev, &save);
3375 }
3376
3377 void r100_clock_startup(struct radeon_device *rdev)
3378 {
3379         u32 tmp;
3380
3381         if (radeon_dynclks != -1 && radeon_dynclks)
3382                 radeon_legacy_set_clock_gating(rdev, 1);
3383         /* We need to force on some of the block */
3384         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3385         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3386         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3387                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3388         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3389 }
3390
3391 static int r100_startup(struct radeon_device *rdev)
3392 {
3393         int r;
3394
3395         /* set common regs */
3396         r100_set_common_regs(rdev);
3397         /* program mc */
3398         r100_mc_program(rdev);
3399         /* Resume clock */
3400         r100_clock_startup(rdev);
3401         /* Initialize GPU configuration (# pipes, ...) */
3402         r100_gpu_init(rdev);
3403         /* Initialize GART (initialize after TTM so we can allocate
3404          * memory through TTM but finalize after TTM) */
3405         r100_enable_bm(rdev);
3406         if (rdev->flags & RADEON_IS_PCI) {
3407                 r = r100_pci_gart_enable(rdev);
3408                 if (r)
3409                         return r;
3410         }
3411         /* Enable IRQ */
3412         r100_irq_set(rdev);
3413         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3414         /* 1M ring buffer */
3415         r = r100_cp_init(rdev, 1024 * 1024);
3416         if (r) {
3417                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3418                 return r;
3419         }
3420         r = r100_wb_init(rdev);
3421         if (r)
3422                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3423         r = r100_ib_init(rdev);
3424         if (r) {
3425                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3426                 return r;
3427         }
3428         return 0;
3429 }
3430
3431 int r100_resume(struct radeon_device *rdev)
3432 {
3433         /* Make sur GART are not working */
3434         if (rdev->flags & RADEON_IS_PCI)
3435                 r100_pci_gart_disable(rdev);
3436         /* Resume clock before doing reset */
3437         r100_clock_startup(rdev);
3438         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3439         if (radeon_gpu_reset(rdev)) {
3440                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3441                         RREG32(R_000E40_RBBM_STATUS),
3442                         RREG32(R_0007C0_CP_STAT));
3443         }
3444         /* post */
3445         radeon_combios_asic_init(rdev->ddev);
3446         /* Resume clock after posting */
3447         r100_clock_startup(rdev);
3448         /* Initialize surface registers */
3449         radeon_surface_init(rdev);
3450         return r100_startup(rdev);
3451 }
3452
3453 int r100_suspend(struct radeon_device *rdev)
3454 {
3455         r100_cp_disable(rdev);
3456         r100_wb_disable(rdev);
3457         r100_irq_disable(rdev);
3458         if (rdev->flags & RADEON_IS_PCI)
3459                 r100_pci_gart_disable(rdev);
3460         return 0;
3461 }
3462
3463 void r100_fini(struct radeon_device *rdev)
3464 {
3465         radeon_pm_fini(rdev);
3466         r100_cp_fini(rdev);
3467         r100_wb_fini(rdev);
3468         r100_ib_fini(rdev);
3469         radeon_gem_fini(rdev);
3470         if (rdev->flags & RADEON_IS_PCI)
3471                 r100_pci_gart_fini(rdev);
3472         radeon_agp_fini(rdev);
3473         radeon_irq_kms_fini(rdev);
3474         radeon_fence_driver_fini(rdev);
3475         radeon_bo_fini(rdev);
3476         radeon_atombios_fini(rdev);
3477         kfree(rdev->bios);
3478         rdev->bios = NULL;
3479 }
3480
3481 int r100_init(struct radeon_device *rdev)
3482 {
3483         int r;
3484
3485         /* Register debugfs file specific to this group of asics */
3486         r100_debugfs(rdev);
3487         /* Disable VGA */
3488         r100_vga_render_disable(rdev);
3489         /* Initialize scratch registers */
3490         radeon_scratch_init(rdev);
3491         /* Initialize surface registers */
3492         radeon_surface_init(rdev);
3493         /* TODO: disable VGA need to use VGA request */
3494         /* BIOS*/
3495         if (!radeon_get_bios(rdev)) {
3496                 if (ASIC_IS_AVIVO(rdev))
3497                         return -EINVAL;
3498         }
3499         if (rdev->is_atom_bios) {
3500                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3501                 return -EINVAL;
3502         } else {
3503                 r = radeon_combios_init(rdev);
3504                 if (r)
3505                         return r;
3506         }
3507         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3508         if (radeon_gpu_reset(rdev)) {
3509                 dev_warn(rdev->dev,
3510                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3511                         RREG32(R_000E40_RBBM_STATUS),
3512                         RREG32(R_0007C0_CP_STAT));
3513         }
3514         /* check if cards are posted or not */
3515         if (radeon_boot_test_post_card(rdev) == false)
3516                 return -EINVAL;
3517         /* Set asic errata */
3518         r100_errata(rdev);
3519         /* Initialize clocks */
3520         radeon_get_clock_info(rdev->ddev);
3521         /* Initialize power management */
3522         radeon_pm_init(rdev);
3523         /* initialize AGP */
3524         if (rdev->flags & RADEON_IS_AGP) {
3525                 r = radeon_agp_init(rdev);
3526                 if (r) {
3527                         radeon_agp_disable(rdev);
3528                 }
3529         }
3530         /* initialize VRAM */
3531         r100_mc_init(rdev);
3532         /* Fence driver */
3533         r = radeon_fence_driver_init(rdev);
3534         if (r)
3535                 return r;
3536         r = radeon_irq_kms_init(rdev);
3537         if (r)
3538                 return r;
3539         /* Memory manager */
3540         r = radeon_bo_init(rdev);
3541         if (r)
3542                 return r;
3543         if (rdev->flags & RADEON_IS_PCI) {
3544                 r = r100_pci_gart_init(rdev);
3545                 if (r)
3546                         return r;
3547         }
3548         r100_set_safe_registers(rdev);
3549         rdev->accel_working = true;
3550         r = r100_startup(rdev);
3551         if (r) {
3552                 /* Somethings want wront with the accel init stop accel */
3553                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3554                 r100_cp_fini(rdev);
3555                 r100_wb_fini(rdev);
3556                 r100_ib_fini(rdev);
3557                 radeon_irq_kms_fini(rdev);
3558                 if (rdev->flags & RADEON_IS_PCI)
3559                         r100_pci_gart_fini(rdev);
3560                 rdev->accel_working = false;
3561         }
3562         return 0;
3563 }