drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_microcode.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35
  36 /* This files gather functions specifics to:
  37  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  38  *
  39  * Some of these functions might be used by newer ASICs.
  40  */
  41 void r100_hdp_reset(struct radeon_device *rdev);
  42 void r100_gpu_init(struct radeon_device *rdev);
  43 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  44 int r100_mc_wait_for_idle(struct radeon_device *rdev);
  45 void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
  46 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
  47 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  48
  49
  50 /*
  51  * PCI GART
  52  */
  53 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  54 {
  55         /* TODO: can we do somethings here ? */
  56         /* It seems hw only cache one entry so we should discard this
  57          * entry otherwise if first GPU GART read hit this entry it
  58          * could end up in wrong address. */
  59 }
  60
  61 int r100_pci_gart_enable(struct radeon_device *rdev)
  62 {
  63         uint32_t tmp;
  64         int r;
  65
  66         /* Initialize common gart structure */
  67         r = radeon_gart_init(rdev);
  68         if (r) {
  69                 return r;
  70         }
  71         if (rdev->gart.table.ram.ptr == NULL) {
  72                 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  73                 r = radeon_gart_table_ram_alloc(rdev);
  74                 if (r) {
  75                         return r;
  76                 }
  77         }
  78         /* discard memory request outside of configured range */
  79         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  80         WREG32(RADEON_AIC_CNTL, tmp);
  81         /* set address range for PCI address translate */
  82         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
  83         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  84         WREG32(RADEON_AIC_HI_ADDR, tmp);
  85         /* Enable bus mastering */
  86         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  87         WREG32(RADEON_BUS_CNTL, tmp);
  88         /* set PCI GART page-table base address */
  89         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
  90         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
  91         WREG32(RADEON_AIC_CNTL, tmp);
  92         r100_pci_gart_tlb_flush(rdev);
  93         rdev->gart.ready = true;
  94         return 0;
  95 }
  96
  97 void r100_pci_gart_disable(struct radeon_device *rdev)
  98 {
  99         uint32_t tmp;
 100
 101         /* discard memory request outside of configured range */
 102         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 103         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 104         WREG32(RADEON_AIC_LO_ADDR, 0);
 105         WREG32(RADEON_AIC_HI_ADDR, 0);
 106 }
 107
 108 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 109 {
 110         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 111                 return -EINVAL;
 112         }
 113         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 114         return 0;
 115 }
 116
 117 int r100_gart_enable(struct radeon_device *rdev)
 118 {
 119         if (rdev->flags & RADEON_IS_AGP) {
 120                 r100_pci_gart_disable(rdev);
 121                 return 0;
 122         }
 123         return r100_pci_gart_enable(rdev);
 124 }
 125
 126
 127 /*
 128  * MC
 129  */
 130 void r100_mc_disable_clients(struct radeon_device *rdev)
 131 {
 132         uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
 133
 134         /* FIXME: is this function correct for rs100,rs200,rs300 ? */
 135         if (r100_gui_wait_for_idle(rdev)) {
 136                 printk(KERN_WARNING "Failed to wait GUI idle while "
 137                        "programming pipes. Bad things might happen.\n");
 138         }
 139
 140         /* stop display and memory access */
 141         ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
 142         WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
 143         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 144         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
 145         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 146
 147         r100_gpu_wait_for_vsync(rdev);
 148
 149         WREG32(RADEON_CRTC_GEN_CNTL,
 150                (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
 151                RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
 152
 153         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 154                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 155
 156                 r100_gpu_wait_for_vsync2(rdev);
 157                 WREG32(RADEON_CRTC2_GEN_CNTL,
 158                        (crtc2_gen_cntl &
 159                         ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
 160                        RADEON_CRTC2_DISP_REQ_EN_B);
 161         }
 162
 163         udelay(500);
 164 }
 165
 166 void r100_mc_setup(struct radeon_device *rdev)
 167 {
 168         uint32_t tmp;
 169         int r;
 170
 171         r = r100_debugfs_mc_info_init(rdev);
 172         if (r) {
 173                 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
 174         }
 175         /* Write VRAM size in case we are limiting it */
 176         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 177         /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
 178          * if the aperture is 64MB but we have 32MB VRAM
 179          * we report only 32MB VRAM but we have to set MC_FB_LOCATION
 180          * to 64MB, otherwise the gpu accidentially dies */
 181         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 182         tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
 183         tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
 184         WREG32(RADEON_MC_FB_LOCATION, tmp);
 185
 186         /* Enable bus mastering */
 187         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 188         WREG32(RADEON_BUS_CNTL, tmp);
 189
 190         if (rdev->flags & RADEON_IS_AGP) {
 191                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 192                 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
 193                 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
 194                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 195                 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
 196         } else {
 197                 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
 198                 WREG32(RADEON_AGP_BASE, 0);
 199         }
 200
 201         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
 202         tmp |= (7 << 28);
 203         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
 204         (void)RREG32(RADEON_HOST_PATH_CNTL);
 205         WREG32(RADEON_HOST_PATH_CNTL, tmp);
 206         (void)RREG32(RADEON_HOST_PATH_CNTL);
 207 }
 208
 209 int r100_mc_init(struct radeon_device *rdev)
 210 {
 211         int r;
 212
 213         if (r100_debugfs_rbbm_init(rdev)) {
 214                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 215         }
 216
 217         r100_gpu_init(rdev);
 218         /* Disable gart which also disable out of gart access */
 219         r100_pci_gart_disable(rdev);
 220
 221         /* Setup GPU memory space */
 222         rdev->mc.gtt_location = 0xFFFFFFFFUL;
 223         if (rdev->flags & RADEON_IS_AGP) {
 224                 r = radeon_agp_init(rdev);
 225                 if (r) {
 226                         printk(KERN_WARNING "[drm] Disabling AGP\n");
 227                         rdev->flags &= ~RADEON_IS_AGP;
 228                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 229                 } else {
 230                         rdev->mc.gtt_location = rdev->mc.agp_base;
 231                 }
 232         }
 233         r = radeon_mc_setup(rdev);
 234         if (r) {
 235                 return r;
 236         }
 237
 238         r100_mc_disable_clients(rdev);
 239         if (r100_mc_wait_for_idle(rdev)) {
 240                 printk(KERN_WARNING "Failed to wait MC idle while "
 241                        "programming pipes. Bad things might happen.\n");
 242         }
 243
 244         r100_mc_setup(rdev);
 245         return 0;
 246 }
 247
 248 void r100_mc_fini(struct radeon_device *rdev)
 249 {
 250         r100_pci_gart_disable(rdev);
 251         radeon_gart_table_ram_free(rdev);
 252         radeon_gart_fini(rdev);
 253 }
 254
 255
 256 /*
 257  * Interrupts
 258  */
 259 int r100_irq_set(struct radeon_device *rdev)
 260 {
 261         uint32_t tmp = 0;
 262
 263         if (rdev->irq.sw_int) {
 264                 tmp |= RADEON_SW_INT_ENABLE;
 265         }
 266         if (rdev->irq.crtc_vblank_int[0]) {
 267                 tmp |= RADEON_CRTC_VBLANK_MASK;
 268         }
 269         if (rdev->irq.crtc_vblank_int[1]) {
 270                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 271         }
 272         WREG32(RADEON_GEN_INT_CNTL, tmp);
 273         return 0;
 274 }
 275
 276 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 277 {
 278         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 279         uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
 280                 RADEON_CRTC2_VBLANK_STAT;
 281
 282         if (irqs) {
 283                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 284         }
 285         return irqs & irq_mask;
 286 }
 287
 288 int r100_irq_process(struct radeon_device *rdev)
 289 {
 290         uint32_t status;
 291
 292         status = r100_irq_ack(rdev);
 293         if (!status) {
 294                 return IRQ_NONE;
 295         }
 296         while (status) {
 297                 /* SW interrupt */
 298                 if (status & RADEON_SW_INT_TEST) {
 299                         radeon_fence_process(rdev);
 300                 }
 301                 /* Vertical blank interrupts */
 302                 if (status & RADEON_CRTC_VBLANK_STAT) {
 303                         drm_handle_vblank(rdev->ddev, 0);
 304                 }
 305                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 306                         drm_handle_vblank(rdev->ddev, 1);
 307                 }
 308                 status = r100_irq_ack(rdev);
 309         }
 310         return IRQ_HANDLED;
 311 }
 312
 313 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 314 {
 315         if (crtc == 0)
 316                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 317         else
 318                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 319 }
 320
 321
 322 /*
 323  * Fence emission
 324  */
 325 void r100_fence_ring_emit(struct radeon_device *rdev,
 326                           struct radeon_fence *fence)
 327 {
 328         /* Who ever call radeon_fence_emit should call ring_lock and ask
 329          * for enough space (today caller are ib schedule and buffer move) */
 330         /* Wait until IDLE & CLEAN */
 331         radeon_ring_write(rdev, PACKET0(0x1720, 0));
 332         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
 333         /* Emit fence sequence & fire IRQ */
 334         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 335         radeon_ring_write(rdev, fence->seq);
 336         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 337         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 338 }
 339
 340
 341 /*
 342  * Writeback
 343  */
 344 int r100_wb_init(struct radeon_device *rdev)
 345 {
 346         int r;
 347
 348         if (rdev->wb.wb_obj == NULL) {
 349                 r = radeon_object_create(rdev, NULL, 4096,
 350                                          true,
 351                                          RADEON_GEM_DOMAIN_GTT,
 352                                          false, &rdev->wb.wb_obj);
 353                 if (r) {
 354                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
 355                         return r;
 356                 }
 357                 r = radeon_object_pin(rdev->wb.wb_obj,
 358                                       RADEON_GEM_DOMAIN_GTT,
 359                                       &rdev->wb.gpu_addr);
 360                 if (r) {
 361                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
 362                         return r;
 363                 }
 364                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 365                 if (r) {
 366                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
 367                         return r;
 368                 }
 369         }
 370         WREG32(0x774, rdev->wb.gpu_addr);
 371         WREG32(0x70C, rdev->wb.gpu_addr + 1024);
 372         WREG32(0x770, 0xff);
 373         return 0;
 374 }
 375
 376 void r100_wb_fini(struct radeon_device *rdev)
 377 {
 378         if (rdev->wb.wb_obj) {
 379                 radeon_object_kunmap(rdev->wb.wb_obj);
 380                 radeon_object_unpin(rdev->wb.wb_obj);
 381                 radeon_object_unref(&rdev->wb.wb_obj);
 382                 rdev->wb.wb = NULL;
 383                 rdev->wb.wb_obj = NULL;
 384         }
 385 }
 386
 387 int r100_copy_blit(struct radeon_device *rdev,
 388                    uint64_t src_offset,
 389                    uint64_t dst_offset,
 390                    unsigned num_pages,
 391                    struct radeon_fence *fence)
 392 {
 393         uint32_t cur_pages;
 394         uint32_t stride_bytes = PAGE_SIZE;
 395         uint32_t pitch;
 396         uint32_t stride_pixels;
 397         unsigned ndw;
 398         int num_loops;
 399         int r = 0;
 400
 401         /* radeon limited to 16k stride */
 402         stride_bytes &= 0x3fff;
 403         /* radeon pitch is /64 */
 404         pitch = stride_bytes / 64;
 405         stride_pixels = stride_bytes / 4;
 406         num_loops = DIV_ROUND_UP(num_pages, 8191);
 407
 408         /* Ask for enough room for blit + flush + fence */
 409         ndw = 64 + (10 * num_loops);
 410         r = radeon_ring_lock(rdev, ndw);
 411         if (r) {
 412                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 413                 return -EINVAL;
 414         }
 415         while (num_pages > 0) {
 416                 cur_pages = num_pages;
 417                 if (cur_pages > 8191) {
 418                         cur_pages = 8191;
 419                 }
 420                 num_pages -= cur_pages;
 421
 422                 /* pages are in Y direction - height
 423                    page width in X direction - width */
 424                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 425                 radeon_ring_write(rdev,
 426                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 427                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 428                                   RADEON_GMC_SRC_CLIPPING |
 429                                   RADEON_GMC_DST_CLIPPING |
 430                                   RADEON_GMC_BRUSH_NONE |
 431                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 432                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 433                                   RADEON_ROP3_S |
 434                                   RADEON_DP_SRC_SOURCE_MEMORY |
 435                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 436                                   RADEON_GMC_WR_MSK_DIS);
 437                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 438                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 439                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 440                 radeon_ring_write(rdev, 0);
 441                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 442                 radeon_ring_write(rdev, num_pages);
 443                 radeon_ring_write(rdev, num_pages);
 444                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 445         }
 446         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 447         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 448         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 449         radeon_ring_write(rdev,
 450                           RADEON_WAIT_2D_IDLECLEAN |
 451                           RADEON_WAIT_HOST_IDLECLEAN |
 452                           RADEON_WAIT_DMA_GUI_IDLE);
 453         if (fence) {
 454                 r = radeon_fence_emit(rdev, fence);
 455         }
 456         radeon_ring_unlock_commit(rdev);
 457         return r;
 458 }
 459
 460
 461 /*
 462  * CP
 463  */
 464 void r100_ring_start(struct radeon_device *rdev)
 465 {
 466         int r;
 467
 468         r = radeon_ring_lock(rdev, 2);
 469         if (r) {
 470                 return;
 471         }
 472         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 473         radeon_ring_write(rdev,
 474                           RADEON_ISYNC_ANY2D_IDLE3D |
 475                           RADEON_ISYNC_ANY3D_IDLE2D |
 476                           RADEON_ISYNC_WAIT_IDLEGUI |
 477                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 478         radeon_ring_unlock_commit(rdev);
 479 }
 480
 481 static void r100_cp_load_microcode(struct radeon_device *rdev)
 482 {
 483         int i;
 484
 485         if (r100_gui_wait_for_idle(rdev)) {
 486                 printk(KERN_WARNING "Failed to wait GUI idle while "
 487                        "programming pipes. Bad things might happen.\n");
 488         }
 489
 490         WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 491         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 492             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 493             (rdev->family == CHIP_RS200)) {
 494                 DRM_INFO("Loading R100 Microcode\n");
 495                 for (i = 0; i < 256; i++) {
 496                         WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
 497                         WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
 498                 }
 499         } else if ((rdev->family == CHIP_R200) ||
 500                    (rdev->family == CHIP_RV250) ||
 501                    (rdev->family == CHIP_RV280) ||
 502                    (rdev->family == CHIP_RS300)) {
 503                 DRM_INFO("Loading R200 Microcode\n");
 504                 for (i = 0; i < 256; i++) {
 505                         WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
 506                         WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
 507                 }
 508         } else if ((rdev->family == CHIP_R300) ||
 509                    (rdev->family == CHIP_R350) ||
 510                    (rdev->family == CHIP_RV350) ||
 511                    (rdev->family == CHIP_RV380) ||
 512                    (rdev->family == CHIP_RS400) ||
 513                    (rdev->family == CHIP_RS480)) {
 514                 DRM_INFO("Loading R300 Microcode\n");
 515                 for (i = 0; i < 256; i++) {
 516                         WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
 517                         WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
 518                 }
 519         } else if ((rdev->family == CHIP_R420) ||
 520                    (rdev->family == CHIP_R423) ||
 521                    (rdev->family == CHIP_RV410)) {
 522                 DRM_INFO("Loading R400 Microcode\n");
 523                 for (i = 0; i < 256; i++) {
 524                         WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
 525                         WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
 526                 }
 527         } else if ((rdev->family == CHIP_RS690) ||
 528                    (rdev->family == CHIP_RS740)) {
 529                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 530                 for (i = 0; i < 256; i++) {
 531                         WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
 532                         WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
 533                 }
 534         } else if (rdev->family == CHIP_RS600) {
 535                 DRM_INFO("Loading RS600 Microcode\n");
 536                 for (i = 0; i < 256; i++) {
 537                         WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
 538                         WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
 539                 }
 540         } else if ((rdev->family == CHIP_RV515) ||
 541                    (rdev->family == CHIP_R520) ||
 542                    (rdev->family == CHIP_RV530) ||
 543                    (rdev->family == CHIP_R580) ||
 544                    (rdev->family == CHIP_RV560) ||
 545                    (rdev->family == CHIP_RV570)) {
 546                 DRM_INFO("Loading R500 Microcode\n");
 547                 for (i = 0; i < 256; i++) {
 548                         WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
 549                         WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
 550                 }
 551         }
 552 }
 553
 554 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 555 {
 556         unsigned rb_bufsz;
 557         unsigned rb_blksz;
 558         unsigned max_fetch;
 559         unsigned pre_write_timer;
 560         unsigned pre_write_limit;
 561         unsigned indirect2_start;
 562         unsigned indirect1_start;
 563         uint32_t tmp;
 564         int r;
 565
 566         if (r100_debugfs_cp_init(rdev)) {
 567                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 568         }
 569         /* Reset CP */
 570         tmp = RREG32(RADEON_CP_CSQ_STAT);
 571         if ((tmp & (1 << 31))) {
 572                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 573                 WREG32(RADEON_CP_CSQ_MODE, 0);
 574                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 575                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 576                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 577                 mdelay(2);
 578                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 579                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 580                 mdelay(2);
 581                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 582                 if ((tmp & (1 << 31))) {
 583                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 584                 }
 585         } else {
 586                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 587         }
 588         /* Align ring size */
 589         rb_bufsz = drm_order(ring_size / 8);
 590         ring_size = (1 << (rb_bufsz + 1)) * 4;
 591         r100_cp_load_microcode(rdev);
 592         r = radeon_ring_init(rdev, ring_size);
 593         if (r) {
 594                 return r;
 595         }
 596         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 597          * the rptr copy in system ram */
 598         rb_blksz = 9;
 599         /* cp will read 128bytes at a time (4 dwords) */
 600         max_fetch = 1;
 601         rdev->cp.align_mask = 16 - 1;
 602         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 603         pre_write_timer = 64;
 604         /* Force CP_RB_WPTR write if written more than one time before the
 605          * delay expire
 606          */
 607         pre_write_limit = 0;
 608         /* Setup the cp cache like this (cache size is 96 dwords) :
 609          *      RING            0  to 15
 610          *      INDIRECT1       16 to 79
 611          *      INDIRECT2       80 to 95
 612          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 613          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 614          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 615          * Idea being that most of the gpu cmd will be through indirect1 buffer
 616          * so it gets the bigger cache.
 617          */
 618         indirect2_start = 80;
 619         indirect1_start = 16;
 620         /* cp setup */
 621         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 622         WREG32(RADEON_CP_RB_CNTL,
 623 #ifdef __BIG_ENDIAN
 624                RADEON_BUF_SWAP_32BIT |
 625 #endif
 626                REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 627                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 628                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 629                RADEON_RB_NO_UPDATE);
 630         /* Set ring address */
 631         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 632         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 633         /* Force read & write ptr to 0 */
 634         tmp = RREG32(RADEON_CP_RB_CNTL);
 635         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 636         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 637         WREG32(RADEON_CP_RB_WPTR, 0);
 638         WREG32(RADEON_CP_RB_CNTL, tmp);
 639         udelay(10);
 640         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 641         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 642         /* Set cp mode to bus mastering & enable cp*/
 643         WREG32(RADEON_CP_CSQ_MODE,
 644                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 645                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 646         WREG32(0x718, 0);
 647         WREG32(0x744, 0x00004D4D);
 648         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 649         radeon_ring_start(rdev);
 650         r = radeon_ring_test(rdev);
 651         if (r) {
 652                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 653                 return r;
 654         }
 655         rdev->cp.ready = true;
 656         return 0;
 657 }
 658
 659 void r100_cp_fini(struct radeon_device *rdev)
 660 {
 661         /* Disable ring */
 662         rdev->cp.ready = false;
 663         WREG32(RADEON_CP_CSQ_CNTL, 0);
 664         radeon_ring_fini(rdev);
 665         DRM_INFO("radeon: cp finalized\n");
 666 }
 667
 668 void r100_cp_disable(struct radeon_device *rdev)
 669 {
 670         /* Disable ring */
 671         rdev->cp.ready = false;
 672         WREG32(RADEON_CP_CSQ_MODE, 0);
 673         WREG32(RADEON_CP_CSQ_CNTL, 0);
 674         if (r100_gui_wait_for_idle(rdev)) {
 675                 printk(KERN_WARNING "Failed to wait GUI idle while "
 676                        "programming pipes. Bad things might happen.\n");
 677         }
 678 }
 679
 680 int r100_cp_reset(struct radeon_device *rdev)
 681 {
 682         uint32_t tmp;
 683         bool reinit_cp;
 684         int i;
 685
 686         reinit_cp = rdev->cp.ready;
 687         rdev->cp.ready = false;
 688         WREG32(RADEON_CP_CSQ_MODE, 0);
 689         WREG32(RADEON_CP_CSQ_CNTL, 0);
 690         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 691         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 692         udelay(200);
 693         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 694         /* Wait to prevent race in RBBM_STATUS */
 695         mdelay(1);
 696         for (i = 0; i < rdev->usec_timeout; i++) {
 697                 tmp = RREG32(RADEON_RBBM_STATUS);
 698                 if (!(tmp & (1 << 16))) {
 699                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 700                                  tmp);
 701                         if (reinit_cp) {
 702                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 703                         }
 704                         return 0;
 705                 }
 706                 DRM_UDELAY(1);
 707         }
 708         tmp = RREG32(RADEON_RBBM_STATUS);
 709         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 710         return -1;
 711 }
 712
 713
 714 /*
 715  * CS functions
 716  */
 717 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 718                           struct radeon_cs_packet *pkt,
 719                           const unsigned *auth, unsigned n,
 720                           radeon_packet0_check_t check)
 721 {
 722         unsigned reg;
 723         unsigned i, j, m;
 724         unsigned idx;
 725         int r;
 726
 727         idx = pkt->idx + 1;
 728         reg = pkt->reg;
 729         /* Check that register fall into register range
 730          * determined by the number of entry (n) in the
 731          * safe register bitmap.
 732          */
 733         if (pkt->one_reg_wr) {
 734                 if ((reg >> 7) > n) {
 735                         return -EINVAL;
 736                 }
 737         } else {
 738                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 739                         return -EINVAL;
 740                 }
 741         }
 742         for (i = 0; i <= pkt->count; i++, idx++) {
 743                 j = (reg >> 7);
 744                 m = 1 << ((reg >> 2) & 31);
 745                 if (auth[j] & m) {
 746                         r = check(p, pkt, idx, reg);
 747                         if (r) {
 748                                 return r;
 749                         }
 750                 }
 751                 if (pkt->one_reg_wr) {
 752                         if (!(auth[j] & m)) {
 753                                 break;
 754                         }
 755                 } else {
 756                         reg += 4;
 757                 }
 758         }
 759         return 0;
 760 }
 761
 762 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 763                          struct radeon_cs_packet *pkt)
 764 {
 765         struct radeon_cs_chunk *ib_chunk;
 766         volatile uint32_t *ib;
 767         unsigned i;
 768         unsigned idx;
 769
 770         ib = p->ib->ptr;
 771         ib_chunk = &p->chunks[p->chunk_ib_idx];
 772         idx = pkt->idx;
 773         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 774                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 775         }
 776 }
 777
 778 /**
 779  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 780  * @parser:     parser structure holding parsing context.
 781  * @pkt:        where to store packet informations
 782  *
 783  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 784  * if packet is bigger than remaining ib size. or if packets is unknown.
 785  **/
 786 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 787                          struct radeon_cs_packet *pkt,
 788                          unsigned idx)
 789 {
 790         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 791         uint32_t header;
 792
 793         if (idx >= ib_chunk->length_dw) {
 794                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 795                           idx, ib_chunk->length_dw);
 796                 return -EINVAL;
 797         }
 798         header = ib_chunk->kdata[idx];
 799         pkt->idx = idx;
 800         pkt->type = CP_PACKET_GET_TYPE(header);
 801         pkt->count = CP_PACKET_GET_COUNT(header);
 802         switch (pkt->type) {
 803         case PACKET_TYPE0:
 804                 pkt->reg = CP_PACKET0_GET_REG(header);
 805                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 806                 break;
 807         case PACKET_TYPE3:
 808                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 809                 break;
 810         case PACKET_TYPE2:
 811                 pkt->count = -1;
 812                 break;
 813         default:
 814                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 815                 return -EINVAL;
 816         }
 817         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 818                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 819                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 820                 return -EINVAL;
 821         }
 822         return 0;
 823 }
 824
 825 /**
 826  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 827  * @parser:             parser structure holding parsing context.
 828  *
 829  * Userspace sends a special sequence for VLINE waits.
 830  * PACKET0 - VLINE_START_END + value
 831  * PACKET0 - WAIT_UNTIL +_value
 832  * RELOC (P3) - crtc_id in reloc.
 833  *
 834  * This function parses this and relocates the VLINE START END
 835  * and WAIT UNTIL packets to the correct crtc.
 836  * It also detects a switched off crtc and nulls out the
 837  * wait in that case.
 838  */
 839 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 840 {
 841         struct radeon_cs_chunk *ib_chunk;
 842         struct drm_mode_object *obj;
 843         struct drm_crtc *crtc;
 844         struct radeon_crtc *radeon_crtc;
 845         struct radeon_cs_packet p3reloc, waitreloc;
 846         int crtc_id;
 847         int r;
 848         uint32_t header, h_idx, reg;
 849
 850         ib_chunk = &p->chunks[p->chunk_ib_idx];
 851
 852         /* parse the wait until */
 853         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 854         if (r)
 855                 return r;
 856
 857         /* check its a wait until and only 1 count */
 858         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 859             waitreloc.count != 0) {
 860                 DRM_ERROR("vline wait had illegal wait until segment\n");
 861                 r = -EINVAL;
 862                 return r;
 863         }
 864
 865         if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) {
 866                 DRM_ERROR("vline wait had illegal wait until\n");
 867                 r = -EINVAL;
 868                 return r;
 869         }
 870
 871         /* jump over the NOP */
 872         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 873         if (r)
 874                 return r;
 875
 876         h_idx = p->idx - 2;
 877         p->idx += waitreloc.count;
 878         p->idx += p3reloc.count;
 879
 880         header = ib_chunk->kdata[h_idx];
 881         crtc_id = ib_chunk->kdata[h_idx + 5];
 882         reg = ib_chunk->kdata[h_idx] >> 2;
 883         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 884         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 885         if (!obj) {
 886                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 887                 r = -EINVAL;
 888                 goto out;
 889         }
 890         crtc = obj_to_crtc(obj);
 891         radeon_crtc = to_radeon_crtc(crtc);
 892         crtc_id = radeon_crtc->crtc_id;
 893
 894         if (!crtc->enabled) {
 895                 /* if the CRTC isn't enabled - we need to nop out the wait until */
 896                 ib_chunk->kdata[h_idx + 2] = PACKET2(0);
 897                 ib_chunk->kdata[h_idx + 3] = PACKET2(0);
 898         } else if (crtc_id == 1) {
 899                 switch (reg) {
 900                 case AVIVO_D1MODE_VLINE_START_END:
 901                         header &= R300_CP_PACKET0_REG_MASK;
 902                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 903                         break;
 904                 case RADEON_CRTC_GUI_TRIG_VLINE:
 905                         header &= R300_CP_PACKET0_REG_MASK;
 906                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
 907                         break;
 908                 default:
 909                         DRM_ERROR("unknown crtc reloc\n");
 910                         r = -EINVAL;
 911                         goto out;
 912                 }
 913                 ib_chunk->kdata[h_idx] = header;
 914                 ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
 915         }
 916 out:
 917         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
 918         return r;
 919 }
 920
 921 /**
 922  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 923  * @parser:             parser structure holding parsing context.
 924  * @data:               pointer to relocation data
 925  * @offset_start:       starting offset
 926  * @offset_mask:        offset mask (to align start offset on)
 927  * @reloc:              reloc informations
 928  *
 929  * Check next packet is relocation packet3, do bo validation and compute
 930  * GPU offset using the provided start.
 931  **/
 932 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
 933                               struct radeon_cs_reloc **cs_reloc)
 934 {
 935         struct radeon_cs_chunk *ib_chunk;
 936         struct radeon_cs_chunk *relocs_chunk;
 937         struct radeon_cs_packet p3reloc;
 938         unsigned idx;
 939         int r;
 940
 941         if (p->chunk_relocs_idx == -1) {
 942                 DRM_ERROR("No relocation chunk !\n");
 943                 return -EINVAL;
 944         }
 945         *cs_reloc = NULL;
 946         ib_chunk = &p->chunks[p->chunk_ib_idx];
 947         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 948         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 949         if (r) {
 950                 return r;
 951         }
 952         p->idx += p3reloc.count + 2;
 953         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 954                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 955                           p3reloc.idx);
 956                 r100_cs_dump_packet(p, &p3reloc);
 957                 return -EINVAL;
 958         }
 959         idx = ib_chunk->kdata[p3reloc.idx + 1];
 960         if (idx >= relocs_chunk->length_dw) {
 961                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 962                           idx, relocs_chunk->length_dw);
 963                 r100_cs_dump_packet(p, &p3reloc);
 964                 return -EINVAL;
 965         }
 966         /* FIXME: we assume reloc size is 4 dwords */
 967         *cs_reloc = p->relocs_ptr[(idx / 4)];
 968         return 0;
 969 }
 970
 971 static int r100_packet0_check(struct radeon_cs_parser *p,
 972                               struct radeon_cs_packet *pkt)
 973 {
 974         struct radeon_cs_chunk *ib_chunk;
 975         struct radeon_cs_reloc *reloc;
 976         volatile uint32_t *ib;
 977         uint32_t tmp;
 978         unsigned reg;
 979         unsigned i;
 980         unsigned idx;
 981         bool onereg;
 982         int r;
 983         u32 tile_flags = 0;
 984
 985         ib = p->ib->ptr;
 986         ib_chunk = &p->chunks[p->chunk_ib_idx];
 987         idx = pkt->idx + 1;
 988         reg = pkt->reg;
 989         onereg = false;
 990         if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
 991                 onereg = true;
 992         }
 993         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 994                 switch (reg) {
 995                 case RADEON_CRTC_GUI_TRIG_VLINE:
 996                         r = r100_cs_packet_parse_vline(p);
 997                         if (r) {
 998                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 999                                                 idx, reg);
1000                                 r100_cs_dump_packet(p, pkt);
1001                                 return r;
1002                         }
1003                         break;
1004                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1005                  * range access */
1006                 case RADEON_DST_PITCH_OFFSET:
1007                 case RADEON_SRC_PITCH_OFFSET:
1008                         r = r100_cs_packet_next_reloc(p, &reloc);
1009                         if (r) {
1010                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1011                                           idx, reg);
1012                                 r100_cs_dump_packet(p, pkt);
1013                                 return r;
1014                         }
1015                         tmp = ib_chunk->kdata[idx] & 0x003fffff;
1016                         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1017
1018                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1019                                 tile_flags |= RADEON_DST_TILE_MACRO;
1020                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1021                                 if (reg == RADEON_SRC_PITCH_OFFSET) {
1022                                         DRM_ERROR("Cannot src blit from microtiled surface\n");
1023                                         r100_cs_dump_packet(p, pkt);
1024                                         return -EINVAL;
1025                                 }
1026                                 tile_flags |= RADEON_DST_TILE_MICRO;
1027                         }
1028
1029                         tmp |= tile_flags;
1030                         ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
1031                         break;
1032                 case RADEON_RB3D_DEPTHOFFSET:
1033                 case RADEON_RB3D_COLOROFFSET:
1034                 case R300_RB3D_COLOROFFSET0:
1035                 case R300_ZB_DEPTHOFFSET:
1036                 case R200_PP_TXOFFSET_0:
1037                 case R200_PP_TXOFFSET_1:
1038                 case R200_PP_TXOFFSET_2:
1039                 case R200_PP_TXOFFSET_3:
1040                 case R200_PP_TXOFFSET_4:
1041                 case R200_PP_TXOFFSET_5:
1042                 case RADEON_PP_TXOFFSET_0:
1043                 case RADEON_PP_TXOFFSET_1:
1044                 case RADEON_PP_TXOFFSET_2:
1045                 case R300_TX_OFFSET_0:
1046                 case R300_TX_OFFSET_0+4:
1047                 case R300_TX_OFFSET_0+8:
1048                 case R300_TX_OFFSET_0+12:
1049                 case R300_TX_OFFSET_0+16:
1050                 case R300_TX_OFFSET_0+20:
1051                 case R300_TX_OFFSET_0+24:
1052                 case R300_TX_OFFSET_0+28:
1053                 case R300_TX_OFFSET_0+32:
1054                 case R300_TX_OFFSET_0+36:
1055                 case R300_TX_OFFSET_0+40:
1056                 case R300_TX_OFFSET_0+44:
1057                 case R300_TX_OFFSET_0+48:
1058                 case R300_TX_OFFSET_0+52:
1059                 case R300_TX_OFFSET_0+56:
1060                 case R300_TX_OFFSET_0+60:
1061                         /* rn50 has no 3D engine so fail on any 3d setup */
1062                         if (ASIC_IS_RN50(p->rdev)) {
1063                                 DRM_ERROR("attempt to use RN50 3D engine failed\n");
1064                                 return -EINVAL;
1065                         }
1066                         r = r100_cs_packet_next_reloc(p, &reloc);
1067                         if (r) {
1068                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1069                                           idx, reg);
1070                                 r100_cs_dump_packet(p, pkt);
1071                                 return r;
1072                         }
1073                         ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1074                         break;
1075                 case R300_RB3D_COLORPITCH0:
1076                 case RADEON_RB3D_COLORPITCH:
1077                         r = r100_cs_packet_next_reloc(p, &reloc);
1078                         if (r) {
1079                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1080                                           idx, reg);
1081                                 r100_cs_dump_packet(p, pkt);
1082                                 return r;
1083                         }
1084
1085                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1086                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1087                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1088                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1089
1090                         tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1091                         tmp |= tile_flags;
1092                         ib[idx] = tmp;
1093                         break;
1094                 case RADEON_RB3D_ZPASS_ADDR:
1095                         r = r100_cs_packet_next_reloc(p, &reloc);
1096                         if (r) {
1097                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1098                                           idx, reg);
1099                                 r100_cs_dump_packet(p, pkt);
1100                                 return r;
1101                         }
1102                         ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1103                         break;
1104                 default:
1105                         /* FIXME: we don't want to allow anyothers packet */
1106                         break;
1107                 }
1108                 if (onereg) {
1109                         /* FIXME: forbid onereg write to register on relocate */
1110                         break;
1111                 }
1112         }
1113         return 0;
1114 }
1115
1116 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1117                                          struct radeon_cs_packet *pkt,
1118                                          struct radeon_object *robj)
1119 {
1120         struct radeon_cs_chunk *ib_chunk;
1121         unsigned idx;
1122
1123         ib_chunk = &p->chunks[p->chunk_ib_idx];
1124         idx = pkt->idx + 1;
1125         if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
1126                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1127                           "(need %u have %lu) !\n",
1128                           ib_chunk->kdata[idx+2] + 1,
1129                           radeon_object_size(robj));
1130                 return -EINVAL;
1131         }
1132         return 0;
1133 }
1134
1135 static int r100_packet3_check(struct radeon_cs_parser *p,
1136                               struct radeon_cs_packet *pkt)
1137 {
1138         struct radeon_cs_chunk *ib_chunk;
1139         struct radeon_cs_reloc *reloc;
1140         unsigned idx;
1141         unsigned i, c;
1142         volatile uint32_t *ib;
1143         int r;
1144
1145         ib = p->ib->ptr;
1146         ib_chunk = &p->chunks[p->chunk_ib_idx];
1147         idx = pkt->idx + 1;
1148         switch (pkt->opcode) {
1149         case PACKET3_3D_LOAD_VBPNTR:
1150                 c = ib_chunk->kdata[idx++];
1151                 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1152                         r = r100_cs_packet_next_reloc(p, &reloc);
1153                         if (r) {
1154                                 DRM_ERROR("No reloc for packet3 %d\n",
1155                                           pkt->opcode);
1156                                 r100_cs_dump_packet(p, pkt);
1157                                 return r;
1158                         }
1159                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1160                         r = r100_cs_packet_next_reloc(p, &reloc);
1161                         if (r) {
1162                                 DRM_ERROR("No reloc for packet3 %d\n",
1163                                           pkt->opcode);
1164                                 r100_cs_dump_packet(p, pkt);
1165                                 return r;
1166                         }
1167                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1168                 }
1169                 if (c & 1) {
1170                         r = r100_cs_packet_next_reloc(p, &reloc);
1171                         if (r) {
1172                                 DRM_ERROR("No reloc for packet3 %d\n",
1173                                           pkt->opcode);
1174                                 r100_cs_dump_packet(p, pkt);
1175                                 return r;
1176                         }
1177                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1178                 }
1179                 break;
1180         case PACKET3_INDX_BUFFER:
1181                 r = r100_cs_packet_next_reloc(p, &reloc);
1182                 if (r) {
1183                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1184                         r100_cs_dump_packet(p, pkt);
1185                         return r;
1186                 }
1187                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1188                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1189                 if (r) {
1190                         return r;
1191                 }
1192                 break;
1193         case 0x23:
1194                 /* FIXME: cleanup */
1195                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1196                 r = r100_cs_packet_next_reloc(p, &reloc);
1197                 if (r) {
1198                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1199                         r100_cs_dump_packet(p, pkt);
1200                         return r;
1201                 }
1202                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1203                 break;
1204         case PACKET3_3D_DRAW_IMMD:
1205                 /* triggers drawing using in-packet vertex data */
1206         case PACKET3_3D_DRAW_IMMD_2:
1207                 /* triggers drawing using in-packet vertex data */
1208         case PACKET3_3D_DRAW_VBUF_2:
1209                 /* triggers drawing of vertex buffers setup elsewhere */
1210         case PACKET3_3D_DRAW_INDX_2:
1211                 /* triggers drawing using indices to vertex buffer */
1212         case PACKET3_3D_DRAW_VBUF:
1213                 /* triggers drawing of vertex buffers setup elsewhere */
1214         case PACKET3_3D_DRAW_INDX:
1215                 /* triggers drawing using indices to vertex buffer */
1216         case PACKET3_NOP:
1217                 break;
1218         default:
1219                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1220                 return -EINVAL;
1221         }
1222         return 0;
1223 }
1224
1225 int r100_cs_parse(struct radeon_cs_parser *p)
1226 {
1227         struct radeon_cs_packet pkt;
1228         int r;
1229
1230         do {
1231                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1232                 if (r) {
1233                         return r;
1234                 }
1235                 p->idx += pkt.count + 2;
1236                 switch (pkt.type) {
1237                         case PACKET_TYPE0:
1238                                 r = r100_packet0_check(p, &pkt);
1239                                 break;
1240                         case PACKET_TYPE2:
1241                                 break;
1242                         case PACKET_TYPE3:
1243                                 r = r100_packet3_check(p, &pkt);
1244                                 break;
1245                         default:
1246                                 DRM_ERROR("Unknown packet type %d !\n",
1247                                           pkt.type);
1248                                 return -EINVAL;
1249                 }
1250                 if (r) {
1251                         return r;
1252                 }
1253         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1254         return 0;
1255 }
1256
1257
1258 /*
1259  * Global GPU functions
1260  */
1261 void r100_errata(struct radeon_device *rdev)
1262 {
1263         rdev->pll_errata = 0;
1264
1265         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1266                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1267         }
1268
1269         if (rdev->family == CHIP_RV100 ||
1270             rdev->family == CHIP_RS100 ||
1271             rdev->family == CHIP_RS200) {
1272                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1273         }
1274 }
1275
1276 /* Wait for vertical sync on primary CRTC */
1277 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1278 {
1279         uint32_t crtc_gen_cntl, tmp;
1280         int i;
1281
1282         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1283         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1284             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1285                 return;
1286         }
1287         /* Clear the CRTC_VBLANK_SAVE bit */
1288         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1289         for (i = 0; i < rdev->usec_timeout; i++) {
1290                 tmp = RREG32(RADEON_CRTC_STATUS);
1291                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1292                         return;
1293                 }
1294                 DRM_UDELAY(1);
1295         }
1296 }
1297
1298 /* Wait for vertical sync on secondary CRTC */
1299 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1300 {
1301         uint32_t crtc2_gen_cntl, tmp;
1302         int i;
1303
1304         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1305         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1306             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1307                 return;
1308
1309         /* Clear the CRTC_VBLANK_SAVE bit */
1310         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1311         for (i = 0; i < rdev->usec_timeout; i++) {
1312                 tmp = RREG32(RADEON_CRTC2_STATUS);
1313                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1314                         return;
1315                 }
1316                 DRM_UDELAY(1);
1317         }
1318 }
1319
1320 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1321 {
1322         unsigned i;
1323         uint32_t tmp;
1324
1325         for (i = 0; i < rdev->usec_timeout; i++) {
1326                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1327                 if (tmp >= n) {
1328                         return 0;
1329                 }
1330                 DRM_UDELAY(1);
1331         }
1332         return -1;
1333 }
1334
1335 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1336 {
1337         unsigned i;
1338         uint32_t tmp;
1339
1340         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1341                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1342                        " Bad things might happen.\n");
1343         }
1344         for (i = 0; i < rdev->usec_timeout; i++) {
1345                 tmp = RREG32(RADEON_RBBM_STATUS);
1346                 if (!(tmp & (1 << 31))) {
1347                         return 0;
1348                 }
1349                 DRM_UDELAY(1);
1350         }
1351         return -1;
1352 }
1353
1354 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1355 {
1356         unsigned i;
1357         uint32_t tmp;
1358
1359         for (i = 0; i < rdev->usec_timeout; i++) {
1360                 /* read MC_STATUS */
1361                 tmp = RREG32(0x0150);
1362                 if (tmp & (1 << 2)) {
1363                         return 0;
1364                 }
1365                 DRM_UDELAY(1);
1366         }
1367         return -1;
1368 }
1369
1370 void r100_gpu_init(struct radeon_device *rdev)
1371 {
1372         /* TODO: anythings to do here ? pipes ? */
1373         r100_hdp_reset(rdev);
1374 }
1375
1376 void r100_hdp_reset(struct radeon_device *rdev)
1377 {
1378         uint32_t tmp;
1379
1380         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1381         tmp |= (7 << 28);
1382         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1383         (void)RREG32(RADEON_HOST_PATH_CNTL);
1384         udelay(200);
1385         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1386         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1387         (void)RREG32(RADEON_HOST_PATH_CNTL);
1388 }
1389
1390 int r100_rb2d_reset(struct radeon_device *rdev)
1391 {
1392         uint32_t tmp;
1393         int i;
1394
1395         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1396         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1397         udelay(200);
1398         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1399         /* Wait to prevent race in RBBM_STATUS */
1400         mdelay(1);
1401         for (i = 0; i < rdev->usec_timeout; i++) {
1402                 tmp = RREG32(RADEON_RBBM_STATUS);
1403                 if (!(tmp & (1 << 26))) {
1404                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1405                                  tmp);
1406                         return 0;
1407                 }
1408                 DRM_UDELAY(1);
1409         }
1410         tmp = RREG32(RADEON_RBBM_STATUS);
1411         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1412         return -1;
1413 }
1414
1415 int r100_gpu_reset(struct radeon_device *rdev)
1416 {
1417         uint32_t status;
1418
1419         /* reset order likely matter */
1420         status = RREG32(RADEON_RBBM_STATUS);
1421         /* reset HDP */
1422         r100_hdp_reset(rdev);
1423         /* reset rb2d */
1424         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1425                 r100_rb2d_reset(rdev);
1426         }
1427         /* TODO: reset 3D engine */
1428         /* reset CP */
1429         status = RREG32(RADEON_RBBM_STATUS);
1430         if (status & (1 << 16)) {
1431                 r100_cp_reset(rdev);
1432         }
1433         /* Check if GPU is idle */
1434         status = RREG32(RADEON_RBBM_STATUS);
1435         if (status & (1 << 31)) {
1436                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1437                 return -1;
1438         }
1439         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1440         return 0;
1441 }
1442
1443
1444 /*
1445  * VRAM info
1446  */
1447 static void r100_vram_get_type(struct radeon_device *rdev)
1448 {
1449         uint32_t tmp;
1450
1451         rdev->mc.vram_is_ddr = false;
1452         if (rdev->flags & RADEON_IS_IGP)
1453                 rdev->mc.vram_is_ddr = true;
1454         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1455                 rdev->mc.vram_is_ddr = true;
1456         if ((rdev->family == CHIP_RV100) ||
1457             (rdev->family == CHIP_RS100) ||
1458             (rdev->family == CHIP_RS200)) {
1459                 tmp = RREG32(RADEON_MEM_CNTL);
1460                 if (tmp & RV100_HALF_MODE) {
1461                         rdev->mc.vram_width = 32;
1462                 } else {
1463                         rdev->mc.vram_width = 64;
1464                 }
1465                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1466                         rdev->mc.vram_width /= 4;
1467                         rdev->mc.vram_is_ddr = true;
1468                 }
1469         } else if (rdev->family <= CHIP_RV280) {
1470                 tmp = RREG32(RADEON_MEM_CNTL);
1471                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1472                         rdev->mc.vram_width = 128;
1473                 } else {
1474                         rdev->mc.vram_width = 64;
1475                 }
1476         } else {
1477                 /* newer IGPs */
1478                 rdev->mc.vram_width = 128;
1479         }
1480 }
1481
1482 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1483 {
1484         u32 aper_size;
1485         u8 byte;
1486
1487         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1488
1489         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1490          * that is has the 2nd generation multifunction PCI interface
1491          */
1492         if (rdev->family == CHIP_RV280 ||
1493             rdev->family >= CHIP_RV350) {
1494                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1495                        ~RADEON_HDP_APER_CNTL);
1496                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1497                 return aper_size * 2;
1498         }
1499
1500         /* Older cards have all sorts of funny issues to deal with. First
1501          * check if it's a multifunction card by reading the PCI config
1502          * header type... Limit those to one aperture size
1503          */
1504         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1505         if (byte & 0x80) {
1506                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1507                 DRM_INFO("Limiting VRAM to one aperture\n");
1508                 return aper_size;
1509         }
1510
1511         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1512          * have set it up. We don't write this as it's broken on some ASICs but
1513          * we expect the BIOS to have done the right thing (might be too optimistic...)
1514          */
1515         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1516                 return aper_size * 2;
1517         return aper_size;
1518 }
1519
1520 void r100_vram_init_sizes(struct radeon_device *rdev)
1521 {
1522         u64 config_aper_size;
1523         u32 accessible;
1524
1525         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1526
1527         if (rdev->flags & RADEON_IS_IGP) {
1528                 uint32_t tom;
1529                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1530                 tom = RREG32(RADEON_NB_TOM);
1531                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1532                 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1533                 rdev->mc.vram_location = (tom & 0xffff) << 16;
1534                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1535                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1536         } else {
1537                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1538                 /* Some production boards of m6 will report 0
1539                  * if it's 8 MB
1540                  */
1541                 if (rdev->mc.real_vram_size == 0) {
1542                         rdev->mc.real_vram_size = 8192 * 1024;
1543                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1544                 }
1545                 /* let driver place VRAM */
1546                 rdev->mc.vram_location = 0xFFFFFFFFUL;
1547                  /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1548                   * Novell bug 204882 + along with lots of ubuntu ones */
1549                 if (config_aper_size > rdev->mc.real_vram_size)
1550                         rdev->mc.mc_vram_size = config_aper_size;
1551                 else
1552                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1553         }
1554
1555         /* work out accessible VRAM */
1556         accessible = r100_get_accessible_vram(rdev);
1557
1558         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1559         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1560
1561         if (accessible > rdev->mc.aper_size)
1562                 accessible = rdev->mc.aper_size;
1563
1564         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1565                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1566
1567         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1568                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1569 }
1570
1571 void r100_vram_info(struct radeon_device *rdev)
1572 {
1573         r100_vram_get_type(rdev);
1574
1575         r100_vram_init_sizes(rdev);
1576 }
1577
1578
1579 /*
1580  * Indirect registers accessor
1581  */
1582 void r100_pll_errata_after_index(struct radeon_device *rdev)
1583 {
1584         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1585                 return;
1586         }
1587         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1588         (void)RREG32(RADEON_CRTC_GEN_CNTL);
1589 }
1590
1591 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1592 {
1593         /* This workarounds is necessary on RV100, RS100 and RS200 chips
1594          * or the chip could hang on a subsequent access
1595          */
1596         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1597                 udelay(5000);
1598         }
1599
1600         /* This function is required to workaround a hardware bug in some (all?)
1601          * revisions of the R300.  This workaround should be called after every
1602          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
1603          * may not be correct.
1604          */
1605         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1606                 uint32_t save, tmp;
1607
1608                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1609                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1610                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1611                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1612                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1613         }
1614 }
1615
1616 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1617 {
1618         uint32_t data;
1619
1620         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1621         r100_pll_errata_after_index(rdev);
1622         data = RREG32(RADEON_CLOCK_CNTL_DATA);
1623         r100_pll_errata_after_data(rdev);
1624         return data;
1625 }
1626
1627 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1628 {
1629         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1630         r100_pll_errata_after_index(rdev);
1631         WREG32(RADEON_CLOCK_CNTL_DATA, v);
1632         r100_pll_errata_after_data(rdev);
1633 }
1634
1635 int r100_init(struct radeon_device *rdev)
1636 {
1637         return 0;
1638 }
1639
1640 /*
1641  * Debugfs info
1642  */
1643 #if defined(CONFIG_DEBUG_FS)
1644 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1645 {
1646         struct drm_info_node *node = (struct drm_info_node *) m->private;
1647         struct drm_device *dev = node->minor->dev;
1648         struct radeon_device *rdev = dev->dev_private;
1649         uint32_t reg, value;
1650         unsigned i;
1651
1652         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1653         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1654         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1655         for (i = 0; i < 64; i++) {
1656                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1657                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1658                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1659                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1660                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1661         }
1662         return 0;
1663 }
1664
1665 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1666 {
1667         struct drm_info_node *node = (struct drm_info_node *) m->private;
1668         struct drm_device *dev = node->minor->dev;
1669         struct radeon_device *rdev = dev->dev_private;
1670         uint32_t rdp, wdp;
1671         unsigned count, i, j;
1672
1673         radeon_ring_free_size(rdev);
1674         rdp = RREG32(RADEON_CP_RB_RPTR);
1675         wdp = RREG32(RADEON_CP_RB_WPTR);
1676         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1677         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1678         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1679         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1680         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1681         seq_printf(m, "%u dwords in ring\n", count);
1682         for (j = 0; j <= count; j++) {
1683                 i = (rdp + j) & rdev->cp.ptr_mask;
1684                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1685         }
1686         return 0;
1687 }
1688
1689
1690 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1691 {
1692         struct drm_info_node *node = (struct drm_info_node *) m->private;
1693         struct drm_device *dev = node->minor->dev;
1694         struct radeon_device *rdev = dev->dev_private;
1695         uint32_t csq_stat, csq2_stat, tmp;
1696         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1697         unsigned i;
1698
1699         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1700         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1701         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1702         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1703         r_rptr = (csq_stat >> 0) & 0x3ff;
1704         r_wptr = (csq_stat >> 10) & 0x3ff;
1705         ib1_rptr = (csq_stat >> 20) & 0x3ff;
1706         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1707         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1708         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1709         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1710         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1711         seq_printf(m, "Ring rptr %u\n", r_rptr);
1712         seq_printf(m, "Ring wptr %u\n", r_wptr);
1713         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1714         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1715         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1716         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1717         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1718          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1719         seq_printf(m, "Ring fifo:\n");
1720         for (i = 0; i < 256; i++) {
1721                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1722                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1723                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1724         }
1725         seq_printf(m, "Indirect1 fifo:\n");
1726         for (i = 256; i <= 512; i++) {
1727                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1728                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1729                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1730         }
1731         seq_printf(m, "Indirect2 fifo:\n");
1732         for (i = 640; i < ib1_wptr; i++) {
1733                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1734                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1735                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1736         }
1737         return 0;
1738 }
1739
1740 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1741 {
1742         struct drm_info_node *node = (struct drm_info_node *) m->private;
1743         struct drm_device *dev = node->minor->dev;
1744         struct radeon_device *rdev = dev->dev_private;
1745         uint32_t tmp;
1746
1747         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1748         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1749         tmp = RREG32(RADEON_MC_FB_LOCATION);
1750         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1751         tmp = RREG32(RADEON_BUS_CNTL);
1752         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1753         tmp = RREG32(RADEON_MC_AGP_LOCATION);
1754         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1755         tmp = RREG32(RADEON_AGP_BASE);
1756         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1757         tmp = RREG32(RADEON_HOST_PATH_CNTL);
1758         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1759         tmp = RREG32(0x01D0);
1760         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1761         tmp = RREG32(RADEON_AIC_LO_ADDR);
1762         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1763         tmp = RREG32(RADEON_AIC_HI_ADDR);
1764         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1765         tmp = RREG32(0x01E4);
1766         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1767         return 0;
1768 }
1769
1770 static struct drm_info_list r100_debugfs_rbbm_list[] = {
1771         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1772 };
1773
1774 static struct drm_info_list r100_debugfs_cp_list[] = {
1775         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1776         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1777 };
1778
1779 static struct drm_info_list r100_debugfs_mc_info_list[] = {
1780         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1781 };
1782 #endif
1783
1784 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
1785 {
1786 #if defined(CONFIG_DEBUG_FS)
1787         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
1788 #else
1789         return 0;
1790 #endif
1791 }
1792
1793 int r100_debugfs_cp_init(struct radeon_device *rdev)
1794 {
1795 #if defined(CONFIG_DEBUG_FS)
1796         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
1797 #else
1798         return 0;
1799 #endif
1800 }
1801
1802 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
1803 {
1804 #if defined(CONFIG_DEBUG_FS)
1805         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
1806 #else
1807         return 0;
1808 #endif
1809 }
1810
1811 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
1812                          uint32_t tiling_flags, uint32_t pitch,
1813                          uint32_t offset, uint32_t obj_size)
1814 {
1815         int surf_index = reg * 16;
1816         int flags = 0;
1817
1818         /* r100/r200 divide by 16 */
1819         if (rdev->family < CHIP_R300)
1820                 flags = pitch / 16;
1821         else
1822                 flags = pitch / 8;
1823
1824         if (rdev->family <= CHIP_RS200) {
1825                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
1826                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
1827                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
1828                 if (tiling_flags & RADEON_TILING_MACRO)
1829                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
1830         } else if (rdev->family <= CHIP_RV280) {
1831                 if (tiling_flags & (RADEON_TILING_MACRO))
1832                         flags |= R200_SURF_TILE_COLOR_MACRO;
1833                 if (tiling_flags & RADEON_TILING_MICRO)
1834                         flags |= R200_SURF_TILE_COLOR_MICRO;
1835         } else {
1836                 if (tiling_flags & RADEON_TILING_MACRO)
1837                         flags |= R300_SURF_TILE_MACRO;
1838                 if (tiling_flags & RADEON_TILING_MICRO)
1839                         flags |= R300_SURF_TILE_MICRO;
1840         }
1841
1842         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1843         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
1844         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
1845         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
1846         return 0;
1847 }
1848
1849 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
1850 {
1851         int surf_index = reg * 16;
1852         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
1853 }
1854
1855 void r100_bandwidth_update(struct radeon_device *rdev)
1856 {
1857         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
1858         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
1859         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
1860         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
1861         fixed20_12 memtcas_ff[8] = {
1862                 fixed_init(1),
1863                 fixed_init(2),
1864                 fixed_init(3),
1865                 fixed_init(0),
1866                 fixed_init_half(1),
1867                 fixed_init_half(2),
1868                 fixed_init(0),
1869         };
1870         fixed20_12 memtcas_rs480_ff[8] = {
1871                 fixed_init(0),
1872                 fixed_init(1),
1873                 fixed_init(2),
1874                 fixed_init(3),
1875                 fixed_init(0),
1876                 fixed_init_half(1),
1877                 fixed_init_half(2),
1878                 fixed_init_half(3),
1879         };
1880         fixed20_12 memtcas2_ff[8] = {
1881                 fixed_init(0),
1882                 fixed_init(1),
1883                 fixed_init(2),
1884                 fixed_init(3),
1885                 fixed_init(4),
1886                 fixed_init(5),
1887                 fixed_init(6),
1888                 fixed_init(7),
1889         };
1890         fixed20_12 memtrbs[8] = {
1891                 fixed_init(1),
1892                 fixed_init_half(1),
1893                 fixed_init(2),
1894                 fixed_init_half(2),
1895                 fixed_init(3),
1896                 fixed_init_half(3),
1897                 fixed_init(4),
1898                 fixed_init_half(4)
1899         };
1900         fixed20_12 memtrbs_r4xx[8] = {
1901                 fixed_init(4),
1902                 fixed_init(5),
1903                 fixed_init(6),
1904                 fixed_init(7),
1905                 fixed_init(8),
1906                 fixed_init(9),
1907                 fixed_init(10),
1908                 fixed_init(11)
1909         };
1910         fixed20_12 min_mem_eff;
1911         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
1912         fixed20_12 cur_latency_mclk, cur_latency_sclk;
1913         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
1914                 disp_drain_rate2, read_return_rate;
1915         fixed20_12 time_disp1_drop_priority;
1916         int c;
1917         int cur_size = 16;       /* in octawords */
1918         int critical_point = 0, critical_point2;
1919 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
1920         int stop_req, max_stop_req;
1921         struct drm_display_mode *mode1 = NULL;
1922         struct drm_display_mode *mode2 = NULL;
1923         uint32_t pixel_bytes1 = 0;
1924         uint32_t pixel_bytes2 = 0;
1925
1926         if (rdev->mode_info.crtcs[0]->base.enabled) {
1927                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
1928                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
1929         }
1930         if (rdev->mode_info.crtcs[1]->base.enabled) {
1931                 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
1932                 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
1933         }
1934
1935         min_mem_eff.full = rfixed_const_8(0);
1936         /* get modes */
1937         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
1938                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
1939                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
1940                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
1941                 /* check crtc enables */
1942                 if (mode2)
1943                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
1944                 if (mode1)
1945                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
1946                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
1947         }
1948
1949         /*
1950          * determine is there is enough bw for current mode
1951          */
1952         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
1953         temp_ff.full = rfixed_const(100);
1954         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
1955         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
1956         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
1957
1958         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1959         temp_ff.full = rfixed_const(temp);
1960         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
1961
1962         pix_clk.full = 0;
1963         pix_clk2.full = 0;
1964         peak_disp_bw.full = 0;
1965         if (mode1) {
1966                 temp_ff.full = rfixed_const(1000);
1967                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
1968                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
1969                 temp_ff.full = rfixed_const(pixel_bytes1);
1970                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
1971         }
1972         if (mode2) {
1973                 temp_ff.full = rfixed_const(1000);
1974                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
1975                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
1976                 temp_ff.full = rfixed_const(pixel_bytes2);
1977                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
1978         }
1979
1980         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
1981         if (peak_disp_bw.full >= mem_bw.full) {
1982                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
1983                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
1984         }
1985
1986         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
1987         temp = RREG32(RADEON_MEM_TIMING_CNTL);
1988         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
1989                 mem_trcd = ((temp >> 2) & 0x3) + 1;
1990                 mem_trp  = ((temp & 0x3)) + 1;
1991                 mem_tras = ((temp & 0x70) >> 4) + 1;
1992         } else if (rdev->family == CHIP_R300 ||
1993                    rdev->family == CHIP_R350) { /* r300, r350 */
1994                 mem_trcd = (temp & 0x7) + 1;
1995                 mem_trp = ((temp >> 8) & 0x7) + 1;
1996                 mem_tras = ((temp >> 11) & 0xf) + 4;
1997         } else if (rdev->family == CHIP_RV350 ||
1998                    rdev->family <= CHIP_RV380) {
1999                 /* rv3x0 */
2000                 mem_trcd = (temp & 0x7) + 3;
2001                 mem_trp = ((temp >> 8) & 0x7) + 3;
2002                 mem_tras = ((temp >> 11) & 0xf) + 6;
2003         } else if (rdev->family == CHIP_R420 ||
2004                    rdev->family == CHIP_R423 ||
2005                    rdev->family == CHIP_RV410) {
2006                 /* r4xx */
2007                 mem_trcd = (temp & 0xf) + 3;
2008                 if (mem_trcd > 15)
2009                         mem_trcd = 15;
2010                 mem_trp = ((temp >> 8) & 0xf) + 3;
2011                 if (mem_trp > 15)
2012                         mem_trp = 15;
2013                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2014                 if (mem_tras > 31)
2015                         mem_tras = 31;
2016         } else { /* RV200, R200 */
2017                 mem_trcd = (temp & 0x7) + 1;
2018                 mem_trp = ((temp >> 8) & 0x7) + 1;
2019                 mem_tras = ((temp >> 12) & 0xf) + 4;
2020         }
2021         /* convert to FF */
2022         trcd_ff.full = rfixed_const(mem_trcd);
2023         trp_ff.full = rfixed_const(mem_trp);
2024         tras_ff.full = rfixed_const(mem_tras);
2025
2026         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2027         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2028         data = (temp & (7 << 20)) >> 20;
2029         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2030                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2031                         tcas_ff = memtcas_rs480_ff[data];
2032                 else
2033                         tcas_ff = memtcas_ff[data];
2034         } else
2035                 tcas_ff = memtcas2_ff[data];
2036
2037         if (rdev->family == CHIP_RS400 ||
2038             rdev->family == CHIP_RS480) {
2039                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2040                 data = (temp >> 23) & 0x7;
2041                 if (data < 5)
2042                         tcas_ff.full += rfixed_const(data);
2043         }
2044
2045         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2046                 /* on the R300, Tcas is included in Trbs.
2047                  */
2048                 temp = RREG32(RADEON_MEM_CNTL);
2049                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2050                 if (data == 1) {
2051                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2052                                 temp = RREG32(R300_MC_IND_INDEX);
2053                                 temp &= ~R300_MC_IND_ADDR_MASK;
2054                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2055                                 WREG32(R300_MC_IND_INDEX, temp);
2056                                 temp = RREG32(R300_MC_IND_DATA);
2057                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2058                         } else {
2059                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2060                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2061                         }
2062                 } else {
2063                         temp = RREG32(R300_MC_READ_CNTL_AB);
2064                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2065                 }
2066                 if (rdev->family == CHIP_RV410 ||
2067                     rdev->family == CHIP_R420 ||
2068                     rdev->family == CHIP_R423)
2069                         trbs_ff = memtrbs_r4xx[data];
2070                 else
2071                         trbs_ff = memtrbs[data];
2072                 tcas_ff.full += trbs_ff.full;
2073         }
2074
2075         sclk_eff_ff.full = sclk_ff.full;
2076
2077         if (rdev->flags & RADEON_IS_AGP) {
2078                 fixed20_12 agpmode_ff;
2079                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2080                 temp_ff.full = rfixed_const_666(16);
2081                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2082         }
2083         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2084
2085         if (ASIC_IS_R300(rdev)) {
2086                 sclk_delay_ff.full = rfixed_const(250);
2087         } else {
2088                 if ((rdev->family == CHIP_RV100) ||
2089                     rdev->flags & RADEON_IS_IGP) {
2090                         if (rdev->mc.vram_is_ddr)
2091                                 sclk_delay_ff.full = rfixed_const(41);
2092                         else
2093                                 sclk_delay_ff.full = rfixed_const(33);
2094                 } else {
2095                         if (rdev->mc.vram_width == 128)
2096                                 sclk_delay_ff.full = rfixed_const(57);
2097                         else
2098                                 sclk_delay_ff.full = rfixed_const(41);
2099                 }
2100         }
2101
2102         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2103
2104         if (rdev->mc.vram_is_ddr) {
2105                 if (rdev->mc.vram_width == 32) {
2106                         k1.full = rfixed_const(40);
2107                         c  = 3;
2108                 } else {
2109                         k1.full = rfixed_const(20);
2110                         c  = 1;
2111                 }
2112         } else {
2113                 k1.full = rfixed_const(40);
2114                 c  = 3;
2115         }
2116
2117         temp_ff.full = rfixed_const(2);
2118         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2119         temp_ff.full = rfixed_const(c);
2120         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2121         temp_ff.full = rfixed_const(4);
2122         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2123         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2124         mc_latency_mclk.full += k1.full;
2125
2126         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2127         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2128
2129         /*
2130           HW cursor time assuming worst case of full size colour cursor.
2131         */
2132         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2133         temp_ff.full += trcd_ff.full;
2134         if (temp_ff.full < tras_ff.full)
2135                 temp_ff.full = tras_ff.full;
2136         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2137
2138         temp_ff.full = rfixed_const(cur_size);
2139         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2140         /*
2141           Find the total latency for the display data.
2142         */
2143         disp_latency_overhead.full = rfixed_const(80);
2144         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2145         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2146         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2147
2148         if (mc_latency_mclk.full > mc_latency_sclk.full)
2149                 disp_latency.full = mc_latency_mclk.full;
2150         else
2151                 disp_latency.full = mc_latency_sclk.full;
2152
2153         /* setup Max GRPH_STOP_REQ default value */
2154         if (ASIC_IS_RV100(rdev))
2155                 max_stop_req = 0x5c;
2156         else
2157                 max_stop_req = 0x7c;
2158
2159         if (mode1) {
2160                 /*  CRTC1
2161                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2162                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2163                 */
2164                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2165
2166                 if (stop_req > max_stop_req)
2167                         stop_req = max_stop_req;
2168
2169                 /*
2170                   Find the drain rate of the display buffer.
2171                 */
2172                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2173                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2174
2175                 /*
2176                   Find the critical point of the display buffer.
2177                 */
2178                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2179                 crit_point_ff.full += rfixed_const_half(0);
2180
2181                 critical_point = rfixed_trunc(crit_point_ff);
2182
2183                 if (rdev->disp_priority == 2) {
2184                         critical_point = 0;
2185                 }
2186
2187                 /*
2188                   The critical point should never be above max_stop_req-4.  Setting
2189                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2190                 */
2191                 if (max_stop_req - critical_point < 4)
2192                         critical_point = 0;
2193
2194                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2195                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2196                         critical_point = 0x10;
2197                 }
2198
2199                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2200                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2201                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2202                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2203                 if ((rdev->family == CHIP_R350) &&
2204                     (stop_req > 0x15)) {
2205                         stop_req -= 0x10;
2206                 }
2207                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2208                 temp |= RADEON_GRPH_BUFFER_SIZE;
2209                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2210                           RADEON_GRPH_CRITICAL_AT_SOF |
2211                           RADEON_GRPH_STOP_CNTL);
2212                 /*
2213                   Write the result into the register.
2214                 */
2215                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2216                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2217
2218 #if 0
2219                 if ((rdev->family == CHIP_RS400) ||
2220                     (rdev->family == CHIP_RS480)) {
2221                         /* attempt to program RS400 disp regs correctly ??? */
2222                         temp = RREG32(RS400_DISP1_REG_CNTL);
2223                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2224                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2225                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2226                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2227                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2228                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2229                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2230                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2231                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2232                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2233                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2234                 }
2235 #endif
2236
2237                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2238                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2239                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2240         }
2241
2242         if (mode2) {
2243                 u32 grph2_cntl;
2244                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2245
2246                 if (stop_req > max_stop_req)
2247                         stop_req = max_stop_req;
2248
2249                 /*
2250                   Find the drain rate of the display buffer.
2251                 */
2252                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2253                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2254
2255                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2256                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2257                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2258                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2259                 if ((rdev->family == CHIP_R350) &&
2260                     (stop_req > 0x15)) {
2261                         stop_req -= 0x10;
2262                 }
2263                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2264                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2265                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2266                           RADEON_GRPH_CRITICAL_AT_SOF |
2267                           RADEON_GRPH_STOP_CNTL);
2268
2269                 if ((rdev->family == CHIP_RS100) ||
2270                     (rdev->family == CHIP_RS200))
2271                         critical_point2 = 0;
2272                 else {
2273                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2274                         temp_ff.full = rfixed_const(temp);
2275                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2276                         if (sclk_ff.full < temp_ff.full)
2277                                 temp_ff.full = sclk_ff.full;
2278
2279                         read_return_rate.full = temp_ff.full;
2280
2281                         if (mode1) {
2282                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2283                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2284                         } else {
2285                                 time_disp1_drop_priority.full = 0;
2286                         }
2287                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2288                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2289                         crit_point_ff.full += rfixed_const_half(0);
2290
2291                         critical_point2 = rfixed_trunc(crit_point_ff);
2292
2293                         if (rdev->disp_priority == 2) {
2294                                 critical_point2 = 0;
2295                         }
2296
2297                         if (max_stop_req - critical_point2 < 4)
2298                                 critical_point2 = 0;
2299
2300                 }
2301
2302                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2303                         /* some R300 cards have problem with this set to 0 */
2304                         critical_point2 = 0x10;
2305                 }
2306
2307                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2308                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2309
2310                 if ((rdev->family == CHIP_RS400) ||
2311                     (rdev->family == CHIP_RS480)) {
2312 #if 0
2313                         /* attempt to program RS400 disp2 regs correctly ??? */
2314                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2315                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2316                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2317                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2318                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2319                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2320                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2321                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2322                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2323                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2324                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2325                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2326 #endif
2327                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2328                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2329                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2330                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2331                 }
2332
2333                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2334                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2335         }
2336 }