drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "nid.h"
  32 #include "atom.h"
  33 #include "ni_reg.h"
  34 #include "cayman_blit_shaders.h"
  35
  36 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  37 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  39 extern void evergreen_mc_program(struct radeon_device *rdev);
  40 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  41 extern int evergreen_mc_init(struct radeon_device *rdev);
  42 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  43 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  44
  45 #define EVERGREEN_PFP_UCODE_SIZE 1120
  46 #define EVERGREEN_PM4_UCODE_SIZE 1376
  47 #define EVERGREEN_RLC_UCODE_SIZE 768
  48 #define BTC_MC_UCODE_SIZE 6024
  49
  50 #define CAYMAN_PFP_UCODE_SIZE 2176
  51 #define CAYMAN_PM4_UCODE_SIZE 2176
  52 #define CAYMAN_RLC_UCODE_SIZE 1024
  53 #define CAYMAN_MC_UCODE_SIZE 6037
  54
  55 /* Firmware Names */
  56 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  57 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  58 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  59 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  60 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  61 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  62 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  63 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  64 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  65 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  66 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  67 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  68 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  69 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  70
  71 #define BTC_IO_MC_REGS_SIZE 29
  72
  73 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  74         {0x00000077, 0xff010100},
  75         {0x00000078, 0x00000000},
  76         {0x00000079, 0x00001434},
  77         {0x0000007a, 0xcc08ec08},
  78         {0x0000007b, 0x00040000},
  79         {0x0000007c, 0x000080c0},
  80         {0x0000007d, 0x09000000},
  81         {0x0000007e, 0x00210404},
  82         {0x00000081, 0x08a8e800},
  83         {0x00000082, 0x00030444},
  84         {0x00000083, 0x00000000},
  85         {0x00000085, 0x00000001},
  86         {0x00000086, 0x00000002},
  87         {0x00000087, 0x48490000},
  88         {0x00000088, 0x20244647},
  89         {0x00000089, 0x00000005},
  90         {0x0000008b, 0x66030000},
  91         {0x0000008c, 0x00006603},
  92         {0x0000008d, 0x00000100},
  93         {0x0000008f, 0x00001c0a},
  94         {0x00000090, 0xff000001},
  95         {0x00000094, 0x00101101},
  96         {0x00000095, 0x00000fff},
  97         {0x00000096, 0x00116fff},
  98         {0x00000097, 0x60010000},
  99         {0x00000098, 0x10010000},
 100         {0x00000099, 0x00006000},
 101         {0x0000009a, 0x00001000},
 102         {0x0000009f, 0x00946a00}
 103 };
 104
 105 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 106         {0x00000077, 0xff010100},
 107         {0x00000078, 0x00000000},
 108         {0x00000079, 0x00001434},
 109         {0x0000007a, 0xcc08ec08},
 110         {0x0000007b, 0x00040000},
 111         {0x0000007c, 0x000080c0},
 112         {0x0000007d, 0x09000000},
 113         {0x0000007e, 0x00210404},
 114         {0x00000081, 0x08a8e800},
 115         {0x00000082, 0x00030444},
 116         {0x00000083, 0x00000000},
 117         {0x00000085, 0x00000001},
 118         {0x00000086, 0x00000002},
 119         {0x00000087, 0x48490000},
 120         {0x00000088, 0x20244647},
 121         {0x00000089, 0x00000005},
 122         {0x0000008b, 0x66030000},
 123         {0x0000008c, 0x00006603},
 124         {0x0000008d, 0x00000100},
 125         {0x0000008f, 0x00001c0a},
 126         {0x00000090, 0xff000001},
 127         {0x00000094, 0x00101101},
 128         {0x00000095, 0x00000fff},
 129         {0x00000096, 0x00116fff},
 130         {0x00000097, 0x60010000},
 131         {0x00000098, 0x10010000},
 132         {0x00000099, 0x00006000},
 133         {0x0000009a, 0x00001000},
 134         {0x0000009f, 0x00936a00}
 135 };
 136
 137 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 138         {0x00000077, 0xff010100},
 139         {0x00000078, 0x00000000},
 140         {0x00000079, 0x00001434},
 141         {0x0000007a, 0xcc08ec08},
 142         {0x0000007b, 0x00040000},
 143         {0x0000007c, 0x000080c0},
 144         {0x0000007d, 0x09000000},
 145         {0x0000007e, 0x00210404},
 146         {0x00000081, 0x08a8e800},
 147         {0x00000082, 0x00030444},
 148         {0x00000083, 0x00000000},
 149         {0x00000085, 0x00000001},
 150         {0x00000086, 0x00000002},
 151         {0x00000087, 0x48490000},
 152         {0x00000088, 0x20244647},
 153         {0x00000089, 0x00000005},
 154         {0x0000008b, 0x66030000},
 155         {0x0000008c, 0x00006603},
 156         {0x0000008d, 0x00000100},
 157         {0x0000008f, 0x00001c0a},
 158         {0x00000090, 0xff000001},
 159         {0x00000094, 0x00101101},
 160         {0x00000095, 0x00000fff},
 161         {0x00000096, 0x00116fff},
 162         {0x00000097, 0x60010000},
 163         {0x00000098, 0x10010000},
 164         {0x00000099, 0x00006000},
 165         {0x0000009a, 0x00001000},
 166         {0x0000009f, 0x00916a00}
 167 };
 168
 169 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 170         {0x00000077, 0xff010100},
 171         {0x00000078, 0x00000000},
 172         {0x00000079, 0x00001434},
 173         {0x0000007a, 0xcc08ec08},
 174         {0x0000007b, 0x00040000},
 175         {0x0000007c, 0x000080c0},
 176         {0x0000007d, 0x09000000},
 177         {0x0000007e, 0x00210404},
 178         {0x00000081, 0x08a8e800},
 179         {0x00000082, 0x00030444},
 180         {0x00000083, 0x00000000},
 181         {0x00000085, 0x00000001},
 182         {0x00000086, 0x00000002},
 183         {0x00000087, 0x48490000},
 184         {0x00000088, 0x20244647},
 185         {0x00000089, 0x00000005},
 186         {0x0000008b, 0x66030000},
 187         {0x0000008c, 0x00006603},
 188         {0x0000008d, 0x00000100},
 189         {0x0000008f, 0x00001c0a},
 190         {0x00000090, 0xff000001},
 191         {0x00000094, 0x00101101},
 192         {0x00000095, 0x00000fff},
 193         {0x00000096, 0x00116fff},
 194         {0x00000097, 0x60010000},
 195         {0x00000098, 0x10010000},
 196         {0x00000099, 0x00006000},
 197         {0x0000009a, 0x00001000},
 198         {0x0000009f, 0x00976b00}
 199 };
 200
 201 int ni_mc_load_microcode(struct radeon_device *rdev)
 202 {
 203         const __be32 *fw_data;
 204         u32 mem_type, running, blackout = 0;
 205         u32 *io_mc_regs;
 206         int i, ucode_size, regs_size;
 207
 208         if (!rdev->mc_fw)
 209                 return -EINVAL;
 210
 211         switch (rdev->family) {
 212         case CHIP_BARTS:
 213                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 214                 ucode_size = BTC_MC_UCODE_SIZE;
 215                 regs_size = BTC_IO_MC_REGS_SIZE;
 216                 break;
 217         case CHIP_TURKS:
 218                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 219                 ucode_size = BTC_MC_UCODE_SIZE;
 220                 regs_size = BTC_IO_MC_REGS_SIZE;
 221                 break;
 222         case CHIP_CAICOS:
 223         default:
 224                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 225                 ucode_size = BTC_MC_UCODE_SIZE;
 226                 regs_size = BTC_IO_MC_REGS_SIZE;
 227                 break;
 228         case CHIP_CAYMAN:
 229                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 230                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 231                 regs_size = BTC_IO_MC_REGS_SIZE;
 232                 break;
 233         }
 234
 235         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 236         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 237
 238         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 239                 if (running) {
 240                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 241                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 242                 }
 243
 244                 /* reset the engine and set to writable */
 245                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 246                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 247
 248                 /* load mc io regs */
 249                 for (i = 0; i < regs_size; i++) {
 250                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 251                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 252                 }
 253                 /* load the MC ucode */
 254                 fw_data = (const __be32 *)rdev->mc_fw->data;
 255                 for (i = 0; i < ucode_size; i++)
 256                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 257
 258                 /* put the engine back into the active state */
 259                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 260                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 261                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 262
 263                 /* wait for training to complete */
 264                 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
 265                         udelay(10);
 266
 267                 if (running)
 268                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 269         }
 270
 271         return 0;
 272 }
 273
 274 int ni_init_microcode(struct radeon_device *rdev)
 275 {
 276         struct platform_device *pdev;
 277         const char *chip_name;
 278         const char *rlc_chip_name;
 279         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 280         char fw_name[30];
 281         int err;
 282
 283         DRM_DEBUG("\n");
 284
 285         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 286         err = IS_ERR(pdev);
 287         if (err) {
 288                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 289                 return -EINVAL;
 290         }
 291
 292         switch (rdev->family) {
 293         case CHIP_BARTS:
 294                 chip_name = "BARTS";
 295                 rlc_chip_name = "BTC";
 296                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 297                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 298                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 299                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 300                 break;
 301         case CHIP_TURKS:
 302                 chip_name = "TURKS";
 303                 rlc_chip_name = "BTC";
 304                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 305                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 306                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 307                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 308                 break;
 309         case CHIP_CAICOS:
 310                 chip_name = "CAICOS";
 311                 rlc_chip_name = "BTC";
 312                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 313                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 314                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 315                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 316                 break;
 317         case CHIP_CAYMAN:
 318                 chip_name = "CAYMAN";
 319                 rlc_chip_name = "CAYMAN";
 320                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 321                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 322                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 323                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 324                 break;
 325         default: BUG();
 326         }
 327
 328         DRM_INFO("Loading %s Microcode\n", chip_name);
 329
 330         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 331         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 332         if (err)
 333                 goto out;
 334         if (rdev->pfp_fw->size != pfp_req_size) {
 335                 printk(KERN_ERR
 336                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 337                        rdev->pfp_fw->size, fw_name);
 338                 err = -EINVAL;
 339                 goto out;
 340         }
 341
 342         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 343         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 344         if (err)
 345                 goto out;
 346         if (rdev->me_fw->size != me_req_size) {
 347                 printk(KERN_ERR
 348                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 349                        rdev->me_fw->size, fw_name);
 350                 err = -EINVAL;
 351         }
 352
 353         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 354         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 355         if (err)
 356                 goto out;
 357         if (rdev->rlc_fw->size != rlc_req_size) {
 358                 printk(KERN_ERR
 359                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 360                        rdev->rlc_fw->size, fw_name);
 361                 err = -EINVAL;
 362         }
 363
 364         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 365         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 366         if (err)
 367                 goto out;
 368         if (rdev->mc_fw->size != mc_req_size) {
 369                 printk(KERN_ERR
 370                        "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 371                        rdev->mc_fw->size, fw_name);
 372                 err = -EINVAL;
 373         }
 374 out:
 375         platform_device_unregister(pdev);
 376
 377         if (err) {
 378                 if (err != -EINVAL)
 379                         printk(KERN_ERR
 380                                "ni_cp: Failed to load firmware \"%s\"\n",
 381                                fw_name);
 382                 release_firmware(rdev->pfp_fw);
 383                 rdev->pfp_fw = NULL;
 384                 release_firmware(rdev->me_fw);
 385                 rdev->me_fw = NULL;
 386                 release_firmware(rdev->rlc_fw);
 387                 rdev->rlc_fw = NULL;
 388                 release_firmware(rdev->mc_fw);
 389                 rdev->mc_fw = NULL;
 390         }
 391         return err;
 392 }
 393
 394 /*
 395  * Core functions
 396  */
 397 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 398                                                u32 num_tile_pipes,
 399                                                u32 num_backends_per_asic,
 400                                                u32 *backend_disable_mask_per_asic,
 401                                                u32 num_shader_engines)
 402 {
 403         u32 backend_map = 0;
 404         u32 enabled_backends_mask = 0;
 405         u32 enabled_backends_count = 0;
 406         u32 num_backends_per_se;
 407         u32 cur_pipe;
 408         u32 swizzle_pipe[CAYMAN_MAX_PIPES];
 409         u32 cur_backend = 0;
 410         u32 i;
 411         bool force_no_swizzle;
 412
 413         /* force legal values */
 414         if (num_tile_pipes < 1)
 415                 num_tile_pipes = 1;
 416         if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
 417                 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 418         if (num_shader_engines < 1)
 419                 num_shader_engines = 1;
 420         if (num_shader_engines > rdev->config.cayman.max_shader_engines)
 421                 num_shader_engines = rdev->config.cayman.max_shader_engines;
 422         if (num_backends_per_asic < num_shader_engines)
 423                 num_backends_per_asic = num_shader_engines;
 424         if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
 425                 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
 426
 427         /* make sure we have the same number of backends per se */
 428         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 429         /* set up the number of backends per se */
 430         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 431         if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
 432                 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
 433                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 434         }
 435
 436         /* create enable mask and count for enabled backends */
 437         for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 438                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 439                         enabled_backends_mask |= (1 << i);
 440                         ++enabled_backends_count;
 441                 }
 442                 if (enabled_backends_count == num_backends_per_asic)
 443                         break;
 444         }
 445
 446         /* force the backends mask to match the current number of backends */
 447         if (enabled_backends_count != num_backends_per_asic) {
 448                 u32 this_backend_enabled;
 449                 u32 shader_engine;
 450                 u32 backend_per_se;
 451
 452                 enabled_backends_mask = 0;
 453                 enabled_backends_count = 0;
 454                 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
 455                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 456                         /* calc the current se */
 457                         shader_engine = i / rdev->config.cayman.max_backends_per_se;
 458                         /* calc the backend per se */
 459                         backend_per_se = i % rdev->config.cayman.max_backends_per_se;
 460                         /* default to not enabled */
 461                         this_backend_enabled = 0;
 462                         if ((shader_engine < num_shader_engines) &&
 463                             (backend_per_se < num_backends_per_se))
 464                                 this_backend_enabled = 1;
 465                         if (this_backend_enabled) {
 466                                 enabled_backends_mask |= (1 << i);
 467                                 *backend_disable_mask_per_asic &= ~(1 << i);
 468                                 ++enabled_backends_count;
 469                         }
 470                 }
 471         }
 472
 473
 474         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
 475         switch (rdev->family) {
 476         case CHIP_CAYMAN:
 477                 force_no_swizzle = true;
 478                 break;
 479         default:
 480                 force_no_swizzle = false;
 481                 break;
 482         }
 483         if (force_no_swizzle) {
 484                 bool last_backend_enabled = false;
 485
 486                 force_no_swizzle = false;
 487                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 488                         if (((enabled_backends_mask >> i) & 1) == 1) {
 489                                 if (last_backend_enabled)
 490                                         force_no_swizzle = true;
 491                                 last_backend_enabled = true;
 492                         } else
 493                                 last_backend_enabled = false;
 494                 }
 495         }
 496
 497         switch (num_tile_pipes) {
 498         case 1:
 499         case 3:
 500         case 5:
 501         case 7:
 502                 DRM_ERROR("odd number of pipes!\n");
 503                 break;
 504         case 2:
 505                 swizzle_pipe[0] = 0;
 506                 swizzle_pipe[1] = 1;
 507                 break;
 508         case 4:
 509                 if (force_no_swizzle) {
 510                         swizzle_pipe[0] = 0;
 511                         swizzle_pipe[1] = 1;
 512                         swizzle_pipe[2] = 2;
 513                         swizzle_pipe[3] = 3;
 514                 } else {
 515                         swizzle_pipe[0] = 0;
 516                         swizzle_pipe[1] = 2;
 517                         swizzle_pipe[2] = 1;
 518                         swizzle_pipe[3] = 3;
 519                 }
 520                 break;
 521         case 6:
 522                 if (force_no_swizzle) {
 523                         swizzle_pipe[0] = 0;
 524                         swizzle_pipe[1] = 1;
 525                         swizzle_pipe[2] = 2;
 526                         swizzle_pipe[3] = 3;
 527                         swizzle_pipe[4] = 4;
 528                         swizzle_pipe[5] = 5;
 529                 } else {
 530                         swizzle_pipe[0] = 0;
 531                         swizzle_pipe[1] = 2;
 532                         swizzle_pipe[2] = 4;
 533                         swizzle_pipe[3] = 1;
 534                         swizzle_pipe[4] = 3;
 535                         swizzle_pipe[5] = 5;
 536                 }
 537                 break;
 538         case 8:
 539                 if (force_no_swizzle) {
 540                         swizzle_pipe[0] = 0;
 541                         swizzle_pipe[1] = 1;
 542                         swizzle_pipe[2] = 2;
 543                         swizzle_pipe[3] = 3;
 544                         swizzle_pipe[4] = 4;
 545                         swizzle_pipe[5] = 5;
 546                         swizzle_pipe[6] = 6;
 547                         swizzle_pipe[7] = 7;
 548                 } else {
 549                         swizzle_pipe[0] = 0;
 550                         swizzle_pipe[1] = 2;
 551                         swizzle_pipe[2] = 4;
 552                         swizzle_pipe[3] = 6;
 553                         swizzle_pipe[4] = 1;
 554                         swizzle_pipe[5] = 3;
 555                         swizzle_pipe[6] = 5;
 556                         swizzle_pipe[7] = 7;
 557                 }
 558                 break;
 559         }
 560
 561         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 562                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 563                         cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 564
 565                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 566
 567                 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 568         }
 569
 570         return backend_map;
 571 }
 572
 573 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
 574                                             u32 disable_mask_per_se,
 575                                             u32 max_disable_mask_per_se,
 576                                             u32 num_shader_engines)
 577 {
 578         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
 579         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
 580
 581         if (num_shader_engines == 1)
 582                 return disable_mask_per_asic;
 583         else if (num_shader_engines == 2)
 584                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
 585         else
 586                 return 0xffffffff;
 587 }
 588
 589 static void cayman_gpu_init(struct radeon_device *rdev)
 590 {
 591         u32 cc_rb_backend_disable = 0;
 592         u32 cc_gc_shader_pipe_config;
 593         u32 gb_addr_config = 0;
 594         u32 mc_shared_chmap, mc_arb_ramcfg;
 595         u32 gb_backend_map;
 596         u32 cgts_tcc_disable;
 597         u32 sx_debug_1;
 598         u32 smx_dc_ctl0;
 599         u32 gc_user_shader_pipe_config;
 600         u32 gc_user_rb_backend_disable;
 601         u32 cgts_user_tcc_disable;
 602         u32 cgts_sm_ctrl_reg;
 603         u32 hdp_host_path_cntl;
 604         u32 tmp;
 605         int i, j;
 606
 607         switch (rdev->family) {
 608         case CHIP_CAYMAN:
 609         default:
 610                 rdev->config.cayman.max_shader_engines = 2;
 611                 rdev->config.cayman.max_pipes_per_simd = 4;
 612                 rdev->config.cayman.max_tile_pipes = 8;
 613                 rdev->config.cayman.max_simds_per_se = 12;
 614                 rdev->config.cayman.max_backends_per_se = 4;
 615                 rdev->config.cayman.max_texture_channel_caches = 8;
 616                 rdev->config.cayman.max_gprs = 256;
 617                 rdev->config.cayman.max_threads = 256;
 618                 rdev->config.cayman.max_gs_threads = 32;
 619                 rdev->config.cayman.max_stack_entries = 512;
 620                 rdev->config.cayman.sx_num_of_sets = 8;
 621                 rdev->config.cayman.sx_max_export_size = 256;
 622                 rdev->config.cayman.sx_max_export_pos_size = 64;
 623                 rdev->config.cayman.sx_max_export_smx_size = 192;
 624                 rdev->config.cayman.max_hw_contexts = 8;
 625                 rdev->config.cayman.sq_num_cf_insts = 2;
 626
 627                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 628                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 629                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 630                 break;
 631         }
 632
 633         /* Initialize HDP */
 634         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 635                 WREG32((0x2c14 + j), 0x00000000);
 636                 WREG32((0x2c18 + j), 0x00000000);
 637                 WREG32((0x2c1c + j), 0x00000000);
 638                 WREG32((0x2c20 + j), 0x00000000);
 639                 WREG32((0x2c24 + j), 0x00000000);
 640         }
 641
 642         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 643
 644         evergreen_fix_pci_max_read_req_size(rdev);
 645
 646         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 647         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 648
 649         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 650         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
 651         cgts_tcc_disable = 0xff000000;
 652         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 653         gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 654         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
 655
 656         rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
 657         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
 658         rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
 659         rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 660         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
 661         rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
 662         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 663         rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
 664         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 665         rdev->config.cayman.backend_disable_mask_per_asic =
 666                 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
 667                                                  rdev->config.cayman.num_shader_engines);
 668         rdev->config.cayman.backend_map =
 669                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 670                                                     rdev->config.cayman.num_backends_per_se *
 671                                                     rdev->config.cayman.num_shader_engines,
 672                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 673                                                     rdev->config.cayman.num_shader_engines);
 674         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
 675         rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
 676         tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
 677         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 678         if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
 679                 rdev->config.cayman.mem_max_burst_length_bytes = 512;
 680         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 681         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 682         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 683                 rdev->config.cayman.mem_row_size_in_kb = 4;
 684         /* XXX use MC settings? */
 685         rdev->config.cayman.shader_engine_tile_size = 32;
 686         rdev->config.cayman.num_gpus = 1;
 687         rdev->config.cayman.multi_gpu_tile_size = 64;
 688
 689         //gb_addr_config = 0x02011003
 690 #if 0
 691         gb_addr_config = RREG32(GB_ADDR_CONFIG);
 692 #else
 693         gb_addr_config = 0;
 694         switch (rdev->config.cayman.num_tile_pipes) {
 695         case 1:
 696         default:
 697                 gb_addr_config |= NUM_PIPES(0);
 698                 break;
 699         case 2:
 700                 gb_addr_config |= NUM_PIPES(1);
 701                 break;
 702         case 4:
 703                 gb_addr_config |= NUM_PIPES(2);
 704                 break;
 705         case 8:
 706                 gb_addr_config |= NUM_PIPES(3);
 707                 break;
 708         }
 709
 710         tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
 711         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
 712         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
 713         tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
 714         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
 715         switch (rdev->config.cayman.num_gpus) {
 716         case 1:
 717         default:
 718                 gb_addr_config |= NUM_GPUS(0);
 719                 break;
 720         case 2:
 721                 gb_addr_config |= NUM_GPUS(1);
 722                 break;
 723         case 4:
 724                 gb_addr_config |= NUM_GPUS(2);
 725                 break;
 726         }
 727         switch (rdev->config.cayman.multi_gpu_tile_size) {
 728         case 16:
 729                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
 730                 break;
 731         case 32:
 732         default:
 733                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
 734                 break;
 735         case 64:
 736                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
 737                 break;
 738         case 128:
 739                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
 740                 break;
 741         }
 742         switch (rdev->config.cayman.mem_row_size_in_kb) {
 743         case 1:
 744         default:
 745                 gb_addr_config |= ROW_SIZE(0);
 746                 break;
 747         case 2:
 748                 gb_addr_config |= ROW_SIZE(1);
 749                 break;
 750         case 4:
 751                 gb_addr_config |= ROW_SIZE(2);
 752                 break;
 753         }
 754 #endif
 755
 756         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 757         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 758         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 759         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 760         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 761         rdev->config.cayman.num_shader_engines = tmp + 1;
 762         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 763         rdev->config.cayman.num_gpus = tmp + 1;
 764         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 765         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 766         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 767         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 768
 769         //gb_backend_map = 0x76541032;
 770 #if 0
 771         gb_backend_map = RREG32(GB_BACKEND_MAP);
 772 #else
 773         gb_backend_map =
 774                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 775                                                     rdev->config.cayman.num_backends_per_se *
 776                                                     rdev->config.cayman.num_shader_engines,
 777                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 778                                                     rdev->config.cayman.num_shader_engines);
 779 #endif
 780         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 781          * not have bank info, so create a custom tiling dword.
 782          * bits 3:0   num_pipes
 783          * bits 7:4   num_banks
 784          * bits 11:8  group_size
 785          * bits 15:12 row_size
 786          */
 787         rdev->config.cayman.tile_config = 0;
 788         switch (rdev->config.cayman.num_tile_pipes) {
 789         case 1:
 790         default:
 791                 rdev->config.cayman.tile_config |= (0 << 0);
 792                 break;
 793         case 2:
 794                 rdev->config.cayman.tile_config |= (1 << 0);
 795                 break;
 796         case 4:
 797                 rdev->config.cayman.tile_config |= (2 << 0);
 798                 break;
 799         case 8:
 800                 rdev->config.cayman.tile_config |= (3 << 0);
 801                 break;
 802         }
 803         rdev->config.cayman.tile_config |=
 804                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
 805         rdev->config.cayman.tile_config |=
 806                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 807         rdev->config.cayman.tile_config |=
 808                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 809
 810         rdev->config.cayman.backend_map = gb_backend_map;
 811         WREG32(GB_BACKEND_MAP, gb_backend_map);
 812         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 813         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 814         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 815
 816         /* primary versions */
 817         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 818         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 819         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 820
 821         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 822         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 823
 824         /* user versions */
 825         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 826         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 827         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 828
 829         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 830         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 831
 832         /* reprogram the shader complex */
 833         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 834         for (i = 0; i < 16; i++)
 835                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 836         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 837
 838         /* set HW defaults for 3D engine */
 839         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 840
 841         sx_debug_1 = RREG32(SX_DEBUG_1);
 842         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 843         WREG32(SX_DEBUG_1, sx_debug_1);
 844
 845         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 846         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 847         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 848         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 849
 850         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 851
 852         /* need to be explicitly zero-ed */
 853         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 854         WREG32(SQ_LSTMP_RING_BASE, 0);
 855         WREG32(SQ_HSTMP_RING_BASE, 0);
 856         WREG32(SQ_ESTMP_RING_BASE, 0);
 857         WREG32(SQ_GSTMP_RING_BASE, 0);
 858         WREG32(SQ_VSTMP_RING_BASE, 0);
 859         WREG32(SQ_PSTMP_RING_BASE, 0);
 860
 861         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 862
 863         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 864                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 865                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 866
 867         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 868                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 869                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 870
 871
 872         WREG32(VGT_NUM_INSTANCES, 1);
 873
 874         WREG32(CP_PERFMON_CNTL, 0);
 875
 876         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 877                                   FETCH_FIFO_HIWATER(0x4) |
 878                                   DONE_FIFO_HIWATER(0xe0) |
 879                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 880
 881         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 882         WREG32(SQ_CONFIG, (VC_ENABLE |
 883                            EXPORT_SRC_C |
 884                            GFX_PRIO(0) |
 885                            CS1_PRIO(0) |
 886                            CS2_PRIO(1)));
 887         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 888
 889         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 890                                           FORCE_EOV_MAX_REZ_CNT(255)));
 891
 892         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 893                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 894
 895         WREG32(VGT_GS_VERTEX_REUSE, 16);
 896         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 897
 898         WREG32(CB_PERF_CTR0_SEL_0, 0);
 899         WREG32(CB_PERF_CTR0_SEL_1, 0);
 900         WREG32(CB_PERF_CTR1_SEL_0, 0);
 901         WREG32(CB_PERF_CTR1_SEL_1, 0);
 902         WREG32(CB_PERF_CTR2_SEL_0, 0);
 903         WREG32(CB_PERF_CTR2_SEL_1, 0);
 904         WREG32(CB_PERF_CTR3_SEL_0, 0);
 905         WREG32(CB_PERF_CTR3_SEL_1, 0);
 906
 907         tmp = RREG32(HDP_MISC_CNTL);
 908         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 909         WREG32(HDP_MISC_CNTL, tmp);
 910
 911         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 912         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 913
 914         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 915
 916         udelay(50);
 917 }
 918
 919 /*
 920  * GART
 921  */
 922 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 923 {
 924         /* flush hdp cache */
 925         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 926
 927         /* bits 0-7 are the VM contexts0-7 */
 928         WREG32(VM_INVALIDATE_REQUEST, 1);
 929 }
 930
 931 int cayman_pcie_gart_enable(struct radeon_device *rdev)
 932 {
 933         int r;
 934
 935         if (rdev->gart.table.vram.robj == NULL) {
 936                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 937                 return -EINVAL;
 938         }
 939         r = radeon_gart_table_vram_pin(rdev);
 940         if (r)
 941                 return r;
 942         radeon_gart_restore(rdev);
 943         /* Setup TLB control */
 944         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
 945                ENABLE_L1_FRAGMENT_PROCESSING |
 946                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 947                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 948         /* Setup L2 cache */
 949         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
 950                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 951                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 952                EFFECTIVE_L2_QUEUE_SIZE(7) |
 953                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 954         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
 955         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 956                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 957         /* setup context0 */
 958         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 959         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 960         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 961         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 962                         (u32)(rdev->dummy_page.addr >> 12));
 963         WREG32(VM_CONTEXT0_CNTL2, 0);
 964         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 965                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 966         /* disable context1-7 */
 967         WREG32(VM_CONTEXT1_CNTL2, 0);
 968         WREG32(VM_CONTEXT1_CNTL, 0);
 969
 970         cayman_pcie_gart_tlb_flush(rdev);
 971         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 972                  (unsigned)(rdev->mc.gtt_size >> 20),
 973                  (unsigned long long)rdev->gart.table_addr);
 974         rdev->gart.ready = true;
 975         return 0;
 976 }
 977
 978 void cayman_pcie_gart_disable(struct radeon_device *rdev)
 979 {
 980         int r;
 981
 982         /* Disable all tables */
 983         WREG32(VM_CONTEXT0_CNTL, 0);
 984         WREG32(VM_CONTEXT1_CNTL, 0);
 985         /* Setup TLB control */
 986         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
 987                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 988                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 989         /* Setup L2 cache */
 990         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 991                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 992                EFFECTIVE_L2_QUEUE_SIZE(7) |
 993                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 994         WREG32(VM_L2_CNTL2, 0);
 995         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 996                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 997         if (rdev->gart.table.vram.robj) {
 998                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 999                 if (likely(r == 0)) {
1000                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1001                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1002                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1003                 }
1004         }
1005 }
1006
1007 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1008 {
1009         cayman_pcie_gart_disable(rdev);
1010         radeon_gart_table_vram_free(rdev);
1011         radeon_gart_fini(rdev);
1012 }
1013
1014 /*
1015  * CP.
1016  */
1017 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1018 {
1019         if (enable)
1020                 WREG32(CP_ME_CNTL, 0);
1021         else {
1022                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1023                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1024                 WREG32(SCRATCH_UMSK, 0);
1025         }
1026 }
1027
1028 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1029 {
1030         const __be32 *fw_data;
1031         int i;
1032
1033         if (!rdev->me_fw || !rdev->pfp_fw)
1034                 return -EINVAL;
1035
1036         cayman_cp_enable(rdev, false);
1037
1038         fw_data = (const __be32 *)rdev->pfp_fw->data;
1039         WREG32(CP_PFP_UCODE_ADDR, 0);
1040         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1041                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1042         WREG32(CP_PFP_UCODE_ADDR, 0);
1043
1044         fw_data = (const __be32 *)rdev->me_fw->data;
1045         WREG32(CP_ME_RAM_WADDR, 0);
1046         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1047                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1048
1049         WREG32(CP_PFP_UCODE_ADDR, 0);
1050         WREG32(CP_ME_RAM_WADDR, 0);
1051         WREG32(CP_ME_RAM_RADDR, 0);
1052         return 0;
1053 }
1054
1055 static int cayman_cp_start(struct radeon_device *rdev)
1056 {
1057         int r, i;
1058
1059         r = radeon_ring_lock(rdev, 7);
1060         if (r) {
1061                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1062                 return r;
1063         }
1064         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1065         radeon_ring_write(rdev, 0x1);
1066         radeon_ring_write(rdev, 0x0);
1067         radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
1068         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1069         radeon_ring_write(rdev, 0);
1070         radeon_ring_write(rdev, 0);
1071         radeon_ring_unlock_commit(rdev);
1072
1073         cayman_cp_enable(rdev, true);
1074
1075         r = radeon_ring_lock(rdev, cayman_default_size + 19);
1076         if (r) {
1077                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1078                 return r;
1079         }
1080
1081         /* setup clear context state */
1082         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1083         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1084
1085         for (i = 0; i < cayman_default_size; i++)
1086                 radeon_ring_write(rdev, cayman_default_state[i]);
1087
1088         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1089         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1090
1091         /* set clear context state */
1092         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1093         radeon_ring_write(rdev, 0);
1094
1095         /* SQ_VTX_BASE_VTX_LOC */
1096         radeon_ring_write(rdev, 0xc0026f00);
1097         radeon_ring_write(rdev, 0x00000000);
1098         radeon_ring_write(rdev, 0x00000000);
1099         radeon_ring_write(rdev, 0x00000000);
1100
1101         /* Clear consts */
1102         radeon_ring_write(rdev, 0xc0036f00);
1103         radeon_ring_write(rdev, 0x00000bc4);
1104         radeon_ring_write(rdev, 0xffffffff);
1105         radeon_ring_write(rdev, 0xffffffff);
1106         radeon_ring_write(rdev, 0xffffffff);
1107
1108         radeon_ring_write(rdev, 0xc0026900);
1109         radeon_ring_write(rdev, 0x00000316);
1110         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1111         radeon_ring_write(rdev, 0x00000010); /*  */
1112
1113         radeon_ring_unlock_commit(rdev);
1114
1115         /* XXX init other rings */
1116
1117         return 0;
1118 }
1119
1120 static void cayman_cp_fini(struct radeon_device *rdev)
1121 {
1122         cayman_cp_enable(rdev, false);
1123         radeon_ring_fini(rdev);
1124 }
1125
1126 int cayman_cp_resume(struct radeon_device *rdev)
1127 {
1128         u32 tmp;
1129         u32 rb_bufsz;
1130         int r;
1131
1132         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1133         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1134                                  SOFT_RESET_PA |
1135                                  SOFT_RESET_SH |
1136                                  SOFT_RESET_VGT |
1137                                  SOFT_RESET_SPI |
1138                                  SOFT_RESET_SX));
1139         RREG32(GRBM_SOFT_RESET);
1140         mdelay(15);
1141         WREG32(GRBM_SOFT_RESET, 0);
1142         RREG32(GRBM_SOFT_RESET);
1143
1144         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1145
1146         /* Set the write pointer delay */
1147         WREG32(CP_RB_WPTR_DELAY, 0);
1148
1149         WREG32(CP_DEBUG, (1 << 27));
1150
1151         /* ring 0 - compute and gfx */
1152         /* Set ring buffer size */
1153         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1154         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1155 #ifdef __BIG_ENDIAN
1156         tmp |= BUF_SWAP_32BIT;
1157 #endif
1158         WREG32(CP_RB0_CNTL, tmp);
1159
1160         /* Initialize the ring buffer's read and write pointers */
1161         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1162         rdev->cp.wptr = 0;
1163         WREG32(CP_RB0_WPTR, rdev->cp.wptr);
1164
1165         /* set the wb address wether it's enabled or not */
1166         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1167         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1168         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1169
1170         if (rdev->wb.enabled)
1171                 WREG32(SCRATCH_UMSK, 0xff);
1172         else {
1173                 tmp |= RB_NO_UPDATE;
1174                 WREG32(SCRATCH_UMSK, 0);
1175         }
1176
1177         mdelay(1);
1178         WREG32(CP_RB0_CNTL, tmp);
1179
1180         WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
1181
1182         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1183
1184         /* ring1  - compute only */
1185         /* Set ring buffer size */
1186         rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
1187         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1188 #ifdef __BIG_ENDIAN
1189         tmp |= BUF_SWAP_32BIT;
1190 #endif
1191         WREG32(CP_RB1_CNTL, tmp);
1192
1193         /* Initialize the ring buffer's read and write pointers */
1194         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1195         rdev->cp1.wptr = 0;
1196         WREG32(CP_RB1_WPTR, rdev->cp1.wptr);
1197
1198         /* set the wb address wether it's enabled or not */
1199         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1200         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1201
1202         mdelay(1);
1203         WREG32(CP_RB1_CNTL, tmp);
1204
1205         WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
1206
1207         rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
1208
1209         /* ring2 - compute only */
1210         /* Set ring buffer size */
1211         rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
1212         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1213 #ifdef __BIG_ENDIAN
1214         tmp |= BUF_SWAP_32BIT;
1215 #endif
1216         WREG32(CP_RB2_CNTL, tmp);
1217
1218         /* Initialize the ring buffer's read and write pointers */
1219         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1220         rdev->cp2.wptr = 0;
1221         WREG32(CP_RB2_WPTR, rdev->cp2.wptr);
1222
1223         /* set the wb address wether it's enabled or not */
1224         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1225         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1226
1227         mdelay(1);
1228         WREG32(CP_RB2_CNTL, tmp);
1229
1230         WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
1231
1232         rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
1233
1234         /* start the rings */
1235         cayman_cp_start(rdev);
1236         rdev->cp.ready = true;
1237         rdev->cp1.ready = true;
1238         rdev->cp2.ready = true;
1239         /* this only test cp0 */
1240         r = radeon_ring_test(rdev);
1241         if (r) {
1242                 rdev->cp.ready = false;
1243                 rdev->cp1.ready = false;
1244                 rdev->cp2.ready = false;
1245                 return r;
1246         }
1247
1248         return 0;
1249 }
1250
1251 bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1252 {
1253         u32 srbm_status;
1254         u32 grbm_status;
1255         u32 grbm_status_se0, grbm_status_se1;
1256         struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1257         int r;
1258
1259         srbm_status = RREG32(SRBM_STATUS);
1260         grbm_status = RREG32(GRBM_STATUS);
1261         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1262         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1263         if (!(grbm_status & GUI_ACTIVE)) {
1264                 r100_gpu_lockup_update(lockup, &rdev->cp);
1265                 return false;
1266         }
1267         /* force CP activities */
1268         r = radeon_ring_lock(rdev, 2);
1269         if (!r) {
1270                 /* PACKET2 NOP */
1271                 radeon_ring_write(rdev, 0x80000000);
1272                 radeon_ring_write(rdev, 0x80000000);
1273                 radeon_ring_unlock_commit(rdev);
1274         }
1275         /* XXX deal with CP0,1,2 */
1276         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1277         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1278 }
1279
1280 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1281 {
1282         struct evergreen_mc_save save;
1283         u32 grbm_reset = 0;
1284
1285         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1286                 return 0;
1287
1288         dev_info(rdev->dev, "GPU softreset \n");
1289         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1290                 RREG32(GRBM_STATUS));
1291         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1292                 RREG32(GRBM_STATUS_SE0));
1293         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1294                 RREG32(GRBM_STATUS_SE1));
1295         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1296                 RREG32(SRBM_STATUS));
1297         evergreen_mc_stop(rdev, &save);
1298         if (evergreen_mc_wait_for_idle(rdev)) {
1299                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1300         }
1301         /* Disable CP parsing/prefetching */
1302         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1303
1304         /* reset all the gfx blocks */
1305         grbm_reset = (SOFT_RESET_CP |
1306                       SOFT_RESET_CB |
1307                       SOFT_RESET_DB |
1308                       SOFT_RESET_GDS |
1309                       SOFT_RESET_PA |
1310                       SOFT_RESET_SC |
1311                       SOFT_RESET_SPI |
1312                       SOFT_RESET_SH |
1313                       SOFT_RESET_SX |
1314                       SOFT_RESET_TC |
1315                       SOFT_RESET_TA |
1316                       SOFT_RESET_VGT |
1317                       SOFT_RESET_IA);
1318
1319         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1320         WREG32(GRBM_SOFT_RESET, grbm_reset);
1321         (void)RREG32(GRBM_SOFT_RESET);
1322         udelay(50);
1323         WREG32(GRBM_SOFT_RESET, 0);
1324         (void)RREG32(GRBM_SOFT_RESET);
1325         /* Wait a little for things to settle down */
1326         udelay(50);
1327         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1328                 RREG32(GRBM_STATUS));
1329         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1330                 RREG32(GRBM_STATUS_SE0));
1331         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1332                 RREG32(GRBM_STATUS_SE1));
1333         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1334                 RREG32(SRBM_STATUS));
1335         evergreen_mc_resume(rdev, &save);
1336         return 0;
1337 }
1338
1339 int cayman_asic_reset(struct radeon_device *rdev)
1340 {
1341         return cayman_gpu_soft_reset(rdev);
1342 }
1343
1344 static int cayman_startup(struct radeon_device *rdev)
1345 {
1346         int r;
1347
1348         /* enable pcie gen2 link */
1349         evergreen_pcie_gen2_enable(rdev);
1350
1351         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1352                 r = ni_init_microcode(rdev);
1353                 if (r) {
1354                         DRM_ERROR("Failed to load firmware!\n");
1355                         return r;
1356                 }
1357         }
1358         r = ni_mc_load_microcode(rdev);
1359         if (r) {
1360                 DRM_ERROR("Failed to load MC firmware!\n");
1361                 return r;
1362         }
1363
1364         evergreen_mc_program(rdev);
1365         r = cayman_pcie_gart_enable(rdev);
1366         if (r)
1367                 return r;
1368         cayman_gpu_init(rdev);
1369
1370         r = evergreen_blit_init(rdev);
1371         if (r) {
1372                 r600_blit_fini(rdev);
1373                 rdev->asic->copy = NULL;
1374                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1375         }
1376
1377         /* allocate wb buffer */
1378         r = radeon_wb_init(rdev);
1379         if (r)
1380                 return r;
1381
1382         /* Enable IRQ */
1383         r = r600_irq_init(rdev);
1384         if (r) {
1385                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1386                 radeon_irq_kms_fini(rdev);
1387                 return r;
1388         }
1389         evergreen_irq_set(rdev);
1390
1391         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1392         if (r)
1393                 return r;
1394         r = cayman_cp_load_microcode(rdev);
1395         if (r)
1396                 return r;
1397         r = cayman_cp_resume(rdev);
1398         if (r)
1399                 return r;
1400
1401         return 0;
1402 }
1403
1404 int cayman_resume(struct radeon_device *rdev)
1405 {
1406         int r;
1407
1408         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1409          * posting will perform necessary task to bring back GPU into good
1410          * shape.
1411          */
1412         /* post card */
1413         atom_asic_init(rdev->mode_info.atom_context);
1414
1415         r = cayman_startup(rdev);
1416         if (r) {
1417                 DRM_ERROR("cayman startup failed on resume\n");
1418                 return r;
1419         }
1420
1421         r = r600_ib_test(rdev);
1422         if (r) {
1423                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1424                 return r;
1425         }
1426
1427         return r;
1428
1429 }
1430
1431 int cayman_suspend(struct radeon_device *rdev)
1432 {
1433         /* FIXME: we should wait for ring to be empty */
1434         cayman_cp_enable(rdev, false);
1435         rdev->cp.ready = false;
1436         evergreen_irq_suspend(rdev);
1437         radeon_wb_disable(rdev);
1438         cayman_pcie_gart_disable(rdev);
1439         r600_blit_suspend(rdev);
1440
1441         return 0;
1442 }
1443
1444 /* Plan is to move initialization in that function and use
1445  * helper function so that radeon_device_init pretty much
1446  * do nothing more than calling asic specific function. This
1447  * should also allow to remove a bunch of callback function
1448  * like vram_info.
1449  */
1450 int cayman_init(struct radeon_device *rdev)
1451 {
1452         int r;
1453
1454         /* This don't do much */
1455         r = radeon_gem_init(rdev);
1456         if (r)
1457                 return r;
1458         /* Read BIOS */
1459         if (!radeon_get_bios(rdev)) {
1460                 if (ASIC_IS_AVIVO(rdev))
1461                         return -EINVAL;
1462         }
1463         /* Must be an ATOMBIOS */
1464         if (!rdev->is_atom_bios) {
1465                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1466                 return -EINVAL;
1467         }
1468         r = radeon_atombios_init(rdev);
1469         if (r)
1470                 return r;
1471
1472         /* Post card if necessary */
1473         if (!radeon_card_posted(rdev)) {
1474                 if (!rdev->bios) {
1475                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1476                         return -EINVAL;
1477                 }
1478                 DRM_INFO("GPU not posted. posting now...\n");
1479                 atom_asic_init(rdev->mode_info.atom_context);
1480         }
1481         /* Initialize scratch registers */
1482         r600_scratch_init(rdev);
1483         /* Initialize surface registers */
1484         radeon_surface_init(rdev);
1485         /* Initialize clocks */
1486         radeon_get_clock_info(rdev->ddev);
1487         /* Fence driver */
1488         r = radeon_fence_driver_init(rdev);
1489         if (r)
1490                 return r;
1491         /* initialize memory controller */
1492         r = evergreen_mc_init(rdev);
1493         if (r)
1494                 return r;
1495         /* Memory manager */
1496         r = radeon_bo_init(rdev);
1497         if (r)
1498                 return r;
1499
1500         r = radeon_irq_kms_init(rdev);
1501         if (r)
1502                 return r;
1503
1504         rdev->cp.ring_obj = NULL;
1505         r600_ring_init(rdev, 1024 * 1024);
1506
1507         rdev->ih.ring_obj = NULL;
1508         r600_ih_ring_init(rdev, 64 * 1024);
1509
1510         r = r600_pcie_gart_init(rdev);
1511         if (r)
1512                 return r;
1513
1514         rdev->accel_working = true;
1515         r = cayman_startup(rdev);
1516         if (r) {
1517                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1518                 cayman_cp_fini(rdev);
1519                 r600_irq_fini(rdev);
1520                 radeon_wb_fini(rdev);
1521                 radeon_irq_kms_fini(rdev);
1522                 cayman_pcie_gart_fini(rdev);
1523                 rdev->accel_working = false;
1524         }
1525         if (rdev->accel_working) {
1526                 r = radeon_ib_pool_init(rdev);
1527                 if (r) {
1528                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1529                         rdev->accel_working = false;
1530                 }
1531                 r = r600_ib_test(rdev);
1532                 if (r) {
1533                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1534                         rdev->accel_working = false;
1535                 }
1536         }
1537
1538         /* Don't start up if the MC ucode is missing.
1539          * The default clocks and voltages before the MC ucode
1540          * is loaded are not suffient for advanced operations.
1541          */
1542         if (!rdev->mc_fw) {
1543                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1544                 return -EINVAL;
1545         }
1546
1547         return 0;
1548 }
1549
1550 void cayman_fini(struct radeon_device *rdev)
1551 {
1552         r600_blit_fini(rdev);
1553         cayman_cp_fini(rdev);
1554         r600_irq_fini(rdev);
1555         radeon_wb_fini(rdev);
1556         radeon_ib_pool_fini(rdev);
1557         radeon_irq_kms_fini(rdev);
1558         cayman_pcie_gart_fini(rdev);
1559         radeon_gem_fini(rdev);
1560         radeon_fence_driver_fini(rdev);
1561         radeon_bo_fini(rdev);
1562         radeon_atombios_fini(rdev);
1563         kfree(rdev->bios);
1564         rdev->bios = NULL;
1565 }
1566