drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "nid.h"
  32 #include "atom.h"
  33 #include "ni_reg.h"
  34 #include "cayman_blit_shaders.h"
  35
  36 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  37 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  39 extern void evergreen_mc_program(struct radeon_device *rdev);
  40 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  41 extern int evergreen_mc_init(struct radeon_device *rdev);
  42 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  43
  44 #define EVERGREEN_PFP_UCODE_SIZE 1120
  45 #define EVERGREEN_PM4_UCODE_SIZE 1376
  46 #define EVERGREEN_RLC_UCODE_SIZE 768
  47 #define BTC_MC_UCODE_SIZE 6024
  48
  49 #define CAYMAN_PFP_UCODE_SIZE 2176
  50 #define CAYMAN_PM4_UCODE_SIZE 2176
  51 #define CAYMAN_RLC_UCODE_SIZE 1024
  52 #define CAYMAN_MC_UCODE_SIZE 6037
  53
  54 /* Firmware Names */
  55 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  56 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  57 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  58 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  59 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  60 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  61 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  62 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  63 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  64 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  65 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  66 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  67 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  68 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  69
  70 #define BTC_IO_MC_REGS_SIZE 29
  71
  72 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  73         {0x00000077, 0xff010100},
  74         {0x00000078, 0x00000000},
  75         {0x00000079, 0x00001434},
  76         {0x0000007a, 0xcc08ec08},
  77         {0x0000007b, 0x00040000},
  78         {0x0000007c, 0x000080c0},
  79         {0x0000007d, 0x09000000},
  80         {0x0000007e, 0x00210404},
  81         {0x00000081, 0x08a8e800},
  82         {0x00000082, 0x00030444},
  83         {0x00000083, 0x00000000},
  84         {0x00000085, 0x00000001},
  85         {0x00000086, 0x00000002},
  86         {0x00000087, 0x48490000},
  87         {0x00000088, 0x20244647},
  88         {0x00000089, 0x00000005},
  89         {0x0000008b, 0x66030000},
  90         {0x0000008c, 0x00006603},
  91         {0x0000008d, 0x00000100},
  92         {0x0000008f, 0x00001c0a},
  93         {0x00000090, 0xff000001},
  94         {0x00000094, 0x00101101},
  95         {0x00000095, 0x00000fff},
  96         {0x00000096, 0x00116fff},
  97         {0x00000097, 0x60010000},
  98         {0x00000098, 0x10010000},
  99         {0x00000099, 0x00006000},
 100         {0x0000009a, 0x00001000},
 101         {0x0000009f, 0x00946a00}
 102 };
 103
 104 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 105         {0x00000077, 0xff010100},
 106         {0x00000078, 0x00000000},
 107         {0x00000079, 0x00001434},
 108         {0x0000007a, 0xcc08ec08},
 109         {0x0000007b, 0x00040000},
 110         {0x0000007c, 0x000080c0},
 111         {0x0000007d, 0x09000000},
 112         {0x0000007e, 0x00210404},
 113         {0x00000081, 0x08a8e800},
 114         {0x00000082, 0x00030444},
 115         {0x00000083, 0x00000000},
 116         {0x00000085, 0x00000001},
 117         {0x00000086, 0x00000002},
 118         {0x00000087, 0x48490000},
 119         {0x00000088, 0x20244647},
 120         {0x00000089, 0x00000005},
 121         {0x0000008b, 0x66030000},
 122         {0x0000008c, 0x00006603},
 123         {0x0000008d, 0x00000100},
 124         {0x0000008f, 0x00001c0a},
 125         {0x00000090, 0xff000001},
 126         {0x00000094, 0x00101101},
 127         {0x00000095, 0x00000fff},
 128         {0x00000096, 0x00116fff},
 129         {0x00000097, 0x60010000},
 130         {0x00000098, 0x10010000},
 131         {0x00000099, 0x00006000},
 132         {0x0000009a, 0x00001000},
 133         {0x0000009f, 0x00936a00}
 134 };
 135
 136 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 137         {0x00000077, 0xff010100},
 138         {0x00000078, 0x00000000},
 139         {0x00000079, 0x00001434},
 140         {0x0000007a, 0xcc08ec08},
 141         {0x0000007b, 0x00040000},
 142         {0x0000007c, 0x000080c0},
 143         {0x0000007d, 0x09000000},
 144         {0x0000007e, 0x00210404},
 145         {0x00000081, 0x08a8e800},
 146         {0x00000082, 0x00030444},
 147         {0x00000083, 0x00000000},
 148         {0x00000085, 0x00000001},
 149         {0x00000086, 0x00000002},
 150         {0x00000087, 0x48490000},
 151         {0x00000088, 0x20244647},
 152         {0x00000089, 0x00000005},
 153         {0x0000008b, 0x66030000},
 154         {0x0000008c, 0x00006603},
 155         {0x0000008d, 0x00000100},
 156         {0x0000008f, 0x00001c0a},
 157         {0x00000090, 0xff000001},
 158         {0x00000094, 0x00101101},
 159         {0x00000095, 0x00000fff},
 160         {0x00000096, 0x00116fff},
 161         {0x00000097, 0x60010000},
 162         {0x00000098, 0x10010000},
 163         {0x00000099, 0x00006000},
 164         {0x0000009a, 0x00001000},
 165         {0x0000009f, 0x00916a00}
 166 };
 167
 168 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 169         {0x00000077, 0xff010100},
 170         {0x00000078, 0x00000000},
 171         {0x00000079, 0x00001434},
 172         {0x0000007a, 0xcc08ec08},
 173         {0x0000007b, 0x00040000},
 174         {0x0000007c, 0x000080c0},
 175         {0x0000007d, 0x09000000},
 176         {0x0000007e, 0x00210404},
 177         {0x00000081, 0x08a8e800},
 178         {0x00000082, 0x00030444},
 179         {0x00000083, 0x00000000},
 180         {0x00000085, 0x00000001},
 181         {0x00000086, 0x00000002},
 182         {0x00000087, 0x48490000},
 183         {0x00000088, 0x20244647},
 184         {0x00000089, 0x00000005},
 185         {0x0000008b, 0x66030000},
 186         {0x0000008c, 0x00006603},
 187         {0x0000008d, 0x00000100},
 188         {0x0000008f, 0x00001c0a},
 189         {0x00000090, 0xff000001},
 190         {0x00000094, 0x00101101},
 191         {0x00000095, 0x00000fff},
 192         {0x00000096, 0x00116fff},
 193         {0x00000097, 0x60010000},
 194         {0x00000098, 0x10010000},
 195         {0x00000099, 0x00006000},
 196         {0x0000009a, 0x00001000},
 197         {0x0000009f, 0x00976b00}
 198 };
 199
 200 int ni_mc_load_microcode(struct radeon_device *rdev)
 201 {
 202         const __be32 *fw_data;
 203         u32 mem_type, running, blackout = 0;
 204         u32 *io_mc_regs;
 205         int i, ucode_size, regs_size;
 206
 207         if (!rdev->mc_fw)
 208                 return -EINVAL;
 209
 210         switch (rdev->family) {
 211         case CHIP_BARTS:
 212                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 213                 ucode_size = BTC_MC_UCODE_SIZE;
 214                 regs_size = BTC_IO_MC_REGS_SIZE;
 215                 break;
 216         case CHIP_TURKS:
 217                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 218                 ucode_size = BTC_MC_UCODE_SIZE;
 219                 regs_size = BTC_IO_MC_REGS_SIZE;
 220                 break;
 221         case CHIP_CAICOS:
 222         default:
 223                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 224                 ucode_size = BTC_MC_UCODE_SIZE;
 225                 regs_size = BTC_IO_MC_REGS_SIZE;
 226                 break;
 227         case CHIP_CAYMAN:
 228                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 229                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 230                 regs_size = BTC_IO_MC_REGS_SIZE;
 231                 break;
 232         }
 233
 234         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 235         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 236
 237         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 238                 if (running) {
 239                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 240                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 241                 }
 242
 243                 /* reset the engine and set to writable */
 244                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 245                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 246
 247                 /* load mc io regs */
 248                 for (i = 0; i < regs_size; i++) {
 249                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 250                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 251                 }
 252                 /* load the MC ucode */
 253                 fw_data = (const __be32 *)rdev->mc_fw->data;
 254                 for (i = 0; i < ucode_size; i++)
 255                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 256
 257                 /* put the engine back into the active state */
 258                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 259                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 260                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 261
 262                 /* wait for training to complete */
 263                 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
 264                         udelay(10);
 265
 266                 if (running)
 267                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 268         }
 269
 270         return 0;
 271 }
 272
 273 int ni_init_microcode(struct radeon_device *rdev)
 274 {
 275         struct platform_device *pdev;
 276         const char *chip_name;
 277         const char *rlc_chip_name;
 278         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 279         char fw_name[30];
 280         int err;
 281
 282         DRM_DEBUG("\n");
 283
 284         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 285         err = IS_ERR(pdev);
 286         if (err) {
 287                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 288                 return -EINVAL;
 289         }
 290
 291         switch (rdev->family) {
 292         case CHIP_BARTS:
 293                 chip_name = "BARTS";
 294                 rlc_chip_name = "BTC";
 295                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 296                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 297                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 298                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 299                 break;
 300         case CHIP_TURKS:
 301                 chip_name = "TURKS";
 302                 rlc_chip_name = "BTC";
 303                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 304                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 305                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 306                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 307                 break;
 308         case CHIP_CAICOS:
 309                 chip_name = "CAICOS";
 310                 rlc_chip_name = "BTC";
 311                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 312                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 313                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 314                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 315                 break;
 316         case CHIP_CAYMAN:
 317                 chip_name = "CAYMAN";
 318                 rlc_chip_name = "CAYMAN";
 319                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 320                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 321                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 322                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 323                 break;
 324         default: BUG();
 325         }
 326
 327         DRM_INFO("Loading %s Microcode\n", chip_name);
 328
 329         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 330         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 331         if (err)
 332                 goto out;
 333         if (rdev->pfp_fw->size != pfp_req_size) {
 334                 printk(KERN_ERR
 335                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 336                        rdev->pfp_fw->size, fw_name);
 337                 err = -EINVAL;
 338                 goto out;
 339         }
 340
 341         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 342         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 343         if (err)
 344                 goto out;
 345         if (rdev->me_fw->size != me_req_size) {
 346                 printk(KERN_ERR
 347                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 348                        rdev->me_fw->size, fw_name);
 349                 err = -EINVAL;
 350         }
 351
 352         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 353         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 354         if (err)
 355                 goto out;
 356         if (rdev->rlc_fw->size != rlc_req_size) {
 357                 printk(KERN_ERR
 358                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 359                        rdev->rlc_fw->size, fw_name);
 360                 err = -EINVAL;
 361         }
 362
 363         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 364         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 365         if (err)
 366                 goto out;
 367         if (rdev->mc_fw->size != mc_req_size) {
 368                 printk(KERN_ERR
 369                        "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 370                        rdev->mc_fw->size, fw_name);
 371                 err = -EINVAL;
 372         }
 373 out:
 374         platform_device_unregister(pdev);
 375
 376         if (err) {
 377                 if (err != -EINVAL)
 378                         printk(KERN_ERR
 379                                "ni_cp: Failed to load firmware \"%s\"\n",
 380                                fw_name);
 381                 release_firmware(rdev->pfp_fw);
 382                 rdev->pfp_fw = NULL;
 383                 release_firmware(rdev->me_fw);
 384                 rdev->me_fw = NULL;
 385                 release_firmware(rdev->rlc_fw);
 386                 rdev->rlc_fw = NULL;
 387                 release_firmware(rdev->mc_fw);
 388                 rdev->mc_fw = NULL;
 389         }
 390         return err;
 391 }
 392
 393 /*
 394  * Core functions
 395  */
 396 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 397                                                u32 num_tile_pipes,
 398                                                u32 num_backends_per_asic,
 399                                                u32 *backend_disable_mask_per_asic,
 400                                                u32 num_shader_engines)
 401 {
 402         u32 backend_map = 0;
 403         u32 enabled_backends_mask = 0;
 404         u32 enabled_backends_count = 0;
 405         u32 num_backends_per_se;
 406         u32 cur_pipe;
 407         u32 swizzle_pipe[CAYMAN_MAX_PIPES];
 408         u32 cur_backend = 0;
 409         u32 i;
 410         bool force_no_swizzle;
 411
 412         /* force legal values */
 413         if (num_tile_pipes < 1)
 414                 num_tile_pipes = 1;
 415         if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
 416                 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 417         if (num_shader_engines < 1)
 418                 num_shader_engines = 1;
 419         if (num_shader_engines > rdev->config.cayman.max_shader_engines)
 420                 num_shader_engines = rdev->config.cayman.max_shader_engines;
 421         if (num_backends_per_asic < num_shader_engines)
 422                 num_backends_per_asic = num_shader_engines;
 423         if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
 424                 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
 425
 426         /* make sure we have the same number of backends per se */
 427         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 428         /* set up the number of backends per se */
 429         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 430         if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
 431                 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
 432                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 433         }
 434
 435         /* create enable mask and count for enabled backends */
 436         for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 437                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 438                         enabled_backends_mask |= (1 << i);
 439                         ++enabled_backends_count;
 440                 }
 441                 if (enabled_backends_count == num_backends_per_asic)
 442                         break;
 443         }
 444
 445         /* force the backends mask to match the current number of backends */
 446         if (enabled_backends_count != num_backends_per_asic) {
 447                 u32 this_backend_enabled;
 448                 u32 shader_engine;
 449                 u32 backend_per_se;
 450
 451                 enabled_backends_mask = 0;
 452                 enabled_backends_count = 0;
 453                 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
 454                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 455                         /* calc the current se */
 456                         shader_engine = i / rdev->config.cayman.max_backends_per_se;
 457                         /* calc the backend per se */
 458                         backend_per_se = i % rdev->config.cayman.max_backends_per_se;
 459                         /* default to not enabled */
 460                         this_backend_enabled = 0;
 461                         if ((shader_engine < num_shader_engines) &&
 462                             (backend_per_se < num_backends_per_se))
 463                                 this_backend_enabled = 1;
 464                         if (this_backend_enabled) {
 465                                 enabled_backends_mask |= (1 << i);
 466                                 *backend_disable_mask_per_asic &= ~(1 << i);
 467                                 ++enabled_backends_count;
 468                         }
 469                 }
 470         }
 471
 472
 473         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
 474         switch (rdev->family) {
 475         case CHIP_CAYMAN:
 476                 force_no_swizzle = true;
 477                 break;
 478         default:
 479                 force_no_swizzle = false;
 480                 break;
 481         }
 482         if (force_no_swizzle) {
 483                 bool last_backend_enabled = false;
 484
 485                 force_no_swizzle = false;
 486                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 487                         if (((enabled_backends_mask >> i) & 1) == 1) {
 488                                 if (last_backend_enabled)
 489                                         force_no_swizzle = true;
 490                                 last_backend_enabled = true;
 491                         } else
 492                                 last_backend_enabled = false;
 493                 }
 494         }
 495
 496         switch (num_tile_pipes) {
 497         case 1:
 498         case 3:
 499         case 5:
 500         case 7:
 501                 DRM_ERROR("odd number of pipes!\n");
 502                 break;
 503         case 2:
 504                 swizzle_pipe[0] = 0;
 505                 swizzle_pipe[1] = 1;
 506                 break;
 507         case 4:
 508                 if (force_no_swizzle) {
 509                         swizzle_pipe[0] = 0;
 510                         swizzle_pipe[1] = 1;
 511                         swizzle_pipe[2] = 2;
 512                         swizzle_pipe[3] = 3;
 513                 } else {
 514                         swizzle_pipe[0] = 0;
 515                         swizzle_pipe[1] = 2;
 516                         swizzle_pipe[2] = 1;
 517                         swizzle_pipe[3] = 3;
 518                 }
 519                 break;
 520         case 6:
 521                 if (force_no_swizzle) {
 522                         swizzle_pipe[0] = 0;
 523                         swizzle_pipe[1] = 1;
 524                         swizzle_pipe[2] = 2;
 525                         swizzle_pipe[3] = 3;
 526                         swizzle_pipe[4] = 4;
 527                         swizzle_pipe[5] = 5;
 528                 } else {
 529                         swizzle_pipe[0] = 0;
 530                         swizzle_pipe[1] = 2;
 531                         swizzle_pipe[2] = 4;
 532                         swizzle_pipe[3] = 1;
 533                         swizzle_pipe[4] = 3;
 534                         swizzle_pipe[5] = 5;
 535                 }
 536                 break;
 537         case 8:
 538                 if (force_no_swizzle) {
 539                         swizzle_pipe[0] = 0;
 540                         swizzle_pipe[1] = 1;
 541                         swizzle_pipe[2] = 2;
 542                         swizzle_pipe[3] = 3;
 543                         swizzle_pipe[4] = 4;
 544                         swizzle_pipe[5] = 5;
 545                         swizzle_pipe[6] = 6;
 546                         swizzle_pipe[7] = 7;
 547                 } else {
 548                         swizzle_pipe[0] = 0;
 549                         swizzle_pipe[1] = 2;
 550                         swizzle_pipe[2] = 4;
 551                         swizzle_pipe[3] = 6;
 552                         swizzle_pipe[4] = 1;
 553                         swizzle_pipe[5] = 3;
 554                         swizzle_pipe[6] = 5;
 555                         swizzle_pipe[7] = 7;
 556                 }
 557                 break;
 558         }
 559
 560         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 561                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 562                         cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 563
 564                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 565
 566                 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 567         }
 568
 569         return backend_map;
 570 }
 571
 572 static void cayman_program_channel_remap(struct radeon_device *rdev)
 573 {
 574         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
 575
 576         tmp = RREG32(MC_SHARED_CHMAP);
 577         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 578         case 0:
 579         case 1:
 580         case 2:
 581         case 3:
 582         default:
 583                 /* default mapping */
 584                 mc_shared_chremap = 0x00fac688;
 585                 break;
 586         }
 587
 588         switch (rdev->family) {
 589         case CHIP_CAYMAN:
 590         default:
 591                 //tcp_chan_steer_lo = 0x54763210
 592                 tcp_chan_steer_lo = 0x76543210;
 593                 tcp_chan_steer_hi = 0x0000ba98;
 594                 break;
 595         }
 596
 597         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
 598         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
 599         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
 600 }
 601
 602 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
 603                                             u32 disable_mask_per_se,
 604                                             u32 max_disable_mask_per_se,
 605                                             u32 num_shader_engines)
 606 {
 607         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
 608         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
 609
 610         if (num_shader_engines == 1)
 611                 return disable_mask_per_asic;
 612         else if (num_shader_engines == 2)
 613                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
 614         else
 615                 return 0xffffffff;
 616 }
 617
 618 static void cayman_gpu_init(struct radeon_device *rdev)
 619 {
 620         u32 cc_rb_backend_disable = 0;
 621         u32 cc_gc_shader_pipe_config;
 622         u32 gb_addr_config = 0;
 623         u32 mc_shared_chmap, mc_arb_ramcfg;
 624         u32 gb_backend_map;
 625         u32 cgts_tcc_disable;
 626         u32 sx_debug_1;
 627         u32 smx_dc_ctl0;
 628         u32 gc_user_shader_pipe_config;
 629         u32 gc_user_rb_backend_disable;
 630         u32 cgts_user_tcc_disable;
 631         u32 cgts_sm_ctrl_reg;
 632         u32 hdp_host_path_cntl;
 633         u32 tmp;
 634         int i, j;
 635
 636         switch (rdev->family) {
 637         case CHIP_CAYMAN:
 638         default:
 639                 rdev->config.cayman.max_shader_engines = 2;
 640                 rdev->config.cayman.max_pipes_per_simd = 4;
 641                 rdev->config.cayman.max_tile_pipes = 8;
 642                 rdev->config.cayman.max_simds_per_se = 12;
 643                 rdev->config.cayman.max_backends_per_se = 4;
 644                 rdev->config.cayman.max_texture_channel_caches = 8;
 645                 rdev->config.cayman.max_gprs = 256;
 646                 rdev->config.cayman.max_threads = 256;
 647                 rdev->config.cayman.max_gs_threads = 32;
 648                 rdev->config.cayman.max_stack_entries = 512;
 649                 rdev->config.cayman.sx_num_of_sets = 8;
 650                 rdev->config.cayman.sx_max_export_size = 256;
 651                 rdev->config.cayman.sx_max_export_pos_size = 64;
 652                 rdev->config.cayman.sx_max_export_smx_size = 192;
 653                 rdev->config.cayman.max_hw_contexts = 8;
 654                 rdev->config.cayman.sq_num_cf_insts = 2;
 655
 656                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 657                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 658                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 659                 break;
 660         }
 661
 662         /* Initialize HDP */
 663         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 664                 WREG32((0x2c14 + j), 0x00000000);
 665                 WREG32((0x2c18 + j), 0x00000000);
 666                 WREG32((0x2c1c + j), 0x00000000);
 667                 WREG32((0x2c20 + j), 0x00000000);
 668                 WREG32((0x2c24 + j), 0x00000000);
 669         }
 670
 671         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 672
 673         evergreen_fix_pci_max_read_req_size(rdev);
 674
 675         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 676         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 677
 678         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 679         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
 680         cgts_tcc_disable = 0xff000000;
 681         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 682         gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 683         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
 684
 685         rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
 686         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
 687         rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
 688         rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 689         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
 690         rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
 691         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 692         rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
 693         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 694         rdev->config.cayman.backend_disable_mask_per_asic =
 695                 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
 696                                                  rdev->config.cayman.num_shader_engines);
 697         rdev->config.cayman.backend_map =
 698                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 699                                                     rdev->config.cayman.num_backends_per_se *
 700                                                     rdev->config.cayman.num_shader_engines,
 701                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 702                                                     rdev->config.cayman.num_shader_engines);
 703         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
 704         rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
 705         tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
 706         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 707         if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
 708                 rdev->config.cayman.mem_max_burst_length_bytes = 512;
 709         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 710         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 711         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 712                 rdev->config.cayman.mem_row_size_in_kb = 4;
 713         /* XXX use MC settings? */
 714         rdev->config.cayman.shader_engine_tile_size = 32;
 715         rdev->config.cayman.num_gpus = 1;
 716         rdev->config.cayman.multi_gpu_tile_size = 64;
 717
 718         //gb_addr_config = 0x02011003
 719 #if 0
 720         gb_addr_config = RREG32(GB_ADDR_CONFIG);
 721 #else
 722         gb_addr_config = 0;
 723         switch (rdev->config.cayman.num_tile_pipes) {
 724         case 1:
 725         default:
 726                 gb_addr_config |= NUM_PIPES(0);
 727                 break;
 728         case 2:
 729                 gb_addr_config |= NUM_PIPES(1);
 730                 break;
 731         case 4:
 732                 gb_addr_config |= NUM_PIPES(2);
 733                 break;
 734         case 8:
 735                 gb_addr_config |= NUM_PIPES(3);
 736                 break;
 737         }
 738
 739         tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
 740         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
 741         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
 742         tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
 743         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
 744         switch (rdev->config.cayman.num_gpus) {
 745         case 1:
 746         default:
 747                 gb_addr_config |= NUM_GPUS(0);
 748                 break;
 749         case 2:
 750                 gb_addr_config |= NUM_GPUS(1);
 751                 break;
 752         case 4:
 753                 gb_addr_config |= NUM_GPUS(2);
 754                 break;
 755         }
 756         switch (rdev->config.cayman.multi_gpu_tile_size) {
 757         case 16:
 758                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
 759                 break;
 760         case 32:
 761         default:
 762                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
 763                 break;
 764         case 64:
 765                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
 766                 break;
 767         case 128:
 768                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
 769                 break;
 770         }
 771         switch (rdev->config.cayman.mem_row_size_in_kb) {
 772         case 1:
 773         default:
 774                 gb_addr_config |= ROW_SIZE(0);
 775                 break;
 776         case 2:
 777                 gb_addr_config |= ROW_SIZE(1);
 778                 break;
 779         case 4:
 780                 gb_addr_config |= ROW_SIZE(2);
 781                 break;
 782         }
 783 #endif
 784
 785         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 786         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 787         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 788         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 789         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 790         rdev->config.cayman.num_shader_engines = tmp + 1;
 791         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 792         rdev->config.cayman.num_gpus = tmp + 1;
 793         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 794         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 795         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 796         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 797
 798         //gb_backend_map = 0x76541032;
 799 #if 0
 800         gb_backend_map = RREG32(GB_BACKEND_MAP);
 801 #else
 802         gb_backend_map =
 803                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 804                                                     rdev->config.cayman.num_backends_per_se *
 805                                                     rdev->config.cayman.num_shader_engines,
 806                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 807                                                     rdev->config.cayman.num_shader_engines);
 808 #endif
 809         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 810          * not have bank info, so create a custom tiling dword.
 811          * bits 3:0   num_pipes
 812          * bits 7:4   num_banks
 813          * bits 11:8  group_size
 814          * bits 15:12 row_size
 815          */
 816         rdev->config.cayman.tile_config = 0;
 817         switch (rdev->config.cayman.num_tile_pipes) {
 818         case 1:
 819         default:
 820                 rdev->config.cayman.tile_config |= (0 << 0);
 821                 break;
 822         case 2:
 823                 rdev->config.cayman.tile_config |= (1 << 0);
 824                 break;
 825         case 4:
 826                 rdev->config.cayman.tile_config |= (2 << 0);
 827                 break;
 828         case 8:
 829                 rdev->config.cayman.tile_config |= (3 << 0);
 830                 break;
 831         }
 832         rdev->config.cayman.tile_config |=
 833                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
 834         rdev->config.cayman.tile_config |=
 835                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 836         rdev->config.cayman.tile_config |=
 837                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 838
 839         rdev->config.cayman.backend_map = gb_backend_map;
 840         WREG32(GB_BACKEND_MAP, gb_backend_map);
 841         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 842         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 843         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 844
 845         cayman_program_channel_remap(rdev);
 846
 847         /* primary versions */
 848         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 849         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 850         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 851
 852         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 853         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 854
 855         /* user versions */
 856         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 857         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 858         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 859
 860         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 861         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 862
 863         /* reprogram the shader complex */
 864         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 865         for (i = 0; i < 16; i++)
 866                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 867         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 868
 869         /* set HW defaults for 3D engine */
 870         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 871
 872         sx_debug_1 = RREG32(SX_DEBUG_1);
 873         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 874         WREG32(SX_DEBUG_1, sx_debug_1);
 875
 876         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 877         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 878         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 879         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 880
 881         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 882
 883         /* need to be explicitly zero-ed */
 884         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 885         WREG32(SQ_LSTMP_RING_BASE, 0);
 886         WREG32(SQ_HSTMP_RING_BASE, 0);
 887         WREG32(SQ_ESTMP_RING_BASE, 0);
 888         WREG32(SQ_GSTMP_RING_BASE, 0);
 889         WREG32(SQ_VSTMP_RING_BASE, 0);
 890         WREG32(SQ_PSTMP_RING_BASE, 0);
 891
 892         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 893
 894         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 895                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 896                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 897
 898         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 899                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 900                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 901
 902
 903         WREG32(VGT_NUM_INSTANCES, 1);
 904
 905         WREG32(CP_PERFMON_CNTL, 0);
 906
 907         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 908                                   FETCH_FIFO_HIWATER(0x4) |
 909                                   DONE_FIFO_HIWATER(0xe0) |
 910                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 911
 912         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 913         WREG32(SQ_CONFIG, (VC_ENABLE |
 914                            EXPORT_SRC_C |
 915                            GFX_PRIO(0) |
 916                            CS1_PRIO(0) |
 917                            CS2_PRIO(1)));
 918         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 919
 920         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 921                                           FORCE_EOV_MAX_REZ_CNT(255)));
 922
 923         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 924                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 925
 926         WREG32(VGT_GS_VERTEX_REUSE, 16);
 927         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 928
 929         WREG32(CB_PERF_CTR0_SEL_0, 0);
 930         WREG32(CB_PERF_CTR0_SEL_1, 0);
 931         WREG32(CB_PERF_CTR1_SEL_0, 0);
 932         WREG32(CB_PERF_CTR1_SEL_1, 0);
 933         WREG32(CB_PERF_CTR2_SEL_0, 0);
 934         WREG32(CB_PERF_CTR2_SEL_1, 0);
 935         WREG32(CB_PERF_CTR3_SEL_0, 0);
 936         WREG32(CB_PERF_CTR3_SEL_1, 0);
 937
 938         tmp = RREG32(HDP_MISC_CNTL);
 939         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 940         WREG32(HDP_MISC_CNTL, tmp);
 941
 942         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 943         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 944
 945         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 946
 947         udelay(50);
 948 }
 949
 950 /*
 951  * GART
 952  */
 953 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 954 {
 955         /* flush hdp cache */
 956         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 957
 958         /* bits 0-7 are the VM contexts0-7 */
 959         WREG32(VM_INVALIDATE_REQUEST, 1);
 960 }
 961
 962 int cayman_pcie_gart_enable(struct radeon_device *rdev)
 963 {
 964         int r;
 965
 966         if (rdev->gart.table.vram.robj == NULL) {
 967                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 968                 return -EINVAL;
 969         }
 970         r = radeon_gart_table_vram_pin(rdev);
 971         if (r)
 972                 return r;
 973         radeon_gart_restore(rdev);
 974         /* Setup TLB control */
 975         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
 976                ENABLE_L1_FRAGMENT_PROCESSING |
 977                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 978                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 979         /* Setup L2 cache */
 980         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
 981                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 982                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 983                EFFECTIVE_L2_QUEUE_SIZE(7) |
 984                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 985         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
 986         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 987                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 988         /* setup context0 */
 989         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 990         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 991         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 992         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 993                         (u32)(rdev->dummy_page.addr >> 12));
 994         WREG32(VM_CONTEXT0_CNTL2, 0);
 995         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 996                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 997         /* disable context1-7 */
 998         WREG32(VM_CONTEXT1_CNTL2, 0);
 999         WREG32(VM_CONTEXT1_CNTL, 0);
1000
1001         cayman_pcie_gart_tlb_flush(rdev);
1002         rdev->gart.ready = true;
1003         return 0;
1004 }
1005
1006 void cayman_pcie_gart_disable(struct radeon_device *rdev)
1007 {
1008         int r;
1009
1010         /* Disable all tables */
1011         WREG32(VM_CONTEXT0_CNTL, 0);
1012         WREG32(VM_CONTEXT1_CNTL, 0);
1013         /* Setup TLB control */
1014         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1015                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1016                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1017         /* Setup L2 cache */
1018         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1019                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1020                EFFECTIVE_L2_QUEUE_SIZE(7) |
1021                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1022         WREG32(VM_L2_CNTL2, 0);
1023         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1024                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1025         if (rdev->gart.table.vram.robj) {
1026                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1027                 if (likely(r == 0)) {
1028                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1029                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1030                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1031                 }
1032         }
1033 }
1034
1035 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1036 {
1037         cayman_pcie_gart_disable(rdev);
1038         radeon_gart_table_vram_free(rdev);
1039         radeon_gart_fini(rdev);
1040 }
1041
1042 /*
1043  * CP.
1044  */
1045 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1046 {
1047         if (enable)
1048                 WREG32(CP_ME_CNTL, 0);
1049         else {
1050                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1051                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1052                 WREG32(SCRATCH_UMSK, 0);
1053         }
1054 }
1055
1056 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1057 {
1058         const __be32 *fw_data;
1059         int i;
1060
1061         if (!rdev->me_fw || !rdev->pfp_fw)
1062                 return -EINVAL;
1063
1064         cayman_cp_enable(rdev, false);
1065
1066         fw_data = (const __be32 *)rdev->pfp_fw->data;
1067         WREG32(CP_PFP_UCODE_ADDR, 0);
1068         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1069                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1070         WREG32(CP_PFP_UCODE_ADDR, 0);
1071
1072         fw_data = (const __be32 *)rdev->me_fw->data;
1073         WREG32(CP_ME_RAM_WADDR, 0);
1074         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1075                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1076
1077         WREG32(CP_PFP_UCODE_ADDR, 0);
1078         WREG32(CP_ME_RAM_WADDR, 0);
1079         WREG32(CP_ME_RAM_RADDR, 0);
1080         return 0;
1081 }
1082
1083 static int cayman_cp_start(struct radeon_device *rdev)
1084 {
1085         int r, i;
1086
1087         r = radeon_ring_lock(rdev, 7);
1088         if (r) {
1089                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1090                 return r;
1091         }
1092         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1093         radeon_ring_write(rdev, 0x1);
1094         radeon_ring_write(rdev, 0x0);
1095         radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
1096         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1097         radeon_ring_write(rdev, 0);
1098         radeon_ring_write(rdev, 0);
1099         radeon_ring_unlock_commit(rdev);
1100
1101         cayman_cp_enable(rdev, true);
1102
1103         r = radeon_ring_lock(rdev, cayman_default_size + 19);
1104         if (r) {
1105                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1106                 return r;
1107         }
1108
1109         /* setup clear context state */
1110         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1111         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1112
1113         for (i = 0; i < cayman_default_size; i++)
1114                 radeon_ring_write(rdev, cayman_default_state[i]);
1115
1116         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1117         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1118
1119         /* set clear context state */
1120         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1121         radeon_ring_write(rdev, 0);
1122
1123         /* SQ_VTX_BASE_VTX_LOC */
1124         radeon_ring_write(rdev, 0xc0026f00);
1125         radeon_ring_write(rdev, 0x00000000);
1126         radeon_ring_write(rdev, 0x00000000);
1127         radeon_ring_write(rdev, 0x00000000);
1128
1129         /* Clear consts */
1130         radeon_ring_write(rdev, 0xc0036f00);
1131         radeon_ring_write(rdev, 0x00000bc4);
1132         radeon_ring_write(rdev, 0xffffffff);
1133         radeon_ring_write(rdev, 0xffffffff);
1134         radeon_ring_write(rdev, 0xffffffff);
1135
1136         radeon_ring_write(rdev, 0xc0026900);
1137         radeon_ring_write(rdev, 0x00000316);
1138         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1139         radeon_ring_write(rdev, 0x00000010); /*  */
1140
1141         radeon_ring_unlock_commit(rdev);
1142
1143         /* XXX init other rings */
1144
1145         return 0;
1146 }
1147
1148 static void cayman_cp_fini(struct radeon_device *rdev)
1149 {
1150         cayman_cp_enable(rdev, false);
1151         radeon_ring_fini(rdev);
1152 }
1153
1154 int cayman_cp_resume(struct radeon_device *rdev)
1155 {
1156         u32 tmp;
1157         u32 rb_bufsz;
1158         int r;
1159
1160         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1161         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1162                                  SOFT_RESET_PA |
1163                                  SOFT_RESET_SH |
1164                                  SOFT_RESET_VGT |
1165                                  SOFT_RESET_SPI |
1166                                  SOFT_RESET_SX));
1167         RREG32(GRBM_SOFT_RESET);
1168         mdelay(15);
1169         WREG32(GRBM_SOFT_RESET, 0);
1170         RREG32(GRBM_SOFT_RESET);
1171
1172         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1173
1174         /* Set the write pointer delay */
1175         WREG32(CP_RB_WPTR_DELAY, 0);
1176
1177         WREG32(CP_DEBUG, (1 << 27));
1178
1179         /* ring 0 - compute and gfx */
1180         /* Set ring buffer size */
1181         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1182         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1183 #ifdef __BIG_ENDIAN
1184         tmp |= BUF_SWAP_32BIT;
1185 #endif
1186         WREG32(CP_RB0_CNTL, tmp);
1187
1188         /* Initialize the ring buffer's read and write pointers */
1189         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1190         rdev->cp.wptr = 0;
1191         WREG32(CP_RB0_WPTR, rdev->cp.wptr);
1192
1193         /* set the wb address wether it's enabled or not */
1194         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1195         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1196         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1197
1198         if (rdev->wb.enabled)
1199                 WREG32(SCRATCH_UMSK, 0xff);
1200         else {
1201                 tmp |= RB_NO_UPDATE;
1202                 WREG32(SCRATCH_UMSK, 0);
1203         }
1204
1205         mdelay(1);
1206         WREG32(CP_RB0_CNTL, tmp);
1207
1208         WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
1209
1210         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1211
1212         /* ring1  - compute only */
1213         /* Set ring buffer size */
1214         rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
1215         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1216 #ifdef __BIG_ENDIAN
1217         tmp |= BUF_SWAP_32BIT;
1218 #endif
1219         WREG32(CP_RB1_CNTL, tmp);
1220
1221         /* Initialize the ring buffer's read and write pointers */
1222         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1223         rdev->cp1.wptr = 0;
1224         WREG32(CP_RB1_WPTR, rdev->cp1.wptr);
1225
1226         /* set the wb address wether it's enabled or not */
1227         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1228         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1229
1230         mdelay(1);
1231         WREG32(CP_RB1_CNTL, tmp);
1232
1233         WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
1234
1235         rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
1236
1237         /* ring2 - compute only */
1238         /* Set ring buffer size */
1239         rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
1240         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1241 #ifdef __BIG_ENDIAN
1242         tmp |= BUF_SWAP_32BIT;
1243 #endif
1244         WREG32(CP_RB2_CNTL, tmp);
1245
1246         /* Initialize the ring buffer's read and write pointers */
1247         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1248         rdev->cp2.wptr = 0;
1249         WREG32(CP_RB2_WPTR, rdev->cp2.wptr);
1250
1251         /* set the wb address wether it's enabled or not */
1252         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1253         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1254
1255         mdelay(1);
1256         WREG32(CP_RB2_CNTL, tmp);
1257
1258         WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
1259
1260         rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
1261
1262         /* start the rings */
1263         cayman_cp_start(rdev);
1264         rdev->cp.ready = true;
1265         rdev->cp1.ready = true;
1266         rdev->cp2.ready = true;
1267         /* this only test cp0 */
1268         r = radeon_ring_test(rdev);
1269         if (r) {
1270                 rdev->cp.ready = false;
1271                 rdev->cp1.ready = false;
1272                 rdev->cp2.ready = false;
1273                 return r;
1274         }
1275
1276         return 0;
1277 }
1278
1279 bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1280 {
1281         u32 srbm_status;
1282         u32 grbm_status;
1283         u32 grbm_status_se0, grbm_status_se1;
1284         struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1285         int r;
1286
1287         srbm_status = RREG32(SRBM_STATUS);
1288         grbm_status = RREG32(GRBM_STATUS);
1289         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1290         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1291         if (!(grbm_status & GUI_ACTIVE)) {
1292                 r100_gpu_lockup_update(lockup, &rdev->cp);
1293                 return false;
1294         }
1295         /* force CP activities */
1296         r = radeon_ring_lock(rdev, 2);
1297         if (!r) {
1298                 /* PACKET2 NOP */
1299                 radeon_ring_write(rdev, 0x80000000);
1300                 radeon_ring_write(rdev, 0x80000000);
1301                 radeon_ring_unlock_commit(rdev);
1302         }
1303         /* XXX deal with CP0,1,2 */
1304         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1305         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1306 }
1307
1308 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1309 {
1310         struct evergreen_mc_save save;
1311         u32 grbm_reset = 0;
1312
1313         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1314                 return 0;
1315
1316         dev_info(rdev->dev, "GPU softreset \n");
1317         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1318                 RREG32(GRBM_STATUS));
1319         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1320                 RREG32(GRBM_STATUS_SE0));
1321         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1322                 RREG32(GRBM_STATUS_SE1));
1323         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1324                 RREG32(SRBM_STATUS));
1325         evergreen_mc_stop(rdev, &save);
1326         if (evergreen_mc_wait_for_idle(rdev)) {
1327                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1328         }
1329         /* Disable CP parsing/prefetching */
1330         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1331
1332         /* reset all the gfx blocks */
1333         grbm_reset = (SOFT_RESET_CP |
1334                       SOFT_RESET_CB |
1335                       SOFT_RESET_DB |
1336                       SOFT_RESET_GDS |
1337                       SOFT_RESET_PA |
1338                       SOFT_RESET_SC |
1339                       SOFT_RESET_SPI |
1340                       SOFT_RESET_SH |
1341                       SOFT_RESET_SX |
1342                       SOFT_RESET_TC |
1343                       SOFT_RESET_TA |
1344                       SOFT_RESET_VGT |
1345                       SOFT_RESET_IA);
1346
1347         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1348         WREG32(GRBM_SOFT_RESET, grbm_reset);
1349         (void)RREG32(GRBM_SOFT_RESET);
1350         udelay(50);
1351         WREG32(GRBM_SOFT_RESET, 0);
1352         (void)RREG32(GRBM_SOFT_RESET);
1353         /* Wait a little for things to settle down */
1354         udelay(50);
1355         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1356                 RREG32(GRBM_STATUS));
1357         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1358                 RREG32(GRBM_STATUS_SE0));
1359         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1360                 RREG32(GRBM_STATUS_SE1));
1361         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1362                 RREG32(SRBM_STATUS));
1363         evergreen_mc_resume(rdev, &save);
1364         return 0;
1365 }
1366
1367 int cayman_asic_reset(struct radeon_device *rdev)
1368 {
1369         return cayman_gpu_soft_reset(rdev);
1370 }
1371
1372 static int cayman_startup(struct radeon_device *rdev)
1373 {
1374         int r;
1375
1376         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1377                 r = ni_init_microcode(rdev);
1378                 if (r) {
1379                         DRM_ERROR("Failed to load firmware!\n");
1380                         return r;
1381                 }
1382         }
1383         r = ni_mc_load_microcode(rdev);
1384         if (r) {
1385                 DRM_ERROR("Failed to load MC firmware!\n");
1386                 return r;
1387         }
1388
1389         evergreen_mc_program(rdev);
1390         r = cayman_pcie_gart_enable(rdev);
1391         if (r)
1392                 return r;
1393         cayman_gpu_init(rdev);
1394
1395         r = evergreen_blit_init(rdev);
1396         if (r) {
1397                 evergreen_blit_fini(rdev);
1398                 rdev->asic->copy = NULL;
1399                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1400         }
1401
1402         /* allocate wb buffer */
1403         r = radeon_wb_init(rdev);
1404         if (r)
1405                 return r;
1406
1407         /* Enable IRQ */
1408         r = r600_irq_init(rdev);
1409         if (r) {
1410                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1411                 radeon_irq_kms_fini(rdev);
1412                 return r;
1413         }
1414         evergreen_irq_set(rdev);
1415
1416         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1417         if (r)
1418                 return r;
1419         r = cayman_cp_load_microcode(rdev);
1420         if (r)
1421                 return r;
1422         r = cayman_cp_resume(rdev);
1423         if (r)
1424                 return r;
1425
1426         return 0;
1427 }
1428
1429 int cayman_resume(struct radeon_device *rdev)
1430 {
1431         int r;
1432
1433         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1434          * posting will perform necessary task to bring back GPU into good
1435          * shape.
1436          */
1437         /* post card */
1438         atom_asic_init(rdev->mode_info.atom_context);
1439
1440         r = cayman_startup(rdev);
1441         if (r) {
1442                 DRM_ERROR("cayman startup failed on resume\n");
1443                 return r;
1444         }
1445
1446         r = r600_ib_test(rdev);
1447         if (r) {
1448                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1449                 return r;
1450         }
1451
1452         return r;
1453
1454 }
1455
1456 int cayman_suspend(struct radeon_device *rdev)
1457 {
1458         int r;
1459
1460         /* FIXME: we should wait for ring to be empty */
1461         cayman_cp_enable(rdev, false);
1462         rdev->cp.ready = false;
1463         evergreen_irq_suspend(rdev);
1464         radeon_wb_disable(rdev);
1465         cayman_pcie_gart_disable(rdev);
1466
1467         /* unpin shaders bo */
1468         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1469         if (likely(r == 0)) {
1470                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1471                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1472         }
1473
1474         return 0;
1475 }
1476
1477 /* Plan is to move initialization in that function and use
1478  * helper function so that radeon_device_init pretty much
1479  * do nothing more than calling asic specific function. This
1480  * should also allow to remove a bunch of callback function
1481  * like vram_info.
1482  */
1483 int cayman_init(struct radeon_device *rdev)
1484 {
1485         int r;
1486
1487         /* This don't do much */
1488         r = radeon_gem_init(rdev);
1489         if (r)
1490                 return r;
1491         /* Read BIOS */
1492         if (!radeon_get_bios(rdev)) {
1493                 if (ASIC_IS_AVIVO(rdev))
1494                         return -EINVAL;
1495         }
1496         /* Must be an ATOMBIOS */
1497         if (!rdev->is_atom_bios) {
1498                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1499                 return -EINVAL;
1500         }
1501         r = radeon_atombios_init(rdev);
1502         if (r)
1503                 return r;
1504
1505         /* Post card if necessary */
1506         if (!radeon_card_posted(rdev)) {
1507                 if (!rdev->bios) {
1508                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1509                         return -EINVAL;
1510                 }
1511                 DRM_INFO("GPU not posted. posting now...\n");
1512                 atom_asic_init(rdev->mode_info.atom_context);
1513         }
1514         /* Initialize scratch registers */
1515         r600_scratch_init(rdev);
1516         /* Initialize surface registers */
1517         radeon_surface_init(rdev);
1518         /* Initialize clocks */
1519         radeon_get_clock_info(rdev->ddev);
1520         /* Fence driver */
1521         r = radeon_fence_driver_init(rdev);
1522         if (r)
1523                 return r;
1524         /* initialize memory controller */
1525         r = evergreen_mc_init(rdev);
1526         if (r)
1527                 return r;
1528         /* Memory manager */
1529         r = radeon_bo_init(rdev);
1530         if (r)
1531                 return r;
1532
1533         r = radeon_irq_kms_init(rdev);
1534         if (r)
1535                 return r;
1536
1537         rdev->cp.ring_obj = NULL;
1538         r600_ring_init(rdev, 1024 * 1024);
1539
1540         rdev->ih.ring_obj = NULL;
1541         r600_ih_ring_init(rdev, 64 * 1024);
1542
1543         r = r600_pcie_gart_init(rdev);
1544         if (r)
1545                 return r;
1546
1547         rdev->accel_working = true;
1548         r = cayman_startup(rdev);
1549         if (r) {
1550                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1551                 cayman_cp_fini(rdev);
1552                 r600_irq_fini(rdev);
1553                 radeon_wb_fini(rdev);
1554                 radeon_irq_kms_fini(rdev);
1555                 cayman_pcie_gart_fini(rdev);
1556                 rdev->accel_working = false;
1557         }
1558         if (rdev->accel_working) {
1559                 r = radeon_ib_pool_init(rdev);
1560                 if (r) {
1561                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1562                         rdev->accel_working = false;
1563                 }
1564                 r = r600_ib_test(rdev);
1565                 if (r) {
1566                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1567                         rdev->accel_working = false;
1568                 }
1569         }
1570
1571         /* Don't start up if the MC ucode is missing.
1572          * The default clocks and voltages before the MC ucode
1573          * is loaded are not suffient for advanced operations.
1574          */
1575         if (!rdev->mc_fw) {
1576                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1577                 return -EINVAL;
1578         }
1579
1580         return 0;
1581 }
1582
1583 void cayman_fini(struct radeon_device *rdev)
1584 {
1585         evergreen_blit_fini(rdev);
1586         cayman_cp_fini(rdev);
1587         r600_irq_fini(rdev);
1588         radeon_wb_fini(rdev);
1589         radeon_ib_pool_fini(rdev);
1590         radeon_irq_kms_fini(rdev);
1591         cayman_pcie_gart_fini(rdev);
1592         radeon_gem_fini(rdev);
1593         radeon_fence_driver_fini(rdev);
1594         radeon_bo_fini(rdev);
1595         radeon_atombios_fini(rdev);
1596         kfree(rdev->bios);
1597         rdev->bios = NULL;
1598 }
1599