2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define EVERGREEN_MAX_SH_GPRS 256
28 #define EVERGREEN_MAX_TEMP_GPRS 16
29 #define EVERGREEN_MAX_SH_THREADS 256
30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384
32 #define EVERGREEN_MAX_BACKENDS 8
33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34 #define EVERGREEN_MAX_SIMDS 16
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36 #define EVERGREEN_MAX_PIPES 8
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
42 #define RCU_IND_INDEX 0x100
43 #define RCU_IND_DATA 0x104
45 #define GRBM_GFX_INDEX 0x802C
46 #define INSTANCE_INDEX(x) ((x) << 0)
47 #define SE_INDEX(x) ((x) << 16)
48 #define INSTANCE_BROADCAST_WRITES (1 << 30)
49 #define SE_BROADCAST_WRITES (1 << 31)
50 #define RLC_GFX_INDEX 0x3fC4
51 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
52 #define WRITE_DIS (1 << 0)
53 #define CC_RB_BACKEND_DISABLE 0x98F4
54 #define BACKEND_DISABLE(x) ((x) << 16)
55 #define GB_ADDR_CONFIG 0x98F8
56 #define NUM_PIPES(x) ((x) << 0)
57 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59 #define NUM_SHADER_ENGINES(x) ((x) << 12)
60 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61 #define NUM_GPUS(x) ((x) << 20)
62 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63 #define ROW_SIZE(x) ((x) << 28)
64 #define GB_BACKEND_MAP 0x98FC
65 #define DMIF_ADDR_CONFIG 0xBD4
66 #define HDP_ADDR_CONFIG 0x2F48
68 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
69 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
71 #define CGTS_SYS_TCC_DISABLE 0x3F90
72 #define CGTS_TCC_DISABLE 0x9148
73 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
74 #define CGTS_USER_TCC_DISABLE 0x914C
76 #define CONFIG_MEMSIZE 0x5428
78 #define CP_ME_CNTL 0x86D8
79 #define CP_ME_HALT (1 << 28)
80 #define CP_PFP_HALT (1 << 26)
81 #define CP_ME_RAM_DATA 0xC160
82 #define CP_ME_RAM_RADDR 0xC158
83 #define CP_ME_RAM_WADDR 0xC15C
84 #define CP_MEQ_THRESHOLDS 0x8764
85 #define STQ_SPLIT(x) ((x) << 0)
86 #define CP_PERFMON_CNTL 0x87FC
87 #define CP_PFP_UCODE_ADDR 0xC150
88 #define CP_PFP_UCODE_DATA 0xC154
89 #define CP_QUEUE_THRESHOLDS 0x8760
90 #define ROQ_IB1_START(x) ((x) << 0)
91 #define ROQ_IB2_START(x) ((x) << 8)
92 #define CP_RB_BASE 0xC100
93 #define CP_RB_CNTL 0xC104
94 #define RB_BUFSZ(x) ((x) << 0)
95 #define RB_BLKSZ(x) ((x) << 8)
96 #define RB_NO_UPDATE (1 << 27)
97 #define RB_RPTR_WR_ENA (1 << 31)
98 #define BUF_SWAP_32BIT (2 << 16)
99 #define CP_RB_RPTR 0x8700
100 #define CP_RB_RPTR_ADDR 0xC10C
101 #define CP_RB_RPTR_ADDR_HI 0xC110
102 #define CP_RB_RPTR_WR 0xC108
103 #define CP_RB_WPTR 0xC114
104 #define CP_RB_WPTR_ADDR 0xC118
105 #define CP_RB_WPTR_ADDR_HI 0xC11C
106 #define CP_RB_WPTR_DELAY 0x8704
107 #define CP_SEM_WAIT_TIMER 0x85BC
108 #define CP_DEBUG 0xC1FC
111 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
112 #define INACTIVE_QD_PIPES(x) ((x) << 8)
113 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
114 #define INACTIVE_SIMDS(x) ((x) << 16)
115 #define INACTIVE_SIMDS_MASK 0x00FF0000
117 #define GRBM_CNTL 0x8000
118 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
119 #define GRBM_SOFT_RESET 0x8020
120 #define SOFT_RESET_CP (1 << 0)
121 #define SOFT_RESET_CB (1 << 1)
122 #define SOFT_RESET_DB (1 << 3)
123 #define SOFT_RESET_PA (1 << 5)
124 #define SOFT_RESET_SC (1 << 6)
125 #define SOFT_RESET_SPI (1 << 8)
126 #define SOFT_RESET_SH (1 << 9)
127 #define SOFT_RESET_SX (1 << 10)
128 #define SOFT_RESET_TC (1 << 11)
129 #define SOFT_RESET_TA (1 << 12)
130 #define SOFT_RESET_VC (1 << 13)
131 #define SOFT_RESET_VGT (1 << 14)
133 #define GRBM_STATUS 0x8010
134 #define CMDFIFO_AVAIL_MASK 0x0000000F
135 #define SRBM_RQ_PENDING (1 << 5)
136 #define CF_RQ_PENDING (1 << 7)
137 #define PF_RQ_PENDING (1 << 8)
138 #define GRBM_EE_BUSY (1 << 10)
139 #define SX_CLEAN (1 << 11)
140 #define DB_CLEAN (1 << 12)
141 #define CB_CLEAN (1 << 13)
142 #define TA_BUSY (1 << 14)
143 #define VGT_BUSY_NO_DMA (1 << 16)
144 #define VGT_BUSY (1 << 17)
145 #define SX_BUSY (1 << 20)
146 #define SH_BUSY (1 << 21)
147 #define SPI_BUSY (1 << 22)
148 #define SC_BUSY (1 << 24)
149 #define PA_BUSY (1 << 25)
150 #define DB_BUSY (1 << 26)
151 #define CP_COHERENCY_BUSY (1 << 28)
152 #define CP_BUSY (1 << 29)
153 #define CB_BUSY (1 << 30)
154 #define GUI_ACTIVE (1 << 31)
155 #define GRBM_STATUS_SE0 0x8014
156 #define GRBM_STATUS_SE1 0x8018
157 #define SE_SX_CLEAN (1 << 0)
158 #define SE_DB_CLEAN (1 << 1)
159 #define SE_CB_CLEAN (1 << 2)
160 #define SE_TA_BUSY (1 << 25)
161 #define SE_SX_BUSY (1 << 26)
162 #define SE_SPI_BUSY (1 << 27)
163 #define SE_SH_BUSY (1 << 28)
164 #define SE_SC_BUSY (1 << 29)
165 #define SE_DB_BUSY (1 << 30)
166 #define SE_CB_BUSY (1 << 31)
168 #define HDP_HOST_PATH_CNTL 0x2C00
169 #define HDP_NONSURFACE_BASE 0x2C04
170 #define HDP_NONSURFACE_INFO 0x2C08
171 #define HDP_NONSURFACE_SIZE 0x2C0C
172 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
173 #define HDP_TILING_CONFIG 0x2F3C
175 #define MC_SHARED_CHMAP 0x2004
176 #define NOOFCHAN_SHIFT 12
177 #define NOOFCHAN_MASK 0x00003000
179 #define MC_ARB_RAMCFG 0x2760
180 #define NOOFBANK_SHIFT 0
181 #define NOOFBANK_MASK 0x00000003
182 #define NOOFRANK_SHIFT 2
183 #define NOOFRANK_MASK 0x00000004
184 #define NOOFROWS_SHIFT 3
185 #define NOOFROWS_MASK 0x00000038
186 #define NOOFCOLS_SHIFT 6
187 #define NOOFCOLS_MASK 0x000000C0
188 #define CHANSIZE_SHIFT 8
189 #define CHANSIZE_MASK 0x00000100
190 #define BURSTLENGTH_SHIFT 9
191 #define BURSTLENGTH_MASK 0x00000200
192 #define CHANSIZE_OVERRIDE (1 << 11)
193 #define MC_VM_AGP_TOP 0x2028
194 #define MC_VM_AGP_BOT 0x202C
195 #define MC_VM_AGP_BASE 0x2030
196 #define MC_VM_FB_LOCATION 0x2024
197 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
198 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
199 #define MC_VM_MB_L1_TLB2_CNTL 0x223C
200 #define MC_VM_MB_L1_TLB3_CNTL 0x2240
201 #define ENABLE_L1_TLB (1 << 0)
202 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
203 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
204 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
205 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
206 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
207 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
208 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
209 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
210 #define MC_VM_MD_L1_TLB0_CNTL 0x2654
211 #define MC_VM_MD_L1_TLB1_CNTL 0x2658
212 #define MC_VM_MD_L1_TLB2_CNTL 0x265C
213 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
214 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
215 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
217 #define PA_CL_ENHANCE 0x8A14
218 #define CLIP_VTX_REORDER_ENA (1 << 0)
219 #define NUM_CLIP_SEQ(x) ((x) << 1)
220 #define PA_SC_AA_CONFIG 0x28C04
221 #define PA_SC_CLIPRECT_RULE 0x2820C
222 #define PA_SC_EDGERULE 0x28230
223 #define PA_SC_FIFO_SIZE 0x8BCC
224 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
225 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
226 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
227 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
228 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
229 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
230 #define PA_SC_LINE_STIPPLE 0x28A0C
231 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
233 #define SCRATCH_REG0 0x8500
234 #define SCRATCH_REG1 0x8504
235 #define SCRATCH_REG2 0x8508
236 #define SCRATCH_REG3 0x850C
237 #define SCRATCH_REG4 0x8510
238 #define SCRATCH_REG5 0x8514
239 #define SCRATCH_REG6 0x8518
240 #define SCRATCH_REG7 0x851C
241 #define SCRATCH_UMSK 0x8540
242 #define SCRATCH_ADDR 0x8544
244 #define SMX_DC_CTL0 0xA020
245 #define USE_HASH_FUNCTION (1 << 0)
246 #define NUMBER_OF_SETS(x) ((x) << 1)
247 #define FLUSH_ALL_ON_EVENT (1 << 10)
248 #define STALL_ON_EVENT (1 << 11)
249 #define SMX_EVENT_CTL 0xA02C
250 #define ES_FLUSH_CTL(x) ((x) << 0)
251 #define GS_FLUSH_CTL(x) ((x) << 3)
252 #define ACK_FLUSH_CTL(x) ((x) << 6)
253 #define SYNC_FLUSH_CTL (1 << 8)
255 #define SPI_CONFIG_CNTL 0x9100
256 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
257 #define SPI_CONFIG_CNTL_1 0x913C
258 #define VTX_DONE_DELAY(x) ((x) << 0)
259 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
260 #define SPI_INPUT_Z 0x286D8
261 #define SPI_PS_IN_CONTROL_0 0x286CC
262 #define NUM_INTERP(x) ((x)<<0)
263 #define POSITION_ENA (1<<8)
264 #define POSITION_CENTROID (1<<9)
265 #define POSITION_ADDR(x) ((x)<<10)
266 #define PARAM_GEN(x) ((x)<<15)
267 #define PARAM_GEN_ADDR(x) ((x)<<19)
268 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
269 #define PERSP_GRADIENT_ENA (1<<28)
270 #define LINEAR_GRADIENT_ENA (1<<29)
271 #define POSITION_SAMPLE (1<<30)
272 #define BARYC_AT_SAMPLE_ENA (1<<31)
274 #define SQ_CONFIG 0x8C00
275 #define VC_ENABLE (1 << 0)
276 #define EXPORT_SRC_C (1 << 1)
277 #define CS_PRIO(x) ((x) << 18)
278 #define LS_PRIO(x) ((x) << 20)
279 #define HS_PRIO(x) ((x) << 22)
280 #define PS_PRIO(x) ((x) << 24)
281 #define VS_PRIO(x) ((x) << 26)
282 #define GS_PRIO(x) ((x) << 28)
283 #define ES_PRIO(x) ((x) << 30)
284 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
285 #define NUM_PS_GPRS(x) ((x) << 0)
286 #define NUM_VS_GPRS(x) ((x) << 16)
287 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
288 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
289 #define NUM_GS_GPRS(x) ((x) << 0)
290 #define NUM_ES_GPRS(x) ((x) << 16)
291 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
292 #define NUM_HS_GPRS(x) ((x) << 0)
293 #define NUM_LS_GPRS(x) ((x) << 16)
294 #define SQ_THREAD_RESOURCE_MGMT 0x8C18
295 #define NUM_PS_THREADS(x) ((x) << 0)
296 #define NUM_VS_THREADS(x) ((x) << 8)
297 #define NUM_GS_THREADS(x) ((x) << 16)
298 #define NUM_ES_THREADS(x) ((x) << 24)
299 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
300 #define NUM_HS_THREADS(x) ((x) << 0)
301 #define NUM_LS_THREADS(x) ((x) << 8)
302 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20
303 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
304 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
305 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24
306 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
307 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
308 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28
309 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
310 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
311 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
312 #define SQ_LDS_RESOURCE_MGMT 0x8E2C
314 #define SQ_MS_FIFO_SIZES 0x8CF0
315 #define CACHE_FIFO_SIZE(x) ((x) << 0)
316 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
317 #define DONE_FIFO_HIWATER(x) ((x) << 16)
318 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
320 #define SX_DEBUG_1 0x9058
321 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
322 #define SX_EXPORT_BUFFER_SIZES 0x900C
323 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
324 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
325 #define SMX_BUFFER_SIZE(x) ((x) << 16)
326 #define SX_MISC 0x28350
328 #define CB_PERF_CTR0_SEL_0 0x9A20
329 #define CB_PERF_CTR0_SEL_1 0x9A24
330 #define CB_PERF_CTR1_SEL_0 0x9A28
331 #define CB_PERF_CTR1_SEL_1 0x9A2C
332 #define CB_PERF_CTR2_SEL_0 0x9A30
333 #define CB_PERF_CTR2_SEL_1 0x9A34
334 #define CB_PERF_CTR3_SEL_0 0x9A38
335 #define CB_PERF_CTR3_SEL_1 0x9A3C
337 #define TA_CNTL_AUX 0x9508
338 #define DISABLE_CUBE_WRAP (1 << 0)
339 #define DISABLE_CUBE_ANISO (1 << 1)
340 #define SYNC_GRADIENT (1 << 24)
341 #define SYNC_WALKER (1 << 25)
342 #define SYNC_ALIGNER (1 << 26)
344 #define VGT_CACHE_INVALIDATION 0x88C4
345 #define CACHE_INVALIDATION(x) ((x) << 0)
349 #define AUTO_INVLD_EN(x) ((x) << 6)
353 #define ES_AND_GS_AUTO 3
354 #define VGT_GS_VERTEX_REUSE 0x88D4
355 #define VGT_NUM_INSTANCES 0x8974
356 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
357 #define DEALLOC_DIST_MASK 0x0000007F
358 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
359 #define VTX_REUSE_DEPTH_MASK 0x000000FF
361 #define VM_CONTEXT0_CNTL 0x1410
362 #define ENABLE_CONTEXT (1 << 0)
363 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
364 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
365 #define VM_CONTEXT1_CNTL 0x1414
366 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
367 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
368 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
369 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
370 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
371 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
372 #define RESPONSE_TYPE_MASK 0x000000F0
373 #define RESPONSE_TYPE_SHIFT 4
374 #define VM_L2_CNTL 0x1400
375 #define ENABLE_L2_CACHE (1 << 0)
376 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
377 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
378 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
379 #define VM_L2_CNTL2 0x1404
380 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
381 #define INVALIDATE_L2_CACHE (1 << 1)
382 #define VM_L2_CNTL3 0x1408
383 #define BANK_SELECT(x) ((x) << 0)
384 #define CACHE_UPDATE_MODE(x) ((x) << 6)
385 #define VM_L2_STATUS 0x140C
386 #define L2_BUSY (1 << 0)
388 #define WAIT_UNTIL 0x8040
390 #define SRBM_STATUS 0x0E50
391 #define SRBM_SOFT_RESET 0x0E60
392 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
393 #define SOFT_RESET_BIF (1 << 1)
394 #define SOFT_RESET_CG (1 << 2)
395 #define SOFT_RESET_DC (1 << 5)
396 #define SOFT_RESET_GRBM (1 << 8)
397 #define SOFT_RESET_HDP (1 << 9)
398 #define SOFT_RESET_IH (1 << 10)
399 #define SOFT_RESET_MC (1 << 11)
400 #define SOFT_RESET_RLC (1 << 13)
401 #define SOFT_RESET_ROM (1 << 14)
402 #define SOFT_RESET_SEM (1 << 15)
403 #define SOFT_RESET_VMC (1 << 17)
404 #define SOFT_RESET_TST (1 << 21)
405 #define SOFT_RESET_REGBB (1 << 22)
406 #define SOFT_RESET_ORB (1 << 23)
408 #define IH_RB_CNTL 0x3e00
409 # define IH_RB_ENABLE (1 << 0)
410 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
411 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
412 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
413 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
414 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
415 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
416 #define IH_RB_BASE 0x3e04
417 #define IH_RB_RPTR 0x3e08
418 #define IH_RB_WPTR 0x3e0c
419 # define RB_OVERFLOW (1 << 0)
420 # define WPTR_OFFSET_MASK 0x3fffc
421 #define IH_RB_WPTR_ADDR_HI 0x3e10
422 #define IH_RB_WPTR_ADDR_LO 0x3e14
423 #define IH_CNTL 0x3e18
424 # define ENABLE_INTR (1 << 0)
425 # define IH_MC_SWAP(x) ((x) << 2)
426 # define IH_MC_SWAP_NONE 0
427 # define IH_MC_SWAP_16BIT 1
428 # define IH_MC_SWAP_32BIT 2
429 # define IH_MC_SWAP_64BIT 3
430 # define RPTR_REARM (1 << 4)
431 # define MC_WRREQ_CREDIT(x) ((x) << 15)
432 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
434 #define CP_INT_CNTL 0xc124
435 # define CNTX_BUSY_INT_ENABLE (1 << 19)
436 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
437 # define SCRATCH_INT_ENABLE (1 << 25)
438 # define TIME_STAMP_INT_ENABLE (1 << 26)
439 # define IB2_INT_ENABLE (1 << 29)
440 # define IB1_INT_ENABLE (1 << 30)
441 # define RB_INT_ENABLE (1 << 31)
442 #define CP_INT_STATUS 0xc128
443 # define SCRATCH_INT_STAT (1 << 25)
444 # define TIME_STAMP_INT_STAT (1 << 26)
445 # define IB2_INT_STAT (1 << 29)
446 # define IB1_INT_STAT (1 << 30)
447 # define RB_INT_STAT (1 << 31)
449 #define GRBM_INT_CNTL 0x8060
450 # define RDERR_INT_ENABLE (1 << 0)
451 # define GUI_IDLE_INT_ENABLE (1 << 19)
453 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
454 #define CRTC_STATUS_FRAME_COUNT 0x6e98
456 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
457 #define VLINE_STATUS 0x6bb8
458 # define VLINE_OCCURRED (1 << 0)
459 # define VLINE_ACK (1 << 4)
460 # define VLINE_STAT (1 << 12)
461 # define VLINE_INTERRUPT (1 << 16)
462 # define VLINE_INTERRUPT_TYPE (1 << 17)
463 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
464 #define VBLANK_STATUS 0x6bbc
465 # define VBLANK_OCCURRED (1 << 0)
466 # define VBLANK_ACK (1 << 4)
467 # define VBLANK_STAT (1 << 12)
468 # define VBLANK_INTERRUPT (1 << 16)
469 # define VBLANK_INTERRUPT_TYPE (1 << 17)
471 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
472 #define INT_MASK 0x6b40
473 # define VBLANK_INT_MASK (1 << 0)
474 # define VLINE_INT_MASK (1 << 4)
476 #define DISP_INTERRUPT_STATUS 0x60f4
477 # define LB_D1_VLINE_INTERRUPT (1 << 2)
478 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
479 # define DC_HPD1_INTERRUPT (1 << 17)
480 # define DC_HPD1_RX_INTERRUPT (1 << 18)
481 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
482 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
483 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
484 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
485 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
486 # define LB_D2_VLINE_INTERRUPT (1 << 2)
487 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
488 # define DC_HPD2_INTERRUPT (1 << 17)
489 # define DC_HPD2_RX_INTERRUPT (1 << 18)
490 # define DISP_TIMER_INTERRUPT (1 << 24)
491 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
492 # define LB_D3_VLINE_INTERRUPT (1 << 2)
493 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
494 # define DC_HPD3_INTERRUPT (1 << 17)
495 # define DC_HPD3_RX_INTERRUPT (1 << 18)
496 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
497 # define LB_D4_VLINE_INTERRUPT (1 << 2)
498 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
499 # define DC_HPD4_INTERRUPT (1 << 17)
500 # define DC_HPD4_RX_INTERRUPT (1 << 18)
501 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
502 # define LB_D5_VLINE_INTERRUPT (1 << 2)
503 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
504 # define DC_HPD5_INTERRUPT (1 << 17)
505 # define DC_HPD5_RX_INTERRUPT (1 << 18)
506 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050
507 # define LB_D6_VLINE_INTERRUPT (1 << 2)
508 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
509 # define DC_HPD6_INTERRUPT (1 << 17)
510 # define DC_HPD6_RX_INTERRUPT (1 << 18)
512 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
513 #define GRPH_INT_STATUS 0x6858
514 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
515 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
516 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
517 #define GRPH_INT_CONTROL 0x685c
518 # define GRPH_PFLIP_INT_MASK (1 << 0)
519 # define GRPH_PFLIP_INT_TYPE (1 << 8)
521 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
522 #define DACB_AUTODETECT_INT_CONTROL 0x67c8
524 #define DC_HPD1_INT_STATUS 0x601c
525 #define DC_HPD2_INT_STATUS 0x6028
526 #define DC_HPD3_INT_STATUS 0x6034
527 #define DC_HPD4_INT_STATUS 0x6040
528 #define DC_HPD5_INT_STATUS 0x604c
529 #define DC_HPD6_INT_STATUS 0x6058
530 # define DC_HPDx_INT_STATUS (1 << 0)
531 # define DC_HPDx_SENSE (1 << 1)
532 # define DC_HPDx_RX_INT_STATUS (1 << 8)
534 #define DC_HPD1_INT_CONTROL 0x6020
535 #define DC_HPD2_INT_CONTROL 0x602c
536 #define DC_HPD3_INT_CONTROL 0x6038
537 #define DC_HPD4_INT_CONTROL 0x6044
538 #define DC_HPD5_INT_CONTROL 0x6050
539 #define DC_HPD6_INT_CONTROL 0x605c
540 # define DC_HPDx_INT_ACK (1 << 0)
541 # define DC_HPDx_INT_POLARITY (1 << 8)
542 # define DC_HPDx_INT_EN (1 << 16)
543 # define DC_HPDx_RX_INT_ACK (1 << 20)
544 # define DC_HPDx_RX_INT_EN (1 << 24)
546 #define DC_HPD1_CONTROL 0x6024
547 #define DC_HPD2_CONTROL 0x6030
548 #define DC_HPD3_CONTROL 0x603c
549 #define DC_HPD4_CONTROL 0x6048
550 #define DC_HPD5_CONTROL 0x6054
551 #define DC_HPD6_CONTROL 0x6060
552 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
553 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
554 # define DC_HPDx_EN (1 << 28)
git.openpandora.org / pandora-kernel.git / blob