drivers/gpu/drm/radeon/evergreen_cs.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "evergreend.h"
  31 #include "evergreen_reg_safe.h"
  32 #include "cayman_reg_safe.h"
  33
  34 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
  35                                           struct radeon_cs_reloc **cs_reloc);
  36
  37 struct evergreen_cs_track {
  38         u32                     group_size;
  39         u32                     nbanks;
  40         u32                     npipes;
  41         /* value we track */
  42         u32                     nsamples;
  43         u32                     cb_color_base_last[12];
  44         struct radeon_bo        *cb_color_bo[12];
  45         u32                     cb_color_bo_offset[12];
  46         struct radeon_bo        *cb_color_fmask_bo[8];
  47         struct radeon_bo        *cb_color_cmask_bo[8];
  48         u32                     cb_color_info[12];
  49         u32                     cb_color_view[12];
  50         u32                     cb_color_pitch_idx[12];
  51         u32                     cb_color_slice_idx[12];
  52         u32                     cb_color_dim_idx[12];
  53         u32                     cb_color_dim[12];
  54         u32                     cb_color_pitch[12];
  55         u32                     cb_color_slice[12];
  56         u32                     cb_color_cmask_slice[8];
  57         u32                     cb_color_fmask_slice[8];
  58         u32                     cb_target_mask;
  59         u32                     cb_shader_mask;
  60         u32                     vgt_strmout_config;
  61         u32                     vgt_strmout_buffer_config;
  62         u32                     db_depth_control;
  63         u32                     db_depth_view;
  64         u32                     db_depth_size;
  65         u32                     db_depth_size_idx;
  66         u32                     db_z_info;
  67         u32                     db_z_idx;
  68         u32                     db_z_read_offset;
  69         u32                     db_z_write_offset;
  70         struct radeon_bo        *db_z_read_bo;
  71         struct radeon_bo        *db_z_write_bo;
  72         u32                     db_s_info;
  73         u32                     db_s_idx;
  74         u32                     db_s_read_offset;
  75         u32                     db_s_write_offset;
  76         struct radeon_bo        *db_s_read_bo;
  77         struct radeon_bo        *db_s_write_bo;
  78 };
  79
  80 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
  81 {
  82         int i;
  83
  84         for (i = 0; i < 8; i++) {
  85                 track->cb_color_fmask_bo[i] = NULL;
  86                 track->cb_color_cmask_bo[i] = NULL;
  87                 track->cb_color_cmask_slice[i] = 0;
  88                 track->cb_color_fmask_slice[i] = 0;
  89         }
  90
  91         for (i = 0; i < 12; i++) {
  92                 track->cb_color_base_last[i] = 0;
  93                 track->cb_color_bo[i] = NULL;
  94                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
  95                 track->cb_color_info[i] = 0;
  96                 track->cb_color_view[i] = 0;
  97                 track->cb_color_pitch_idx[i] = 0;
  98                 track->cb_color_slice_idx[i] = 0;
  99                 track->cb_color_dim[i] = 0;
 100                 track->cb_color_pitch[i] = 0;
 101                 track->cb_color_slice[i] = 0;
 102                 track->cb_color_dim[i] = 0;
 103         }
 104         track->cb_target_mask = 0xFFFFFFFF;
 105         track->cb_shader_mask = 0xFFFFFFFF;
 106
 107         track->db_depth_view = 0xFFFFC000;
 108         track->db_depth_size = 0xFFFFFFFF;
 109         track->db_depth_size_idx = 0;
 110         track->db_depth_control = 0xFFFFFFFF;
 111         track->db_z_info = 0xFFFFFFFF;
 112         track->db_z_idx = 0xFFFFFFFF;
 113         track->db_z_read_offset = 0xFFFFFFFF;
 114         track->db_z_write_offset = 0xFFFFFFFF;
 115         track->db_z_read_bo = NULL;
 116         track->db_z_write_bo = NULL;
 117         track->db_s_info = 0xFFFFFFFF;
 118         track->db_s_idx = 0xFFFFFFFF;
 119         track->db_s_read_offset = 0xFFFFFFFF;
 120         track->db_s_write_offset = 0xFFFFFFFF;
 121         track->db_s_read_bo = NULL;
 122         track->db_s_write_bo = NULL;
 123 }
 124
 125 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
 126 {
 127         struct evergreen_cs_track *track = p->track;
 128
 129         /* we don't support stream out buffer yet */
 130         if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) {
 131                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
 132                 return -EINVAL;
 133         }
 134
 135         /* XXX fill in */
 136         return 0;
 137 }
 138
 139 /**
 140  * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
 141  * @parser:     parser structure holding parsing context.
 142  * @pkt:        where to store packet informations
 143  *
 144  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 145  * if packet is bigger than remaining ib size. or if packets is unknown.
 146  **/
 147 int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
 148                               struct radeon_cs_packet *pkt,
 149                               unsigned idx)
 150 {
 151         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 152         uint32_t header;
 153
 154         if (idx >= ib_chunk->length_dw) {
 155                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 156                           idx, ib_chunk->length_dw);
 157                 return -EINVAL;
 158         }
 159         header = radeon_get_ib_value(p, idx);
 160         pkt->idx = idx;
 161         pkt->type = CP_PACKET_GET_TYPE(header);
 162         pkt->count = CP_PACKET_GET_COUNT(header);
 163         pkt->one_reg_wr = 0;
 164         switch (pkt->type) {
 165         case PACKET_TYPE0:
 166                 pkt->reg = CP_PACKET0_GET_REG(header);
 167                 break;
 168         case PACKET_TYPE3:
 169                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 170                 break;
 171         case PACKET_TYPE2:
 172                 pkt->count = -1;
 173                 break;
 174         default:
 175                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 176                 return -EINVAL;
 177         }
 178         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 179                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 180                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 181                 return -EINVAL;
 182         }
 183         return 0;
 184 }
 185
 186 /**
 187  * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 188  * @parser:             parser structure holding parsing context.
 189  * @data:               pointer to relocation data
 190  * @offset_start:       starting offset
 191  * @offset_mask:        offset mask (to align start offset on)
 192  * @reloc:              reloc informations
 193  *
 194  * Check next packet is relocation packet3, do bo validation and compute
 195  * GPU offset using the provided start.
 196  **/
 197 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
 198                                           struct radeon_cs_reloc **cs_reloc)
 199 {
 200         struct radeon_cs_chunk *relocs_chunk;
 201         struct radeon_cs_packet p3reloc;
 202         unsigned idx;
 203         int r;
 204
 205         if (p->chunk_relocs_idx == -1) {
 206                 DRM_ERROR("No relocation chunk !\n");
 207                 return -EINVAL;
 208         }
 209         *cs_reloc = NULL;
 210         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 211         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
 212         if (r) {
 213                 return r;
 214         }
 215         p->idx += p3reloc.count + 2;
 216         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 217                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 218                           p3reloc.idx);
 219                 return -EINVAL;
 220         }
 221         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 222         if (idx >= relocs_chunk->length_dw) {
 223                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 224                           idx, relocs_chunk->length_dw);
 225                 return -EINVAL;
 226         }
 227         /* FIXME: we assume reloc size is 4 dwords */
 228         *cs_reloc = p->relocs_ptr[(idx / 4)];
 229         return 0;
 230 }
 231
 232 /**
 233  * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
 234  * @parser:             parser structure holding parsing context.
 235  *
 236  * Userspace sends a special sequence for VLINE waits.
 237  * PACKET0 - VLINE_START_END + value
 238  * PACKET3 - WAIT_REG_MEM poll vline status reg
 239  * RELOC (P3) - crtc_id in reloc.
 240  *
 241  * This function parses this and relocates the VLINE START END
 242  * and WAIT_REG_MEM packets to the correct crtc.
 243  * It also detects a switched off crtc and nulls out the
 244  * wait in that case.
 245  */
 246 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
 247 {
 248         struct drm_mode_object *obj;
 249         struct drm_crtc *crtc;
 250         struct radeon_crtc *radeon_crtc;
 251         struct radeon_cs_packet p3reloc, wait_reg_mem;
 252         int crtc_id;
 253         int r;
 254         uint32_t header, h_idx, reg, wait_reg_mem_info;
 255         volatile uint32_t *ib;
 256
 257         ib = p->ib->ptr;
 258
 259         /* parse the WAIT_REG_MEM */
 260         r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
 261         if (r)
 262                 return r;
 263
 264         /* check its a WAIT_REG_MEM */
 265         if (wait_reg_mem.type != PACKET_TYPE3 ||
 266             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 267                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 268                 return -EINVAL;
 269         }
 270
 271         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 272         /* bit 4 is reg (0) or mem (1) */
 273         if (wait_reg_mem_info & 0x10) {
 274                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 275                 return -EINVAL;
 276         }
 277         /* waiting for value to be equal */
 278         if ((wait_reg_mem_info & 0x7) != 0x3) {
 279                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
 280                 return -EINVAL;
 281         }
 282         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
 283                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
 284                 return -EINVAL;
 285         }
 286
 287         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
 288                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
 289                 return -EINVAL;
 290         }
 291
 292         /* jump over the NOP */
 293         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
 294         if (r)
 295                 return r;
 296
 297         h_idx = p->idx - 2;
 298         p->idx += wait_reg_mem.count + 2;
 299         p->idx += p3reloc.count + 2;
 300
 301         header = radeon_get_ib_value(p, h_idx);
 302         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
 303         reg = CP_PACKET0_GET_REG(header);
 304         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 305         if (!obj) {
 306                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 307                 return -EINVAL;
 308         }
 309         crtc = obj_to_crtc(obj);
 310         radeon_crtc = to_radeon_crtc(crtc);
 311         crtc_id = radeon_crtc->crtc_id;
 312
 313         if (!crtc->enabled) {
 314                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
 315                 ib[h_idx + 2] = PACKET2(0);
 316                 ib[h_idx + 3] = PACKET2(0);
 317                 ib[h_idx + 4] = PACKET2(0);
 318                 ib[h_idx + 5] = PACKET2(0);
 319                 ib[h_idx + 6] = PACKET2(0);
 320                 ib[h_idx + 7] = PACKET2(0);
 321                 ib[h_idx + 8] = PACKET2(0);
 322         } else {
 323                 switch (reg) {
 324                 case EVERGREEN_VLINE_START_END:
 325                         header &= ~R600_CP_PACKET0_REG_MASK;
 326                         header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
 327                         ib[h_idx] = header;
 328                         ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
 329                         break;
 330                 default:
 331                         DRM_ERROR("unknown crtc reloc\n");
 332                         return -EINVAL;
 333                 }
 334         }
 335         return 0;
 336 }
 337
 338 static int evergreen_packet0_check(struct radeon_cs_parser *p,
 339                                    struct radeon_cs_packet *pkt,
 340                                    unsigned idx, unsigned reg)
 341 {
 342         int r;
 343
 344         switch (reg) {
 345         case EVERGREEN_VLINE_START_END:
 346                 r = evergreen_cs_packet_parse_vline(p);
 347                 if (r) {
 348                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 349                                         idx, reg);
 350                         return r;
 351                 }
 352                 break;
 353         default:
 354                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
 355                        reg, idx);
 356                 return -EINVAL;
 357         }
 358         return 0;
 359 }
 360
 361 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
 362                                       struct radeon_cs_packet *pkt)
 363 {
 364         unsigned reg, i;
 365         unsigned idx;
 366         int r;
 367
 368         idx = pkt->idx + 1;
 369         reg = pkt->reg;
 370         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 371                 r = evergreen_packet0_check(p, pkt, idx, reg);
 372                 if (r) {
 373                         return r;
 374                 }
 375         }
 376         return 0;
 377 }
 378
 379 /**
 380  * evergreen_cs_check_reg() - check if register is authorized or not
 381  * @parser: parser structure holding parsing context
 382  * @reg: register we are testing
 383  * @idx: index into the cs buffer
 384  *
 385  * This function will test against evergreen_reg_safe_bm and return 0
 386  * if register is safe. If register is not flag as safe this function
 387  * will test it against a list of register needind special handling.
 388  */
 389 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 390 {
 391         struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
 392         struct radeon_cs_reloc *reloc;
 393         u32 last_reg;
 394         u32 m, i, tmp, *ib;
 395         int r;
 396
 397         if (p->rdev->family >= CHIP_CAYMAN)
 398                 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
 399         else
 400                 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
 401
 402         i = (reg >> 7);
 403         if (i >= last_reg) {
 404                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
 405                 return -EINVAL;
 406         }
 407         m = 1 << ((reg >> 2) & 31);
 408         if (p->rdev->family >= CHIP_CAYMAN) {
 409                 if (!(cayman_reg_safe_bm[i] & m))
 410                         return 0;
 411         } else {
 412                 if (!(evergreen_reg_safe_bm[i] & m))
 413                         return 0;
 414         }
 415         ib = p->ib->ptr;
 416         switch (reg) {
 417         /* force following reg to 0 in an attempt to disable out buffer
 418          * which will need us to better understand how it works to perform
 419          * security check on it (Jerome)
 420          */
 421         case SQ_ESGS_RING_SIZE:
 422         case SQ_GSVS_RING_SIZE:
 423         case SQ_ESTMP_RING_SIZE:
 424         case SQ_GSTMP_RING_SIZE:
 425         case SQ_HSTMP_RING_SIZE:
 426         case SQ_LSTMP_RING_SIZE:
 427         case SQ_PSTMP_RING_SIZE:
 428         case SQ_VSTMP_RING_SIZE:
 429         case SQ_ESGS_RING_ITEMSIZE:
 430         case SQ_ESTMP_RING_ITEMSIZE:
 431         case SQ_GSTMP_RING_ITEMSIZE:
 432         case SQ_GSVS_RING_ITEMSIZE:
 433         case SQ_GS_VERT_ITEMSIZE:
 434         case SQ_GS_VERT_ITEMSIZE_1:
 435         case SQ_GS_VERT_ITEMSIZE_2:
 436         case SQ_GS_VERT_ITEMSIZE_3:
 437         case SQ_GSVS_RING_OFFSET_1:
 438         case SQ_GSVS_RING_OFFSET_2:
 439         case SQ_GSVS_RING_OFFSET_3:
 440         case SQ_HSTMP_RING_ITEMSIZE:
 441         case SQ_LSTMP_RING_ITEMSIZE:
 442         case SQ_PSTMP_RING_ITEMSIZE:
 443         case SQ_VSTMP_RING_ITEMSIZE:
 444         case VGT_TF_RING_SIZE:
 445                 /* get value to populate the IB don't remove */
 446                 /*tmp =radeon_get_ib_value(p, idx);
 447                   ib[idx] = 0;*/
 448                 break;
 449         case SQ_ESGS_RING_BASE:
 450         case SQ_GSVS_RING_BASE:
 451         case SQ_ESTMP_RING_BASE:
 452         case SQ_GSTMP_RING_BASE:
 453         case SQ_HSTMP_RING_BASE:
 454         case SQ_LSTMP_RING_BASE:
 455         case SQ_PSTMP_RING_BASE:
 456         case SQ_VSTMP_RING_BASE:
 457                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 458                 if (r) {
 459                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 460                                         "0x%04X\n", reg);
 461                         return -EINVAL;
 462                 }
 463                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 464                 break;
 465         case DB_DEPTH_CONTROL:
 466                 track->db_depth_control = radeon_get_ib_value(p, idx);
 467                 break;
 468         case CAYMAN_DB_EQAA:
 469                 if (p->rdev->family < CHIP_CAYMAN) {
 470                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 471                                  "0x%04X\n", reg);
 472                         return -EINVAL;
 473                 }
 474                 break;
 475         case CAYMAN_DB_DEPTH_INFO:
 476                 if (p->rdev->family < CHIP_CAYMAN) {
 477                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 478                                  "0x%04X\n", reg);
 479                         return -EINVAL;
 480                 }
 481                 break;
 482         case DB_Z_INFO:
 483                 track->db_z_info = radeon_get_ib_value(p, idx);
 484                 if (!p->keep_tiling_flags) {
 485                         r = evergreen_cs_packet_next_reloc(p, &reloc);
 486                         if (r) {
 487                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
 488                                                 "0x%04X\n", reg);
 489                                 return -EINVAL;
 490                         }
 491                         ib[idx] &= ~Z_ARRAY_MODE(0xf);
 492                         track->db_z_info &= ~Z_ARRAY_MODE(0xf);
 493                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 494                                 ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
 495                                 track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
 496                         } else {
 497                                 ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 498                                 track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 499                         }
 500                 }
 501                 break;
 502         case DB_STENCIL_INFO:
 503                 track->db_s_info = radeon_get_ib_value(p, idx);
 504                 break;
 505         case DB_DEPTH_VIEW:
 506                 track->db_depth_view = radeon_get_ib_value(p, idx);
 507                 break;
 508         case DB_DEPTH_SIZE:
 509                 track->db_depth_size = radeon_get_ib_value(p, idx);
 510                 track->db_depth_size_idx = idx;
 511                 break;
 512         case DB_Z_READ_BASE:
 513                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 514                 if (r) {
 515                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 516                                         "0x%04X\n", reg);
 517                         return -EINVAL;
 518                 }
 519                 track->db_z_read_offset = radeon_get_ib_value(p, idx);
 520                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 521                 track->db_z_read_bo = reloc->robj;
 522                 break;
 523         case DB_Z_WRITE_BASE:
 524                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 525                 if (r) {
 526                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 527                                         "0x%04X\n", reg);
 528                         return -EINVAL;
 529                 }
 530                 track->db_z_write_offset = radeon_get_ib_value(p, idx);
 531                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 532                 track->db_z_write_bo = reloc->robj;
 533                 break;
 534         case DB_STENCIL_READ_BASE:
 535                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 536                 if (r) {
 537                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 538                                         "0x%04X\n", reg);
 539                         return -EINVAL;
 540                 }
 541                 track->db_s_read_offset = radeon_get_ib_value(p, idx);
 542                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 543                 track->db_s_read_bo = reloc->robj;
 544                 break;
 545         case DB_STENCIL_WRITE_BASE:
 546                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 547                 if (r) {
 548                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 549                                         "0x%04X\n", reg);
 550                         return -EINVAL;
 551                 }
 552                 track->db_s_write_offset = radeon_get_ib_value(p, idx);
 553                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 554                 track->db_s_write_bo = reloc->robj;
 555                 break;
 556         case VGT_STRMOUT_CONFIG:
 557                 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
 558                 break;
 559         case VGT_STRMOUT_BUFFER_CONFIG:
 560                 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
 561                 break;
 562         case CB_TARGET_MASK:
 563                 track->cb_target_mask = radeon_get_ib_value(p, idx);
 564                 break;
 565         case CB_SHADER_MASK:
 566                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
 567                 break;
 568         case PA_SC_AA_CONFIG:
 569                 if (p->rdev->family >= CHIP_CAYMAN) {
 570                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 571                                  "0x%04X\n", reg);
 572                         return -EINVAL;
 573                 }
 574                 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
 575                 track->nsamples = 1 << tmp;
 576                 break;
 577         case CAYMAN_PA_SC_AA_CONFIG:
 578                 if (p->rdev->family < CHIP_CAYMAN) {
 579                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 580                                  "0x%04X\n", reg);
 581                         return -EINVAL;
 582                 }
 583                 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
 584                 track->nsamples = 1 << tmp;
 585                 break;
 586         case CB_COLOR0_VIEW:
 587         case CB_COLOR1_VIEW:
 588         case CB_COLOR2_VIEW:
 589         case CB_COLOR3_VIEW:
 590         case CB_COLOR4_VIEW:
 591         case CB_COLOR5_VIEW:
 592         case CB_COLOR6_VIEW:
 593         case CB_COLOR7_VIEW:
 594                 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
 595                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
 596                 break;
 597         case CB_COLOR8_VIEW:
 598         case CB_COLOR9_VIEW:
 599         case CB_COLOR10_VIEW:
 600         case CB_COLOR11_VIEW:
 601                 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
 602                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
 603                 break;
 604         case CB_COLOR0_INFO:
 605         case CB_COLOR1_INFO:
 606         case CB_COLOR2_INFO:
 607         case CB_COLOR3_INFO:
 608         case CB_COLOR4_INFO:
 609         case CB_COLOR5_INFO:
 610         case CB_COLOR6_INFO:
 611         case CB_COLOR7_INFO:
 612                 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
 613                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
 614                 if (!p->keep_tiling_flags) {
 615                         r = evergreen_cs_packet_next_reloc(p, &reloc);
 616                         if (r) {
 617                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
 618                                                 "0x%04X\n", reg);
 619                                 return -EINVAL;
 620                         }
 621                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 622                                 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
 623                                 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
 624                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
 625                                 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 626                                 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 627                         }
 628                 }
 629                 break;
 630         case CB_COLOR8_INFO:
 631         case CB_COLOR9_INFO:
 632         case CB_COLOR10_INFO:
 633         case CB_COLOR11_INFO:
 634                 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
 635                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
 636                 if (!p->keep_tiling_flags) {
 637                         r = evergreen_cs_packet_next_reloc(p, &reloc);
 638                         if (r) {
 639                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
 640                                                 "0x%04X\n", reg);
 641                                 return -EINVAL;
 642                         }
 643                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
 644                                 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
 645                                 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
 646                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
 647                                 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 648                                 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 649                         }
 650                 }
 651                 break;
 652         case CB_COLOR0_PITCH:
 653         case CB_COLOR1_PITCH:
 654         case CB_COLOR2_PITCH:
 655         case CB_COLOR3_PITCH:
 656         case CB_COLOR4_PITCH:
 657         case CB_COLOR5_PITCH:
 658         case CB_COLOR6_PITCH:
 659         case CB_COLOR7_PITCH:
 660                 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
 661                 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
 662                 track->cb_color_pitch_idx[tmp] = idx;
 663                 break;
 664         case CB_COLOR8_PITCH:
 665         case CB_COLOR9_PITCH:
 666         case CB_COLOR10_PITCH:
 667         case CB_COLOR11_PITCH:
 668                 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
 669                 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
 670                 track->cb_color_pitch_idx[tmp] = idx;
 671                 break;
 672         case CB_COLOR0_SLICE:
 673         case CB_COLOR1_SLICE:
 674         case CB_COLOR2_SLICE:
 675         case CB_COLOR3_SLICE:
 676         case CB_COLOR4_SLICE:
 677         case CB_COLOR5_SLICE:
 678         case CB_COLOR6_SLICE:
 679         case CB_COLOR7_SLICE:
 680                 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
 681                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
 682                 track->cb_color_slice_idx[tmp] = idx;
 683                 break;
 684         case CB_COLOR8_SLICE:
 685         case CB_COLOR9_SLICE:
 686         case CB_COLOR10_SLICE:
 687         case CB_COLOR11_SLICE:
 688                 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
 689                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
 690                 track->cb_color_slice_idx[tmp] = idx;
 691                 break;
 692         case CB_COLOR0_ATTRIB:
 693         case CB_COLOR1_ATTRIB:
 694         case CB_COLOR2_ATTRIB:
 695         case CB_COLOR3_ATTRIB:
 696         case CB_COLOR4_ATTRIB:
 697         case CB_COLOR5_ATTRIB:
 698         case CB_COLOR6_ATTRIB:
 699         case CB_COLOR7_ATTRIB:
 700         case CB_COLOR8_ATTRIB:
 701         case CB_COLOR9_ATTRIB:
 702         case CB_COLOR10_ATTRIB:
 703         case CB_COLOR11_ATTRIB:
 704                 break;
 705         case CB_COLOR0_DIM:
 706         case CB_COLOR1_DIM:
 707         case CB_COLOR2_DIM:
 708         case CB_COLOR3_DIM:
 709         case CB_COLOR4_DIM:
 710         case CB_COLOR5_DIM:
 711         case CB_COLOR6_DIM:
 712         case CB_COLOR7_DIM:
 713                 tmp = (reg - CB_COLOR0_DIM) / 0x3c;
 714                 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
 715                 track->cb_color_dim_idx[tmp] = idx;
 716                 break;
 717         case CB_COLOR8_DIM:
 718         case CB_COLOR9_DIM:
 719         case CB_COLOR10_DIM:
 720         case CB_COLOR11_DIM:
 721                 tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8;
 722                 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
 723                 track->cb_color_dim_idx[tmp] = idx;
 724                 break;
 725         case CB_COLOR0_FMASK:
 726         case CB_COLOR1_FMASK:
 727         case CB_COLOR2_FMASK:
 728         case CB_COLOR3_FMASK:
 729         case CB_COLOR4_FMASK:
 730         case CB_COLOR5_FMASK:
 731         case CB_COLOR6_FMASK:
 732         case CB_COLOR7_FMASK:
 733                 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
 734                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 735                 if (r) {
 736                         dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
 737                         return -EINVAL;
 738                 }
 739                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 740                 track->cb_color_fmask_bo[tmp] = reloc->robj;
 741                 break;
 742         case CB_COLOR0_CMASK:
 743         case CB_COLOR1_CMASK:
 744         case CB_COLOR2_CMASK:
 745         case CB_COLOR3_CMASK:
 746         case CB_COLOR4_CMASK:
 747         case CB_COLOR5_CMASK:
 748         case CB_COLOR6_CMASK:
 749         case CB_COLOR7_CMASK:
 750                 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
 751                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 752                 if (r) {
 753                         dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
 754                         return -EINVAL;
 755                 }
 756                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 757                 track->cb_color_cmask_bo[tmp] = reloc->robj;
 758                 break;
 759         case CB_COLOR0_FMASK_SLICE:
 760         case CB_COLOR1_FMASK_SLICE:
 761         case CB_COLOR2_FMASK_SLICE:
 762         case CB_COLOR3_FMASK_SLICE:
 763         case CB_COLOR4_FMASK_SLICE:
 764         case CB_COLOR5_FMASK_SLICE:
 765         case CB_COLOR6_FMASK_SLICE:
 766         case CB_COLOR7_FMASK_SLICE:
 767                 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
 768                 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
 769                 break;
 770         case CB_COLOR0_CMASK_SLICE:
 771         case CB_COLOR1_CMASK_SLICE:
 772         case CB_COLOR2_CMASK_SLICE:
 773         case CB_COLOR3_CMASK_SLICE:
 774         case CB_COLOR4_CMASK_SLICE:
 775         case CB_COLOR5_CMASK_SLICE:
 776         case CB_COLOR6_CMASK_SLICE:
 777         case CB_COLOR7_CMASK_SLICE:
 778                 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
 779                 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
 780                 break;
 781         case CB_COLOR0_BASE:
 782         case CB_COLOR1_BASE:
 783         case CB_COLOR2_BASE:
 784         case CB_COLOR3_BASE:
 785         case CB_COLOR4_BASE:
 786         case CB_COLOR5_BASE:
 787         case CB_COLOR6_BASE:
 788         case CB_COLOR7_BASE:
 789                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 790                 if (r) {
 791                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 792                                         "0x%04X\n", reg);
 793                         return -EINVAL;
 794                 }
 795                 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
 796                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
 797                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 798                 track->cb_color_base_last[tmp] = ib[idx];
 799                 track->cb_color_bo[tmp] = reloc->robj;
 800                 break;
 801         case CB_COLOR8_BASE:
 802         case CB_COLOR9_BASE:
 803         case CB_COLOR10_BASE:
 804         case CB_COLOR11_BASE:
 805                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 806                 if (r) {
 807                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 808                                         "0x%04X\n", reg);
 809                         return -EINVAL;
 810                 }
 811                 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
 812                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
 813                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 814                 track->cb_color_base_last[tmp] = ib[idx];
 815                 track->cb_color_bo[tmp] = reloc->robj;
 816                 break;
 817         case CB_IMMED0_BASE:
 818         case CB_IMMED1_BASE:
 819         case CB_IMMED2_BASE:
 820         case CB_IMMED3_BASE:
 821         case CB_IMMED4_BASE:
 822         case CB_IMMED5_BASE:
 823         case CB_IMMED6_BASE:
 824         case CB_IMMED7_BASE:
 825         case CB_IMMED8_BASE:
 826         case CB_IMMED9_BASE:
 827         case CB_IMMED10_BASE:
 828         case CB_IMMED11_BASE:
 829         case DB_HTILE_DATA_BASE:
 830         case SQ_PGM_START_FS:
 831         case SQ_PGM_START_ES:
 832         case SQ_PGM_START_VS:
 833         case SQ_PGM_START_GS:
 834         case SQ_PGM_START_PS:
 835         case SQ_PGM_START_HS:
 836         case SQ_PGM_START_LS:
 837         case SQ_CONST_MEM_BASE:
 838         case SQ_ALU_CONST_CACHE_GS_0:
 839         case SQ_ALU_CONST_CACHE_GS_1:
 840         case SQ_ALU_CONST_CACHE_GS_2:
 841         case SQ_ALU_CONST_CACHE_GS_3:
 842         case SQ_ALU_CONST_CACHE_GS_4:
 843         case SQ_ALU_CONST_CACHE_GS_5:
 844         case SQ_ALU_CONST_CACHE_GS_6:
 845         case SQ_ALU_CONST_CACHE_GS_7:
 846         case SQ_ALU_CONST_CACHE_GS_8:
 847         case SQ_ALU_CONST_CACHE_GS_9:
 848         case SQ_ALU_CONST_CACHE_GS_10:
 849         case SQ_ALU_CONST_CACHE_GS_11:
 850         case SQ_ALU_CONST_CACHE_GS_12:
 851         case SQ_ALU_CONST_CACHE_GS_13:
 852         case SQ_ALU_CONST_CACHE_GS_14:
 853         case SQ_ALU_CONST_CACHE_GS_15:
 854         case SQ_ALU_CONST_CACHE_PS_0:
 855         case SQ_ALU_CONST_CACHE_PS_1:
 856         case SQ_ALU_CONST_CACHE_PS_2:
 857         case SQ_ALU_CONST_CACHE_PS_3:
 858         case SQ_ALU_CONST_CACHE_PS_4:
 859         case SQ_ALU_CONST_CACHE_PS_5:
 860         case SQ_ALU_CONST_CACHE_PS_6:
 861         case SQ_ALU_CONST_CACHE_PS_7:
 862         case SQ_ALU_CONST_CACHE_PS_8:
 863         case SQ_ALU_CONST_CACHE_PS_9:
 864         case SQ_ALU_CONST_CACHE_PS_10:
 865         case SQ_ALU_CONST_CACHE_PS_11:
 866         case SQ_ALU_CONST_CACHE_PS_12:
 867         case SQ_ALU_CONST_CACHE_PS_13:
 868         case SQ_ALU_CONST_CACHE_PS_14:
 869         case SQ_ALU_CONST_CACHE_PS_15:
 870         case SQ_ALU_CONST_CACHE_VS_0:
 871         case SQ_ALU_CONST_CACHE_VS_1:
 872         case SQ_ALU_CONST_CACHE_VS_2:
 873         case SQ_ALU_CONST_CACHE_VS_3:
 874         case SQ_ALU_CONST_CACHE_VS_4:
 875         case SQ_ALU_CONST_CACHE_VS_5:
 876         case SQ_ALU_CONST_CACHE_VS_6:
 877         case SQ_ALU_CONST_CACHE_VS_7:
 878         case SQ_ALU_CONST_CACHE_VS_8:
 879         case SQ_ALU_CONST_CACHE_VS_9:
 880         case SQ_ALU_CONST_CACHE_VS_10:
 881         case SQ_ALU_CONST_CACHE_VS_11:
 882         case SQ_ALU_CONST_CACHE_VS_12:
 883         case SQ_ALU_CONST_CACHE_VS_13:
 884         case SQ_ALU_CONST_CACHE_VS_14:
 885         case SQ_ALU_CONST_CACHE_VS_15:
 886         case SQ_ALU_CONST_CACHE_HS_0:
 887         case SQ_ALU_CONST_CACHE_HS_1:
 888         case SQ_ALU_CONST_CACHE_HS_2:
 889         case SQ_ALU_CONST_CACHE_HS_3:
 890         case SQ_ALU_CONST_CACHE_HS_4:
 891         case SQ_ALU_CONST_CACHE_HS_5:
 892         case SQ_ALU_CONST_CACHE_HS_6:
 893         case SQ_ALU_CONST_CACHE_HS_7:
 894         case SQ_ALU_CONST_CACHE_HS_8:
 895         case SQ_ALU_CONST_CACHE_HS_9:
 896         case SQ_ALU_CONST_CACHE_HS_10:
 897         case SQ_ALU_CONST_CACHE_HS_11:
 898         case SQ_ALU_CONST_CACHE_HS_12:
 899         case SQ_ALU_CONST_CACHE_HS_13:
 900         case SQ_ALU_CONST_CACHE_HS_14:
 901         case SQ_ALU_CONST_CACHE_HS_15:
 902         case SQ_ALU_CONST_CACHE_LS_0:
 903         case SQ_ALU_CONST_CACHE_LS_1:
 904         case SQ_ALU_CONST_CACHE_LS_2:
 905         case SQ_ALU_CONST_CACHE_LS_3:
 906         case SQ_ALU_CONST_CACHE_LS_4:
 907         case SQ_ALU_CONST_CACHE_LS_5:
 908         case SQ_ALU_CONST_CACHE_LS_6:
 909         case SQ_ALU_CONST_CACHE_LS_7:
 910         case SQ_ALU_CONST_CACHE_LS_8:
 911         case SQ_ALU_CONST_CACHE_LS_9:
 912         case SQ_ALU_CONST_CACHE_LS_10:
 913         case SQ_ALU_CONST_CACHE_LS_11:
 914         case SQ_ALU_CONST_CACHE_LS_12:
 915         case SQ_ALU_CONST_CACHE_LS_13:
 916         case SQ_ALU_CONST_CACHE_LS_14:
 917         case SQ_ALU_CONST_CACHE_LS_15:
 918                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 919                 if (r) {
 920                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 921                                         "0x%04X\n", reg);
 922                         return -EINVAL;
 923                 }
 924                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 925                 break;
 926         case SX_MEMORY_EXPORT_BASE:
 927                 if (p->rdev->family >= CHIP_CAYMAN) {
 928                         dev_warn(p->dev, "bad SET_CONFIG_REG "
 929                                  "0x%04X\n", reg);
 930                         return -EINVAL;
 931                 }
 932                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 933                 if (r) {
 934                         dev_warn(p->dev, "bad SET_CONFIG_REG "
 935                                         "0x%04X\n", reg);
 936                         return -EINVAL;
 937                 }
 938                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 939                 break;
 940         case CAYMAN_SX_SCATTER_EXPORT_BASE:
 941                 if (p->rdev->family < CHIP_CAYMAN) {
 942                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 943                                  "0x%04X\n", reg);
 944                         return -EINVAL;
 945                 }
 946                 r = evergreen_cs_packet_next_reloc(p, &reloc);
 947                 if (r) {
 948                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
 949                                         "0x%04X\n", reg);
 950                         return -EINVAL;
 951                 }
 952                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
 953                 break;
 954         default:
 955                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
 956                 return -EINVAL;
 957         }
 958         return 0;
 959 }
 960
 961 /**
 962  * evergreen_check_texture_resource() - check if register is authorized or not
 963  * @p: parser structure holding parsing context
 964  * @idx: index into the cs buffer
 965  * @texture: texture's bo structure
 966  * @mipmap: mipmap's bo structure
 967  *
 968  * This function will check that the resource has valid field and that
 969  * the texture and mipmap bo object are big enough to cover this resource.
 970  */
 971 static int evergreen_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
 972                                                    struct radeon_bo *texture,
 973                                                    struct radeon_bo *mipmap)
 974 {
 975         /* XXX fill in */
 976         return 0;
 977 }
 978
 979 static int evergreen_packet3_check(struct radeon_cs_parser *p,
 980                                    struct radeon_cs_packet *pkt)
 981 {
 982         struct radeon_cs_reloc *reloc;
 983         struct evergreen_cs_track *track;
 984         volatile u32 *ib;
 985         unsigned idx;
 986         unsigned i;
 987         unsigned start_reg, end_reg, reg;
 988         int r;
 989         u32 idx_value;
 990
 991         track = (struct evergreen_cs_track *)p->track;
 992         ib = p->ib->ptr;
 993         idx = pkt->idx + 1;
 994         idx_value = radeon_get_ib_value(p, idx);
 995
 996         switch (pkt->opcode) {
 997         case PACKET3_SET_PREDICATION:
 998         {
 999                 int pred_op;
1000                 int tmp;
1001                 if (pkt->count != 1) {
1002                         DRM_ERROR("bad SET PREDICATION\n");
1003                         return -EINVAL;
1004                 }
1005
1006                 tmp = radeon_get_ib_value(p, idx + 1);
1007                 pred_op = (tmp >> 16) & 0x7;
1008
1009                 /* for the clear predicate operation */
1010                 if (pred_op == 0)
1011                         return 0;
1012
1013                 if (pred_op > 2) {
1014                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1015                         return -EINVAL;
1016                 }
1017
1018                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1019                 if (r) {
1020                         DRM_ERROR("bad SET PREDICATION\n");
1021                         return -EINVAL;
1022                 }
1023
1024                 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1025                 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1026         }
1027         break;
1028         case PACKET3_CONTEXT_CONTROL:
1029                 if (pkt->count != 1) {
1030                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1031                         return -EINVAL;
1032                 }
1033                 break;
1034         case PACKET3_INDEX_TYPE:
1035         case PACKET3_NUM_INSTANCES:
1036         case PACKET3_CLEAR_STATE:
1037                 if (pkt->count) {
1038                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1039                         return -EINVAL;
1040                 }
1041                 break;
1042         case CAYMAN_PACKET3_DEALLOC_STATE:
1043                 if (p->rdev->family < CHIP_CAYMAN) {
1044                         DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1045                         return -EINVAL;
1046                 }
1047                 if (pkt->count) {
1048                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1049                         return -EINVAL;
1050                 }
1051                 break;
1052         case PACKET3_INDEX_BASE:
1053                 if (pkt->count != 1) {
1054                         DRM_ERROR("bad INDEX_BASE\n");
1055                         return -EINVAL;
1056                 }
1057                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1058                 if (r) {
1059                         DRM_ERROR("bad INDEX_BASE\n");
1060                         return -EINVAL;
1061                 }
1062                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1063                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1064                 r = evergreen_cs_track_check(p);
1065                 if (r) {
1066                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1067                         return r;
1068                 }
1069                 break;
1070         case PACKET3_DRAW_INDEX:
1071                 if (pkt->count != 3) {
1072                         DRM_ERROR("bad DRAW_INDEX\n");
1073                         return -EINVAL;
1074                 }
1075                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1076                 if (r) {
1077                         DRM_ERROR("bad DRAW_INDEX\n");
1078                         return -EINVAL;
1079                 }
1080                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1081                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1082                 r = evergreen_cs_track_check(p);
1083                 if (r) {
1084                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1085                         return r;
1086                 }
1087                 break;
1088         case PACKET3_DRAW_INDEX_2:
1089                 if (pkt->count != 4) {
1090                         DRM_ERROR("bad DRAW_INDEX_2\n");
1091                         return -EINVAL;
1092                 }
1093                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1094                 if (r) {
1095                         DRM_ERROR("bad DRAW_INDEX_2\n");
1096                         return -EINVAL;
1097                 }
1098                 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1099                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1100                 r = evergreen_cs_track_check(p);
1101                 if (r) {
1102                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1103                         return r;
1104                 }
1105                 break;
1106         case PACKET3_DRAW_INDEX_AUTO:
1107                 if (pkt->count != 1) {
1108                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1109                         return -EINVAL;
1110                 }
1111                 r = evergreen_cs_track_check(p);
1112                 if (r) {
1113                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1114                         return r;
1115                 }
1116                 break;
1117         case PACKET3_DRAW_INDEX_MULTI_AUTO:
1118                 if (pkt->count != 2) {
1119                         DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
1120                         return -EINVAL;
1121                 }
1122                 r = evergreen_cs_track_check(p);
1123                 if (r) {
1124                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1125                         return r;
1126                 }
1127                 break;
1128         case PACKET3_DRAW_INDEX_IMMD:
1129                 if (pkt->count < 2) {
1130                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1131                         return -EINVAL;
1132                 }
1133                 r = evergreen_cs_track_check(p);
1134                 if (r) {
1135                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1136                         return r;
1137                 }
1138                 break;
1139         case PACKET3_DRAW_INDEX_OFFSET:
1140                 if (pkt->count != 2) {
1141                         DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
1142                         return -EINVAL;
1143                 }
1144                 r = evergreen_cs_track_check(p);
1145                 if (r) {
1146                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1147                         return r;
1148                 }
1149                 break;
1150         case PACKET3_DRAW_INDEX_OFFSET_2:
1151                 if (pkt->count != 3) {
1152                         DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
1153                         return -EINVAL;
1154                 }
1155                 r = evergreen_cs_track_check(p);
1156                 if (r) {
1157                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1158                         return r;
1159                 }
1160                 break;
1161         case PACKET3_DISPATCH_DIRECT:
1162                 if (pkt->count != 3) {
1163                         DRM_ERROR("bad DISPATCH_DIRECT\n");
1164                         return -EINVAL;
1165                 }
1166                 r = evergreen_cs_track_check(p);
1167                 if (r) {
1168                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1169                         return r;
1170                 }
1171                 break;
1172         case PACKET3_DISPATCH_INDIRECT:
1173                 if (pkt->count != 1) {
1174                         DRM_ERROR("bad DISPATCH_INDIRECT\n");
1175                         return -EINVAL;
1176                 }
1177                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1178                 if (r) {
1179                         DRM_ERROR("bad DISPATCH_INDIRECT\n");
1180                         return -EINVAL;
1181                 }
1182                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1183                 r = evergreen_cs_track_check(p);
1184                 if (r) {
1185                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1186                         return r;
1187                 }
1188                 break;
1189         case PACKET3_WAIT_REG_MEM:
1190                 if (pkt->count != 5) {
1191                         DRM_ERROR("bad WAIT_REG_MEM\n");
1192                         return -EINVAL;
1193                 }
1194                 /* bit 4 is reg (0) or mem (1) */
1195                 if (idx_value & 0x10) {
1196                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1197                         if (r) {
1198                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1199                                 return -EINVAL;
1200                         }
1201                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1202                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1203                 }
1204                 break;
1205         case PACKET3_SURFACE_SYNC:
1206                 if (pkt->count != 3) {
1207                         DRM_ERROR("bad SURFACE_SYNC\n");
1208                         return -EINVAL;
1209                 }
1210                 /* 0xffffffff/0x0 is flush all cache flag */
1211                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1212                     radeon_get_ib_value(p, idx + 2) != 0) {
1213                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1214                         if (r) {
1215                                 DRM_ERROR("bad SURFACE_SYNC\n");
1216                                 return -EINVAL;
1217                         }
1218                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1219                 }
1220                 break;
1221         case PACKET3_EVENT_WRITE:
1222                 if (pkt->count != 2 && pkt->count != 0) {
1223                         DRM_ERROR("bad EVENT_WRITE\n");
1224                         return -EINVAL;
1225                 }
1226                 if (pkt->count) {
1227                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1228                         if (r) {
1229                                 DRM_ERROR("bad EVENT_WRITE\n");
1230                                 return -EINVAL;
1231                         }
1232                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1233                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1234                 }
1235                 break;
1236         case PACKET3_EVENT_WRITE_EOP:
1237                 if (pkt->count != 4) {
1238                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1239                         return -EINVAL;
1240                 }
1241                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1242                 if (r) {
1243                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1244                         return -EINVAL;
1245                 }
1246                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1247                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1248                 break;
1249         case PACKET3_EVENT_WRITE_EOS:
1250                 if (pkt->count != 3) {
1251                         DRM_ERROR("bad EVENT_WRITE_EOS\n");
1252                         return -EINVAL;
1253                 }
1254                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1255                 if (r) {
1256                         DRM_ERROR("bad EVENT_WRITE_EOS\n");
1257                         return -EINVAL;
1258                 }
1259                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1260                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1261                 break;
1262         case PACKET3_SET_CONFIG_REG:
1263                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
1264                 end_reg = 4 * pkt->count + start_reg - 4;
1265                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
1266                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1267                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1268                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1269                         return -EINVAL;
1270                 }
1271                 for (i = 0; i < pkt->count; i++) {
1272                         reg = start_reg + (4 * i);
1273                         r = evergreen_cs_check_reg(p, reg, idx+1+i);
1274                         if (r)
1275                                 return r;
1276                 }
1277                 break;
1278         case PACKET3_SET_CONTEXT_REG:
1279                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
1280                 end_reg = 4 * pkt->count + start_reg - 4;
1281                 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
1282                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1283                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1284                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1285                         return -EINVAL;
1286                 }
1287                 for (i = 0; i < pkt->count; i++) {
1288                         reg = start_reg + (4 * i);
1289                         r = evergreen_cs_check_reg(p, reg, idx+1+i);
1290                         if (r)
1291                                 return r;
1292                 }
1293                 break;
1294         case PACKET3_SET_RESOURCE:
1295                 if (pkt->count % 8) {
1296                         DRM_ERROR("bad SET_RESOURCE\n");
1297                         return -EINVAL;
1298                 }
1299                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
1300                 end_reg = 4 * pkt->count + start_reg - 4;
1301                 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
1302                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1303                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1304                         DRM_ERROR("bad SET_RESOURCE\n");
1305                         return -EINVAL;
1306                 }
1307                 for (i = 0; i < (pkt->count / 8); i++) {
1308                         struct radeon_bo *texture, *mipmap;
1309                         u32 size, offset;
1310
1311                         switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
1312                         case SQ_TEX_VTX_VALID_TEXTURE:
1313                                 /* tex base */
1314                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1315                                 if (r) {
1316                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
1317                                         return -EINVAL;
1318                                 }
1319                                 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1320                                 if (!p->keep_tiling_flags) {
1321                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1322                                                 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
1323                                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1324                                                 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
1325                                 }
1326                                 texture = reloc->robj;
1327                                 /* tex mip base */
1328                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1329                                 if (r) {
1330                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
1331                                         return -EINVAL;
1332                                 }
1333                                 ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1334                                 mipmap = reloc->robj;
1335                                 r = evergreen_check_texture_resource(p,  idx+1+(i*8),
1336                                                 texture, mipmap);
1337                                 if (r)
1338                                         return r;
1339                                 break;
1340                         case SQ_TEX_VTX_VALID_BUFFER:
1341                                 /* vtx base */
1342                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1343                                 if (r) {
1344                                         DRM_ERROR("bad SET_RESOURCE (vtx)\n");
1345                                         return -EINVAL;
1346                                 }
1347                                 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
1348                                 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
1349                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1350                                         /* force size to size of the buffer */
1351                                         dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1352                                         ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj);
1353                                 }
1354                                 ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1355                                 ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1356                                 break;
1357                         case SQ_TEX_VTX_INVALID_TEXTURE:
1358                         case SQ_TEX_VTX_INVALID_BUFFER:
1359                         default:
1360                                 DRM_ERROR("bad SET_RESOURCE\n");
1361                                 return -EINVAL;
1362                         }
1363                 }
1364                 break;
1365         case PACKET3_SET_ALU_CONST:
1366                 /* XXX fix me ALU const buffers only */
1367                 break;
1368         case PACKET3_SET_BOOL_CONST:
1369                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
1370                 end_reg = 4 * pkt->count + start_reg - 4;
1371                 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
1372                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1373                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1374                         DRM_ERROR("bad SET_BOOL_CONST\n");
1375                         return -EINVAL;
1376                 }
1377                 break;
1378         case PACKET3_SET_LOOP_CONST:
1379                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
1380                 end_reg = 4 * pkt->count + start_reg - 4;
1381                 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
1382                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1383                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1384                         DRM_ERROR("bad SET_LOOP_CONST\n");
1385                         return -EINVAL;
1386                 }
1387                 break;
1388         case PACKET3_SET_CTL_CONST:
1389                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
1390                 end_reg = 4 * pkt->count + start_reg - 4;
1391                 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
1392                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1393                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1394                         DRM_ERROR("bad SET_CTL_CONST\n");
1395                         return -EINVAL;
1396                 }
1397                 break;
1398         case PACKET3_SET_SAMPLER:
1399                 if (pkt->count % 3) {
1400                         DRM_ERROR("bad SET_SAMPLER\n");
1401                         return -EINVAL;
1402                 }
1403                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
1404                 end_reg = 4 * pkt->count + start_reg - 4;
1405                 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
1406                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1407                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1408                         DRM_ERROR("bad SET_SAMPLER\n");
1409                         return -EINVAL;
1410                 }
1411                 break;
1412         case PACKET3_NOP:
1413                 break;
1414         default:
1415                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1416                 return -EINVAL;
1417         }
1418         return 0;
1419 }
1420
1421 int evergreen_cs_parse(struct radeon_cs_parser *p)
1422 {
1423         struct radeon_cs_packet pkt;
1424         struct evergreen_cs_track *track;
1425         int r;
1426
1427         if (p->track == NULL) {
1428                 /* initialize tracker, we are in kms */
1429                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1430                 if (track == NULL)
1431                         return -ENOMEM;
1432                 evergreen_cs_track_init(track);
1433                 track->npipes = p->rdev->config.evergreen.tiling_npipes;
1434                 track->nbanks = p->rdev->config.evergreen.tiling_nbanks;
1435                 track->group_size = p->rdev->config.evergreen.tiling_group_size;
1436                 p->track = track;
1437         }
1438         do {
1439                 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
1440                 if (r) {
1441                         kfree(p->track);
1442                         p->track = NULL;
1443                         return r;
1444                 }
1445                 p->idx += pkt.count + 2;
1446                 switch (pkt.type) {
1447                 case PACKET_TYPE0:
1448                         r = evergreen_cs_parse_packet0(p, &pkt);
1449                         break;
1450                 case PACKET_TYPE2:
1451                         break;
1452                 case PACKET_TYPE3:
1453                         r = evergreen_packet3_check(p, &pkt);
1454                         break;
1455                 default:
1456                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1457                         kfree(p->track);
1458                         p->track = NULL;
1459                         return -EINVAL;
1460                 }
1461                 if (r) {
1462                         kfree(p->track);
1463                         p->track = NULL;
1464                         return r;
1465                 }
1466         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1467 #if 0
1468         for (r = 0; r < p->ib->length_dw; r++) {
1469                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1470                 mdelay(1);
1471         }
1472 #endif
1473         kfree(p->track);
1474         p->track = NULL;
1475         return 0;
1476 }
1477