drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  45 {
  46         u16 ctl, v;
  47         int cap, err;
  48
  49         cap = pci_pcie_cap(rdev->pdev);
  50         if (!cap)
  51                 return;
  52
  53         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  54         if (err)
  55                 return;
  56
  57         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  58
  59         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  60          * to avoid hangs or perfomance issues
  61          */
  62         if ((v == 0) || (v == 6) || (v == 7)) {
  63                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
  64                 ctl |= (2 << 12);
  65                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
  66         }
  67 }
  68
  69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  70 {
  71         /* enable the pflip int */
  72         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  73 }
  74
  75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  76 {
  77         /* disable the pflip int */
  78         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  79 }
  80
  81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  82 {
  83         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  84         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  85
  86         /* Lock the graphics update lock */
  87         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  88         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  89
  90         /* update the scanout addresses */
  91         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  92                upper_32_bits(crtc_base));
  93         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  94                (u32)crtc_base);
  95
  96         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  97                upper_32_bits(crtc_base));
  98         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  99                (u32)crtc_base);
 100
 101         /* Wait for update_pending to go high. */
 102         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
 103         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 104
 105         /* Unlock the lock, so double-buffering can take place inside vblank */
 106         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 107         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 108
 109         /* Return current update_pending status: */
 110         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 111 }
 112
 113 /* get temperature in millidegrees */
 114 int evergreen_get_temp(struct radeon_device *rdev)
 115 {
 116         u32 temp, toffset;
 117         int actual_temp = 0;
 118
 119         if (rdev->family == CHIP_JUNIPER) {
 120                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 121                         TOFFSET_SHIFT;
 122                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 123                         TS0_ADC_DOUT_SHIFT;
 124
 125                 if (toffset & 0x100)
 126                         actual_temp = temp / 2 - (0x200 - toffset);
 127                 else
 128                         actual_temp = temp / 2 + toffset;
 129
 130                 actual_temp = actual_temp * 1000;
 131
 132         } else {
 133                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 134                         ASIC_T_SHIFT;
 135
 136                 if (temp & 0x400)
 137                         actual_temp = -256;
 138                 else if (temp & 0x200)
 139                         actual_temp = 255;
 140                 else if (temp & 0x100) {
 141                         actual_temp = temp & 0x1ff;
 142                         actual_temp |= ~0x1ff;
 143                 } else
 144                         actual_temp = temp & 0xff;
 145
 146                 actual_temp = (actual_temp * 1000) / 2;
 147         }
 148
 149         return actual_temp;
 150 }
 151
 152 int sumo_get_temp(struct radeon_device *rdev)
 153 {
 154         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 155         int actual_temp = temp - 49;
 156
 157         return actual_temp * 1000;
 158 }
 159
 160 void evergreen_pm_misc(struct radeon_device *rdev)
 161 {
 162         int req_ps_idx = rdev->pm.requested_power_state_index;
 163         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 164         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 165         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 166
 167         if (voltage->type == VOLTAGE_SW) {
 168                 /* 0xff01 is a flag rather then an actual voltage */
 169                 if (voltage->voltage == 0xff01)
 170                         return;
 171                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 172                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 173                         rdev->pm.current_vddc = voltage->voltage;
 174                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 175                 }
 176                 /* 0xff01 is a flag rather then an actual voltage */
 177                 if (voltage->vddci == 0xff01)
 178                         return;
 179                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 180                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 181                         rdev->pm.current_vddci = voltage->vddci;
 182                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 183                 }
 184         }
 185 }
 186
 187 void evergreen_pm_prepare(struct radeon_device *rdev)
 188 {
 189         struct drm_device *ddev = rdev->ddev;
 190         struct drm_crtc *crtc;
 191         struct radeon_crtc *radeon_crtc;
 192         u32 tmp;
 193
 194         /* disable any active CRTCs */
 195         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 196                 radeon_crtc = to_radeon_crtc(crtc);
 197                 if (radeon_crtc->enabled) {
 198                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 199                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 200                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 201                 }
 202         }
 203 }
 204
 205 void evergreen_pm_finish(struct radeon_device *rdev)
 206 {
 207         struct drm_device *ddev = rdev->ddev;
 208         struct drm_crtc *crtc;
 209         struct radeon_crtc *radeon_crtc;
 210         u32 tmp;
 211
 212         /* enable any active CRTCs */
 213         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 214                 radeon_crtc = to_radeon_crtc(crtc);
 215                 if (radeon_crtc->enabled) {
 216                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 217                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 218                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 219                 }
 220         }
 221 }
 222
 223 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 224 {
 225         bool connected = false;
 226
 227         switch (hpd) {
 228         case RADEON_HPD_1:
 229                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 230                         connected = true;
 231                 break;
 232         case RADEON_HPD_2:
 233                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 234                         connected = true;
 235                 break;
 236         case RADEON_HPD_3:
 237                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 238                         connected = true;
 239                 break;
 240         case RADEON_HPD_4:
 241                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 242                         connected = true;
 243                 break;
 244         case RADEON_HPD_5:
 245                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 246                         connected = true;
 247                 break;
 248         case RADEON_HPD_6:
 249                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 250                         connected = true;
 251                         break;
 252         default:
 253                 break;
 254         }
 255
 256         return connected;
 257 }
 258
 259 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 260                                 enum radeon_hpd_id hpd)
 261 {
 262         u32 tmp;
 263         bool connected = evergreen_hpd_sense(rdev, hpd);
 264
 265         switch (hpd) {
 266         case RADEON_HPD_1:
 267                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 268                 if (connected)
 269                         tmp &= ~DC_HPDx_INT_POLARITY;
 270                 else
 271                         tmp |= DC_HPDx_INT_POLARITY;
 272                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 273                 break;
 274         case RADEON_HPD_2:
 275                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 276                 if (connected)
 277                         tmp &= ~DC_HPDx_INT_POLARITY;
 278                 else
 279                         tmp |= DC_HPDx_INT_POLARITY;
 280                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 281                 break;
 282         case RADEON_HPD_3:
 283                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 284                 if (connected)
 285                         tmp &= ~DC_HPDx_INT_POLARITY;
 286                 else
 287                         tmp |= DC_HPDx_INT_POLARITY;
 288                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 289                 break;
 290         case RADEON_HPD_4:
 291                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 292                 if (connected)
 293                         tmp &= ~DC_HPDx_INT_POLARITY;
 294                 else
 295                         tmp |= DC_HPDx_INT_POLARITY;
 296                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 297                 break;
 298         case RADEON_HPD_5:
 299                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 300                 if (connected)
 301                         tmp &= ~DC_HPDx_INT_POLARITY;
 302                 else
 303                         tmp |= DC_HPDx_INT_POLARITY;
 304                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 305                         break;
 306         case RADEON_HPD_6:
 307                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 308                 if (connected)
 309                         tmp &= ~DC_HPDx_INT_POLARITY;
 310                 else
 311                         tmp |= DC_HPDx_INT_POLARITY;
 312                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 313                 break;
 314         default:
 315                 break;
 316         }
 317 }
 318
 319 void evergreen_hpd_init(struct radeon_device *rdev)
 320 {
 321         struct drm_device *dev = rdev->ddev;
 322         struct drm_connector *connector;
 323         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 324                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 325
 326         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 327                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 328                 switch (radeon_connector->hpd.hpd) {
 329                 case RADEON_HPD_1:
 330                         WREG32(DC_HPD1_CONTROL, tmp);
 331                         rdev->irq.hpd[0] = true;
 332                         break;
 333                 case RADEON_HPD_2:
 334                         WREG32(DC_HPD2_CONTROL, tmp);
 335                         rdev->irq.hpd[1] = true;
 336                         break;
 337                 case RADEON_HPD_3:
 338                         WREG32(DC_HPD3_CONTROL, tmp);
 339                         rdev->irq.hpd[2] = true;
 340                         break;
 341                 case RADEON_HPD_4:
 342                         WREG32(DC_HPD4_CONTROL, tmp);
 343                         rdev->irq.hpd[3] = true;
 344                         break;
 345                 case RADEON_HPD_5:
 346                         WREG32(DC_HPD5_CONTROL, tmp);
 347                         rdev->irq.hpd[4] = true;
 348                         break;
 349                 case RADEON_HPD_6:
 350                         WREG32(DC_HPD6_CONTROL, tmp);
 351                         rdev->irq.hpd[5] = true;
 352                         break;
 353                 default:
 354                         break;
 355                 }
 356         }
 357         if (rdev->irq.installed)
 358                 evergreen_irq_set(rdev);
 359 }
 360
 361 void evergreen_hpd_fini(struct radeon_device *rdev)
 362 {
 363         struct drm_device *dev = rdev->ddev;
 364         struct drm_connector *connector;
 365
 366         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 367                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 368                 switch (radeon_connector->hpd.hpd) {
 369                 case RADEON_HPD_1:
 370                         WREG32(DC_HPD1_CONTROL, 0);
 371                         rdev->irq.hpd[0] = false;
 372                         break;
 373                 case RADEON_HPD_2:
 374                         WREG32(DC_HPD2_CONTROL, 0);
 375                         rdev->irq.hpd[1] = false;
 376                         break;
 377                 case RADEON_HPD_3:
 378                         WREG32(DC_HPD3_CONTROL, 0);
 379                         rdev->irq.hpd[2] = false;
 380                         break;
 381                 case RADEON_HPD_4:
 382                         WREG32(DC_HPD4_CONTROL, 0);
 383                         rdev->irq.hpd[3] = false;
 384                         break;
 385                 case RADEON_HPD_5:
 386                         WREG32(DC_HPD5_CONTROL, 0);
 387                         rdev->irq.hpd[4] = false;
 388                         break;
 389                 case RADEON_HPD_6:
 390                         WREG32(DC_HPD6_CONTROL, 0);
 391                         rdev->irq.hpd[5] = false;
 392                         break;
 393                 default:
 394                         break;
 395                 }
 396         }
 397 }
 398
 399 /* watermark setup */
 400
 401 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 402                                         struct radeon_crtc *radeon_crtc,
 403                                         struct drm_display_mode *mode,
 404                                         struct drm_display_mode *other_mode)
 405 {
 406         u32 tmp;
 407         /*
 408          * Line Buffer Setup
 409          * There are 3 line buffers, each one shared by 2 display controllers.
 410          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 411          * the display controllers.  The paritioning is done via one of four
 412          * preset allocations specified in bits 2:0:
 413          * first display controller
 414          *  0 - first half of lb (3840 * 2)
 415          *  1 - first 3/4 of lb (5760 * 2)
 416          *  2 - whole lb (7680 * 2), other crtc must be disabled
 417          *  3 - first 1/4 of lb (1920 * 2)
 418          * second display controller
 419          *  4 - second half of lb (3840 * 2)
 420          *  5 - second 3/4 of lb (5760 * 2)
 421          *  6 - whole lb (7680 * 2), other crtc must be disabled
 422          *  7 - last 1/4 of lb (1920 * 2)
 423          */
 424         /* this can get tricky if we have two large displays on a paired group
 425          * of crtcs.  Ideally for multiple large displays we'd assign them to
 426          * non-linked crtcs for maximum line buffer allocation.
 427          */
 428         if (radeon_crtc->base.enabled && mode) {
 429                 if (other_mode)
 430                         tmp = 0; /* 1/2 */
 431                 else
 432                         tmp = 2; /* whole */
 433         } else
 434                 tmp = 0;
 435
 436         /* second controller of the pair uses second half of the lb */
 437         if (radeon_crtc->crtc_id % 2)
 438                 tmp += 4;
 439         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 440
 441         if (radeon_crtc->base.enabled && mode) {
 442                 switch (tmp) {
 443                 case 0:
 444                 case 4:
 445                 default:
 446                         if (ASIC_IS_DCE5(rdev))
 447                                 return 4096 * 2;
 448                         else
 449                                 return 3840 * 2;
 450                 case 1:
 451                 case 5:
 452                         if (ASIC_IS_DCE5(rdev))
 453                                 return 6144 * 2;
 454                         else
 455                                 return 5760 * 2;
 456                 case 2:
 457                 case 6:
 458                         if (ASIC_IS_DCE5(rdev))
 459                                 return 8192 * 2;
 460                         else
 461                                 return 7680 * 2;
 462                 case 3:
 463                 case 7:
 464                         if (ASIC_IS_DCE5(rdev))
 465                                 return 2048 * 2;
 466                         else
 467                                 return 1920 * 2;
 468                 }
 469         }
 470
 471         /* controller not enabled, so no lb used */
 472         return 0;
 473 }
 474
 475 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 476 {
 477         u32 tmp = RREG32(MC_SHARED_CHMAP);
 478
 479         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 480         case 0:
 481         default:
 482                 return 1;
 483         case 1:
 484                 return 2;
 485         case 2:
 486                 return 4;
 487         case 3:
 488                 return 8;
 489         }
 490 }
 491
 492 struct evergreen_wm_params {
 493         u32 dram_channels; /* number of dram channels */
 494         u32 yclk;          /* bandwidth per dram data pin in kHz */
 495         u32 sclk;          /* engine clock in kHz */
 496         u32 disp_clk;      /* display clock in kHz */
 497         u32 src_width;     /* viewport width */
 498         u32 active_time;   /* active display time in ns */
 499         u32 blank_time;    /* blank time in ns */
 500         bool interlaced;    /* mode is interlaced */
 501         fixed20_12 vsc;    /* vertical scale ratio */
 502         u32 num_heads;     /* number of active crtcs */
 503         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 504         u32 lb_size;       /* line buffer allocated to pipe */
 505         u32 vtaps;         /* vertical scaler taps */
 506 };
 507
 508 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 509 {
 510         /* Calculate DRAM Bandwidth and the part allocated to display. */
 511         fixed20_12 dram_efficiency; /* 0.7 */
 512         fixed20_12 yclk, dram_channels, bandwidth;
 513         fixed20_12 a;
 514
 515         a.full = dfixed_const(1000);
 516         yclk.full = dfixed_const(wm->yclk);
 517         yclk.full = dfixed_div(yclk, a);
 518         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 519         a.full = dfixed_const(10);
 520         dram_efficiency.full = dfixed_const(7);
 521         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 522         bandwidth.full = dfixed_mul(dram_channels, yclk);
 523         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 524
 525         return dfixed_trunc(bandwidth);
 526 }
 527
 528 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 529 {
 530         /* Calculate DRAM Bandwidth and the part allocated to display. */
 531         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 532         fixed20_12 yclk, dram_channels, bandwidth;
 533         fixed20_12 a;
 534
 535         a.full = dfixed_const(1000);
 536         yclk.full = dfixed_const(wm->yclk);
 537         yclk.full = dfixed_div(yclk, a);
 538         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 539         a.full = dfixed_const(10);
 540         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 541         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 542         bandwidth.full = dfixed_mul(dram_channels, yclk);
 543         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 544
 545         return dfixed_trunc(bandwidth);
 546 }
 547
 548 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 549 {
 550         /* Calculate the display Data return Bandwidth */
 551         fixed20_12 return_efficiency; /* 0.8 */
 552         fixed20_12 sclk, bandwidth;
 553         fixed20_12 a;
 554
 555         a.full = dfixed_const(1000);
 556         sclk.full = dfixed_const(wm->sclk);
 557         sclk.full = dfixed_div(sclk, a);
 558         a.full = dfixed_const(10);
 559         return_efficiency.full = dfixed_const(8);
 560         return_efficiency.full = dfixed_div(return_efficiency, a);
 561         a.full = dfixed_const(32);
 562         bandwidth.full = dfixed_mul(a, sclk);
 563         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 564
 565         return dfixed_trunc(bandwidth);
 566 }
 567
 568 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 569 {
 570         /* Calculate the DMIF Request Bandwidth */
 571         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 572         fixed20_12 disp_clk, bandwidth;
 573         fixed20_12 a;
 574
 575         a.full = dfixed_const(1000);
 576         disp_clk.full = dfixed_const(wm->disp_clk);
 577         disp_clk.full = dfixed_div(disp_clk, a);
 578         a.full = dfixed_const(10);
 579         disp_clk_request_efficiency.full = dfixed_const(8);
 580         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 581         a.full = dfixed_const(32);
 582         bandwidth.full = dfixed_mul(a, disp_clk);
 583         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 584
 585         return dfixed_trunc(bandwidth);
 586 }
 587
 588 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 589 {
 590         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 591         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 592         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 593         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 594
 595         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 596 }
 597
 598 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 599 {
 600         /* Calculate the display mode Average Bandwidth
 601          * DisplayMode should contain the source and destination dimensions,
 602          * timing, etc.
 603          */
 604         fixed20_12 bpp;
 605         fixed20_12 line_time;
 606         fixed20_12 src_width;
 607         fixed20_12 bandwidth;
 608         fixed20_12 a;
 609
 610         a.full = dfixed_const(1000);
 611         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 612         line_time.full = dfixed_div(line_time, a);
 613         bpp.full = dfixed_const(wm->bytes_per_pixel);
 614         src_width.full = dfixed_const(wm->src_width);
 615         bandwidth.full = dfixed_mul(src_width, bpp);
 616         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 617         bandwidth.full = dfixed_div(bandwidth, line_time);
 618
 619         return dfixed_trunc(bandwidth);
 620 }
 621
 622 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 623 {
 624         /* First calcualte the latency in ns */
 625         u32 mc_latency = 2000; /* 2000 ns. */
 626         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 627         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 628         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 629         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 630         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 631                 (wm->num_heads * cursor_line_pair_return_time);
 632         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 633         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 634         fixed20_12 a, b, c;
 635
 636         if (wm->num_heads == 0)
 637                 return 0;
 638
 639         a.full = dfixed_const(2);
 640         b.full = dfixed_const(1);
 641         if ((wm->vsc.full > a.full) ||
 642             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 643             (wm->vtaps >= 5) ||
 644             ((wm->vsc.full >= a.full) && wm->interlaced))
 645                 max_src_lines_per_dst_line = 4;
 646         else
 647                 max_src_lines_per_dst_line = 2;
 648
 649         a.full = dfixed_const(available_bandwidth);
 650         b.full = dfixed_const(wm->num_heads);
 651         a.full = dfixed_div(a, b);
 652
 653         b.full = dfixed_const(1000);
 654         c.full = dfixed_const(wm->disp_clk);
 655         b.full = dfixed_div(c, b);
 656         c.full = dfixed_const(wm->bytes_per_pixel);
 657         b.full = dfixed_mul(b, c);
 658
 659         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 660
 661         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 662         b.full = dfixed_const(1000);
 663         c.full = dfixed_const(lb_fill_bw);
 664         b.full = dfixed_div(c, b);
 665         a.full = dfixed_div(a, b);
 666         line_fill_time = dfixed_trunc(a);
 667
 668         if (line_fill_time < wm->active_time)
 669                 return latency;
 670         else
 671                 return latency + (line_fill_time - wm->active_time);
 672
 673 }
 674
 675 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 676 {
 677         if (evergreen_average_bandwidth(wm) <=
 678             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 679                 return true;
 680         else
 681                 return false;
 682 };
 683
 684 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 685 {
 686         if (evergreen_average_bandwidth(wm) <=
 687             (evergreen_available_bandwidth(wm) / wm->num_heads))
 688                 return true;
 689         else
 690                 return false;
 691 };
 692
 693 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 694 {
 695         u32 lb_partitions = wm->lb_size / wm->src_width;
 696         u32 line_time = wm->active_time + wm->blank_time;
 697         u32 latency_tolerant_lines;
 698         u32 latency_hiding;
 699         fixed20_12 a;
 700
 701         a.full = dfixed_const(1);
 702         if (wm->vsc.full > a.full)
 703                 latency_tolerant_lines = 1;
 704         else {
 705                 if (lb_partitions <= (wm->vtaps + 1))
 706                         latency_tolerant_lines = 1;
 707                 else
 708                         latency_tolerant_lines = 2;
 709         }
 710
 711         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 712
 713         if (evergreen_latency_watermark(wm) <= latency_hiding)
 714                 return true;
 715         else
 716                 return false;
 717 }
 718
 719 static void evergreen_program_watermarks(struct radeon_device *rdev,
 720                                          struct radeon_crtc *radeon_crtc,
 721                                          u32 lb_size, u32 num_heads)
 722 {
 723         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 724         struct evergreen_wm_params wm;
 725         u32 pixel_period;
 726         u32 line_time = 0;
 727         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 728         u32 priority_a_mark = 0, priority_b_mark = 0;
 729         u32 priority_a_cnt = PRIORITY_OFF;
 730         u32 priority_b_cnt = PRIORITY_OFF;
 731         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 732         u32 tmp, arb_control3;
 733         fixed20_12 a, b, c;
 734
 735         if (radeon_crtc->base.enabled && num_heads && mode) {
 736                 pixel_period = 1000000 / (u32)mode->clock;
 737                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 738                 priority_a_cnt = 0;
 739                 priority_b_cnt = 0;
 740
 741                 wm.yclk = rdev->pm.current_mclk * 10;
 742                 wm.sclk = rdev->pm.current_sclk * 10;
 743                 wm.disp_clk = mode->clock;
 744                 wm.src_width = mode->crtc_hdisplay;
 745                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 746                 wm.blank_time = line_time - wm.active_time;
 747                 wm.interlaced = false;
 748                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 749                         wm.interlaced = true;
 750                 wm.vsc = radeon_crtc->vsc;
 751                 wm.vtaps = 1;
 752                 if (radeon_crtc->rmx_type != RMX_OFF)
 753                         wm.vtaps = 2;
 754                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 755                 wm.lb_size = lb_size;
 756                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 757                 wm.num_heads = num_heads;
 758
 759                 /* set for high clocks */
 760                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 761                 /* set for low clocks */
 762                 /* wm.yclk = low clk; wm.sclk = low clk */
 763                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 764
 765                 /* possibly force display priority to high */
 766                 /* should really do this at mode validation time... */
 767                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 768                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 769                     !evergreen_check_latency_hiding(&wm) ||
 770                     (rdev->disp_priority == 2)) {
 771                         DRM_DEBUG_KMS("force priority to high\n");
 772                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 773                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 774                 }
 775
 776                 a.full = dfixed_const(1000);
 777                 b.full = dfixed_const(mode->clock);
 778                 b.full = dfixed_div(b, a);
 779                 c.full = dfixed_const(latency_watermark_a);
 780                 c.full = dfixed_mul(c, b);
 781                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 782                 c.full = dfixed_div(c, a);
 783                 a.full = dfixed_const(16);
 784                 c.full = dfixed_div(c, a);
 785                 priority_a_mark = dfixed_trunc(c);
 786                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 787
 788                 a.full = dfixed_const(1000);
 789                 b.full = dfixed_const(mode->clock);
 790                 b.full = dfixed_div(b, a);
 791                 c.full = dfixed_const(latency_watermark_b);
 792                 c.full = dfixed_mul(c, b);
 793                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 794                 c.full = dfixed_div(c, a);
 795                 a.full = dfixed_const(16);
 796                 c.full = dfixed_div(c, a);
 797                 priority_b_mark = dfixed_trunc(c);
 798                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 799         }
 800
 801         /* select wm A */
 802         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 803         tmp = arb_control3;
 804         tmp &= ~LATENCY_WATERMARK_MASK(3);
 805         tmp |= LATENCY_WATERMARK_MASK(1);
 806         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 807         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 808                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 809                 LATENCY_HIGH_WATERMARK(line_time)));
 810         /* select wm B */
 811         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 812         tmp &= ~LATENCY_WATERMARK_MASK(3);
 813         tmp |= LATENCY_WATERMARK_MASK(2);
 814         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 815         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 816                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 817                 LATENCY_HIGH_WATERMARK(line_time)));
 818         /* restore original selection */
 819         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 820
 821         /* write the priority marks */
 822         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 823         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 824
 825 }
 826
 827 void evergreen_bandwidth_update(struct radeon_device *rdev)
 828 {
 829         struct drm_display_mode *mode0 = NULL;
 830         struct drm_display_mode *mode1 = NULL;
 831         u32 num_heads = 0, lb_size;
 832         int i;
 833
 834         radeon_update_display_priority(rdev);
 835
 836         for (i = 0; i < rdev->num_crtc; i++) {
 837                 if (rdev->mode_info.crtcs[i]->base.enabled)
 838                         num_heads++;
 839         }
 840         for (i = 0; i < rdev->num_crtc; i += 2) {
 841                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 842                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 843                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 844                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 845                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 846                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 847         }
 848 }
 849
 850 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 851 {
 852         unsigned i;
 853         u32 tmp;
 854
 855         for (i = 0; i < rdev->usec_timeout; i++) {
 856                 /* read MC_STATUS */
 857                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 858                 if (!tmp)
 859                         return 0;
 860                 udelay(1);
 861         }
 862         return -1;
 863 }
 864
 865 /*
 866  * GART
 867  */
 868 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 869 {
 870         unsigned i;
 871         u32 tmp;
 872
 873         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 874
 875         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 876         for (i = 0; i < rdev->usec_timeout; i++) {
 877                 /* read MC_STATUS */
 878                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 879                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 880                 if (tmp == 2) {
 881                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 882                         return;
 883                 }
 884                 if (tmp) {
 885                         return;
 886                 }
 887                 udelay(1);
 888         }
 889 }
 890
 891 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 892 {
 893         u32 tmp;
 894         int r;
 895
 896         if (rdev->gart.table.vram.robj == NULL) {
 897                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 898                 return -EINVAL;
 899         }
 900         r = radeon_gart_table_vram_pin(rdev);
 901         if (r)
 902                 return r;
 903         radeon_gart_restore(rdev);
 904         /* Setup L2 cache */
 905         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 906                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 907                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 908         WREG32(VM_L2_CNTL2, 0);
 909         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 910         /* Setup TLB control */
 911         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 912                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 913                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 914                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 915         if (rdev->flags & RADEON_IS_IGP) {
 916                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
 917                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
 918                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
 919         } else {
 920                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 921                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 922                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 923         }
 924         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 925         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 926         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 927         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 928         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 929         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 930         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 931         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 932                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 933         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 934                         (u32)(rdev->dummy_page.addr >> 12));
 935         WREG32(VM_CONTEXT1_CNTL, 0);
 936
 937         evergreen_pcie_gart_tlb_flush(rdev);
 938         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 939                  (unsigned)(rdev->mc.gtt_size >> 20),
 940                  (unsigned long long)rdev->gart.table_addr);
 941         rdev->gart.ready = true;
 942         return 0;
 943 }
 944
 945 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 946 {
 947         u32 tmp;
 948         int r;
 949
 950         /* Disable all tables */
 951         WREG32(VM_CONTEXT0_CNTL, 0);
 952         WREG32(VM_CONTEXT1_CNTL, 0);
 953
 954         /* Setup L2 cache */
 955         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 956                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 957         WREG32(VM_L2_CNTL2, 0);
 958         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 959         /* Setup TLB control */
 960         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 961         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 962         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 963         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 964         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 965         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 966         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 967         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 968         if (rdev->gart.table.vram.robj) {
 969                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 970                 if (likely(r == 0)) {
 971                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 972                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 973                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 974                 }
 975         }
 976 }
 977
 978 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 979 {
 980         evergreen_pcie_gart_disable(rdev);
 981         radeon_gart_table_vram_free(rdev);
 982         radeon_gart_fini(rdev);
 983 }
 984
 985
 986 void evergreen_agp_enable(struct radeon_device *rdev)
 987 {
 988         u32 tmp;
 989
 990         /* Setup L2 cache */
 991         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 992                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 993                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 994         WREG32(VM_L2_CNTL2, 0);
 995         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 996         /* Setup TLB control */
 997         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 998                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 999                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1000                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1001         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1002         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1003         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1004         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1005         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1006         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1007         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1008         WREG32(VM_CONTEXT0_CNTL, 0);
1009         WREG32(VM_CONTEXT1_CNTL, 0);
1010 }
1011
1012 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1013 {
1014         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1015         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1016         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1017         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1018         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1019         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1020         if (rdev->num_crtc >= 4) {
1021                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1022                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1023                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1024                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1025         }
1026         if (rdev->num_crtc >= 6) {
1027                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1028                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1029                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1030                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1031         }
1032
1033         /* Stop all video */
1034         WREG32(VGA_RENDER_CONTROL, 0);
1035         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1036         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1037         if (rdev->num_crtc >= 4) {
1038                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1039                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1040         }
1041         if (rdev->num_crtc >= 6) {
1042                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1043                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1044         }
1045         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1046         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1047         if (rdev->num_crtc >= 4) {
1048                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1049                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1050         }
1051         if (rdev->num_crtc >= 6) {
1052                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1053                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1054         }
1055         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1056         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1057         if (rdev->num_crtc >= 4) {
1058                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1059                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1060         }
1061         if (rdev->num_crtc >= 6) {
1062                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1063                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1064         }
1065
1066         WREG32(D1VGA_CONTROL, 0);
1067         WREG32(D2VGA_CONTROL, 0);
1068         if (rdev->num_crtc >= 4) {
1069                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1070                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1071         }
1072         if (rdev->num_crtc >= 6) {
1073                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1074                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1075         }
1076 }
1077
1078 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1079 {
1080         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1081                upper_32_bits(rdev->mc.vram_start));
1082         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1083                upper_32_bits(rdev->mc.vram_start));
1084         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1085                (u32)rdev->mc.vram_start);
1086         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1087                (u32)rdev->mc.vram_start);
1088
1089         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1090                upper_32_bits(rdev->mc.vram_start));
1091         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1092                upper_32_bits(rdev->mc.vram_start));
1093         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1094                (u32)rdev->mc.vram_start);
1095         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1096                (u32)rdev->mc.vram_start);
1097
1098         if (rdev->num_crtc >= 4) {
1099                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1100                        upper_32_bits(rdev->mc.vram_start));
1101                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1102                        upper_32_bits(rdev->mc.vram_start));
1103                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1104                        (u32)rdev->mc.vram_start);
1105                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1106                        (u32)rdev->mc.vram_start);
1107
1108                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1109                        upper_32_bits(rdev->mc.vram_start));
1110                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1111                        upper_32_bits(rdev->mc.vram_start));
1112                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1113                        (u32)rdev->mc.vram_start);
1114                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1115                        (u32)rdev->mc.vram_start);
1116         }
1117         if (rdev->num_crtc >= 6) {
1118                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1119                        upper_32_bits(rdev->mc.vram_start));
1120                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1121                        upper_32_bits(rdev->mc.vram_start));
1122                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1123                        (u32)rdev->mc.vram_start);
1124                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1125                        (u32)rdev->mc.vram_start);
1126
1127                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1128                        upper_32_bits(rdev->mc.vram_start));
1129                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1130                        upper_32_bits(rdev->mc.vram_start));
1131                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1132                        (u32)rdev->mc.vram_start);
1133                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1134                        (u32)rdev->mc.vram_start);
1135         }
1136
1137         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1138         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1139         /* Unlock host access */
1140         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1141         mdelay(1);
1142         /* Restore video state */
1143         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1144         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1145         if (rdev->num_crtc >= 4) {
1146                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1147                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1148         }
1149         if (rdev->num_crtc >= 6) {
1150                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1151                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1152         }
1153         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1154         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1155         if (rdev->num_crtc >= 4) {
1156                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1157                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1158         }
1159         if (rdev->num_crtc >= 6) {
1160                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1161                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1162         }
1163         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1164         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1165         if (rdev->num_crtc >= 4) {
1166                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1167                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1168         }
1169         if (rdev->num_crtc >= 6) {
1170                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1171                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1172         }
1173         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1174         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1175         if (rdev->num_crtc >= 4) {
1176                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1177                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1178         }
1179         if (rdev->num_crtc >= 6) {
1180                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1181                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1182         }
1183         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1184 }
1185
1186 void evergreen_mc_program(struct radeon_device *rdev)
1187 {
1188         struct evergreen_mc_save save;
1189         u32 tmp;
1190         int i, j;
1191
1192         /* Initialize HDP */
1193         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1194                 WREG32((0x2c14 + j), 0x00000000);
1195                 WREG32((0x2c18 + j), 0x00000000);
1196                 WREG32((0x2c1c + j), 0x00000000);
1197                 WREG32((0x2c20 + j), 0x00000000);
1198                 WREG32((0x2c24 + j), 0x00000000);
1199         }
1200         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1201
1202         evergreen_mc_stop(rdev, &save);
1203         if (evergreen_mc_wait_for_idle(rdev)) {
1204                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1205         }
1206         /* Lockout access through VGA aperture*/
1207         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1208         /* Update configuration */
1209         if (rdev->flags & RADEON_IS_AGP) {
1210                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1211                         /* VRAM before AGP */
1212                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1213                                 rdev->mc.vram_start >> 12);
1214                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1215                                 rdev->mc.gtt_end >> 12);
1216                 } else {
1217                         /* VRAM after AGP */
1218                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1219                                 rdev->mc.gtt_start >> 12);
1220                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1221                                 rdev->mc.vram_end >> 12);
1222                 }
1223         } else {
1224                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1225                         rdev->mc.vram_start >> 12);
1226                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1227                         rdev->mc.vram_end >> 12);
1228         }
1229         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1230         if (rdev->flags & RADEON_IS_IGP) {
1231                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1232                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1233                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1234                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1235         }
1236         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1237         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1238         WREG32(MC_VM_FB_LOCATION, tmp);
1239         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1240         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1241         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1242         if (rdev->flags & RADEON_IS_AGP) {
1243                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1244                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1245                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1246         } else {
1247                 WREG32(MC_VM_AGP_BASE, 0);
1248                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1249                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1250         }
1251         if (evergreen_mc_wait_for_idle(rdev)) {
1252                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1253         }
1254         evergreen_mc_resume(rdev, &save);
1255         /* we need to own VRAM, so turn off the VGA renderer here
1256          * to stop it overwriting our objects */
1257         rv515_vga_render_disable(rdev);
1258 }
1259
1260 /*
1261  * CP.
1262  */
1263 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1264 {
1265         /* set to DX10/11 mode */
1266         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1267         radeon_ring_write(rdev, 1);
1268         /* FIXME: implement */
1269         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1270         radeon_ring_write(rdev,
1271 #ifdef __BIG_ENDIAN
1272                           (2 << 0) |
1273 #endif
1274                           (ib->gpu_addr & 0xFFFFFFFC));
1275         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1276         radeon_ring_write(rdev, ib->length_dw);
1277 }
1278
1279
1280 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1281 {
1282         const __be32 *fw_data;
1283         int i;
1284
1285         if (!rdev->me_fw || !rdev->pfp_fw)
1286                 return -EINVAL;
1287
1288         r700_cp_stop(rdev);
1289         WREG32(CP_RB_CNTL,
1290 #ifdef __BIG_ENDIAN
1291                BUF_SWAP_32BIT |
1292 #endif
1293                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1294
1295         fw_data = (const __be32 *)rdev->pfp_fw->data;
1296         WREG32(CP_PFP_UCODE_ADDR, 0);
1297         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1298                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1299         WREG32(CP_PFP_UCODE_ADDR, 0);
1300
1301         fw_data = (const __be32 *)rdev->me_fw->data;
1302         WREG32(CP_ME_RAM_WADDR, 0);
1303         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1304                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1305
1306         WREG32(CP_PFP_UCODE_ADDR, 0);
1307         WREG32(CP_ME_RAM_WADDR, 0);
1308         WREG32(CP_ME_RAM_RADDR, 0);
1309         return 0;
1310 }
1311
1312 static int evergreen_cp_start(struct radeon_device *rdev)
1313 {
1314         int r, i;
1315         uint32_t cp_me;
1316
1317         r = radeon_ring_lock(rdev, 7);
1318         if (r) {
1319                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1320                 return r;
1321         }
1322         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1323         radeon_ring_write(rdev, 0x1);
1324         radeon_ring_write(rdev, 0x0);
1325         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1326         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1327         radeon_ring_write(rdev, 0);
1328         radeon_ring_write(rdev, 0);
1329         radeon_ring_unlock_commit(rdev);
1330
1331         cp_me = 0xff;
1332         WREG32(CP_ME_CNTL, cp_me);
1333
1334         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1335         if (r) {
1336                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1337                 return r;
1338         }
1339
1340         /* setup clear context state */
1341         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1342         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1343
1344         for (i = 0; i < evergreen_default_size; i++)
1345                 radeon_ring_write(rdev, evergreen_default_state[i]);
1346
1347         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1348         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1349
1350         /* set clear context state */
1351         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1352         radeon_ring_write(rdev, 0);
1353
1354         /* SQ_VTX_BASE_VTX_LOC */
1355         radeon_ring_write(rdev, 0xc0026f00);
1356         radeon_ring_write(rdev, 0x00000000);
1357         radeon_ring_write(rdev, 0x00000000);
1358         radeon_ring_write(rdev, 0x00000000);
1359
1360         /* Clear consts */
1361         radeon_ring_write(rdev, 0xc0036f00);
1362         radeon_ring_write(rdev, 0x00000bc4);
1363         radeon_ring_write(rdev, 0xffffffff);
1364         radeon_ring_write(rdev, 0xffffffff);
1365         radeon_ring_write(rdev, 0xffffffff);
1366
1367         radeon_ring_write(rdev, 0xc0026900);
1368         radeon_ring_write(rdev, 0x00000316);
1369         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1370         radeon_ring_write(rdev, 0x00000010); /*  */
1371
1372         radeon_ring_unlock_commit(rdev);
1373
1374         return 0;
1375 }
1376
1377 int evergreen_cp_resume(struct radeon_device *rdev)
1378 {
1379         u32 tmp;
1380         u32 rb_bufsz;
1381         int r;
1382
1383         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1384         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1385                                  SOFT_RESET_PA |
1386                                  SOFT_RESET_SH |
1387                                  SOFT_RESET_VGT |
1388                                  SOFT_RESET_SPI |
1389                                  SOFT_RESET_SX));
1390         RREG32(GRBM_SOFT_RESET);
1391         mdelay(15);
1392         WREG32(GRBM_SOFT_RESET, 0);
1393         RREG32(GRBM_SOFT_RESET);
1394
1395         /* Set ring buffer size */
1396         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1397         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1398 #ifdef __BIG_ENDIAN
1399         tmp |= BUF_SWAP_32BIT;
1400 #endif
1401         WREG32(CP_RB_CNTL, tmp);
1402         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1403
1404         /* Set the write pointer delay */
1405         WREG32(CP_RB_WPTR_DELAY, 0);
1406
1407         /* Initialize the ring buffer's read and write pointers */
1408         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1409         WREG32(CP_RB_RPTR_WR, 0);
1410         rdev->cp.wptr = 0;
1411         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1412
1413         /* set the wb address wether it's enabled or not */
1414         WREG32(CP_RB_RPTR_ADDR,
1415                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1416         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1417         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1418
1419         if (rdev->wb.enabled)
1420                 WREG32(SCRATCH_UMSK, 0xff);
1421         else {
1422                 tmp |= RB_NO_UPDATE;
1423                 WREG32(SCRATCH_UMSK, 0);
1424         }
1425
1426         mdelay(1);
1427         WREG32(CP_RB_CNTL, tmp);
1428
1429         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1430         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1431
1432         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1433
1434         evergreen_cp_start(rdev);
1435         rdev->cp.ready = true;
1436         r = radeon_ring_test(rdev);
1437         if (r) {
1438                 rdev->cp.ready = false;
1439                 return r;
1440         }
1441         return 0;
1442 }
1443
1444 /*
1445  * Core functions
1446  */
1447 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1448                                                   u32 num_tile_pipes,
1449                                                   u32 num_backends,
1450                                                   u32 backend_disable_mask)
1451 {
1452         u32 backend_map = 0;
1453         u32 enabled_backends_mask = 0;
1454         u32 enabled_backends_count = 0;
1455         u32 cur_pipe;
1456         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1457         u32 cur_backend = 0;
1458         u32 i;
1459         bool force_no_swizzle;
1460
1461         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1462                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1463         if (num_tile_pipes < 1)
1464                 num_tile_pipes = 1;
1465         if (num_backends > EVERGREEN_MAX_BACKENDS)
1466                 num_backends = EVERGREEN_MAX_BACKENDS;
1467         if (num_backends < 1)
1468                 num_backends = 1;
1469
1470         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1471                 if (((backend_disable_mask >> i) & 1) == 0) {
1472                         enabled_backends_mask |= (1 << i);
1473                         ++enabled_backends_count;
1474                 }
1475                 if (enabled_backends_count == num_backends)
1476                         break;
1477         }
1478
1479         if (enabled_backends_count == 0) {
1480                 enabled_backends_mask = 1;
1481                 enabled_backends_count = 1;
1482         }
1483
1484         if (enabled_backends_count != num_backends)
1485                 num_backends = enabled_backends_count;
1486
1487         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1488         switch (rdev->family) {
1489         case CHIP_CEDAR:
1490         case CHIP_REDWOOD:
1491         case CHIP_PALM:
1492         case CHIP_SUMO:
1493         case CHIP_SUMO2:
1494         case CHIP_TURKS:
1495         case CHIP_CAICOS:
1496                 force_no_swizzle = false;
1497                 break;
1498         case CHIP_CYPRESS:
1499         case CHIP_HEMLOCK:
1500         case CHIP_JUNIPER:
1501         case CHIP_BARTS:
1502         default:
1503                 force_no_swizzle = true;
1504                 break;
1505         }
1506         if (force_no_swizzle) {
1507                 bool last_backend_enabled = false;
1508
1509                 force_no_swizzle = false;
1510                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1511                         if (((enabled_backends_mask >> i) & 1) == 1) {
1512                                 if (last_backend_enabled)
1513                                         force_no_swizzle = true;
1514                                 last_backend_enabled = true;
1515                         } else
1516                                 last_backend_enabled = false;
1517                 }
1518         }
1519
1520         switch (num_tile_pipes) {
1521         case 1:
1522         case 3:
1523         case 5:
1524         case 7:
1525                 DRM_ERROR("odd number of pipes!\n");
1526                 break;
1527         case 2:
1528                 swizzle_pipe[0] = 0;
1529                 swizzle_pipe[1] = 1;
1530                 break;
1531         case 4:
1532                 if (force_no_swizzle) {
1533                         swizzle_pipe[0] = 0;
1534                         swizzle_pipe[1] = 1;
1535                         swizzle_pipe[2] = 2;
1536                         swizzle_pipe[3] = 3;
1537                 } else {
1538                         swizzle_pipe[0] = 0;
1539                         swizzle_pipe[1] = 2;
1540                         swizzle_pipe[2] = 1;
1541                         swizzle_pipe[3] = 3;
1542                 }
1543                 break;
1544         case 6:
1545                 if (force_no_swizzle) {
1546                         swizzle_pipe[0] = 0;
1547                         swizzle_pipe[1] = 1;
1548                         swizzle_pipe[2] = 2;
1549                         swizzle_pipe[3] = 3;
1550                         swizzle_pipe[4] = 4;
1551                         swizzle_pipe[5] = 5;
1552                 } else {
1553                         swizzle_pipe[0] = 0;
1554                         swizzle_pipe[1] = 2;
1555                         swizzle_pipe[2] = 4;
1556                         swizzle_pipe[3] = 1;
1557                         swizzle_pipe[4] = 3;
1558                         swizzle_pipe[5] = 5;
1559                 }
1560                 break;
1561         case 8:
1562                 if (force_no_swizzle) {
1563                         swizzle_pipe[0] = 0;
1564                         swizzle_pipe[1] = 1;
1565                         swizzle_pipe[2] = 2;
1566                         swizzle_pipe[3] = 3;
1567                         swizzle_pipe[4] = 4;
1568                         swizzle_pipe[5] = 5;
1569                         swizzle_pipe[6] = 6;
1570                         swizzle_pipe[7] = 7;
1571                 } else {
1572                         swizzle_pipe[0] = 0;
1573                         swizzle_pipe[1] = 2;
1574                         swizzle_pipe[2] = 4;
1575                         swizzle_pipe[3] = 6;
1576                         swizzle_pipe[4] = 1;
1577                         swizzle_pipe[5] = 3;
1578                         swizzle_pipe[6] = 5;
1579                         swizzle_pipe[7] = 7;
1580                 }
1581                 break;
1582         }
1583
1584         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1585                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1586                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1587
1588                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1589
1590                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1591         }
1592
1593         return backend_map;
1594 }
1595
1596 static void evergreen_gpu_init(struct radeon_device *rdev)
1597 {
1598         u32 cc_rb_backend_disable = 0;
1599         u32 cc_gc_shader_pipe_config;
1600         u32 gb_addr_config = 0;
1601         u32 mc_shared_chmap, mc_arb_ramcfg;
1602         u32 gb_backend_map;
1603         u32 grbm_gfx_index;
1604         u32 sx_debug_1;
1605         u32 smx_dc_ctl0;
1606         u32 sq_config;
1607         u32 sq_lds_resource_mgmt;
1608         u32 sq_gpr_resource_mgmt_1;
1609         u32 sq_gpr_resource_mgmt_2;
1610         u32 sq_gpr_resource_mgmt_3;
1611         u32 sq_thread_resource_mgmt;
1612         u32 sq_thread_resource_mgmt_2;
1613         u32 sq_stack_resource_mgmt_1;
1614         u32 sq_stack_resource_mgmt_2;
1615         u32 sq_stack_resource_mgmt_3;
1616         u32 vgt_cache_invalidation;
1617         u32 hdp_host_path_cntl, tmp;
1618         int i, j, num_shader_engines, ps_thread_count;
1619
1620         switch (rdev->family) {
1621         case CHIP_CYPRESS:
1622         case CHIP_HEMLOCK:
1623                 rdev->config.evergreen.num_ses = 2;
1624                 rdev->config.evergreen.max_pipes = 4;
1625                 rdev->config.evergreen.max_tile_pipes = 8;
1626                 rdev->config.evergreen.max_simds = 10;
1627                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1628                 rdev->config.evergreen.max_gprs = 256;
1629                 rdev->config.evergreen.max_threads = 248;
1630                 rdev->config.evergreen.max_gs_threads = 32;
1631                 rdev->config.evergreen.max_stack_entries = 512;
1632                 rdev->config.evergreen.sx_num_of_sets = 4;
1633                 rdev->config.evergreen.sx_max_export_size = 256;
1634                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1635                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1636                 rdev->config.evergreen.max_hw_contexts = 8;
1637                 rdev->config.evergreen.sq_num_cf_insts = 2;
1638
1639                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1640                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1641                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1642                 break;
1643         case CHIP_JUNIPER:
1644                 rdev->config.evergreen.num_ses = 1;
1645                 rdev->config.evergreen.max_pipes = 4;
1646                 rdev->config.evergreen.max_tile_pipes = 4;
1647                 rdev->config.evergreen.max_simds = 10;
1648                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1649                 rdev->config.evergreen.max_gprs = 256;
1650                 rdev->config.evergreen.max_threads = 248;
1651                 rdev->config.evergreen.max_gs_threads = 32;
1652                 rdev->config.evergreen.max_stack_entries = 512;
1653                 rdev->config.evergreen.sx_num_of_sets = 4;
1654                 rdev->config.evergreen.sx_max_export_size = 256;
1655                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1656                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1657                 rdev->config.evergreen.max_hw_contexts = 8;
1658                 rdev->config.evergreen.sq_num_cf_insts = 2;
1659
1660                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1661                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1662                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1663                 break;
1664         case CHIP_REDWOOD:
1665                 rdev->config.evergreen.num_ses = 1;
1666                 rdev->config.evergreen.max_pipes = 4;
1667                 rdev->config.evergreen.max_tile_pipes = 4;
1668                 rdev->config.evergreen.max_simds = 5;
1669                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1670                 rdev->config.evergreen.max_gprs = 256;
1671                 rdev->config.evergreen.max_threads = 248;
1672                 rdev->config.evergreen.max_gs_threads = 32;
1673                 rdev->config.evergreen.max_stack_entries = 256;
1674                 rdev->config.evergreen.sx_num_of_sets = 4;
1675                 rdev->config.evergreen.sx_max_export_size = 256;
1676                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1677                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1678                 rdev->config.evergreen.max_hw_contexts = 8;
1679                 rdev->config.evergreen.sq_num_cf_insts = 2;
1680
1681                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1682                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1683                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1684                 break;
1685         case CHIP_CEDAR:
1686         default:
1687                 rdev->config.evergreen.num_ses = 1;
1688                 rdev->config.evergreen.max_pipes = 2;
1689                 rdev->config.evergreen.max_tile_pipes = 2;
1690                 rdev->config.evergreen.max_simds = 2;
1691                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1692                 rdev->config.evergreen.max_gprs = 256;
1693                 rdev->config.evergreen.max_threads = 192;
1694                 rdev->config.evergreen.max_gs_threads = 16;
1695                 rdev->config.evergreen.max_stack_entries = 256;
1696                 rdev->config.evergreen.sx_num_of_sets = 4;
1697                 rdev->config.evergreen.sx_max_export_size = 128;
1698                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1699                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1700                 rdev->config.evergreen.max_hw_contexts = 4;
1701                 rdev->config.evergreen.sq_num_cf_insts = 1;
1702
1703                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1704                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1705                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1706                 break;
1707         case CHIP_PALM:
1708                 rdev->config.evergreen.num_ses = 1;
1709                 rdev->config.evergreen.max_pipes = 2;
1710                 rdev->config.evergreen.max_tile_pipes = 2;
1711                 rdev->config.evergreen.max_simds = 2;
1712                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1713                 rdev->config.evergreen.max_gprs = 256;
1714                 rdev->config.evergreen.max_threads = 192;
1715                 rdev->config.evergreen.max_gs_threads = 16;
1716                 rdev->config.evergreen.max_stack_entries = 256;
1717                 rdev->config.evergreen.sx_num_of_sets = 4;
1718                 rdev->config.evergreen.sx_max_export_size = 128;
1719                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1720                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1721                 rdev->config.evergreen.max_hw_contexts = 4;
1722                 rdev->config.evergreen.sq_num_cf_insts = 1;
1723
1724                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1725                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1726                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1727                 break;
1728         case CHIP_SUMO:
1729                 rdev->config.evergreen.num_ses = 1;
1730                 rdev->config.evergreen.max_pipes = 4;
1731                 rdev->config.evergreen.max_tile_pipes = 2;
1732                 if (rdev->pdev->device == 0x9648)
1733                         rdev->config.evergreen.max_simds = 3;
1734                 else if ((rdev->pdev->device == 0x9647) ||
1735                          (rdev->pdev->device == 0x964a))
1736                         rdev->config.evergreen.max_simds = 4;
1737                 else
1738                         rdev->config.evergreen.max_simds = 5;
1739                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1740                 rdev->config.evergreen.max_gprs = 256;
1741                 rdev->config.evergreen.max_threads = 248;
1742                 rdev->config.evergreen.max_gs_threads = 32;
1743                 rdev->config.evergreen.max_stack_entries = 256;
1744                 rdev->config.evergreen.sx_num_of_sets = 4;
1745                 rdev->config.evergreen.sx_max_export_size = 256;
1746                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1747                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1748                 rdev->config.evergreen.max_hw_contexts = 8;
1749                 rdev->config.evergreen.sq_num_cf_insts = 2;
1750
1751                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1752                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1753                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1754                 break;
1755         case CHIP_SUMO2:
1756                 rdev->config.evergreen.num_ses = 1;
1757                 rdev->config.evergreen.max_pipes = 4;
1758                 rdev->config.evergreen.max_tile_pipes = 4;
1759                 rdev->config.evergreen.max_simds = 2;
1760                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1761                 rdev->config.evergreen.max_gprs = 256;
1762                 rdev->config.evergreen.max_threads = 248;
1763                 rdev->config.evergreen.max_gs_threads = 32;
1764                 rdev->config.evergreen.max_stack_entries = 512;
1765                 rdev->config.evergreen.sx_num_of_sets = 4;
1766                 rdev->config.evergreen.sx_max_export_size = 256;
1767                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1768                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1769                 rdev->config.evergreen.max_hw_contexts = 8;
1770                 rdev->config.evergreen.sq_num_cf_insts = 2;
1771
1772                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1773                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1774                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1775                 break;
1776         case CHIP_BARTS:
1777                 rdev->config.evergreen.num_ses = 2;
1778                 rdev->config.evergreen.max_pipes = 4;
1779                 rdev->config.evergreen.max_tile_pipes = 8;
1780                 rdev->config.evergreen.max_simds = 7;
1781                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1782                 rdev->config.evergreen.max_gprs = 256;
1783                 rdev->config.evergreen.max_threads = 248;
1784                 rdev->config.evergreen.max_gs_threads = 32;
1785                 rdev->config.evergreen.max_stack_entries = 512;
1786                 rdev->config.evergreen.sx_num_of_sets = 4;
1787                 rdev->config.evergreen.sx_max_export_size = 256;
1788                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1789                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1790                 rdev->config.evergreen.max_hw_contexts = 8;
1791                 rdev->config.evergreen.sq_num_cf_insts = 2;
1792
1793                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1794                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1795                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1796                 break;
1797         case CHIP_TURKS:
1798                 rdev->config.evergreen.num_ses = 1;
1799                 rdev->config.evergreen.max_pipes = 4;
1800                 rdev->config.evergreen.max_tile_pipes = 4;
1801                 rdev->config.evergreen.max_simds = 6;
1802                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1803                 rdev->config.evergreen.max_gprs = 256;
1804                 rdev->config.evergreen.max_threads = 248;
1805                 rdev->config.evergreen.max_gs_threads = 32;
1806                 rdev->config.evergreen.max_stack_entries = 256;
1807                 rdev->config.evergreen.sx_num_of_sets = 4;
1808                 rdev->config.evergreen.sx_max_export_size = 256;
1809                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1810                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1811                 rdev->config.evergreen.max_hw_contexts = 8;
1812                 rdev->config.evergreen.sq_num_cf_insts = 2;
1813
1814                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1815                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1816                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1817                 break;
1818         case CHIP_CAICOS:
1819                 rdev->config.evergreen.num_ses = 1;
1820                 rdev->config.evergreen.max_pipes = 4;
1821                 rdev->config.evergreen.max_tile_pipes = 2;
1822                 rdev->config.evergreen.max_simds = 2;
1823                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1824                 rdev->config.evergreen.max_gprs = 256;
1825                 rdev->config.evergreen.max_threads = 192;
1826                 rdev->config.evergreen.max_gs_threads = 16;
1827                 rdev->config.evergreen.max_stack_entries = 256;
1828                 rdev->config.evergreen.sx_num_of_sets = 4;
1829                 rdev->config.evergreen.sx_max_export_size = 128;
1830                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1831                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1832                 rdev->config.evergreen.max_hw_contexts = 4;
1833                 rdev->config.evergreen.sq_num_cf_insts = 1;
1834
1835                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1836                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1837                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1838                 break;
1839         }
1840
1841         /* Initialize HDP */
1842         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1843                 WREG32((0x2c14 + j), 0x00000000);
1844                 WREG32((0x2c18 + j), 0x00000000);
1845                 WREG32((0x2c1c + j), 0x00000000);
1846                 WREG32((0x2c20 + j), 0x00000000);
1847                 WREG32((0x2c24 + j), 0x00000000);
1848         }
1849
1850         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1851
1852         evergreen_fix_pci_max_read_req_size(rdev);
1853
1854         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1855
1856         cc_gc_shader_pipe_config |=
1857                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1858                                   & EVERGREEN_MAX_PIPES_MASK);
1859         cc_gc_shader_pipe_config |=
1860                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1861                                & EVERGREEN_MAX_SIMDS_MASK);
1862
1863         cc_rb_backend_disable =
1864                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1865                                 & EVERGREEN_MAX_BACKENDS_MASK);
1866
1867
1868         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1869         if (rdev->flags & RADEON_IS_IGP)
1870                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1871         else
1872                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1873
1874         switch (rdev->config.evergreen.max_tile_pipes) {
1875         case 1:
1876         default:
1877                 gb_addr_config |= NUM_PIPES(0);
1878                 break;
1879         case 2:
1880                 gb_addr_config |= NUM_PIPES(1);
1881                 break;
1882         case 4:
1883                 gb_addr_config |= NUM_PIPES(2);
1884                 break;
1885         case 8:
1886                 gb_addr_config |= NUM_PIPES(3);
1887                 break;
1888         }
1889
1890         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1891         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1892         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1893         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1894         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1895         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1896
1897         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1898                 gb_addr_config |= ROW_SIZE(2);
1899         else
1900                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1901
1902         if (rdev->ddev->pdev->device == 0x689e) {
1903                 u32 efuse_straps_4;
1904                 u32 efuse_straps_3;
1905                 u8 efuse_box_bit_131_124;
1906
1907                 WREG32(RCU_IND_INDEX, 0x204);
1908                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1909                 WREG32(RCU_IND_INDEX, 0x203);
1910                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1911                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1912
1913                 switch(efuse_box_bit_131_124) {
1914                 case 0x00:
1915                         gb_backend_map = 0x76543210;
1916                         break;
1917                 case 0x55:
1918                         gb_backend_map = 0x77553311;
1919                         break;
1920                 case 0x56:
1921                         gb_backend_map = 0x77553300;
1922                         break;
1923                 case 0x59:
1924                         gb_backend_map = 0x77552211;
1925                         break;
1926                 case 0x66:
1927                         gb_backend_map = 0x77443300;
1928                         break;
1929                 case 0x99:
1930                         gb_backend_map = 0x66552211;
1931                         break;
1932                 case 0x5a:
1933                         gb_backend_map = 0x77552200;
1934                         break;
1935                 case 0xaa:
1936                         gb_backend_map = 0x66442200;
1937                         break;
1938                 case 0x95:
1939                         gb_backend_map = 0x66553311;
1940                         break;
1941                 default:
1942                         DRM_ERROR("bad backend map, using default\n");
1943                         gb_backend_map =
1944                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1945                                                                        rdev->config.evergreen.max_tile_pipes,
1946                                                                        rdev->config.evergreen.max_backends,
1947                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1948                                                                    rdev->config.evergreen.max_backends) &
1949                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1950                         break;
1951                 }
1952         } else if (rdev->ddev->pdev->device == 0x68b9) {
1953                 u32 efuse_straps_3;
1954                 u8 efuse_box_bit_127_124;
1955
1956                 WREG32(RCU_IND_INDEX, 0x203);
1957                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1958                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1959
1960                 switch(efuse_box_bit_127_124) {
1961                 case 0x0:
1962                         gb_backend_map = 0x00003210;
1963                         break;
1964                 case 0x5:
1965                 case 0x6:
1966                 case 0x9:
1967                 case 0xa:
1968                         gb_backend_map = 0x00003311;
1969                         break;
1970                 default:
1971                         DRM_ERROR("bad backend map, using default\n");
1972                         gb_backend_map =
1973                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1974                                                                        rdev->config.evergreen.max_tile_pipes,
1975                                                                        rdev->config.evergreen.max_backends,
1976                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1977                                                                    rdev->config.evergreen.max_backends) &
1978                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1979                         break;
1980                 }
1981         } else {
1982                 switch (rdev->family) {
1983                 case CHIP_CYPRESS:
1984                 case CHIP_HEMLOCK:
1985                 case CHIP_BARTS:
1986                         gb_backend_map = 0x66442200;
1987                         break;
1988                 case CHIP_JUNIPER:
1989                         gb_backend_map = 0x00002200;
1990                         break;
1991                 default:
1992                         gb_backend_map =
1993                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1994                                                                        rdev->config.evergreen.max_tile_pipes,
1995                                                                        rdev->config.evergreen.max_backends,
1996                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1997                                                                          rdev->config.evergreen.max_backends) &
1998                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1999                 }
2000         }
2001
2002         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2003          * not have bank info, so create a custom tiling dword.
2004          * bits 3:0   num_pipes
2005          * bits 7:4   num_banks
2006          * bits 11:8  group_size
2007          * bits 15:12 row_size
2008          */
2009         rdev->config.evergreen.tile_config = 0;
2010         switch (rdev->config.evergreen.max_tile_pipes) {
2011         case 1:
2012         default:
2013                 rdev->config.evergreen.tile_config |= (0 << 0);
2014                 break;
2015         case 2:
2016                 rdev->config.evergreen.tile_config |= (1 << 0);
2017                 break;
2018         case 4:
2019                 rdev->config.evergreen.tile_config |= (2 << 0);
2020                 break;
2021         case 8:
2022                 rdev->config.evergreen.tile_config |= (3 << 0);
2023                 break;
2024         }
2025         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2026         if (rdev->flags & RADEON_IS_IGP)
2027                 rdev->config.evergreen.tile_config |= 1 << 4;
2028         else
2029                 rdev->config.evergreen.tile_config |=
2030                         ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2031         rdev->config.evergreen.tile_config |=
2032                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2033         rdev->config.evergreen.tile_config |=
2034                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2035
2036         rdev->config.evergreen.backend_map = gb_backend_map;
2037         WREG32(GB_BACKEND_MAP, gb_backend_map);
2038         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2039         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2040         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2041
2042         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2043         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2044
2045         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2046                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2047                 u32 sp = cc_gc_shader_pipe_config;
2048                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2049
2050                 if (i == num_shader_engines) {
2051                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2052                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2053                 }
2054
2055                 WREG32(GRBM_GFX_INDEX, gfx);
2056                 WREG32(RLC_GFX_INDEX, gfx);
2057
2058                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2059                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2060                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2061                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2062         }
2063
2064         grbm_gfx_index |= SE_BROADCAST_WRITES;
2065         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2066         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2067
2068         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2069         WREG32(CGTS_TCC_DISABLE, 0);
2070         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2071         WREG32(CGTS_USER_TCC_DISABLE, 0);
2072
2073         /* set HW defaults for 3D engine */
2074         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2075                                      ROQ_IB2_START(0x2b)));
2076
2077         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2078
2079         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2080                              SYNC_GRADIENT |
2081                              SYNC_WALKER |
2082                              SYNC_ALIGNER));
2083
2084         sx_debug_1 = RREG32(SX_DEBUG_1);
2085         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2086         WREG32(SX_DEBUG_1, sx_debug_1);
2087
2088
2089         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2090         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2091         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2092         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2093
2094         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2095                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2096                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2097
2098         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2099                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2100                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2101
2102         WREG32(VGT_NUM_INSTANCES, 1);
2103         WREG32(SPI_CONFIG_CNTL, 0);
2104         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2105         WREG32(CP_PERFMON_CNTL, 0);
2106
2107         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2108                                   FETCH_FIFO_HIWATER(0x4) |
2109                                   DONE_FIFO_HIWATER(0xe0) |
2110                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2111
2112         sq_config = RREG32(SQ_CONFIG);
2113         sq_config &= ~(PS_PRIO(3) |
2114                        VS_PRIO(3) |
2115                        GS_PRIO(3) |
2116                        ES_PRIO(3));
2117         sq_config |= (VC_ENABLE |
2118                       EXPORT_SRC_C |
2119                       PS_PRIO(0) |
2120                       VS_PRIO(1) |
2121                       GS_PRIO(2) |
2122                       ES_PRIO(3));
2123
2124         switch (rdev->family) {
2125         case CHIP_CEDAR:
2126         case CHIP_PALM:
2127         case CHIP_SUMO:
2128         case CHIP_SUMO2:
2129         case CHIP_CAICOS:
2130                 /* no vertex cache */
2131                 sq_config &= ~VC_ENABLE;
2132                 break;
2133         default:
2134                 break;
2135         }
2136
2137         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2138
2139         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2140         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2141         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2142         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2143         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2144         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2145         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2146
2147         switch (rdev->family) {
2148         case CHIP_CEDAR:
2149         case CHIP_PALM:
2150         case CHIP_SUMO:
2151         case CHIP_SUMO2:
2152                 ps_thread_count = 96;
2153                 break;
2154         default:
2155                 ps_thread_count = 128;
2156                 break;
2157         }
2158
2159         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2160         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2161         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2163         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2164         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2165
2166         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2167         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2171         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2172
2173         WREG32(SQ_CONFIG, sq_config);
2174         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2175         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2176         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2177         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2178         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2179         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2180         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2181         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2182         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2183         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2184
2185         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2186                                           FORCE_EOV_MAX_REZ_CNT(255)));
2187
2188         switch (rdev->family) {
2189         case CHIP_CEDAR:
2190         case CHIP_PALM:
2191         case CHIP_SUMO:
2192         case CHIP_SUMO2:
2193         case CHIP_CAICOS:
2194                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2195                 break;
2196         default:
2197                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2198                 break;
2199         }
2200         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2201         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2202
2203         WREG32(VGT_GS_VERTEX_REUSE, 16);
2204         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2205         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2206
2207         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2208         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2209
2210         WREG32(CB_PERF_CTR0_SEL_0, 0);
2211         WREG32(CB_PERF_CTR0_SEL_1, 0);
2212         WREG32(CB_PERF_CTR1_SEL_0, 0);
2213         WREG32(CB_PERF_CTR1_SEL_1, 0);
2214         WREG32(CB_PERF_CTR2_SEL_0, 0);
2215         WREG32(CB_PERF_CTR2_SEL_1, 0);
2216         WREG32(CB_PERF_CTR3_SEL_0, 0);
2217         WREG32(CB_PERF_CTR3_SEL_1, 0);
2218
2219         /* clear render buffer base addresses */
2220         WREG32(CB_COLOR0_BASE, 0);
2221         WREG32(CB_COLOR1_BASE, 0);
2222         WREG32(CB_COLOR2_BASE, 0);
2223         WREG32(CB_COLOR3_BASE, 0);
2224         WREG32(CB_COLOR4_BASE, 0);
2225         WREG32(CB_COLOR5_BASE, 0);
2226         WREG32(CB_COLOR6_BASE, 0);
2227         WREG32(CB_COLOR7_BASE, 0);
2228         WREG32(CB_COLOR8_BASE, 0);
2229         WREG32(CB_COLOR9_BASE, 0);
2230         WREG32(CB_COLOR10_BASE, 0);
2231         WREG32(CB_COLOR11_BASE, 0);
2232
2233         /* set the shader const cache sizes to 0 */
2234         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2235                 WREG32(i, 0);
2236         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2237                 WREG32(i, 0);
2238
2239         tmp = RREG32(HDP_MISC_CNTL);
2240         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2241         WREG32(HDP_MISC_CNTL, tmp);
2242
2243         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2244         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2245
2246         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2247
2248         udelay(50);
2249
2250 }
2251
2252 int evergreen_mc_init(struct radeon_device *rdev)
2253 {
2254         u32 tmp;
2255         int chansize, numchan;
2256
2257         /* Get VRAM informations */
2258         rdev->mc.vram_is_ddr = true;
2259         if (rdev->flags & RADEON_IS_IGP)
2260                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2261         else
2262                 tmp = RREG32(MC_ARB_RAMCFG);
2263         if (tmp & CHANSIZE_OVERRIDE) {
2264                 chansize = 16;
2265         } else if (tmp & CHANSIZE_MASK) {
2266                 chansize = 64;
2267         } else {
2268                 chansize = 32;
2269         }
2270         tmp = RREG32(MC_SHARED_CHMAP);
2271         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2272         case 0:
2273         default:
2274                 numchan = 1;
2275                 break;
2276         case 1:
2277                 numchan = 2;
2278                 break;
2279         case 2:
2280                 numchan = 4;
2281                 break;
2282         case 3:
2283                 numchan = 8;
2284                 break;
2285         }
2286         rdev->mc.vram_width = numchan * chansize;
2287         /* Could aper size report 0 ? */
2288         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2289         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2290         /* Setup GPU memory space */
2291         if (rdev->flags & RADEON_IS_IGP) {
2292                 /* size in bytes on fusion */
2293                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2294                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2295         } else {
2296                 /* size in MB on evergreen */
2297                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2298                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2299         }
2300         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2301         r700_vram_gtt_location(rdev, &rdev->mc);
2302         radeon_update_bandwidth_info(rdev);
2303
2304         return 0;
2305 }
2306
2307 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2308 {
2309         u32 srbm_status;
2310         u32 grbm_status;
2311         u32 grbm_status_se0, grbm_status_se1;
2312         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2313         int r;
2314
2315         srbm_status = RREG32(SRBM_STATUS);
2316         grbm_status = RREG32(GRBM_STATUS);
2317         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2318         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2319         if (!(grbm_status & GUI_ACTIVE)) {
2320                 r100_gpu_lockup_update(lockup, &rdev->cp);
2321                 return false;
2322         }
2323         /* force CP activities */
2324         r = radeon_ring_lock(rdev, 2);
2325         if (!r) {
2326                 /* PACKET2 NOP */
2327                 radeon_ring_write(rdev, 0x80000000);
2328                 radeon_ring_write(rdev, 0x80000000);
2329                 radeon_ring_unlock_commit(rdev);
2330         }
2331         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2332         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2333 }
2334
2335 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2336 {
2337         struct evergreen_mc_save save;
2338         u32 grbm_reset = 0;
2339
2340         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2341                 return 0;
2342
2343         dev_info(rdev->dev, "GPU softreset \n");
2344         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2345                 RREG32(GRBM_STATUS));
2346         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2347                 RREG32(GRBM_STATUS_SE0));
2348         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2349                 RREG32(GRBM_STATUS_SE1));
2350         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2351                 RREG32(SRBM_STATUS));
2352         evergreen_mc_stop(rdev, &save);
2353         if (evergreen_mc_wait_for_idle(rdev)) {
2354                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2355         }
2356         /* Disable CP parsing/prefetching */
2357         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2358
2359         /* reset all the gfx blocks */
2360         grbm_reset = (SOFT_RESET_CP |
2361                       SOFT_RESET_CB |
2362                       SOFT_RESET_DB |
2363                       SOFT_RESET_PA |
2364                       SOFT_RESET_SC |
2365                       SOFT_RESET_SPI |
2366                       SOFT_RESET_SH |
2367                       SOFT_RESET_SX |
2368                       SOFT_RESET_TC |
2369                       SOFT_RESET_TA |
2370                       SOFT_RESET_VC |
2371                       SOFT_RESET_VGT);
2372
2373         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2374         WREG32(GRBM_SOFT_RESET, grbm_reset);
2375         (void)RREG32(GRBM_SOFT_RESET);
2376         udelay(50);
2377         WREG32(GRBM_SOFT_RESET, 0);
2378         (void)RREG32(GRBM_SOFT_RESET);
2379         /* Wait a little for things to settle down */
2380         udelay(50);
2381         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2382                 RREG32(GRBM_STATUS));
2383         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2384                 RREG32(GRBM_STATUS_SE0));
2385         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2386                 RREG32(GRBM_STATUS_SE1));
2387         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2388                 RREG32(SRBM_STATUS));
2389         evergreen_mc_resume(rdev, &save);
2390         return 0;
2391 }
2392
2393 int evergreen_asic_reset(struct radeon_device *rdev)
2394 {
2395         return evergreen_gpu_soft_reset(rdev);
2396 }
2397
2398 /* Interrupts */
2399
2400 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2401 {
2402         switch (crtc) {
2403         case 0:
2404                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2405         case 1:
2406                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2407         case 2:
2408                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2409         case 3:
2410                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2411         case 4:
2412                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2413         case 5:
2414                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2415         default:
2416                 return 0;
2417         }
2418 }
2419
2420 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2421 {
2422         u32 tmp;
2423
2424         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2425         WREG32(GRBM_INT_CNTL, 0);
2426         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2427         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2428         if (rdev->num_crtc >= 4) {
2429                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2430                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2431         }
2432         if (rdev->num_crtc >= 6) {
2433                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2434                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2435         }
2436
2437         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2438         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2439         if (rdev->num_crtc >= 4) {
2440                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2441                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2442         }
2443         if (rdev->num_crtc >= 6) {
2444                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2445                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2446         }
2447
2448         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2449         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2450
2451         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2452         WREG32(DC_HPD1_INT_CONTROL, tmp);
2453         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2454         WREG32(DC_HPD2_INT_CONTROL, tmp);
2455         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2456         WREG32(DC_HPD3_INT_CONTROL, tmp);
2457         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2458         WREG32(DC_HPD4_INT_CONTROL, tmp);
2459         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2460         WREG32(DC_HPD5_INT_CONTROL, tmp);
2461         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2462         WREG32(DC_HPD6_INT_CONTROL, tmp);
2463
2464 }
2465
2466 int evergreen_irq_set(struct radeon_device *rdev)
2467 {
2468         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2469         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2470         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2471         u32 grbm_int_cntl = 0;
2472         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2473
2474         if (!rdev->irq.installed) {
2475                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2476                 return -EINVAL;
2477         }
2478         /* don't enable anything if the ih is disabled */
2479         if (!rdev->ih.enabled) {
2480                 r600_disable_interrupts(rdev);
2481                 /* force the active interrupt state to all disabled */
2482                 evergreen_disable_interrupt_state(rdev);
2483                 return 0;
2484         }
2485
2486         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2487         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2488         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2489         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2490         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2491         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2492
2493         if (rdev->irq.sw_int) {
2494                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2495                 cp_int_cntl |= RB_INT_ENABLE;
2496                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2497         }
2498         if (rdev->irq.crtc_vblank_int[0] ||
2499             rdev->irq.pflip[0]) {
2500                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2501                 crtc1 |= VBLANK_INT_MASK;
2502         }
2503         if (rdev->irq.crtc_vblank_int[1] ||
2504             rdev->irq.pflip[1]) {
2505                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2506                 crtc2 |= VBLANK_INT_MASK;
2507         }
2508         if (rdev->irq.crtc_vblank_int[2] ||
2509             rdev->irq.pflip[2]) {
2510                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2511                 crtc3 |= VBLANK_INT_MASK;
2512         }
2513         if (rdev->irq.crtc_vblank_int[3] ||
2514             rdev->irq.pflip[3]) {
2515                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2516                 crtc4 |= VBLANK_INT_MASK;
2517         }
2518         if (rdev->irq.crtc_vblank_int[4] ||
2519             rdev->irq.pflip[4]) {
2520                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2521                 crtc5 |= VBLANK_INT_MASK;
2522         }
2523         if (rdev->irq.crtc_vblank_int[5] ||
2524             rdev->irq.pflip[5]) {
2525                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2526                 crtc6 |= VBLANK_INT_MASK;
2527         }
2528         if (rdev->irq.hpd[0]) {
2529                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2530                 hpd1 |= DC_HPDx_INT_EN;
2531         }
2532         if (rdev->irq.hpd[1]) {
2533                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2534                 hpd2 |= DC_HPDx_INT_EN;
2535         }
2536         if (rdev->irq.hpd[2]) {
2537                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2538                 hpd3 |= DC_HPDx_INT_EN;
2539         }
2540         if (rdev->irq.hpd[3]) {
2541                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2542                 hpd4 |= DC_HPDx_INT_EN;
2543         }
2544         if (rdev->irq.hpd[4]) {
2545                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2546                 hpd5 |= DC_HPDx_INT_EN;
2547         }
2548         if (rdev->irq.hpd[5]) {
2549                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2550                 hpd6 |= DC_HPDx_INT_EN;
2551         }
2552         if (rdev->irq.gui_idle) {
2553                 DRM_DEBUG("gui idle\n");
2554                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2555         }
2556
2557         WREG32(CP_INT_CNTL, cp_int_cntl);
2558         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2559
2560         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2561         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2562         if (rdev->num_crtc >= 4) {
2563                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2564                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2565         }
2566         if (rdev->num_crtc >= 6) {
2567                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2568                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2569         }
2570
2571         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2572         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2573         if (rdev->num_crtc >= 4) {
2574                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2575                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2576         }
2577         if (rdev->num_crtc >= 6) {
2578                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2579                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2580         }
2581
2582         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2583         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2584         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2585         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2586         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2587         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2588
2589         return 0;
2590 }
2591
2592 static void evergreen_irq_ack(struct radeon_device *rdev)
2593 {
2594         u32 tmp;
2595
2596         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2597         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2598         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2599         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2600         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2601         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2602         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2603         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2604         if (rdev->num_crtc >= 4) {
2605                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2606                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2607         }
2608         if (rdev->num_crtc >= 6) {
2609                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2610                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2611         }
2612
2613         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2614                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2615         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2616                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2617         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2618                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2619         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2620                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2621         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2622                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2623         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2624                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2625
2626         if (rdev->num_crtc >= 4) {
2627                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2628                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2629                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2630                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2631                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2632                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2633                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2634                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2635                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2636                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2637                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2638                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2639         }
2640
2641         if (rdev->num_crtc >= 6) {
2642                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2643                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2644                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2645                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2646                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2647                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2648                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2649                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2650                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2651                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2652                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2653                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2654         }
2655
2656         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2657                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2658                 tmp |= DC_HPDx_INT_ACK;
2659                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2660         }
2661         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2662                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2663                 tmp |= DC_HPDx_INT_ACK;
2664                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2665         }
2666         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2667                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2668                 tmp |= DC_HPDx_INT_ACK;
2669                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2670         }
2671         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2672                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2673                 tmp |= DC_HPDx_INT_ACK;
2674                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2675         }
2676         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2677                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2678                 tmp |= DC_HPDx_INT_ACK;
2679                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2680         }
2681         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2682                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2683                 tmp |= DC_HPDx_INT_ACK;
2684                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2685         }
2686 }
2687
2688 void evergreen_irq_disable(struct radeon_device *rdev)
2689 {
2690         r600_disable_interrupts(rdev);
2691         /* Wait and acknowledge irq */
2692         mdelay(1);
2693         evergreen_irq_ack(rdev);
2694         evergreen_disable_interrupt_state(rdev);
2695 }
2696
2697 void evergreen_irq_suspend(struct radeon_device *rdev)
2698 {
2699         evergreen_irq_disable(rdev);
2700         r600_rlc_stop(rdev);
2701 }
2702
2703 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2704 {
2705         u32 wptr, tmp;
2706
2707         if (rdev->wb.enabled)
2708                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2709         else
2710                 wptr = RREG32(IH_RB_WPTR);
2711
2712         if (wptr & RB_OVERFLOW) {
2713                 /* When a ring buffer overflow happen start parsing interrupt
2714                  * from the last not overwritten vector (wptr + 16). Hopefully
2715                  * this should allow us to catchup.
2716                  */
2717                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2718                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2719                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2720                 tmp = RREG32(IH_RB_CNTL);
2721                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2722                 WREG32(IH_RB_CNTL, tmp);
2723         }
2724         return (wptr & rdev->ih.ptr_mask);
2725 }
2726
2727 int evergreen_irq_process(struct radeon_device *rdev)
2728 {
2729         u32 wptr;
2730         u32 rptr;
2731         u32 src_id, src_data;
2732         u32 ring_index;
2733         unsigned long flags;
2734         bool queue_hotplug = false;
2735
2736         if (!rdev->ih.enabled || rdev->shutdown)
2737                 return IRQ_NONE;
2738
2739         wptr = evergreen_get_ih_wptr(rdev);
2740         rptr = rdev->ih.rptr;
2741         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2742
2743         spin_lock_irqsave(&rdev->ih.lock, flags);
2744         if (rptr == wptr) {
2745                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2746                 return IRQ_NONE;
2747         }
2748 restart_ih:
2749         /* Order reading of wptr vs. reading of IH ring data */
2750         rmb();
2751
2752         /* display interrupts */
2753         evergreen_irq_ack(rdev);
2754
2755         rdev->ih.wptr = wptr;
2756         while (rptr != wptr) {
2757                 /* wptr/rptr are in bytes! */
2758                 ring_index = rptr / 4;
2759                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2760                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2761
2762                 switch (src_id) {
2763                 case 1: /* D1 vblank/vline */
2764                         switch (src_data) {
2765                         case 0: /* D1 vblank */
2766                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2767                                         if (rdev->irq.crtc_vblank_int[0]) {
2768                                                 drm_handle_vblank(rdev->ddev, 0);
2769                                                 rdev->pm.vblank_sync = true;
2770                                                 wake_up(&rdev->irq.vblank_queue);
2771                                         }
2772                                         if (rdev->irq.pflip[0])
2773                                                 radeon_crtc_handle_flip(rdev, 0);
2774                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2775                                         DRM_DEBUG("IH: D1 vblank\n");
2776                                 }
2777                                 break;
2778                         case 1: /* D1 vline */
2779                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2780                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2781                                         DRM_DEBUG("IH: D1 vline\n");
2782                                 }
2783                                 break;
2784                         default:
2785                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2786                                 break;
2787                         }
2788                         break;
2789                 case 2: /* D2 vblank/vline */
2790                         switch (src_data) {
2791                         case 0: /* D2 vblank */
2792                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2793                                         if (rdev->irq.crtc_vblank_int[1]) {
2794                                                 drm_handle_vblank(rdev->ddev, 1);
2795                                                 rdev->pm.vblank_sync = true;
2796                                                 wake_up(&rdev->irq.vblank_queue);
2797                                         }
2798                                         if (rdev->irq.pflip[1])
2799                                                 radeon_crtc_handle_flip(rdev, 1);
2800                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2801                                         DRM_DEBUG("IH: D2 vblank\n");
2802                                 }
2803                                 break;
2804                         case 1: /* D2 vline */
2805                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2806                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2807                                         DRM_DEBUG("IH: D2 vline\n");
2808                                 }
2809                                 break;
2810                         default:
2811                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2812                                 break;
2813                         }
2814                         break;
2815                 case 3: /* D3 vblank/vline */
2816                         switch (src_data) {
2817                         case 0: /* D3 vblank */
2818                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2819                                         if (rdev->irq.crtc_vblank_int[2]) {
2820                                                 drm_handle_vblank(rdev->ddev, 2);
2821                                                 rdev->pm.vblank_sync = true;
2822                                                 wake_up(&rdev->irq.vblank_queue);
2823                                         }
2824                                         if (rdev->irq.pflip[2])
2825                                                 radeon_crtc_handle_flip(rdev, 2);
2826                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2827                                         DRM_DEBUG("IH: D3 vblank\n");
2828                                 }
2829                                 break;
2830                         case 1: /* D3 vline */
2831                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2832                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2833                                         DRM_DEBUG("IH: D3 vline\n");
2834                                 }
2835                                 break;
2836                         default:
2837                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2838                                 break;
2839                         }
2840                         break;
2841                 case 4: /* D4 vblank/vline */
2842                         switch (src_data) {
2843                         case 0: /* D4 vblank */
2844                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2845                                         if (rdev->irq.crtc_vblank_int[3]) {
2846                                                 drm_handle_vblank(rdev->ddev, 3);
2847                                                 rdev->pm.vblank_sync = true;
2848                                                 wake_up(&rdev->irq.vblank_queue);
2849                                         }
2850                                         if (rdev->irq.pflip[3])
2851                                                 radeon_crtc_handle_flip(rdev, 3);
2852                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2853                                         DRM_DEBUG("IH: D4 vblank\n");
2854                                 }
2855                                 break;
2856                         case 1: /* D4 vline */
2857                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2858                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2859                                         DRM_DEBUG("IH: D4 vline\n");
2860                                 }
2861                                 break;
2862                         default:
2863                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2864                                 break;
2865                         }
2866                         break;
2867                 case 5: /* D5 vblank/vline */
2868                         switch (src_data) {
2869                         case 0: /* D5 vblank */
2870                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2871                                         if (rdev->irq.crtc_vblank_int[4]) {
2872                                                 drm_handle_vblank(rdev->ddev, 4);
2873                                                 rdev->pm.vblank_sync = true;
2874                                                 wake_up(&rdev->irq.vblank_queue);
2875                                         }
2876                                         if (rdev->irq.pflip[4])
2877                                                 radeon_crtc_handle_flip(rdev, 4);
2878                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2879                                         DRM_DEBUG("IH: D5 vblank\n");
2880                                 }
2881                                 break;
2882                         case 1: /* D5 vline */
2883                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2884                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2885                                         DRM_DEBUG("IH: D5 vline\n");
2886                                 }
2887                                 break;
2888                         default:
2889                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2890                                 break;
2891                         }
2892                         break;
2893                 case 6: /* D6 vblank/vline */
2894                         switch (src_data) {
2895                         case 0: /* D6 vblank */
2896                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2897                                         if (rdev->irq.crtc_vblank_int[5]) {
2898                                                 drm_handle_vblank(rdev->ddev, 5);
2899                                                 rdev->pm.vblank_sync = true;
2900                                                 wake_up(&rdev->irq.vblank_queue);
2901                                         }
2902                                         if (rdev->irq.pflip[5])
2903                                                 radeon_crtc_handle_flip(rdev, 5);
2904                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2905                                         DRM_DEBUG("IH: D6 vblank\n");
2906                                 }
2907                                 break;
2908                         case 1: /* D6 vline */
2909                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2910                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2911                                         DRM_DEBUG("IH: D6 vline\n");
2912                                 }
2913                                 break;
2914                         default:
2915                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2916                                 break;
2917                         }
2918                         break;
2919                 case 42: /* HPD hotplug */
2920                         switch (src_data) {
2921                         case 0:
2922                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2923                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2924                                         queue_hotplug = true;
2925                                         DRM_DEBUG("IH: HPD1\n");
2926                                 }
2927                                 break;
2928                         case 1:
2929                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2930                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2931                                         queue_hotplug = true;
2932                                         DRM_DEBUG("IH: HPD2\n");
2933                                 }
2934                                 break;
2935                         case 2:
2936                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2937                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2938                                         queue_hotplug = true;
2939                                         DRM_DEBUG("IH: HPD3\n");
2940                                 }
2941                                 break;
2942                         case 3:
2943                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2944                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2945                                         queue_hotplug = true;
2946                                         DRM_DEBUG("IH: HPD4\n");
2947                                 }
2948                                 break;
2949                         case 4:
2950                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2951                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2952                                         queue_hotplug = true;
2953                                         DRM_DEBUG("IH: HPD5\n");
2954                                 }
2955                                 break;
2956                         case 5:
2957                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2958                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2959                                         queue_hotplug = true;
2960                                         DRM_DEBUG("IH: HPD6\n");
2961                                 }
2962                                 break;
2963                         default:
2964                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2965                                 break;
2966                         }
2967                         break;
2968                 case 176: /* CP_INT in ring buffer */
2969                 case 177: /* CP_INT in IB1 */
2970                 case 178: /* CP_INT in IB2 */
2971                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2972                         radeon_fence_process(rdev);
2973                         break;
2974                 case 181: /* CP EOP event */
2975                         DRM_DEBUG("IH: CP EOP\n");
2976                         radeon_fence_process(rdev);
2977                         break;
2978                 case 233: /* GUI IDLE */
2979                         DRM_DEBUG("IH: GUI idle\n");
2980                         rdev->pm.gui_idle = true;
2981                         wake_up(&rdev->irq.idle_queue);
2982                         break;
2983                 default:
2984                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2985                         break;
2986                 }
2987
2988                 /* wptr/rptr are in bytes! */
2989                 rptr += 16;
2990                 rptr &= rdev->ih.ptr_mask;
2991         }
2992         /* make sure wptr hasn't changed while processing */
2993         wptr = evergreen_get_ih_wptr(rdev);
2994         if (wptr != rdev->ih.wptr)
2995                 goto restart_ih;
2996         if (queue_hotplug)
2997                 schedule_work(&rdev->hotplug_work);
2998         rdev->ih.rptr = rptr;
2999         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3000         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3001         return IRQ_HANDLED;
3002 }
3003
3004 static int evergreen_startup(struct radeon_device *rdev)
3005 {
3006         int r;
3007
3008         /* enable pcie gen2 link */
3009         evergreen_pcie_gen2_enable(rdev);
3010
3011         if (ASIC_IS_DCE5(rdev)) {
3012                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3013                         r = ni_init_microcode(rdev);
3014                         if (r) {
3015                                 DRM_ERROR("Failed to load firmware!\n");
3016                                 return r;
3017                         }
3018                 }
3019                 r = ni_mc_load_microcode(rdev);
3020                 if (r) {
3021                         DRM_ERROR("Failed to load MC firmware!\n");
3022                         return r;
3023                 }
3024         } else {
3025                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3026                         r = r600_init_microcode(rdev);
3027                         if (r) {
3028                                 DRM_ERROR("Failed to load firmware!\n");
3029                                 return r;
3030                         }
3031                 }
3032         }
3033
3034         evergreen_mc_program(rdev);
3035         if (rdev->flags & RADEON_IS_AGP) {
3036                 evergreen_agp_enable(rdev);
3037         } else {
3038                 r = evergreen_pcie_gart_enable(rdev);
3039                 if (r)
3040                         return r;
3041         }
3042         evergreen_gpu_init(rdev);
3043
3044         r = evergreen_blit_init(rdev);
3045         if (r) {
3046                 r600_blit_fini(rdev);
3047                 rdev->asic->copy = NULL;
3048                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3049         }
3050
3051         /* allocate wb buffer */
3052         r = radeon_wb_init(rdev);
3053         if (r)
3054                 return r;
3055
3056         /* Enable IRQ */
3057         r = r600_irq_init(rdev);
3058         if (r) {
3059                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3060                 radeon_irq_kms_fini(rdev);
3061                 return r;
3062         }
3063         evergreen_irq_set(rdev);
3064
3065         r = radeon_ring_init(rdev, rdev->cp.ring_size);
3066         if (r)
3067                 return r;
3068         r = evergreen_cp_load_microcode(rdev);
3069         if (r)
3070                 return r;
3071         r = evergreen_cp_resume(rdev);
3072         if (r)
3073                 return r;
3074
3075         return 0;
3076 }
3077
3078 int evergreen_resume(struct radeon_device *rdev)
3079 {
3080         int r;
3081
3082         /* reset the asic, the gfx blocks are often in a bad state
3083          * after the driver is unloaded or after a resume
3084          */
3085         if (radeon_asic_reset(rdev))
3086                 dev_warn(rdev->dev, "GPU reset failed !\n");
3087         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3088          * posting will perform necessary task to bring back GPU into good
3089          * shape.
3090          */
3091         /* post card */
3092         atom_asic_init(rdev->mode_info.atom_context);
3093
3094         r = evergreen_startup(rdev);
3095         if (r) {
3096                 DRM_ERROR("evergreen startup failed on resume\n");
3097                 return r;
3098         }
3099
3100         r = r600_ib_test(rdev);
3101         if (r) {
3102                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3103                 return r;
3104         }
3105
3106         return r;
3107
3108 }
3109
3110 int evergreen_suspend(struct radeon_device *rdev)
3111 {
3112         /* FIXME: we should wait for ring to be empty */
3113         r700_cp_stop(rdev);
3114         rdev->cp.ready = false;
3115         evergreen_irq_suspend(rdev);
3116         radeon_wb_disable(rdev);
3117         evergreen_pcie_gart_disable(rdev);
3118         r600_blit_suspend(rdev);
3119
3120         return 0;
3121 }
3122
3123 /* Plan is to move initialization in that function and use
3124  * helper function so that radeon_device_init pretty much
3125  * do nothing more than calling asic specific function. This
3126  * should also allow to remove a bunch of callback function
3127  * like vram_info.
3128  */
3129 int evergreen_init(struct radeon_device *rdev)
3130 {
3131         int r;
3132
3133         /* This don't do much */
3134         r = radeon_gem_init(rdev);
3135         if (r)
3136                 return r;
3137         /* Read BIOS */
3138         if (!radeon_get_bios(rdev)) {
3139                 if (ASIC_IS_AVIVO(rdev))
3140                         return -EINVAL;
3141         }
3142         /* Must be an ATOMBIOS */
3143         if (!rdev->is_atom_bios) {
3144                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3145                 return -EINVAL;
3146         }
3147         r = radeon_atombios_init(rdev);
3148         if (r)
3149                 return r;
3150         /* reset the asic, the gfx blocks are often in a bad state
3151          * after the driver is unloaded or after a resume
3152          */
3153         if (radeon_asic_reset(rdev))
3154                 dev_warn(rdev->dev, "GPU reset failed !\n");
3155         /* Post card if necessary */
3156         if (!radeon_card_posted(rdev)) {
3157                 if (!rdev->bios) {
3158                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3159                         return -EINVAL;
3160                 }
3161                 DRM_INFO("GPU not posted. posting now...\n");
3162                 atom_asic_init(rdev->mode_info.atom_context);
3163         }
3164         /* Initialize scratch registers */
3165         r600_scratch_init(rdev);
3166         /* Initialize surface registers */
3167         radeon_surface_init(rdev);
3168         /* Initialize clocks */
3169         radeon_get_clock_info(rdev->ddev);
3170         /* Fence driver */
3171         r = radeon_fence_driver_init(rdev);
3172         if (r)
3173                 return r;
3174         /* initialize AGP */
3175         if (rdev->flags & RADEON_IS_AGP) {
3176                 r = radeon_agp_init(rdev);
3177                 if (r)
3178                         radeon_agp_disable(rdev);
3179         }
3180         /* initialize memory controller */
3181         r = evergreen_mc_init(rdev);
3182         if (r)
3183                 return r;
3184         /* Memory manager */
3185         r = radeon_bo_init(rdev);
3186         if (r)
3187                 return r;
3188
3189         r = radeon_irq_kms_init(rdev);
3190         if (r)
3191                 return r;
3192
3193         rdev->cp.ring_obj = NULL;
3194         r600_ring_init(rdev, 1024 * 1024);
3195
3196         rdev->ih.ring_obj = NULL;
3197         r600_ih_ring_init(rdev, 64 * 1024);
3198
3199         r = r600_pcie_gart_init(rdev);
3200         if (r)
3201                 return r;
3202
3203         rdev->accel_working = true;
3204         r = evergreen_startup(rdev);
3205         if (r) {
3206                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3207                 r700_cp_fini(rdev);
3208                 r600_irq_fini(rdev);
3209                 radeon_wb_fini(rdev);
3210                 radeon_irq_kms_fini(rdev);
3211                 evergreen_pcie_gart_fini(rdev);
3212                 rdev->accel_working = false;
3213         }
3214         if (rdev->accel_working) {
3215                 r = radeon_ib_pool_init(rdev);
3216                 if (r) {
3217                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3218                         rdev->accel_working = false;
3219                 }
3220                 r = r600_ib_test(rdev);
3221                 if (r) {
3222                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3223                         rdev->accel_working = false;
3224                 }
3225         }
3226         return 0;
3227 }
3228
3229 void evergreen_fini(struct radeon_device *rdev)
3230 {
3231         r600_blit_fini(rdev);
3232         r700_cp_fini(rdev);
3233         r600_irq_fini(rdev);
3234         radeon_wb_fini(rdev);
3235         radeon_ib_pool_fini(rdev);
3236         radeon_irq_kms_fini(rdev);
3237         evergreen_pcie_gart_fini(rdev);
3238         radeon_gem_fini(rdev);
3239         radeon_fence_driver_fini(rdev);
3240         radeon_agp_fini(rdev);
3241         radeon_bo_fini(rdev);
3242         radeon_atombios_fini(rdev);
3243         kfree(rdev->bios);
3244         rdev->bios = NULL;
3245 }
3246
3247 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3248 {
3249         u32 link_width_cntl, speed_cntl;
3250
3251         if (radeon_pcie_gen2 == 0)
3252                 return;
3253
3254         if (rdev->flags & RADEON_IS_IGP)
3255                 return;
3256
3257         if (!(rdev->flags & RADEON_IS_PCIE))
3258                 return;
3259
3260         /* x2 cards have a special sequence */
3261         if (ASIC_IS_X2(rdev))
3262                 return;
3263
3264         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3265         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3266             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3267
3268                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3269                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3270                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3271
3272                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3273                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3274                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3275
3276                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3277                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3278                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3279
3280                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3281                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3282                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3283
3284                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3285                 speed_cntl |= LC_GEN2_EN_STRAP;
3286                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3287
3288         } else {
3289                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3290                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3291                 if (1)
3292                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3293                 else
3294                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3295                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3296         }
3297 }