drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  45 {
  46         u16 ctl, v;
  47         int cap, err;
  48
  49         cap = pci_pcie_cap(rdev->pdev);
  50         if (!cap)
  51                 return;
  52
  53         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  54         if (err)
  55                 return;
  56
  57         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  58
  59         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  60          * to avoid hangs or perfomance issues
  61          */
  62         if ((v == 0) || (v == 6) || (v == 7)) {
  63                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
  64                 ctl |= (2 << 12);
  65                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
  66         }
  67 }
  68
  69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  70 {
  71         /* enable the pflip int */
  72         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  73 }
  74
  75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  76 {
  77         /* disable the pflip int */
  78         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  79 }
  80
  81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  82 {
  83         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  84         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  85
  86         /* Lock the graphics update lock */
  87         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  88         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  89
  90         /* update the scanout addresses */
  91         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  92                upper_32_bits(crtc_base));
  93         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  94                (u32)crtc_base);
  95
  96         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  97                upper_32_bits(crtc_base));
  98         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  99                (u32)crtc_base);
 100
 101         /* Wait for update_pending to go high. */
 102         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
 103         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 104
 105         /* Unlock the lock, so double-buffering can take place inside vblank */
 106         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 107         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 108
 109         /* Return current update_pending status: */
 110         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 111 }
 112
 113 /* get temperature in millidegrees */
 114 int evergreen_get_temp(struct radeon_device *rdev)
 115 {
 116         u32 temp, toffset;
 117         int actual_temp = 0;
 118
 119         if (rdev->family == CHIP_JUNIPER) {
 120                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 121                         TOFFSET_SHIFT;
 122                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 123                         TS0_ADC_DOUT_SHIFT;
 124
 125                 if (toffset & 0x100)
 126                         actual_temp = temp / 2 - (0x200 - toffset);
 127                 else
 128                         actual_temp = temp / 2 + toffset;
 129
 130                 actual_temp = actual_temp * 1000;
 131
 132         } else {
 133                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 134                         ASIC_T_SHIFT;
 135
 136                 if (temp & 0x400)
 137                         actual_temp = -256;
 138                 else if (temp & 0x200)
 139                         actual_temp = 255;
 140                 else if (temp & 0x100) {
 141                         actual_temp = temp & 0x1ff;
 142                         actual_temp |= ~0x1ff;
 143                 } else
 144                         actual_temp = temp & 0xff;
 145
 146                 actual_temp = (actual_temp * 1000) / 2;
 147         }
 148
 149         return actual_temp;
 150 }
 151
 152 int sumo_get_temp(struct radeon_device *rdev)
 153 {
 154         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 155         int actual_temp = temp - 49;
 156
 157         return actual_temp * 1000;
 158 }
 159
 160 void evergreen_pm_misc(struct radeon_device *rdev)
 161 {
 162         int req_ps_idx = rdev->pm.requested_power_state_index;
 163         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 164         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 165         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 166
 167         if (voltage->type == VOLTAGE_SW) {
 168                 /* 0xff01 is a flag rather then an actual voltage */
 169                 if (voltage->voltage == 0xff01)
 170                         return;
 171                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 172                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 173                         rdev->pm.current_vddc = voltage->voltage;
 174                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 175                 }
 176                 /* 0xff01 is a flag rather then an actual voltage */
 177                 if (voltage->vddci == 0xff01)
 178                         return;
 179                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 180                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 181                         rdev->pm.current_vddci = voltage->vddci;
 182                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 183                 }
 184         }
 185 }
 186
 187 void evergreen_pm_prepare(struct radeon_device *rdev)
 188 {
 189         struct drm_device *ddev = rdev->ddev;
 190         struct drm_crtc *crtc;
 191         struct radeon_crtc *radeon_crtc;
 192         u32 tmp;
 193
 194         /* disable any active CRTCs */
 195         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 196                 radeon_crtc = to_radeon_crtc(crtc);
 197                 if (radeon_crtc->enabled) {
 198                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 199                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 200                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 201                 }
 202         }
 203 }
 204
 205 void evergreen_pm_finish(struct radeon_device *rdev)
 206 {
 207         struct drm_device *ddev = rdev->ddev;
 208         struct drm_crtc *crtc;
 209         struct radeon_crtc *radeon_crtc;
 210         u32 tmp;
 211
 212         /* enable any active CRTCs */
 213         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 214                 radeon_crtc = to_radeon_crtc(crtc);
 215                 if (radeon_crtc->enabled) {
 216                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 217                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 218                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 219                 }
 220         }
 221 }
 222
 223 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 224 {
 225         bool connected = false;
 226
 227         switch (hpd) {
 228         case RADEON_HPD_1:
 229                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 230                         connected = true;
 231                 break;
 232         case RADEON_HPD_2:
 233                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 234                         connected = true;
 235                 break;
 236         case RADEON_HPD_3:
 237                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 238                         connected = true;
 239                 break;
 240         case RADEON_HPD_4:
 241                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 242                         connected = true;
 243                 break;
 244         case RADEON_HPD_5:
 245                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 246                         connected = true;
 247                 break;
 248         case RADEON_HPD_6:
 249                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 250                         connected = true;
 251                         break;
 252         default:
 253                 break;
 254         }
 255
 256         return connected;
 257 }
 258
 259 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 260                                 enum radeon_hpd_id hpd)
 261 {
 262         u32 tmp;
 263         bool connected = evergreen_hpd_sense(rdev, hpd);
 264
 265         switch (hpd) {
 266         case RADEON_HPD_1:
 267                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 268                 if (connected)
 269                         tmp &= ~DC_HPDx_INT_POLARITY;
 270                 else
 271                         tmp |= DC_HPDx_INT_POLARITY;
 272                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 273                 break;
 274         case RADEON_HPD_2:
 275                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 276                 if (connected)
 277                         tmp &= ~DC_HPDx_INT_POLARITY;
 278                 else
 279                         tmp |= DC_HPDx_INT_POLARITY;
 280                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 281                 break;
 282         case RADEON_HPD_3:
 283                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 284                 if (connected)
 285                         tmp &= ~DC_HPDx_INT_POLARITY;
 286                 else
 287                         tmp |= DC_HPDx_INT_POLARITY;
 288                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 289                 break;
 290         case RADEON_HPD_4:
 291                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 292                 if (connected)
 293                         tmp &= ~DC_HPDx_INT_POLARITY;
 294                 else
 295                         tmp |= DC_HPDx_INT_POLARITY;
 296                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 297                 break;
 298         case RADEON_HPD_5:
 299                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 300                 if (connected)
 301                         tmp &= ~DC_HPDx_INT_POLARITY;
 302                 else
 303                         tmp |= DC_HPDx_INT_POLARITY;
 304                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 305                         break;
 306         case RADEON_HPD_6:
 307                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 308                 if (connected)
 309                         tmp &= ~DC_HPDx_INT_POLARITY;
 310                 else
 311                         tmp |= DC_HPDx_INT_POLARITY;
 312                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 313                 break;
 314         default:
 315                 break;
 316         }
 317 }
 318
 319 void evergreen_hpd_init(struct radeon_device *rdev)
 320 {
 321         struct drm_device *dev = rdev->ddev;
 322         struct drm_connector *connector;
 323         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 324                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 325
 326         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 327                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 328                 switch (radeon_connector->hpd.hpd) {
 329                 case RADEON_HPD_1:
 330                         WREG32(DC_HPD1_CONTROL, tmp);
 331                         rdev->irq.hpd[0] = true;
 332                         break;
 333                 case RADEON_HPD_2:
 334                         WREG32(DC_HPD2_CONTROL, tmp);
 335                         rdev->irq.hpd[1] = true;
 336                         break;
 337                 case RADEON_HPD_3:
 338                         WREG32(DC_HPD3_CONTROL, tmp);
 339                         rdev->irq.hpd[2] = true;
 340                         break;
 341                 case RADEON_HPD_4:
 342                         WREG32(DC_HPD4_CONTROL, tmp);
 343                         rdev->irq.hpd[3] = true;
 344                         break;
 345                 case RADEON_HPD_5:
 346                         WREG32(DC_HPD5_CONTROL, tmp);
 347                         rdev->irq.hpd[4] = true;
 348                         break;
 349                 case RADEON_HPD_6:
 350                         WREG32(DC_HPD6_CONTROL, tmp);
 351                         rdev->irq.hpd[5] = true;
 352                         break;
 353                 default:
 354                         break;
 355                 }
 356         }
 357         if (rdev->irq.installed)
 358                 evergreen_irq_set(rdev);
 359 }
 360
 361 void evergreen_hpd_fini(struct radeon_device *rdev)
 362 {
 363         struct drm_device *dev = rdev->ddev;
 364         struct drm_connector *connector;
 365
 366         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 367                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 368                 switch (radeon_connector->hpd.hpd) {
 369                 case RADEON_HPD_1:
 370                         WREG32(DC_HPD1_CONTROL, 0);
 371                         rdev->irq.hpd[0] = false;
 372                         break;
 373                 case RADEON_HPD_2:
 374                         WREG32(DC_HPD2_CONTROL, 0);
 375                         rdev->irq.hpd[1] = false;
 376                         break;
 377                 case RADEON_HPD_3:
 378                         WREG32(DC_HPD3_CONTROL, 0);
 379                         rdev->irq.hpd[2] = false;
 380                         break;
 381                 case RADEON_HPD_4:
 382                         WREG32(DC_HPD4_CONTROL, 0);
 383                         rdev->irq.hpd[3] = false;
 384                         break;
 385                 case RADEON_HPD_5:
 386                         WREG32(DC_HPD5_CONTROL, 0);
 387                         rdev->irq.hpd[4] = false;
 388                         break;
 389                 case RADEON_HPD_6:
 390                         WREG32(DC_HPD6_CONTROL, 0);
 391                         rdev->irq.hpd[5] = false;
 392                         break;
 393                 default:
 394                         break;
 395                 }
 396         }
 397 }
 398
 399 /* watermark setup */
 400
 401 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 402                                         struct radeon_crtc *radeon_crtc,
 403                                         struct drm_display_mode *mode,
 404                                         struct drm_display_mode *other_mode)
 405 {
 406         u32 tmp;
 407         /*
 408          * Line Buffer Setup
 409          * There are 3 line buffers, each one shared by 2 display controllers.
 410          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 411          * the display controllers.  The paritioning is done via one of four
 412          * preset allocations specified in bits 2:0:
 413          * first display controller
 414          *  0 - first half of lb (3840 * 2)
 415          *  1 - first 3/4 of lb (5760 * 2)
 416          *  2 - whole lb (7680 * 2), other crtc must be disabled
 417          *  3 - first 1/4 of lb (1920 * 2)
 418          * second display controller
 419          *  4 - second half of lb (3840 * 2)
 420          *  5 - second 3/4 of lb (5760 * 2)
 421          *  6 - whole lb (7680 * 2), other crtc must be disabled
 422          *  7 - last 1/4 of lb (1920 * 2)
 423          */
 424         /* this can get tricky if we have two large displays on a paired group
 425          * of crtcs.  Ideally for multiple large displays we'd assign them to
 426          * non-linked crtcs for maximum line buffer allocation.
 427          */
 428         if (radeon_crtc->base.enabled && mode) {
 429                 if (other_mode)
 430                         tmp = 0; /* 1/2 */
 431                 else
 432                         tmp = 2; /* whole */
 433         } else
 434                 tmp = 0;
 435
 436         /* second controller of the pair uses second half of the lb */
 437         if (radeon_crtc->crtc_id % 2)
 438                 tmp += 4;
 439         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 440
 441         if (radeon_crtc->base.enabled && mode) {
 442                 switch (tmp) {
 443                 case 0:
 444                 case 4:
 445                 default:
 446                         if (ASIC_IS_DCE5(rdev))
 447                                 return 4096 * 2;
 448                         else
 449                                 return 3840 * 2;
 450                 case 1:
 451                 case 5:
 452                         if (ASIC_IS_DCE5(rdev))
 453                                 return 6144 * 2;
 454                         else
 455                                 return 5760 * 2;
 456                 case 2:
 457                 case 6:
 458                         if (ASIC_IS_DCE5(rdev))
 459                                 return 8192 * 2;
 460                         else
 461                                 return 7680 * 2;
 462                 case 3:
 463                 case 7:
 464                         if (ASIC_IS_DCE5(rdev))
 465                                 return 2048 * 2;
 466                         else
 467                                 return 1920 * 2;
 468                 }
 469         }
 470
 471         /* controller not enabled, so no lb used */
 472         return 0;
 473 }
 474
 475 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 476 {
 477         u32 tmp = RREG32(MC_SHARED_CHMAP);
 478
 479         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 480         case 0:
 481         default:
 482                 return 1;
 483         case 1:
 484                 return 2;
 485         case 2:
 486                 return 4;
 487         case 3:
 488                 return 8;
 489         }
 490 }
 491
 492 struct evergreen_wm_params {
 493         u32 dram_channels; /* number of dram channels */
 494         u32 yclk;          /* bandwidth per dram data pin in kHz */
 495         u32 sclk;          /* engine clock in kHz */
 496         u32 disp_clk;      /* display clock in kHz */
 497         u32 src_width;     /* viewport width */
 498         u32 active_time;   /* active display time in ns */
 499         u32 blank_time;    /* blank time in ns */
 500         bool interlaced;    /* mode is interlaced */
 501         fixed20_12 vsc;    /* vertical scale ratio */
 502         u32 num_heads;     /* number of active crtcs */
 503         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 504         u32 lb_size;       /* line buffer allocated to pipe */
 505         u32 vtaps;         /* vertical scaler taps */
 506 };
 507
 508 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 509 {
 510         /* Calculate DRAM Bandwidth and the part allocated to display. */
 511         fixed20_12 dram_efficiency; /* 0.7 */
 512         fixed20_12 yclk, dram_channels, bandwidth;
 513         fixed20_12 a;
 514
 515         a.full = dfixed_const(1000);
 516         yclk.full = dfixed_const(wm->yclk);
 517         yclk.full = dfixed_div(yclk, a);
 518         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 519         a.full = dfixed_const(10);
 520         dram_efficiency.full = dfixed_const(7);
 521         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 522         bandwidth.full = dfixed_mul(dram_channels, yclk);
 523         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 524
 525         return dfixed_trunc(bandwidth);
 526 }
 527
 528 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 529 {
 530         /* Calculate DRAM Bandwidth and the part allocated to display. */
 531         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 532         fixed20_12 yclk, dram_channels, bandwidth;
 533         fixed20_12 a;
 534
 535         a.full = dfixed_const(1000);
 536         yclk.full = dfixed_const(wm->yclk);
 537         yclk.full = dfixed_div(yclk, a);
 538         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 539         a.full = dfixed_const(10);
 540         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 541         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 542         bandwidth.full = dfixed_mul(dram_channels, yclk);
 543         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 544
 545         return dfixed_trunc(bandwidth);
 546 }
 547
 548 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 549 {
 550         /* Calculate the display Data return Bandwidth */
 551         fixed20_12 return_efficiency; /* 0.8 */
 552         fixed20_12 sclk, bandwidth;
 553         fixed20_12 a;
 554
 555         a.full = dfixed_const(1000);
 556         sclk.full = dfixed_const(wm->sclk);
 557         sclk.full = dfixed_div(sclk, a);
 558         a.full = dfixed_const(10);
 559         return_efficiency.full = dfixed_const(8);
 560         return_efficiency.full = dfixed_div(return_efficiency, a);
 561         a.full = dfixed_const(32);
 562         bandwidth.full = dfixed_mul(a, sclk);
 563         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 564
 565         return dfixed_trunc(bandwidth);
 566 }
 567
 568 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 569 {
 570         /* Calculate the DMIF Request Bandwidth */
 571         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 572         fixed20_12 disp_clk, bandwidth;
 573         fixed20_12 a;
 574
 575         a.full = dfixed_const(1000);
 576         disp_clk.full = dfixed_const(wm->disp_clk);
 577         disp_clk.full = dfixed_div(disp_clk, a);
 578         a.full = dfixed_const(10);
 579         disp_clk_request_efficiency.full = dfixed_const(8);
 580         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 581         a.full = dfixed_const(32);
 582         bandwidth.full = dfixed_mul(a, disp_clk);
 583         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 584
 585         return dfixed_trunc(bandwidth);
 586 }
 587
 588 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 589 {
 590         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 591         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 592         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 593         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 594
 595         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 596 }
 597
 598 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 599 {
 600         /* Calculate the display mode Average Bandwidth
 601          * DisplayMode should contain the source and destination dimensions,
 602          * timing, etc.
 603          */
 604         fixed20_12 bpp;
 605         fixed20_12 line_time;
 606         fixed20_12 src_width;
 607         fixed20_12 bandwidth;
 608         fixed20_12 a;
 609
 610         a.full = dfixed_const(1000);
 611         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 612         line_time.full = dfixed_div(line_time, a);
 613         bpp.full = dfixed_const(wm->bytes_per_pixel);
 614         src_width.full = dfixed_const(wm->src_width);
 615         bandwidth.full = dfixed_mul(src_width, bpp);
 616         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 617         bandwidth.full = dfixed_div(bandwidth, line_time);
 618
 619         return dfixed_trunc(bandwidth);
 620 }
 621
 622 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 623 {
 624         /* First calcualte the latency in ns */
 625         u32 mc_latency = 2000; /* 2000 ns. */
 626         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 627         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 628         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 629         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 630         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 631                 (wm->num_heads * cursor_line_pair_return_time);
 632         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 633         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 634         fixed20_12 a, b, c;
 635
 636         if (wm->num_heads == 0)
 637                 return 0;
 638
 639         a.full = dfixed_const(2);
 640         b.full = dfixed_const(1);
 641         if ((wm->vsc.full > a.full) ||
 642             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 643             (wm->vtaps >= 5) ||
 644             ((wm->vsc.full >= a.full) && wm->interlaced))
 645                 max_src_lines_per_dst_line = 4;
 646         else
 647                 max_src_lines_per_dst_line = 2;
 648
 649         a.full = dfixed_const(available_bandwidth);
 650         b.full = dfixed_const(wm->num_heads);
 651         a.full = dfixed_div(a, b);
 652
 653         b.full = dfixed_const(1000);
 654         c.full = dfixed_const(wm->disp_clk);
 655         b.full = dfixed_div(c, b);
 656         c.full = dfixed_const(wm->bytes_per_pixel);
 657         b.full = dfixed_mul(b, c);
 658
 659         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 660
 661         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 662         b.full = dfixed_const(1000);
 663         c.full = dfixed_const(lb_fill_bw);
 664         b.full = dfixed_div(c, b);
 665         a.full = dfixed_div(a, b);
 666         line_fill_time = dfixed_trunc(a);
 667
 668         if (line_fill_time < wm->active_time)
 669                 return latency;
 670         else
 671                 return latency + (line_fill_time - wm->active_time);
 672
 673 }
 674
 675 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 676 {
 677         if (evergreen_average_bandwidth(wm) <=
 678             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 679                 return true;
 680         else
 681                 return false;
 682 };
 683
 684 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 685 {
 686         if (evergreen_average_bandwidth(wm) <=
 687             (evergreen_available_bandwidth(wm) / wm->num_heads))
 688                 return true;
 689         else
 690                 return false;
 691 };
 692
 693 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 694 {
 695         u32 lb_partitions = wm->lb_size / wm->src_width;
 696         u32 line_time = wm->active_time + wm->blank_time;
 697         u32 latency_tolerant_lines;
 698         u32 latency_hiding;
 699         fixed20_12 a;
 700
 701         a.full = dfixed_const(1);
 702         if (wm->vsc.full > a.full)
 703                 latency_tolerant_lines = 1;
 704         else {
 705                 if (lb_partitions <= (wm->vtaps + 1))
 706                         latency_tolerant_lines = 1;
 707                 else
 708                         latency_tolerant_lines = 2;
 709         }
 710
 711         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 712
 713         if (evergreen_latency_watermark(wm) <= latency_hiding)
 714                 return true;
 715         else
 716                 return false;
 717 }
 718
 719 static void evergreen_program_watermarks(struct radeon_device *rdev,
 720                                          struct radeon_crtc *radeon_crtc,
 721                                          u32 lb_size, u32 num_heads)
 722 {
 723         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 724         struct evergreen_wm_params wm;
 725         u32 pixel_period;
 726         u32 line_time = 0;
 727         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 728         u32 priority_a_mark = 0, priority_b_mark = 0;
 729         u32 priority_a_cnt = PRIORITY_OFF;
 730         u32 priority_b_cnt = PRIORITY_OFF;
 731         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 732         u32 tmp, arb_control3;
 733         fixed20_12 a, b, c;
 734
 735         if (radeon_crtc->base.enabled && num_heads && mode) {
 736                 pixel_period = 1000000 / (u32)mode->clock;
 737                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 738                 priority_a_cnt = 0;
 739                 priority_b_cnt = 0;
 740
 741                 wm.yclk = rdev->pm.current_mclk * 10;
 742                 wm.sclk = rdev->pm.current_sclk * 10;
 743                 wm.disp_clk = mode->clock;
 744                 wm.src_width = mode->crtc_hdisplay;
 745                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 746                 wm.blank_time = line_time - wm.active_time;
 747                 wm.interlaced = false;
 748                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 749                         wm.interlaced = true;
 750                 wm.vsc = radeon_crtc->vsc;
 751                 wm.vtaps = 1;
 752                 if (radeon_crtc->rmx_type != RMX_OFF)
 753                         wm.vtaps = 2;
 754                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 755                 wm.lb_size = lb_size;
 756                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 757                 wm.num_heads = num_heads;
 758
 759                 /* set for high clocks */
 760                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 761                 /* set for low clocks */
 762                 /* wm.yclk = low clk; wm.sclk = low clk */
 763                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 764
 765                 /* possibly force display priority to high */
 766                 /* should really do this at mode validation time... */
 767                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 768                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 769                     !evergreen_check_latency_hiding(&wm) ||
 770                     (rdev->disp_priority == 2)) {
 771                         DRM_DEBUG_KMS("force priority to high\n");
 772                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 773                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 774                 }
 775
 776                 a.full = dfixed_const(1000);
 777                 b.full = dfixed_const(mode->clock);
 778                 b.full = dfixed_div(b, a);
 779                 c.full = dfixed_const(latency_watermark_a);
 780                 c.full = dfixed_mul(c, b);
 781                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 782                 c.full = dfixed_div(c, a);
 783                 a.full = dfixed_const(16);
 784                 c.full = dfixed_div(c, a);
 785                 priority_a_mark = dfixed_trunc(c);
 786                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 787
 788                 a.full = dfixed_const(1000);
 789                 b.full = dfixed_const(mode->clock);
 790                 b.full = dfixed_div(b, a);
 791                 c.full = dfixed_const(latency_watermark_b);
 792                 c.full = dfixed_mul(c, b);
 793                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 794                 c.full = dfixed_div(c, a);
 795                 a.full = dfixed_const(16);
 796                 c.full = dfixed_div(c, a);
 797                 priority_b_mark = dfixed_trunc(c);
 798                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 799         }
 800
 801         /* select wm A */
 802         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 803         tmp = arb_control3;
 804         tmp &= ~LATENCY_WATERMARK_MASK(3);
 805         tmp |= LATENCY_WATERMARK_MASK(1);
 806         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 807         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 808                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 809                 LATENCY_HIGH_WATERMARK(line_time)));
 810         /* select wm B */
 811         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 812         tmp &= ~LATENCY_WATERMARK_MASK(3);
 813         tmp |= LATENCY_WATERMARK_MASK(2);
 814         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 815         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 816                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 817                 LATENCY_HIGH_WATERMARK(line_time)));
 818         /* restore original selection */
 819         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 820
 821         /* write the priority marks */
 822         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 823         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 824
 825 }
 826
 827 void evergreen_bandwidth_update(struct radeon_device *rdev)
 828 {
 829         struct drm_display_mode *mode0 = NULL;
 830         struct drm_display_mode *mode1 = NULL;
 831         u32 num_heads = 0, lb_size;
 832         int i;
 833
 834         radeon_update_display_priority(rdev);
 835
 836         for (i = 0; i < rdev->num_crtc; i++) {
 837                 if (rdev->mode_info.crtcs[i]->base.enabled)
 838                         num_heads++;
 839         }
 840         for (i = 0; i < rdev->num_crtc; i += 2) {
 841                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 842                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 843                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 844                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 845                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 846                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 847         }
 848 }
 849
 850 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 851 {
 852         unsigned i;
 853         u32 tmp;
 854
 855         for (i = 0; i < rdev->usec_timeout; i++) {
 856                 /* read MC_STATUS */
 857                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 858                 if (!tmp)
 859                         return 0;
 860                 udelay(1);
 861         }
 862         return -1;
 863 }
 864
 865 /*
 866  * GART
 867  */
 868 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 869 {
 870         unsigned i;
 871         u32 tmp;
 872
 873         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 874
 875         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 876         for (i = 0; i < rdev->usec_timeout; i++) {
 877                 /* read MC_STATUS */
 878                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 879                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 880                 if (tmp == 2) {
 881                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 882                         return;
 883                 }
 884                 if (tmp) {
 885                         return;
 886                 }
 887                 udelay(1);
 888         }
 889 }
 890
 891 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 892 {
 893         u32 tmp;
 894         int r;
 895
 896         if (rdev->gart.table.vram.robj == NULL) {
 897                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 898                 return -EINVAL;
 899         }
 900         r = radeon_gart_table_vram_pin(rdev);
 901         if (r)
 902                 return r;
 903         radeon_gart_restore(rdev);
 904         /* Setup L2 cache */
 905         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 906                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 907                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 908         WREG32(VM_L2_CNTL2, 0);
 909         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 910         /* Setup TLB control */
 911         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 912                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 913                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 914                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 915         if (rdev->flags & RADEON_IS_IGP) {
 916                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
 917                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
 918                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
 919         } else {
 920                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 921                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 922                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 923         }
 924         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 925         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 926         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 927         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 928         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 929         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 930         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 931         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 932                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 933         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 934                         (u32)(rdev->dummy_page.addr >> 12));
 935         WREG32(VM_CONTEXT1_CNTL, 0);
 936
 937         evergreen_pcie_gart_tlb_flush(rdev);
 938         rdev->gart.ready = true;
 939         return 0;
 940 }
 941
 942 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 943 {
 944         u32 tmp;
 945         int r;
 946
 947         /* Disable all tables */
 948         WREG32(VM_CONTEXT0_CNTL, 0);
 949         WREG32(VM_CONTEXT1_CNTL, 0);
 950
 951         /* Setup L2 cache */
 952         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 953                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 954         WREG32(VM_L2_CNTL2, 0);
 955         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 956         /* Setup TLB control */
 957         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 958         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 959         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 960         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 961         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 962         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 963         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 964         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 965         if (rdev->gart.table.vram.robj) {
 966                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 967                 if (likely(r == 0)) {
 968                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 969                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 970                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 971                 }
 972         }
 973 }
 974
 975 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 976 {
 977         evergreen_pcie_gart_disable(rdev);
 978         radeon_gart_table_vram_free(rdev);
 979         radeon_gart_fini(rdev);
 980 }
 981
 982
 983 void evergreen_agp_enable(struct radeon_device *rdev)
 984 {
 985         u32 tmp;
 986
 987         /* Setup L2 cache */
 988         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 989                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 990                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 991         WREG32(VM_L2_CNTL2, 0);
 992         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 993         /* Setup TLB control */
 994         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 995                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 996                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 997                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 998         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 999         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1000         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1001         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1002         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1003         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1004         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1005         WREG32(VM_CONTEXT0_CNTL, 0);
1006         WREG32(VM_CONTEXT1_CNTL, 0);
1007 }
1008
1009 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1010 {
1011         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1012         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1013         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1014         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1015         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1016         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1017         if (rdev->num_crtc >= 4) {
1018                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1019                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1020                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1021                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1022         }
1023         if (rdev->num_crtc >= 6) {
1024                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1025                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1026                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1027                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1028         }
1029
1030         /* Stop all video */
1031         WREG32(VGA_RENDER_CONTROL, 0);
1032         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1033         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1034         if (rdev->num_crtc >= 4) {
1035                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1036                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1037         }
1038         if (rdev->num_crtc >= 6) {
1039                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1040                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1041         }
1042         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1043         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1044         if (rdev->num_crtc >= 4) {
1045                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1046                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1047         }
1048         if (rdev->num_crtc >= 6) {
1049                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1050                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1051         }
1052         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1053         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1054         if (rdev->num_crtc >= 4) {
1055                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1056                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1057         }
1058         if (rdev->num_crtc >= 6) {
1059                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1060                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1061         }
1062
1063         WREG32(D1VGA_CONTROL, 0);
1064         WREG32(D2VGA_CONTROL, 0);
1065         if (rdev->num_crtc >= 4) {
1066                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1067                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1068         }
1069         if (rdev->num_crtc >= 6) {
1070                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1071                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1072         }
1073 }
1074
1075 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1076 {
1077         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1078                upper_32_bits(rdev->mc.vram_start));
1079         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1080                upper_32_bits(rdev->mc.vram_start));
1081         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1082                (u32)rdev->mc.vram_start);
1083         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1084                (u32)rdev->mc.vram_start);
1085
1086         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1087                upper_32_bits(rdev->mc.vram_start));
1088         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1089                upper_32_bits(rdev->mc.vram_start));
1090         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1091                (u32)rdev->mc.vram_start);
1092         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1093                (u32)rdev->mc.vram_start);
1094
1095         if (rdev->num_crtc >= 4) {
1096                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1097                        upper_32_bits(rdev->mc.vram_start));
1098                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1099                        upper_32_bits(rdev->mc.vram_start));
1100                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1101                        (u32)rdev->mc.vram_start);
1102                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1103                        (u32)rdev->mc.vram_start);
1104
1105                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1106                        upper_32_bits(rdev->mc.vram_start));
1107                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1108                        upper_32_bits(rdev->mc.vram_start));
1109                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1110                        (u32)rdev->mc.vram_start);
1111                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1112                        (u32)rdev->mc.vram_start);
1113         }
1114         if (rdev->num_crtc >= 6) {
1115                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1116                        upper_32_bits(rdev->mc.vram_start));
1117                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1118                        upper_32_bits(rdev->mc.vram_start));
1119                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1120                        (u32)rdev->mc.vram_start);
1121                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1122                        (u32)rdev->mc.vram_start);
1123
1124                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1125                        upper_32_bits(rdev->mc.vram_start));
1126                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1127                        upper_32_bits(rdev->mc.vram_start));
1128                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1129                        (u32)rdev->mc.vram_start);
1130                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1131                        (u32)rdev->mc.vram_start);
1132         }
1133
1134         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1135         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1136         /* Unlock host access */
1137         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1138         mdelay(1);
1139         /* Restore video state */
1140         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1141         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1142         if (rdev->num_crtc >= 4) {
1143                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1144                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1145         }
1146         if (rdev->num_crtc >= 6) {
1147                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1148                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1149         }
1150         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1151         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1152         if (rdev->num_crtc >= 4) {
1153                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1154                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1155         }
1156         if (rdev->num_crtc >= 6) {
1157                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1158                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1159         }
1160         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1161         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1162         if (rdev->num_crtc >= 4) {
1163                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1164                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1165         }
1166         if (rdev->num_crtc >= 6) {
1167                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1168                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1169         }
1170         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1171         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1172         if (rdev->num_crtc >= 4) {
1173                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1174                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1175         }
1176         if (rdev->num_crtc >= 6) {
1177                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1178                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1179         }
1180         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1181 }
1182
1183 void evergreen_mc_program(struct radeon_device *rdev)
1184 {
1185         struct evergreen_mc_save save;
1186         u32 tmp;
1187         int i, j;
1188
1189         /* Initialize HDP */
1190         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1191                 WREG32((0x2c14 + j), 0x00000000);
1192                 WREG32((0x2c18 + j), 0x00000000);
1193                 WREG32((0x2c1c + j), 0x00000000);
1194                 WREG32((0x2c20 + j), 0x00000000);
1195                 WREG32((0x2c24 + j), 0x00000000);
1196         }
1197         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1198
1199         evergreen_mc_stop(rdev, &save);
1200         if (evergreen_mc_wait_for_idle(rdev)) {
1201                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1202         }
1203         /* Lockout access through VGA aperture*/
1204         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1205         /* Update configuration */
1206         if (rdev->flags & RADEON_IS_AGP) {
1207                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1208                         /* VRAM before AGP */
1209                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1210                                 rdev->mc.vram_start >> 12);
1211                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1212                                 rdev->mc.gtt_end >> 12);
1213                 } else {
1214                         /* VRAM after AGP */
1215                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1216                                 rdev->mc.gtt_start >> 12);
1217                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1218                                 rdev->mc.vram_end >> 12);
1219                 }
1220         } else {
1221                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1222                         rdev->mc.vram_start >> 12);
1223                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1224                         rdev->mc.vram_end >> 12);
1225         }
1226         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1227         if (rdev->flags & RADEON_IS_IGP) {
1228                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1229                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1230                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1231                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1232         }
1233         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1234         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1235         WREG32(MC_VM_FB_LOCATION, tmp);
1236         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1237         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1238         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1239         if (rdev->flags & RADEON_IS_AGP) {
1240                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1241                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1242                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1243         } else {
1244                 WREG32(MC_VM_AGP_BASE, 0);
1245                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1246                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1247         }
1248         if (evergreen_mc_wait_for_idle(rdev)) {
1249                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1250         }
1251         evergreen_mc_resume(rdev, &save);
1252         /* we need to own VRAM, so turn off the VGA renderer here
1253          * to stop it overwriting our objects */
1254         rv515_vga_render_disable(rdev);
1255 }
1256
1257 /*
1258  * CP.
1259  */
1260 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1261 {
1262         /* set to DX10/11 mode */
1263         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1264         radeon_ring_write(rdev, 1);
1265         /* FIXME: implement */
1266         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1267         radeon_ring_write(rdev,
1268 #ifdef __BIG_ENDIAN
1269                           (2 << 0) |
1270 #endif
1271                           (ib->gpu_addr & 0xFFFFFFFC));
1272         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1273         radeon_ring_write(rdev, ib->length_dw);
1274 }
1275
1276
1277 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1278 {
1279         const __be32 *fw_data;
1280         int i;
1281
1282         if (!rdev->me_fw || !rdev->pfp_fw)
1283                 return -EINVAL;
1284
1285         r700_cp_stop(rdev);
1286         WREG32(CP_RB_CNTL,
1287 #ifdef __BIG_ENDIAN
1288                BUF_SWAP_32BIT |
1289 #endif
1290                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1291
1292         fw_data = (const __be32 *)rdev->pfp_fw->data;
1293         WREG32(CP_PFP_UCODE_ADDR, 0);
1294         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1295                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1296         WREG32(CP_PFP_UCODE_ADDR, 0);
1297
1298         fw_data = (const __be32 *)rdev->me_fw->data;
1299         WREG32(CP_ME_RAM_WADDR, 0);
1300         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1301                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1302
1303         WREG32(CP_PFP_UCODE_ADDR, 0);
1304         WREG32(CP_ME_RAM_WADDR, 0);
1305         WREG32(CP_ME_RAM_RADDR, 0);
1306         return 0;
1307 }
1308
1309 static int evergreen_cp_start(struct radeon_device *rdev)
1310 {
1311         int r, i;
1312         uint32_t cp_me;
1313
1314         r = radeon_ring_lock(rdev, 7);
1315         if (r) {
1316                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1317                 return r;
1318         }
1319         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1320         radeon_ring_write(rdev, 0x1);
1321         radeon_ring_write(rdev, 0x0);
1322         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1323         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1324         radeon_ring_write(rdev, 0);
1325         radeon_ring_write(rdev, 0);
1326         radeon_ring_unlock_commit(rdev);
1327
1328         cp_me = 0xff;
1329         WREG32(CP_ME_CNTL, cp_me);
1330
1331         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1332         if (r) {
1333                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1334                 return r;
1335         }
1336
1337         /* setup clear context state */
1338         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1339         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1340
1341         for (i = 0; i < evergreen_default_size; i++)
1342                 radeon_ring_write(rdev, evergreen_default_state[i]);
1343
1344         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1345         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1346
1347         /* set clear context state */
1348         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1349         radeon_ring_write(rdev, 0);
1350
1351         /* SQ_VTX_BASE_VTX_LOC */
1352         radeon_ring_write(rdev, 0xc0026f00);
1353         radeon_ring_write(rdev, 0x00000000);
1354         radeon_ring_write(rdev, 0x00000000);
1355         radeon_ring_write(rdev, 0x00000000);
1356
1357         /* Clear consts */
1358         radeon_ring_write(rdev, 0xc0036f00);
1359         radeon_ring_write(rdev, 0x00000bc4);
1360         radeon_ring_write(rdev, 0xffffffff);
1361         radeon_ring_write(rdev, 0xffffffff);
1362         radeon_ring_write(rdev, 0xffffffff);
1363
1364         radeon_ring_write(rdev, 0xc0026900);
1365         radeon_ring_write(rdev, 0x00000316);
1366         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1367         radeon_ring_write(rdev, 0x00000010); /*  */
1368
1369         radeon_ring_unlock_commit(rdev);
1370
1371         return 0;
1372 }
1373
1374 int evergreen_cp_resume(struct radeon_device *rdev)
1375 {
1376         u32 tmp;
1377         u32 rb_bufsz;
1378         int r;
1379
1380         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1381         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1382                                  SOFT_RESET_PA |
1383                                  SOFT_RESET_SH |
1384                                  SOFT_RESET_VGT |
1385                                  SOFT_RESET_SPI |
1386                                  SOFT_RESET_SX));
1387         RREG32(GRBM_SOFT_RESET);
1388         mdelay(15);
1389         WREG32(GRBM_SOFT_RESET, 0);
1390         RREG32(GRBM_SOFT_RESET);
1391
1392         /* Set ring buffer size */
1393         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1394         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1395 #ifdef __BIG_ENDIAN
1396         tmp |= BUF_SWAP_32BIT;
1397 #endif
1398         WREG32(CP_RB_CNTL, tmp);
1399         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1400
1401         /* Set the write pointer delay */
1402         WREG32(CP_RB_WPTR_DELAY, 0);
1403
1404         /* Initialize the ring buffer's read and write pointers */
1405         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1406         WREG32(CP_RB_RPTR_WR, 0);
1407         rdev->cp.wptr = 0;
1408         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1409
1410         /* set the wb address wether it's enabled or not */
1411         WREG32(CP_RB_RPTR_ADDR,
1412                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1413         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1414         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1415
1416         if (rdev->wb.enabled)
1417                 WREG32(SCRATCH_UMSK, 0xff);
1418         else {
1419                 tmp |= RB_NO_UPDATE;
1420                 WREG32(SCRATCH_UMSK, 0);
1421         }
1422
1423         mdelay(1);
1424         WREG32(CP_RB_CNTL, tmp);
1425
1426         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1427         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1428
1429         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1430
1431         evergreen_cp_start(rdev);
1432         rdev->cp.ready = true;
1433         r = radeon_ring_test(rdev);
1434         if (r) {
1435                 rdev->cp.ready = false;
1436                 return r;
1437         }
1438         return 0;
1439 }
1440
1441 /*
1442  * Core functions
1443  */
1444 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1445                                                   u32 num_tile_pipes,
1446                                                   u32 num_backends,
1447                                                   u32 backend_disable_mask)
1448 {
1449         u32 backend_map = 0;
1450         u32 enabled_backends_mask = 0;
1451         u32 enabled_backends_count = 0;
1452         u32 cur_pipe;
1453         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1454         u32 cur_backend = 0;
1455         u32 i;
1456         bool force_no_swizzle;
1457
1458         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1459                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1460         if (num_tile_pipes < 1)
1461                 num_tile_pipes = 1;
1462         if (num_backends > EVERGREEN_MAX_BACKENDS)
1463                 num_backends = EVERGREEN_MAX_BACKENDS;
1464         if (num_backends < 1)
1465                 num_backends = 1;
1466
1467         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1468                 if (((backend_disable_mask >> i) & 1) == 0) {
1469                         enabled_backends_mask |= (1 << i);
1470                         ++enabled_backends_count;
1471                 }
1472                 if (enabled_backends_count == num_backends)
1473                         break;
1474         }
1475
1476         if (enabled_backends_count == 0) {
1477                 enabled_backends_mask = 1;
1478                 enabled_backends_count = 1;
1479         }
1480
1481         if (enabled_backends_count != num_backends)
1482                 num_backends = enabled_backends_count;
1483
1484         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1485         switch (rdev->family) {
1486         case CHIP_CEDAR:
1487         case CHIP_REDWOOD:
1488         case CHIP_PALM:
1489         case CHIP_SUMO:
1490         case CHIP_SUMO2:
1491         case CHIP_TURKS:
1492         case CHIP_CAICOS:
1493                 force_no_swizzle = false;
1494                 break;
1495         case CHIP_CYPRESS:
1496         case CHIP_HEMLOCK:
1497         case CHIP_JUNIPER:
1498         case CHIP_BARTS:
1499         default:
1500                 force_no_swizzle = true;
1501                 break;
1502         }
1503         if (force_no_swizzle) {
1504                 bool last_backend_enabled = false;
1505
1506                 force_no_swizzle = false;
1507                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1508                         if (((enabled_backends_mask >> i) & 1) == 1) {
1509                                 if (last_backend_enabled)
1510                                         force_no_swizzle = true;
1511                                 last_backend_enabled = true;
1512                         } else
1513                                 last_backend_enabled = false;
1514                 }
1515         }
1516
1517         switch (num_tile_pipes) {
1518         case 1:
1519         case 3:
1520         case 5:
1521         case 7:
1522                 DRM_ERROR("odd number of pipes!\n");
1523                 break;
1524         case 2:
1525                 swizzle_pipe[0] = 0;
1526                 swizzle_pipe[1] = 1;
1527                 break;
1528         case 4:
1529                 if (force_no_swizzle) {
1530                         swizzle_pipe[0] = 0;
1531                         swizzle_pipe[1] = 1;
1532                         swizzle_pipe[2] = 2;
1533                         swizzle_pipe[3] = 3;
1534                 } else {
1535                         swizzle_pipe[0] = 0;
1536                         swizzle_pipe[1] = 2;
1537                         swizzle_pipe[2] = 1;
1538                         swizzle_pipe[3] = 3;
1539                 }
1540                 break;
1541         case 6:
1542                 if (force_no_swizzle) {
1543                         swizzle_pipe[0] = 0;
1544                         swizzle_pipe[1] = 1;
1545                         swizzle_pipe[2] = 2;
1546                         swizzle_pipe[3] = 3;
1547                         swizzle_pipe[4] = 4;
1548                         swizzle_pipe[5] = 5;
1549                 } else {
1550                         swizzle_pipe[0] = 0;
1551                         swizzle_pipe[1] = 2;
1552                         swizzle_pipe[2] = 4;
1553                         swizzle_pipe[3] = 1;
1554                         swizzle_pipe[4] = 3;
1555                         swizzle_pipe[5] = 5;
1556                 }
1557                 break;
1558         case 8:
1559                 if (force_no_swizzle) {
1560                         swizzle_pipe[0] = 0;
1561                         swizzle_pipe[1] = 1;
1562                         swizzle_pipe[2] = 2;
1563                         swizzle_pipe[3] = 3;
1564                         swizzle_pipe[4] = 4;
1565                         swizzle_pipe[5] = 5;
1566                         swizzle_pipe[6] = 6;
1567                         swizzle_pipe[7] = 7;
1568                 } else {
1569                         swizzle_pipe[0] = 0;
1570                         swizzle_pipe[1] = 2;
1571                         swizzle_pipe[2] = 4;
1572                         swizzle_pipe[3] = 6;
1573                         swizzle_pipe[4] = 1;
1574                         swizzle_pipe[5] = 3;
1575                         swizzle_pipe[6] = 5;
1576                         swizzle_pipe[7] = 7;
1577                 }
1578                 break;
1579         }
1580
1581         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1582                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1583                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1584
1585                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1586
1587                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1588         }
1589
1590         return backend_map;
1591 }
1592
1593 static void evergreen_gpu_init(struct radeon_device *rdev)
1594 {
1595         u32 cc_rb_backend_disable = 0;
1596         u32 cc_gc_shader_pipe_config;
1597         u32 gb_addr_config = 0;
1598         u32 mc_shared_chmap, mc_arb_ramcfg;
1599         u32 gb_backend_map;
1600         u32 grbm_gfx_index;
1601         u32 sx_debug_1;
1602         u32 smx_dc_ctl0;
1603         u32 sq_config;
1604         u32 sq_lds_resource_mgmt;
1605         u32 sq_gpr_resource_mgmt_1;
1606         u32 sq_gpr_resource_mgmt_2;
1607         u32 sq_gpr_resource_mgmt_3;
1608         u32 sq_thread_resource_mgmt;
1609         u32 sq_thread_resource_mgmt_2;
1610         u32 sq_stack_resource_mgmt_1;
1611         u32 sq_stack_resource_mgmt_2;
1612         u32 sq_stack_resource_mgmt_3;
1613         u32 vgt_cache_invalidation;
1614         u32 hdp_host_path_cntl, tmp;
1615         int i, j, num_shader_engines, ps_thread_count;
1616
1617         switch (rdev->family) {
1618         case CHIP_CYPRESS:
1619         case CHIP_HEMLOCK:
1620                 rdev->config.evergreen.num_ses = 2;
1621                 rdev->config.evergreen.max_pipes = 4;
1622                 rdev->config.evergreen.max_tile_pipes = 8;
1623                 rdev->config.evergreen.max_simds = 10;
1624                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1625                 rdev->config.evergreen.max_gprs = 256;
1626                 rdev->config.evergreen.max_threads = 248;
1627                 rdev->config.evergreen.max_gs_threads = 32;
1628                 rdev->config.evergreen.max_stack_entries = 512;
1629                 rdev->config.evergreen.sx_num_of_sets = 4;
1630                 rdev->config.evergreen.sx_max_export_size = 256;
1631                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1632                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1633                 rdev->config.evergreen.max_hw_contexts = 8;
1634                 rdev->config.evergreen.sq_num_cf_insts = 2;
1635
1636                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1637                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1638                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1639                 break;
1640         case CHIP_JUNIPER:
1641                 rdev->config.evergreen.num_ses = 1;
1642                 rdev->config.evergreen.max_pipes = 4;
1643                 rdev->config.evergreen.max_tile_pipes = 4;
1644                 rdev->config.evergreen.max_simds = 10;
1645                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1646                 rdev->config.evergreen.max_gprs = 256;
1647                 rdev->config.evergreen.max_threads = 248;
1648                 rdev->config.evergreen.max_gs_threads = 32;
1649                 rdev->config.evergreen.max_stack_entries = 512;
1650                 rdev->config.evergreen.sx_num_of_sets = 4;
1651                 rdev->config.evergreen.sx_max_export_size = 256;
1652                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1653                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1654                 rdev->config.evergreen.max_hw_contexts = 8;
1655                 rdev->config.evergreen.sq_num_cf_insts = 2;
1656
1657                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1658                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1659                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1660                 break;
1661         case CHIP_REDWOOD:
1662                 rdev->config.evergreen.num_ses = 1;
1663                 rdev->config.evergreen.max_pipes = 4;
1664                 rdev->config.evergreen.max_tile_pipes = 4;
1665                 rdev->config.evergreen.max_simds = 5;
1666                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1667                 rdev->config.evergreen.max_gprs = 256;
1668                 rdev->config.evergreen.max_threads = 248;
1669                 rdev->config.evergreen.max_gs_threads = 32;
1670                 rdev->config.evergreen.max_stack_entries = 256;
1671                 rdev->config.evergreen.sx_num_of_sets = 4;
1672                 rdev->config.evergreen.sx_max_export_size = 256;
1673                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1674                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1675                 rdev->config.evergreen.max_hw_contexts = 8;
1676                 rdev->config.evergreen.sq_num_cf_insts = 2;
1677
1678                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1679                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1680                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1681                 break;
1682         case CHIP_CEDAR:
1683         default:
1684                 rdev->config.evergreen.num_ses = 1;
1685                 rdev->config.evergreen.max_pipes = 2;
1686                 rdev->config.evergreen.max_tile_pipes = 2;
1687                 rdev->config.evergreen.max_simds = 2;
1688                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1689                 rdev->config.evergreen.max_gprs = 256;
1690                 rdev->config.evergreen.max_threads = 192;
1691                 rdev->config.evergreen.max_gs_threads = 16;
1692                 rdev->config.evergreen.max_stack_entries = 256;
1693                 rdev->config.evergreen.sx_num_of_sets = 4;
1694                 rdev->config.evergreen.sx_max_export_size = 128;
1695                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1696                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1697                 rdev->config.evergreen.max_hw_contexts = 4;
1698                 rdev->config.evergreen.sq_num_cf_insts = 1;
1699
1700                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1701                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1702                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1703                 break;
1704         case CHIP_PALM:
1705                 rdev->config.evergreen.num_ses = 1;
1706                 rdev->config.evergreen.max_pipes = 2;
1707                 rdev->config.evergreen.max_tile_pipes = 2;
1708                 rdev->config.evergreen.max_simds = 2;
1709                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1710                 rdev->config.evergreen.max_gprs = 256;
1711                 rdev->config.evergreen.max_threads = 192;
1712                 rdev->config.evergreen.max_gs_threads = 16;
1713                 rdev->config.evergreen.max_stack_entries = 256;
1714                 rdev->config.evergreen.sx_num_of_sets = 4;
1715                 rdev->config.evergreen.sx_max_export_size = 128;
1716                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1717                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1718                 rdev->config.evergreen.max_hw_contexts = 4;
1719                 rdev->config.evergreen.sq_num_cf_insts = 1;
1720
1721                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1722                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1723                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1724                 break;
1725         case CHIP_SUMO:
1726                 rdev->config.evergreen.num_ses = 1;
1727                 rdev->config.evergreen.max_pipes = 4;
1728                 rdev->config.evergreen.max_tile_pipes = 2;
1729                 if (rdev->pdev->device == 0x9648)
1730                         rdev->config.evergreen.max_simds = 3;
1731                 else if ((rdev->pdev->device == 0x9647) ||
1732                          (rdev->pdev->device == 0x964a))
1733                         rdev->config.evergreen.max_simds = 4;
1734                 else
1735                         rdev->config.evergreen.max_simds = 5;
1736                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1737                 rdev->config.evergreen.max_gprs = 256;
1738                 rdev->config.evergreen.max_threads = 248;
1739                 rdev->config.evergreen.max_gs_threads = 32;
1740                 rdev->config.evergreen.max_stack_entries = 256;
1741                 rdev->config.evergreen.sx_num_of_sets = 4;
1742                 rdev->config.evergreen.sx_max_export_size = 256;
1743                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1744                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1745                 rdev->config.evergreen.max_hw_contexts = 8;
1746                 rdev->config.evergreen.sq_num_cf_insts = 2;
1747
1748                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1749                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1750                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1751                 break;
1752         case CHIP_SUMO2:
1753                 rdev->config.evergreen.num_ses = 1;
1754                 rdev->config.evergreen.max_pipes = 4;
1755                 rdev->config.evergreen.max_tile_pipes = 4;
1756                 rdev->config.evergreen.max_simds = 2;
1757                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1758                 rdev->config.evergreen.max_gprs = 256;
1759                 rdev->config.evergreen.max_threads = 248;
1760                 rdev->config.evergreen.max_gs_threads = 32;
1761                 rdev->config.evergreen.max_stack_entries = 512;
1762                 rdev->config.evergreen.sx_num_of_sets = 4;
1763                 rdev->config.evergreen.sx_max_export_size = 256;
1764                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1765                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1766                 rdev->config.evergreen.max_hw_contexts = 8;
1767                 rdev->config.evergreen.sq_num_cf_insts = 2;
1768
1769                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1770                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1771                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1772                 break;
1773         case CHIP_BARTS:
1774                 rdev->config.evergreen.num_ses = 2;
1775                 rdev->config.evergreen.max_pipes = 4;
1776                 rdev->config.evergreen.max_tile_pipes = 8;
1777                 rdev->config.evergreen.max_simds = 7;
1778                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1779                 rdev->config.evergreen.max_gprs = 256;
1780                 rdev->config.evergreen.max_threads = 248;
1781                 rdev->config.evergreen.max_gs_threads = 32;
1782                 rdev->config.evergreen.max_stack_entries = 512;
1783                 rdev->config.evergreen.sx_num_of_sets = 4;
1784                 rdev->config.evergreen.sx_max_export_size = 256;
1785                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1786                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1787                 rdev->config.evergreen.max_hw_contexts = 8;
1788                 rdev->config.evergreen.sq_num_cf_insts = 2;
1789
1790                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1791                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1792                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1793                 break;
1794         case CHIP_TURKS:
1795                 rdev->config.evergreen.num_ses = 1;
1796                 rdev->config.evergreen.max_pipes = 4;
1797                 rdev->config.evergreen.max_tile_pipes = 4;
1798                 rdev->config.evergreen.max_simds = 6;
1799                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1800                 rdev->config.evergreen.max_gprs = 256;
1801                 rdev->config.evergreen.max_threads = 248;
1802                 rdev->config.evergreen.max_gs_threads = 32;
1803                 rdev->config.evergreen.max_stack_entries = 256;
1804                 rdev->config.evergreen.sx_num_of_sets = 4;
1805                 rdev->config.evergreen.sx_max_export_size = 256;
1806                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1807                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1808                 rdev->config.evergreen.max_hw_contexts = 8;
1809                 rdev->config.evergreen.sq_num_cf_insts = 2;
1810
1811                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1812                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1813                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1814                 break;
1815         case CHIP_CAICOS:
1816                 rdev->config.evergreen.num_ses = 1;
1817                 rdev->config.evergreen.max_pipes = 4;
1818                 rdev->config.evergreen.max_tile_pipes = 2;
1819                 rdev->config.evergreen.max_simds = 2;
1820                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1821                 rdev->config.evergreen.max_gprs = 256;
1822                 rdev->config.evergreen.max_threads = 192;
1823                 rdev->config.evergreen.max_gs_threads = 16;
1824                 rdev->config.evergreen.max_stack_entries = 256;
1825                 rdev->config.evergreen.sx_num_of_sets = 4;
1826                 rdev->config.evergreen.sx_max_export_size = 128;
1827                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1828                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1829                 rdev->config.evergreen.max_hw_contexts = 4;
1830                 rdev->config.evergreen.sq_num_cf_insts = 1;
1831
1832                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1833                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1834                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1835                 break;
1836         }
1837
1838         /* Initialize HDP */
1839         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1840                 WREG32((0x2c14 + j), 0x00000000);
1841                 WREG32((0x2c18 + j), 0x00000000);
1842                 WREG32((0x2c1c + j), 0x00000000);
1843                 WREG32((0x2c20 + j), 0x00000000);
1844                 WREG32((0x2c24 + j), 0x00000000);
1845         }
1846
1847         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1848
1849         evergreen_fix_pci_max_read_req_size(rdev);
1850
1851         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1852
1853         cc_gc_shader_pipe_config |=
1854                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1855                                   & EVERGREEN_MAX_PIPES_MASK);
1856         cc_gc_shader_pipe_config |=
1857                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1858                                & EVERGREEN_MAX_SIMDS_MASK);
1859
1860         cc_rb_backend_disable =
1861                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1862                                 & EVERGREEN_MAX_BACKENDS_MASK);
1863
1864
1865         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1866         if (rdev->flags & RADEON_IS_IGP)
1867                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1868         else
1869                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1870
1871         switch (rdev->config.evergreen.max_tile_pipes) {
1872         case 1:
1873         default:
1874                 gb_addr_config |= NUM_PIPES(0);
1875                 break;
1876         case 2:
1877                 gb_addr_config |= NUM_PIPES(1);
1878                 break;
1879         case 4:
1880                 gb_addr_config |= NUM_PIPES(2);
1881                 break;
1882         case 8:
1883                 gb_addr_config |= NUM_PIPES(3);
1884                 break;
1885         }
1886
1887         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1888         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1889         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1890         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1891         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1892         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1893
1894         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1895                 gb_addr_config |= ROW_SIZE(2);
1896         else
1897                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1898
1899         if (rdev->ddev->pdev->device == 0x689e) {
1900                 u32 efuse_straps_4;
1901                 u32 efuse_straps_3;
1902                 u8 efuse_box_bit_131_124;
1903
1904                 WREG32(RCU_IND_INDEX, 0x204);
1905                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1906                 WREG32(RCU_IND_INDEX, 0x203);
1907                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1908                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1909
1910                 switch(efuse_box_bit_131_124) {
1911                 case 0x00:
1912                         gb_backend_map = 0x76543210;
1913                         break;
1914                 case 0x55:
1915                         gb_backend_map = 0x77553311;
1916                         break;
1917                 case 0x56:
1918                         gb_backend_map = 0x77553300;
1919                         break;
1920                 case 0x59:
1921                         gb_backend_map = 0x77552211;
1922                         break;
1923                 case 0x66:
1924                         gb_backend_map = 0x77443300;
1925                         break;
1926                 case 0x99:
1927                         gb_backend_map = 0x66552211;
1928                         break;
1929                 case 0x5a:
1930                         gb_backend_map = 0x77552200;
1931                         break;
1932                 case 0xaa:
1933                         gb_backend_map = 0x66442200;
1934                         break;
1935                 case 0x95:
1936                         gb_backend_map = 0x66553311;
1937                         break;
1938                 default:
1939                         DRM_ERROR("bad backend map, using default\n");
1940                         gb_backend_map =
1941                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1942                                                                        rdev->config.evergreen.max_tile_pipes,
1943                                                                        rdev->config.evergreen.max_backends,
1944                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1945                                                                    rdev->config.evergreen.max_backends) &
1946                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1947                         break;
1948                 }
1949         } else if (rdev->ddev->pdev->device == 0x68b9) {
1950                 u32 efuse_straps_3;
1951                 u8 efuse_box_bit_127_124;
1952
1953                 WREG32(RCU_IND_INDEX, 0x203);
1954                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1955                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1956
1957                 switch(efuse_box_bit_127_124) {
1958                 case 0x0:
1959                         gb_backend_map = 0x00003210;
1960                         break;
1961                 case 0x5:
1962                 case 0x6:
1963                 case 0x9:
1964                 case 0xa:
1965                         gb_backend_map = 0x00003311;
1966                         break;
1967                 default:
1968                         DRM_ERROR("bad backend map, using default\n");
1969                         gb_backend_map =
1970                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1971                                                                        rdev->config.evergreen.max_tile_pipes,
1972                                                                        rdev->config.evergreen.max_backends,
1973                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1974                                                                    rdev->config.evergreen.max_backends) &
1975                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1976                         break;
1977                 }
1978         } else {
1979                 switch (rdev->family) {
1980                 case CHIP_CYPRESS:
1981                 case CHIP_HEMLOCK:
1982                 case CHIP_BARTS:
1983                         gb_backend_map = 0x66442200;
1984                         break;
1985                 case CHIP_JUNIPER:
1986                         gb_backend_map = 0x00002200;
1987                         break;
1988                 default:
1989                         gb_backend_map =
1990                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1991                                                                        rdev->config.evergreen.max_tile_pipes,
1992                                                                        rdev->config.evergreen.max_backends,
1993                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1994                                                                          rdev->config.evergreen.max_backends) &
1995                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1996                 }
1997         }
1998
1999         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2000          * not have bank info, so create a custom tiling dword.
2001          * bits 3:0   num_pipes
2002          * bits 7:4   num_banks
2003          * bits 11:8  group_size
2004          * bits 15:12 row_size
2005          */
2006         rdev->config.evergreen.tile_config = 0;
2007         switch (rdev->config.evergreen.max_tile_pipes) {
2008         case 1:
2009         default:
2010                 rdev->config.evergreen.tile_config |= (0 << 0);
2011                 break;
2012         case 2:
2013                 rdev->config.evergreen.tile_config |= (1 << 0);
2014                 break;
2015         case 4:
2016                 rdev->config.evergreen.tile_config |= (2 << 0);
2017                 break;
2018         case 8:
2019                 rdev->config.evergreen.tile_config |= (3 << 0);
2020                 break;
2021         }
2022         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2023         if (rdev->flags & RADEON_IS_IGP)
2024                 rdev->config.evergreen.tile_config |= 1 << 4;
2025         else
2026                 rdev->config.evergreen.tile_config |=
2027                         ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2028         rdev->config.evergreen.tile_config |=
2029                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2030         rdev->config.evergreen.tile_config |=
2031                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2032
2033         rdev->config.evergreen.backend_map = gb_backend_map;
2034         WREG32(GB_BACKEND_MAP, gb_backend_map);
2035         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2036         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2037         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2038
2039         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2040         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2041
2042         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2043                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2044                 u32 sp = cc_gc_shader_pipe_config;
2045                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2046
2047                 if (i == num_shader_engines) {
2048                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2049                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2050                 }
2051
2052                 WREG32(GRBM_GFX_INDEX, gfx);
2053                 WREG32(RLC_GFX_INDEX, gfx);
2054
2055                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2056                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2057                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2058                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2059         }
2060
2061         grbm_gfx_index |= SE_BROADCAST_WRITES;
2062         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2063         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2064
2065         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2066         WREG32(CGTS_TCC_DISABLE, 0);
2067         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2068         WREG32(CGTS_USER_TCC_DISABLE, 0);
2069
2070         /* set HW defaults for 3D engine */
2071         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2072                                      ROQ_IB2_START(0x2b)));
2073
2074         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2075
2076         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2077                              SYNC_GRADIENT |
2078                              SYNC_WALKER |
2079                              SYNC_ALIGNER));
2080
2081         sx_debug_1 = RREG32(SX_DEBUG_1);
2082         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2083         WREG32(SX_DEBUG_1, sx_debug_1);
2084
2085
2086         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2087         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2088         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2089         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2090
2091         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2092                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2093                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2094
2095         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2096                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2097                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2098
2099         WREG32(VGT_NUM_INSTANCES, 1);
2100         WREG32(SPI_CONFIG_CNTL, 0);
2101         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2102         WREG32(CP_PERFMON_CNTL, 0);
2103
2104         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2105                                   FETCH_FIFO_HIWATER(0x4) |
2106                                   DONE_FIFO_HIWATER(0xe0) |
2107                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2108
2109         sq_config = RREG32(SQ_CONFIG);
2110         sq_config &= ~(PS_PRIO(3) |
2111                        VS_PRIO(3) |
2112                        GS_PRIO(3) |
2113                        ES_PRIO(3));
2114         sq_config |= (VC_ENABLE |
2115                       EXPORT_SRC_C |
2116                       PS_PRIO(0) |
2117                       VS_PRIO(1) |
2118                       GS_PRIO(2) |
2119                       ES_PRIO(3));
2120
2121         switch (rdev->family) {
2122         case CHIP_CEDAR:
2123         case CHIP_PALM:
2124         case CHIP_SUMO:
2125         case CHIP_SUMO2:
2126         case CHIP_CAICOS:
2127                 /* no vertex cache */
2128                 sq_config &= ~VC_ENABLE;
2129                 break;
2130         default:
2131                 break;
2132         }
2133
2134         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2135
2136         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2137         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2138         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2139         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2140         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2141         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2142         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2143
2144         switch (rdev->family) {
2145         case CHIP_CEDAR:
2146         case CHIP_PALM:
2147         case CHIP_SUMO:
2148         case CHIP_SUMO2:
2149                 ps_thread_count = 96;
2150                 break;
2151         default:
2152                 ps_thread_count = 128;
2153                 break;
2154         }
2155
2156         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2157         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2158         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2159         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2160         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2161         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162
2163         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2164         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2165         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2166         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2167         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169
2170         WREG32(SQ_CONFIG, sq_config);
2171         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2172         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2173         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2174         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2175         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2176         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2177         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2178         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2179         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2180         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2181
2182         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2183                                           FORCE_EOV_MAX_REZ_CNT(255)));
2184
2185         switch (rdev->family) {
2186         case CHIP_CEDAR:
2187         case CHIP_PALM:
2188         case CHIP_SUMO:
2189         case CHIP_SUMO2:
2190         case CHIP_CAICOS:
2191                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2192                 break;
2193         default:
2194                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2195                 break;
2196         }
2197         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2198         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2199
2200         WREG32(VGT_GS_VERTEX_REUSE, 16);
2201         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2202         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2203
2204         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2205         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2206
2207         WREG32(CB_PERF_CTR0_SEL_0, 0);
2208         WREG32(CB_PERF_CTR0_SEL_1, 0);
2209         WREG32(CB_PERF_CTR1_SEL_0, 0);
2210         WREG32(CB_PERF_CTR1_SEL_1, 0);
2211         WREG32(CB_PERF_CTR2_SEL_0, 0);
2212         WREG32(CB_PERF_CTR2_SEL_1, 0);
2213         WREG32(CB_PERF_CTR3_SEL_0, 0);
2214         WREG32(CB_PERF_CTR3_SEL_1, 0);
2215
2216         /* clear render buffer base addresses */
2217         WREG32(CB_COLOR0_BASE, 0);
2218         WREG32(CB_COLOR1_BASE, 0);
2219         WREG32(CB_COLOR2_BASE, 0);
2220         WREG32(CB_COLOR3_BASE, 0);
2221         WREG32(CB_COLOR4_BASE, 0);
2222         WREG32(CB_COLOR5_BASE, 0);
2223         WREG32(CB_COLOR6_BASE, 0);
2224         WREG32(CB_COLOR7_BASE, 0);
2225         WREG32(CB_COLOR8_BASE, 0);
2226         WREG32(CB_COLOR9_BASE, 0);
2227         WREG32(CB_COLOR10_BASE, 0);
2228         WREG32(CB_COLOR11_BASE, 0);
2229
2230         /* set the shader const cache sizes to 0 */
2231         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2232                 WREG32(i, 0);
2233         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2234                 WREG32(i, 0);
2235
2236         tmp = RREG32(HDP_MISC_CNTL);
2237         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2238         WREG32(HDP_MISC_CNTL, tmp);
2239
2240         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2241         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2242
2243         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2244
2245         udelay(50);
2246
2247 }
2248
2249 int evergreen_mc_init(struct radeon_device *rdev)
2250 {
2251         u32 tmp;
2252         int chansize, numchan;
2253
2254         /* Get VRAM informations */
2255         rdev->mc.vram_is_ddr = true;
2256         if (rdev->flags & RADEON_IS_IGP)
2257                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2258         else
2259                 tmp = RREG32(MC_ARB_RAMCFG);
2260         if (tmp & CHANSIZE_OVERRIDE) {
2261                 chansize = 16;
2262         } else if (tmp & CHANSIZE_MASK) {
2263                 chansize = 64;
2264         } else {
2265                 chansize = 32;
2266         }
2267         tmp = RREG32(MC_SHARED_CHMAP);
2268         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2269         case 0:
2270         default:
2271                 numchan = 1;
2272                 break;
2273         case 1:
2274                 numchan = 2;
2275                 break;
2276         case 2:
2277                 numchan = 4;
2278                 break;
2279         case 3:
2280                 numchan = 8;
2281                 break;
2282         }
2283         rdev->mc.vram_width = numchan * chansize;
2284         /* Could aper size report 0 ? */
2285         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2286         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2287         /* Setup GPU memory space */
2288         if (rdev->flags & RADEON_IS_IGP) {
2289                 /* size in bytes on fusion */
2290                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2291                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2292         } else {
2293                 /* size in MB on evergreen */
2294                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2295                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2296         }
2297         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2298         r700_vram_gtt_location(rdev, &rdev->mc);
2299         radeon_update_bandwidth_info(rdev);
2300
2301         return 0;
2302 }
2303
2304 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2305 {
2306         u32 srbm_status;
2307         u32 grbm_status;
2308         u32 grbm_status_se0, grbm_status_se1;
2309         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2310         int r;
2311
2312         srbm_status = RREG32(SRBM_STATUS);
2313         grbm_status = RREG32(GRBM_STATUS);
2314         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2315         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2316         if (!(grbm_status & GUI_ACTIVE)) {
2317                 r100_gpu_lockup_update(lockup, &rdev->cp);
2318                 return false;
2319         }
2320         /* force CP activities */
2321         r = radeon_ring_lock(rdev, 2);
2322         if (!r) {
2323                 /* PACKET2 NOP */
2324                 radeon_ring_write(rdev, 0x80000000);
2325                 radeon_ring_write(rdev, 0x80000000);
2326                 radeon_ring_unlock_commit(rdev);
2327         }
2328         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2329         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2330 }
2331
2332 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2333 {
2334         struct evergreen_mc_save save;
2335         u32 grbm_reset = 0;
2336
2337         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2338                 return 0;
2339
2340         dev_info(rdev->dev, "GPU softreset \n");
2341         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2342                 RREG32(GRBM_STATUS));
2343         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2344                 RREG32(GRBM_STATUS_SE0));
2345         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2346                 RREG32(GRBM_STATUS_SE1));
2347         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2348                 RREG32(SRBM_STATUS));
2349         evergreen_mc_stop(rdev, &save);
2350         if (evergreen_mc_wait_for_idle(rdev)) {
2351                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2352         }
2353         /* Disable CP parsing/prefetching */
2354         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2355
2356         /* reset all the gfx blocks */
2357         grbm_reset = (SOFT_RESET_CP |
2358                       SOFT_RESET_CB |
2359                       SOFT_RESET_DB |
2360                       SOFT_RESET_PA |
2361                       SOFT_RESET_SC |
2362                       SOFT_RESET_SPI |
2363                       SOFT_RESET_SH |
2364                       SOFT_RESET_SX |
2365                       SOFT_RESET_TC |
2366                       SOFT_RESET_TA |
2367                       SOFT_RESET_VC |
2368                       SOFT_RESET_VGT);
2369
2370         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2371         WREG32(GRBM_SOFT_RESET, grbm_reset);
2372         (void)RREG32(GRBM_SOFT_RESET);
2373         udelay(50);
2374         WREG32(GRBM_SOFT_RESET, 0);
2375         (void)RREG32(GRBM_SOFT_RESET);
2376         /* Wait a little for things to settle down */
2377         udelay(50);
2378         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2379                 RREG32(GRBM_STATUS));
2380         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2381                 RREG32(GRBM_STATUS_SE0));
2382         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2383                 RREG32(GRBM_STATUS_SE1));
2384         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2385                 RREG32(SRBM_STATUS));
2386         evergreen_mc_resume(rdev, &save);
2387         return 0;
2388 }
2389
2390 int evergreen_asic_reset(struct radeon_device *rdev)
2391 {
2392         return evergreen_gpu_soft_reset(rdev);
2393 }
2394
2395 /* Interrupts */
2396
2397 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2398 {
2399         switch (crtc) {
2400         case 0:
2401                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2402         case 1:
2403                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2404         case 2:
2405                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2406         case 3:
2407                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2408         case 4:
2409                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2410         case 5:
2411                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2412         default:
2413                 return 0;
2414         }
2415 }
2416
2417 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2418 {
2419         u32 tmp;
2420
2421         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2422         WREG32(GRBM_INT_CNTL, 0);
2423         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2424         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2425         if (rdev->num_crtc >= 4) {
2426                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2427                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2428         }
2429         if (rdev->num_crtc >= 6) {
2430                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2431                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2432         }
2433
2434         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2435         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2436         if (rdev->num_crtc >= 4) {
2437                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2438                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2439         }
2440         if (rdev->num_crtc >= 6) {
2441                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2442                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2443         }
2444
2445         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2446         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2447
2448         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2449         WREG32(DC_HPD1_INT_CONTROL, tmp);
2450         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2451         WREG32(DC_HPD2_INT_CONTROL, tmp);
2452         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2453         WREG32(DC_HPD3_INT_CONTROL, tmp);
2454         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2455         WREG32(DC_HPD4_INT_CONTROL, tmp);
2456         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2457         WREG32(DC_HPD5_INT_CONTROL, tmp);
2458         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2459         WREG32(DC_HPD6_INT_CONTROL, tmp);
2460
2461 }
2462
2463 int evergreen_irq_set(struct radeon_device *rdev)
2464 {
2465         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2466         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2467         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2468         u32 grbm_int_cntl = 0;
2469         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2470
2471         if (!rdev->irq.installed) {
2472                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2473                 return -EINVAL;
2474         }
2475         /* don't enable anything if the ih is disabled */
2476         if (!rdev->ih.enabled) {
2477                 r600_disable_interrupts(rdev);
2478                 /* force the active interrupt state to all disabled */
2479                 evergreen_disable_interrupt_state(rdev);
2480                 return 0;
2481         }
2482
2483         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2484         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2485         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2486         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2487         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2488         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2489
2490         if (rdev->irq.sw_int) {
2491                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2492                 cp_int_cntl |= RB_INT_ENABLE;
2493                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2494         }
2495         if (rdev->irq.crtc_vblank_int[0] ||
2496             rdev->irq.pflip[0]) {
2497                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2498                 crtc1 |= VBLANK_INT_MASK;
2499         }
2500         if (rdev->irq.crtc_vblank_int[1] ||
2501             rdev->irq.pflip[1]) {
2502                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2503                 crtc2 |= VBLANK_INT_MASK;
2504         }
2505         if (rdev->irq.crtc_vblank_int[2] ||
2506             rdev->irq.pflip[2]) {
2507                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2508                 crtc3 |= VBLANK_INT_MASK;
2509         }
2510         if (rdev->irq.crtc_vblank_int[3] ||
2511             rdev->irq.pflip[3]) {
2512                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2513                 crtc4 |= VBLANK_INT_MASK;
2514         }
2515         if (rdev->irq.crtc_vblank_int[4] ||
2516             rdev->irq.pflip[4]) {
2517                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2518                 crtc5 |= VBLANK_INT_MASK;
2519         }
2520         if (rdev->irq.crtc_vblank_int[5] ||
2521             rdev->irq.pflip[5]) {
2522                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2523                 crtc6 |= VBLANK_INT_MASK;
2524         }
2525         if (rdev->irq.hpd[0]) {
2526                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2527                 hpd1 |= DC_HPDx_INT_EN;
2528         }
2529         if (rdev->irq.hpd[1]) {
2530                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2531                 hpd2 |= DC_HPDx_INT_EN;
2532         }
2533         if (rdev->irq.hpd[2]) {
2534                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2535                 hpd3 |= DC_HPDx_INT_EN;
2536         }
2537         if (rdev->irq.hpd[3]) {
2538                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2539                 hpd4 |= DC_HPDx_INT_EN;
2540         }
2541         if (rdev->irq.hpd[4]) {
2542                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2543                 hpd5 |= DC_HPDx_INT_EN;
2544         }
2545         if (rdev->irq.hpd[5]) {
2546                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2547                 hpd6 |= DC_HPDx_INT_EN;
2548         }
2549         if (rdev->irq.gui_idle) {
2550                 DRM_DEBUG("gui idle\n");
2551                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2552         }
2553
2554         WREG32(CP_INT_CNTL, cp_int_cntl);
2555         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2556
2557         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2558         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2559         if (rdev->num_crtc >= 4) {
2560                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2561                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2562         }
2563         if (rdev->num_crtc >= 6) {
2564                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2565                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2566         }
2567
2568         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2569         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2570         if (rdev->num_crtc >= 4) {
2571                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2572                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2573         }
2574         if (rdev->num_crtc >= 6) {
2575                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2576                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2577         }
2578
2579         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2580         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2581         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2582         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2583         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2584         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2585
2586         return 0;
2587 }
2588
2589 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2590 {
2591         u32 tmp;
2592
2593         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2594         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2595         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2596         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2597         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2598         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2599         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2600         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2601         if (rdev->num_crtc >= 4) {
2602                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2603                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2604         }
2605         if (rdev->num_crtc >= 6) {
2606                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2607                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2608         }
2609
2610         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2611                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2612         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2613                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2614         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2615                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2616         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2617                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2618         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2619                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2620         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2621                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2622
2623         if (rdev->num_crtc >= 4) {
2624                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2625                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2626                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2627                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2628                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2629                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2630                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2631                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2632                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2633                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2634                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2635                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2636         }
2637
2638         if (rdev->num_crtc >= 6) {
2639                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2640                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2641                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2642                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2643                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2644                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2645                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2646                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2647                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2648                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2649                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2650                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2651         }
2652
2653         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2654                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2655                 tmp |= DC_HPDx_INT_ACK;
2656                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2657         }
2658         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2659                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2660                 tmp |= DC_HPDx_INT_ACK;
2661                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2662         }
2663         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2664                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2665                 tmp |= DC_HPDx_INT_ACK;
2666                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2667         }
2668         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2669                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2670                 tmp |= DC_HPDx_INT_ACK;
2671                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2672         }
2673         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2674                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2675                 tmp |= DC_HPDx_INT_ACK;
2676                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2677         }
2678         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2679                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2680                 tmp |= DC_HPDx_INT_ACK;
2681                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2682         }
2683 }
2684
2685 void evergreen_irq_disable(struct radeon_device *rdev)
2686 {
2687         r600_disable_interrupts(rdev);
2688         /* Wait and acknowledge irq */
2689         mdelay(1);
2690         evergreen_irq_ack(rdev);
2691         evergreen_disable_interrupt_state(rdev);
2692 }
2693
2694 void evergreen_irq_suspend(struct radeon_device *rdev)
2695 {
2696         evergreen_irq_disable(rdev);
2697         r600_rlc_stop(rdev);
2698 }
2699
2700 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2701 {
2702         u32 wptr, tmp;
2703
2704         if (rdev->wb.enabled)
2705                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2706         else
2707                 wptr = RREG32(IH_RB_WPTR);
2708
2709         if (wptr & RB_OVERFLOW) {
2710                 /* When a ring buffer overflow happen start parsing interrupt
2711                  * from the last not overwritten vector (wptr + 16). Hopefully
2712                  * this should allow us to catchup.
2713                  */
2714                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2715                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2716                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2717                 tmp = RREG32(IH_RB_CNTL);
2718                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2719                 WREG32(IH_RB_CNTL, tmp);
2720         }
2721         return (wptr & rdev->ih.ptr_mask);
2722 }
2723
2724 int evergreen_irq_process(struct radeon_device *rdev)
2725 {
2726         u32 wptr;
2727         u32 rptr;
2728         u32 src_id, src_data;
2729         u32 ring_index;
2730         unsigned long flags;
2731         bool queue_hotplug = false;
2732
2733         if (!rdev->ih.enabled || rdev->shutdown)
2734                 return IRQ_NONE;
2735
2736         wptr = evergreen_get_ih_wptr(rdev);
2737         rptr = rdev->ih.rptr;
2738         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2739
2740         spin_lock_irqsave(&rdev->ih.lock, flags);
2741         if (rptr == wptr) {
2742                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2743                 return IRQ_NONE;
2744         }
2745 restart_ih:
2746         /* Order reading of wptr vs. reading of IH ring data */
2747         rmb();
2748
2749         /* display interrupts */
2750         evergreen_irq_ack(rdev);
2751
2752         rdev->ih.wptr = wptr;
2753         while (rptr != wptr) {
2754                 /* wptr/rptr are in bytes! */
2755                 ring_index = rptr / 4;
2756                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2757                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2758
2759                 switch (src_id) {
2760                 case 1: /* D1 vblank/vline */
2761                         switch (src_data) {
2762                         case 0: /* D1 vblank */
2763                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2764                                         if (rdev->irq.crtc_vblank_int[0]) {
2765                                                 drm_handle_vblank(rdev->ddev, 0);
2766                                                 rdev->pm.vblank_sync = true;
2767                                                 wake_up(&rdev->irq.vblank_queue);
2768                                         }
2769                                         if (rdev->irq.pflip[0])
2770                                                 radeon_crtc_handle_flip(rdev, 0);
2771                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2772                                         DRM_DEBUG("IH: D1 vblank\n");
2773                                 }
2774                                 break;
2775                         case 1: /* D1 vline */
2776                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2777                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2778                                         DRM_DEBUG("IH: D1 vline\n");
2779                                 }
2780                                 break;
2781                         default:
2782                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2783                                 break;
2784                         }
2785                         break;
2786                 case 2: /* D2 vblank/vline */
2787                         switch (src_data) {
2788                         case 0: /* D2 vblank */
2789                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2790                                         if (rdev->irq.crtc_vblank_int[1]) {
2791                                                 drm_handle_vblank(rdev->ddev, 1);
2792                                                 rdev->pm.vblank_sync = true;
2793                                                 wake_up(&rdev->irq.vblank_queue);
2794                                         }
2795                                         if (rdev->irq.pflip[1])
2796                                                 radeon_crtc_handle_flip(rdev, 1);
2797                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2798                                         DRM_DEBUG("IH: D2 vblank\n");
2799                                 }
2800                                 break;
2801                         case 1: /* D2 vline */
2802                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2803                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2804                                         DRM_DEBUG("IH: D2 vline\n");
2805                                 }
2806                                 break;
2807                         default:
2808                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2809                                 break;
2810                         }
2811                         break;
2812                 case 3: /* D3 vblank/vline */
2813                         switch (src_data) {
2814                         case 0: /* D3 vblank */
2815                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2816                                         if (rdev->irq.crtc_vblank_int[2]) {
2817                                                 drm_handle_vblank(rdev->ddev, 2);
2818                                                 rdev->pm.vblank_sync = true;
2819                                                 wake_up(&rdev->irq.vblank_queue);
2820                                         }
2821                                         if (rdev->irq.pflip[2])
2822                                                 radeon_crtc_handle_flip(rdev, 2);
2823                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2824                                         DRM_DEBUG("IH: D3 vblank\n");
2825                                 }
2826                                 break;
2827                         case 1: /* D3 vline */
2828                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2829                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2830                                         DRM_DEBUG("IH: D3 vline\n");
2831                                 }
2832                                 break;
2833                         default:
2834                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2835                                 break;
2836                         }
2837                         break;
2838                 case 4: /* D4 vblank/vline */
2839                         switch (src_data) {
2840                         case 0: /* D4 vblank */
2841                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2842                                         if (rdev->irq.crtc_vblank_int[3]) {
2843                                                 drm_handle_vblank(rdev->ddev, 3);
2844                                                 rdev->pm.vblank_sync = true;
2845                                                 wake_up(&rdev->irq.vblank_queue);
2846                                         }
2847                                         if (rdev->irq.pflip[3])
2848                                                 radeon_crtc_handle_flip(rdev, 3);
2849                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2850                                         DRM_DEBUG("IH: D4 vblank\n");
2851                                 }
2852                                 break;
2853                         case 1: /* D4 vline */
2854                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2855                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2856                                         DRM_DEBUG("IH: D4 vline\n");
2857                                 }
2858                                 break;
2859                         default:
2860                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2861                                 break;
2862                         }
2863                         break;
2864                 case 5: /* D5 vblank/vline */
2865                         switch (src_data) {
2866                         case 0: /* D5 vblank */
2867                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2868                                         if (rdev->irq.crtc_vblank_int[4]) {
2869                                                 drm_handle_vblank(rdev->ddev, 4);
2870                                                 rdev->pm.vblank_sync = true;
2871                                                 wake_up(&rdev->irq.vblank_queue);
2872                                         }
2873                                         if (rdev->irq.pflip[4])
2874                                                 radeon_crtc_handle_flip(rdev, 4);
2875                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2876                                         DRM_DEBUG("IH: D5 vblank\n");
2877                                 }
2878                                 break;
2879                         case 1: /* D5 vline */
2880                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2881                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2882                                         DRM_DEBUG("IH: D5 vline\n");
2883                                 }
2884                                 break;
2885                         default:
2886                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2887                                 break;
2888                         }
2889                         break;
2890                 case 6: /* D6 vblank/vline */
2891                         switch (src_data) {
2892                         case 0: /* D6 vblank */
2893                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2894                                         if (rdev->irq.crtc_vblank_int[5]) {
2895                                                 drm_handle_vblank(rdev->ddev, 5);
2896                                                 rdev->pm.vblank_sync = true;
2897                                                 wake_up(&rdev->irq.vblank_queue);
2898                                         }
2899                                         if (rdev->irq.pflip[5])
2900                                                 radeon_crtc_handle_flip(rdev, 5);
2901                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2902                                         DRM_DEBUG("IH: D6 vblank\n");
2903                                 }
2904                                 break;
2905                         case 1: /* D6 vline */
2906                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2907                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2908                                         DRM_DEBUG("IH: D6 vline\n");
2909                                 }
2910                                 break;
2911                         default:
2912                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2913                                 break;
2914                         }
2915                         break;
2916                 case 42: /* HPD hotplug */
2917                         switch (src_data) {
2918                         case 0:
2919                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2920                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2921                                         queue_hotplug = true;
2922                                         DRM_DEBUG("IH: HPD1\n");
2923                                 }
2924                                 break;
2925                         case 1:
2926                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2927                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2928                                         queue_hotplug = true;
2929                                         DRM_DEBUG("IH: HPD2\n");
2930                                 }
2931                                 break;
2932                         case 2:
2933                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2934                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2935                                         queue_hotplug = true;
2936                                         DRM_DEBUG("IH: HPD3\n");
2937                                 }
2938                                 break;
2939                         case 3:
2940                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2941                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2942                                         queue_hotplug = true;
2943                                         DRM_DEBUG("IH: HPD4\n");
2944                                 }
2945                                 break;
2946                         case 4:
2947                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2948                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2949                                         queue_hotplug = true;
2950                                         DRM_DEBUG("IH: HPD5\n");
2951                                 }
2952                                 break;
2953                         case 5:
2954                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2955                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2956                                         queue_hotplug = true;
2957                                         DRM_DEBUG("IH: HPD6\n");
2958                                 }
2959                                 break;
2960                         default:
2961                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2962                                 break;
2963                         }
2964                         break;
2965                 case 176: /* CP_INT in ring buffer */
2966                 case 177: /* CP_INT in IB1 */
2967                 case 178: /* CP_INT in IB2 */
2968                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2969                         radeon_fence_process(rdev);
2970                         break;
2971                 case 181: /* CP EOP event */
2972                         DRM_DEBUG("IH: CP EOP\n");
2973                         radeon_fence_process(rdev);
2974                         break;
2975                 case 233: /* GUI IDLE */
2976                         DRM_DEBUG("IH: GUI idle\n");
2977                         rdev->pm.gui_idle = true;
2978                         wake_up(&rdev->irq.idle_queue);
2979                         break;
2980                 default:
2981                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2982                         break;
2983                 }
2984
2985                 /* wptr/rptr are in bytes! */
2986                 rptr += 16;
2987                 rptr &= rdev->ih.ptr_mask;
2988         }
2989         /* make sure wptr hasn't changed while processing */
2990         wptr = evergreen_get_ih_wptr(rdev);
2991         if (wptr != rdev->ih.wptr)
2992                 goto restart_ih;
2993         if (queue_hotplug)
2994                 schedule_work(&rdev->hotplug_work);
2995         rdev->ih.rptr = rptr;
2996         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2997         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2998         return IRQ_HANDLED;
2999 }
3000
3001 static int evergreen_startup(struct radeon_device *rdev)
3002 {
3003         int r;
3004
3005         /* enable pcie gen2 link */
3006         if (!ASIC_IS_DCE5(rdev))
3007                 evergreen_pcie_gen2_enable(rdev);
3008
3009         if (ASIC_IS_DCE5(rdev)) {
3010                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3011                         r = ni_init_microcode(rdev);
3012                         if (r) {
3013                                 DRM_ERROR("Failed to load firmware!\n");
3014                                 return r;
3015                         }
3016                 }
3017                 r = ni_mc_load_microcode(rdev);
3018                 if (r) {
3019                         DRM_ERROR("Failed to load MC firmware!\n");
3020                         return r;
3021                 }
3022         } else {
3023                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3024                         r = r600_init_microcode(rdev);
3025                         if (r) {
3026                                 DRM_ERROR("Failed to load firmware!\n");
3027                                 return r;
3028                         }
3029                 }
3030         }
3031
3032         evergreen_mc_program(rdev);
3033         if (rdev->flags & RADEON_IS_AGP) {
3034                 evergreen_agp_enable(rdev);
3035         } else {
3036                 r = evergreen_pcie_gart_enable(rdev);
3037                 if (r)
3038                         return r;
3039         }
3040         evergreen_gpu_init(rdev);
3041
3042         r = evergreen_blit_init(rdev);
3043         if (r) {
3044                 evergreen_blit_fini(rdev);
3045                 rdev->asic->copy = NULL;
3046                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3047         }
3048
3049         /* allocate wb buffer */
3050         r = radeon_wb_init(rdev);
3051         if (r)
3052                 return r;
3053
3054         /* Enable IRQ */
3055         r = r600_irq_init(rdev);
3056         if (r) {
3057                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3058                 radeon_irq_kms_fini(rdev);
3059                 return r;
3060         }
3061         evergreen_irq_set(rdev);
3062
3063         r = radeon_ring_init(rdev, rdev->cp.ring_size);
3064         if (r)
3065                 return r;
3066         r = evergreen_cp_load_microcode(rdev);
3067         if (r)
3068                 return r;
3069         r = evergreen_cp_resume(rdev);
3070         if (r)
3071                 return r;
3072
3073         return 0;
3074 }
3075
3076 int evergreen_resume(struct radeon_device *rdev)
3077 {
3078         int r;
3079
3080         /* reset the asic, the gfx blocks are often in a bad state
3081          * after the driver is unloaded or after a resume
3082          */
3083         if (radeon_asic_reset(rdev))
3084                 dev_warn(rdev->dev, "GPU reset failed !\n");
3085         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3086          * posting will perform necessary task to bring back GPU into good
3087          * shape.
3088          */
3089         /* post card */
3090         atom_asic_init(rdev->mode_info.atom_context);
3091
3092         r = evergreen_startup(rdev);
3093         if (r) {
3094                 DRM_ERROR("evergreen startup failed on resume\n");
3095                 return r;
3096         }
3097
3098         r = r600_ib_test(rdev);
3099         if (r) {
3100                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3101                 return r;
3102         }
3103
3104         return r;
3105
3106 }
3107
3108 int evergreen_suspend(struct radeon_device *rdev)
3109 {
3110         int r;
3111
3112         /* FIXME: we should wait for ring to be empty */
3113         r700_cp_stop(rdev);
3114         rdev->cp.ready = false;
3115         evergreen_irq_suspend(rdev);
3116         radeon_wb_disable(rdev);
3117         evergreen_pcie_gart_disable(rdev);
3118
3119         /* unpin shaders bo */
3120         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3121         if (likely(r == 0)) {
3122                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3123                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3124         }
3125
3126         return 0;
3127 }
3128
3129 int evergreen_copy_blit(struct radeon_device *rdev,
3130                         uint64_t src_offset,
3131                         uint64_t dst_offset,
3132                         unsigned num_gpu_pages,
3133                         struct radeon_fence *fence)
3134 {
3135         int r;
3136
3137         mutex_lock(&rdev->r600_blit.mutex);
3138         rdev->r600_blit.vb_ib = NULL;
3139         r = evergreen_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3140         if (r) {
3141                 if (rdev->r600_blit.vb_ib)
3142                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3143                 mutex_unlock(&rdev->r600_blit.mutex);
3144                 return r;
3145         }
3146         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3147         evergreen_blit_done_copy(rdev, fence);
3148         mutex_unlock(&rdev->r600_blit.mutex);
3149         return 0;
3150 }
3151
3152 /* Plan is to move initialization in that function and use
3153  * helper function so that radeon_device_init pretty much
3154  * do nothing more than calling asic specific function. This
3155  * should also allow to remove a bunch of callback function
3156  * like vram_info.
3157  */
3158 int evergreen_init(struct radeon_device *rdev)
3159 {
3160         int r;
3161
3162         /* This don't do much */
3163         r = radeon_gem_init(rdev);
3164         if (r)
3165                 return r;
3166         /* Read BIOS */
3167         if (!radeon_get_bios(rdev)) {
3168                 if (ASIC_IS_AVIVO(rdev))
3169                         return -EINVAL;
3170         }
3171         /* Must be an ATOMBIOS */
3172         if (!rdev->is_atom_bios) {
3173                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3174                 return -EINVAL;
3175         }
3176         r = radeon_atombios_init(rdev);
3177         if (r)
3178                 return r;
3179         /* reset the asic, the gfx blocks are often in a bad state
3180          * after the driver is unloaded or after a resume
3181          */
3182         if (radeon_asic_reset(rdev))
3183                 dev_warn(rdev->dev, "GPU reset failed !\n");
3184         /* Post card if necessary */
3185         if (!radeon_card_posted(rdev)) {
3186                 if (!rdev->bios) {
3187                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3188                         return -EINVAL;
3189                 }
3190                 DRM_INFO("GPU not posted. posting now...\n");
3191                 atom_asic_init(rdev->mode_info.atom_context);
3192         }
3193         /* Initialize scratch registers */
3194         r600_scratch_init(rdev);
3195         /* Initialize surface registers */
3196         radeon_surface_init(rdev);
3197         /* Initialize clocks */
3198         radeon_get_clock_info(rdev->ddev);
3199         /* Fence driver */
3200         r = radeon_fence_driver_init(rdev);
3201         if (r)
3202                 return r;
3203         /* initialize AGP */
3204         if (rdev->flags & RADEON_IS_AGP) {
3205                 r = radeon_agp_init(rdev);
3206                 if (r)
3207                         radeon_agp_disable(rdev);
3208         }
3209         /* initialize memory controller */
3210         r = evergreen_mc_init(rdev);
3211         if (r)
3212                 return r;
3213         /* Memory manager */
3214         r = radeon_bo_init(rdev);
3215         if (r)
3216                 return r;
3217
3218         r = radeon_irq_kms_init(rdev);
3219         if (r)
3220                 return r;
3221
3222         rdev->cp.ring_obj = NULL;
3223         r600_ring_init(rdev, 1024 * 1024);
3224
3225         rdev->ih.ring_obj = NULL;
3226         r600_ih_ring_init(rdev, 64 * 1024);
3227
3228         r = r600_pcie_gart_init(rdev);
3229         if (r)
3230                 return r;
3231
3232         rdev->accel_working = true;
3233         r = evergreen_startup(rdev);
3234         if (r) {
3235                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3236                 r700_cp_fini(rdev);
3237                 r600_irq_fini(rdev);
3238                 radeon_wb_fini(rdev);
3239                 radeon_irq_kms_fini(rdev);
3240                 evergreen_pcie_gart_fini(rdev);
3241                 rdev->accel_working = false;
3242         }
3243         if (rdev->accel_working) {
3244                 r = radeon_ib_pool_init(rdev);
3245                 if (r) {
3246                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3247                         rdev->accel_working = false;
3248                 }
3249                 r = r600_ib_test(rdev);
3250                 if (r) {
3251                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3252                         rdev->accel_working = false;
3253                 }
3254         }
3255         return 0;
3256 }
3257
3258 void evergreen_fini(struct radeon_device *rdev)
3259 {
3260         evergreen_blit_fini(rdev);
3261         r700_cp_fini(rdev);
3262         r600_irq_fini(rdev);
3263         radeon_wb_fini(rdev);
3264         radeon_ib_pool_fini(rdev);
3265         radeon_irq_kms_fini(rdev);
3266         evergreen_pcie_gart_fini(rdev);
3267         radeon_gem_fini(rdev);
3268         radeon_fence_driver_fini(rdev);
3269         radeon_agp_fini(rdev);
3270         radeon_bo_fini(rdev);
3271         radeon_atombios_fini(rdev);
3272         kfree(rdev->bios);
3273         rdev->bios = NULL;
3274 }
3275
3276 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3277 {
3278         u32 link_width_cntl, speed_cntl;
3279
3280         if (radeon_pcie_gen2 == 0)
3281                 return;
3282
3283         if (rdev->flags & RADEON_IS_IGP)
3284                 return;
3285
3286         if (!(rdev->flags & RADEON_IS_PCIE))
3287                 return;
3288
3289         /* x2 cards have a special sequence */
3290         if (ASIC_IS_X2(rdev))
3291                 return;
3292
3293         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3294         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3295             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3296
3297                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3298                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3299                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3300
3301                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3302                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3303                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3304
3305                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3306                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3307                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3308
3309                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3310                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3311                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3312
3313                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3314                 speed_cntl |= LC_GEN2_EN_STRAP;
3315                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3316
3317         } else {
3318                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3319                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3320                 if (1)
3321                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3322                 else
3323                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3324                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3325         }
3326 }