drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  45 {
  46         /* enable the pflip int */
  47         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  48 }
  49
  50 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  51 {
  52         /* disable the pflip int */
  53         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  54 }
  55
  56 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  57 {
  58         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  59         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  60
  61         /* Lock the graphics update lock */
  62         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  63         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  64
  65         /* update the scanout addresses */
  66         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  67                upper_32_bits(crtc_base));
  68         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  69                (u32)crtc_base);
  70
  71         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  72                upper_32_bits(crtc_base));
  73         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  74                (u32)crtc_base);
  75
  76         /* Wait for update_pending to go high. */
  77         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
  78         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  79
  80         /* Unlock the lock, so double-buffering can take place inside vblank */
  81         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
  82         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  83
  84         /* Return current update_pending status: */
  85         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
  86 }
  87
  88 /* get temperature in millidegrees */
  89 int evergreen_get_temp(struct radeon_device *rdev)
  90 {
  91         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  92                 ASIC_T_SHIFT;
  93         u32 actual_temp = 0;
  94
  95         if (temp & 0x400)
  96                 actual_temp = -256;
  97         else if (temp & 0x200)
  98                 actual_temp = 255;
  99         else if (temp & 0x100) {
 100                 actual_temp = temp & 0x1ff;
 101                 actual_temp |= ~0x1ff;
 102         } else
 103                 actual_temp = temp & 0xff;
 104
 105         return (actual_temp * 1000) / 2;
 106 }
 107
 108 int sumo_get_temp(struct radeon_device *rdev)
 109 {
 110         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 111         int actual_temp = temp - 49;
 112
 113         return actual_temp * 1000;
 114 }
 115
 116 void evergreen_pm_misc(struct radeon_device *rdev)
 117 {
 118         int req_ps_idx = rdev->pm.requested_power_state_index;
 119         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 120         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 121         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 122
 123         if (voltage->type == VOLTAGE_SW) {
 124                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 125                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 126                         rdev->pm.current_vddc = voltage->voltage;
 127                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 128                 }
 129                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 130                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 131                         rdev->pm.current_vddci = voltage->vddci;
 132                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 133                 }
 134         }
 135 }
 136
 137 void evergreen_pm_prepare(struct radeon_device *rdev)
 138 {
 139         struct drm_device *ddev = rdev->ddev;
 140         struct drm_crtc *crtc;
 141         struct radeon_crtc *radeon_crtc;
 142         u32 tmp;
 143
 144         /* disable any active CRTCs */
 145         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 146                 radeon_crtc = to_radeon_crtc(crtc);
 147                 if (radeon_crtc->enabled) {
 148                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 149                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 150                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 151                 }
 152         }
 153 }
 154
 155 void evergreen_pm_finish(struct radeon_device *rdev)
 156 {
 157         struct drm_device *ddev = rdev->ddev;
 158         struct drm_crtc *crtc;
 159         struct radeon_crtc *radeon_crtc;
 160         u32 tmp;
 161
 162         /* enable any active CRTCs */
 163         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 164                 radeon_crtc = to_radeon_crtc(crtc);
 165                 if (radeon_crtc->enabled) {
 166                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 167                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 168                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 169                 }
 170         }
 171 }
 172
 173 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 174 {
 175         bool connected = false;
 176
 177         switch (hpd) {
 178         case RADEON_HPD_1:
 179                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 180                         connected = true;
 181                 break;
 182         case RADEON_HPD_2:
 183                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 184                         connected = true;
 185                 break;
 186         case RADEON_HPD_3:
 187                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 188                         connected = true;
 189                 break;
 190         case RADEON_HPD_4:
 191                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 192                         connected = true;
 193                 break;
 194         case RADEON_HPD_5:
 195                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 196                         connected = true;
 197                 break;
 198         case RADEON_HPD_6:
 199                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 200                         connected = true;
 201                         break;
 202         default:
 203                 break;
 204         }
 205
 206         return connected;
 207 }
 208
 209 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 210                                 enum radeon_hpd_id hpd)
 211 {
 212         u32 tmp;
 213         bool connected = evergreen_hpd_sense(rdev, hpd);
 214
 215         switch (hpd) {
 216         case RADEON_HPD_1:
 217                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 218                 if (connected)
 219                         tmp &= ~DC_HPDx_INT_POLARITY;
 220                 else
 221                         tmp |= DC_HPDx_INT_POLARITY;
 222                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 223                 break;
 224         case RADEON_HPD_2:
 225                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 226                 if (connected)
 227                         tmp &= ~DC_HPDx_INT_POLARITY;
 228                 else
 229                         tmp |= DC_HPDx_INT_POLARITY;
 230                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 231                 break;
 232         case RADEON_HPD_3:
 233                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 234                 if (connected)
 235                         tmp &= ~DC_HPDx_INT_POLARITY;
 236                 else
 237                         tmp |= DC_HPDx_INT_POLARITY;
 238                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 239                 break;
 240         case RADEON_HPD_4:
 241                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 242                 if (connected)
 243                         tmp &= ~DC_HPDx_INT_POLARITY;
 244                 else
 245                         tmp |= DC_HPDx_INT_POLARITY;
 246                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 247                 break;
 248         case RADEON_HPD_5:
 249                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 250                 if (connected)
 251                         tmp &= ~DC_HPDx_INT_POLARITY;
 252                 else
 253                         tmp |= DC_HPDx_INT_POLARITY;
 254                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 255                         break;
 256         case RADEON_HPD_6:
 257                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 258                 if (connected)
 259                         tmp &= ~DC_HPDx_INT_POLARITY;
 260                 else
 261                         tmp |= DC_HPDx_INT_POLARITY;
 262                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 263                 break;
 264         default:
 265                 break;
 266         }
 267 }
 268
 269 void evergreen_hpd_init(struct radeon_device *rdev)
 270 {
 271         struct drm_device *dev = rdev->ddev;
 272         struct drm_connector *connector;
 273         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 274                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 275
 276         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 277                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 278                 switch (radeon_connector->hpd.hpd) {
 279                 case RADEON_HPD_1:
 280                         WREG32(DC_HPD1_CONTROL, tmp);
 281                         rdev->irq.hpd[0] = true;
 282                         break;
 283                 case RADEON_HPD_2:
 284                         WREG32(DC_HPD2_CONTROL, tmp);
 285                         rdev->irq.hpd[1] = true;
 286                         break;
 287                 case RADEON_HPD_3:
 288                         WREG32(DC_HPD3_CONTROL, tmp);
 289                         rdev->irq.hpd[2] = true;
 290                         break;
 291                 case RADEON_HPD_4:
 292                         WREG32(DC_HPD4_CONTROL, tmp);
 293                         rdev->irq.hpd[3] = true;
 294                         break;
 295                 case RADEON_HPD_5:
 296                         WREG32(DC_HPD5_CONTROL, tmp);
 297                         rdev->irq.hpd[4] = true;
 298                         break;
 299                 case RADEON_HPD_6:
 300                         WREG32(DC_HPD6_CONTROL, tmp);
 301                         rdev->irq.hpd[5] = true;
 302                         break;
 303                 default:
 304                         break;
 305                 }
 306         }
 307         if (rdev->irq.installed)
 308                 evergreen_irq_set(rdev);
 309 }
 310
 311 void evergreen_hpd_fini(struct radeon_device *rdev)
 312 {
 313         struct drm_device *dev = rdev->ddev;
 314         struct drm_connector *connector;
 315
 316         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 317                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 318                 switch (radeon_connector->hpd.hpd) {
 319                 case RADEON_HPD_1:
 320                         WREG32(DC_HPD1_CONTROL, 0);
 321                         rdev->irq.hpd[0] = false;
 322                         break;
 323                 case RADEON_HPD_2:
 324                         WREG32(DC_HPD2_CONTROL, 0);
 325                         rdev->irq.hpd[1] = false;
 326                         break;
 327                 case RADEON_HPD_3:
 328                         WREG32(DC_HPD3_CONTROL, 0);
 329                         rdev->irq.hpd[2] = false;
 330                         break;
 331                 case RADEON_HPD_4:
 332                         WREG32(DC_HPD4_CONTROL, 0);
 333                         rdev->irq.hpd[3] = false;
 334                         break;
 335                 case RADEON_HPD_5:
 336                         WREG32(DC_HPD5_CONTROL, 0);
 337                         rdev->irq.hpd[4] = false;
 338                         break;
 339                 case RADEON_HPD_6:
 340                         WREG32(DC_HPD6_CONTROL, 0);
 341                         rdev->irq.hpd[5] = false;
 342                         break;
 343                 default:
 344                         break;
 345                 }
 346         }
 347 }
 348
 349 /* watermark setup */
 350
 351 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 352                                         struct radeon_crtc *radeon_crtc,
 353                                         struct drm_display_mode *mode,
 354                                         struct drm_display_mode *other_mode)
 355 {
 356         u32 tmp = 0;
 357         /*
 358          * Line Buffer Setup
 359          * There are 3 line buffers, each one shared by 2 display controllers.
 360          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 361          * the display controllers.  The paritioning is done via one of four
 362          * preset allocations specified in bits 2:0:
 363          * first display controller
 364          *  0 - first half of lb (3840 * 2)
 365          *  1 - first 3/4 of lb (5760 * 2)
 366          *  2 - whole lb (7680 * 2)
 367          *  3 - first 1/4 of lb (1920 * 2)
 368          * second display controller
 369          *  4 - second half of lb (3840 * 2)
 370          *  5 - second 3/4 of lb (5760 * 2)
 371          *  6 - whole lb (7680 * 2)
 372          *  7 - last 1/4 of lb (1920 * 2)
 373          */
 374         if (mode && other_mode) {
 375                 if (mode->hdisplay > other_mode->hdisplay) {
 376                         if (mode->hdisplay > 2560)
 377                                 tmp = 1; /* 3/4 */
 378                         else
 379                                 tmp = 0; /* 1/2 */
 380                 } else if (other_mode->hdisplay > mode->hdisplay) {
 381                         if (other_mode->hdisplay > 2560)
 382                                 tmp = 3; /* 1/4 */
 383                         else
 384                                 tmp = 0; /* 1/2 */
 385                 } else
 386                         tmp = 0; /* 1/2 */
 387         } else if (mode)
 388                 tmp = 2; /* whole */
 389         else if (other_mode)
 390                 tmp = 3; /* 1/4 */
 391
 392         /* second controller of the pair uses second half of the lb */
 393         if (radeon_crtc->crtc_id % 2)
 394                 tmp += 4;
 395         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 396
 397         switch (tmp) {
 398         case 0:
 399         case 4:
 400         default:
 401                 if (ASIC_IS_DCE5(rdev))
 402                         return 4096 * 2;
 403                 else
 404                         return 3840 * 2;
 405         case 1:
 406         case 5:
 407                 if (ASIC_IS_DCE5(rdev))
 408                         return 6144 * 2;
 409                 else
 410                         return 5760 * 2;
 411         case 2:
 412         case 6:
 413                 if (ASIC_IS_DCE5(rdev))
 414                         return 8192 * 2;
 415                 else
 416                         return 7680 * 2;
 417         case 3:
 418         case 7:
 419                 if (ASIC_IS_DCE5(rdev))
 420                         return 2048 * 2;
 421                 else
 422                         return 1920 * 2;
 423         }
 424 }
 425
 426 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 427 {
 428         u32 tmp = RREG32(MC_SHARED_CHMAP);
 429
 430         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 431         case 0:
 432         default:
 433                 return 1;
 434         case 1:
 435                 return 2;
 436         case 2:
 437                 return 4;
 438         case 3:
 439                 return 8;
 440         }
 441 }
 442
 443 struct evergreen_wm_params {
 444         u32 dram_channels; /* number of dram channels */
 445         u32 yclk;          /* bandwidth per dram data pin in kHz */
 446         u32 sclk;          /* engine clock in kHz */
 447         u32 disp_clk;      /* display clock in kHz */
 448         u32 src_width;     /* viewport width */
 449         u32 active_time;   /* active display time in ns */
 450         u32 blank_time;    /* blank time in ns */
 451         bool interlaced;    /* mode is interlaced */
 452         fixed20_12 vsc;    /* vertical scale ratio */
 453         u32 num_heads;     /* number of active crtcs */
 454         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 455         u32 lb_size;       /* line buffer allocated to pipe */
 456         u32 vtaps;         /* vertical scaler taps */
 457 };
 458
 459 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 460 {
 461         /* Calculate DRAM Bandwidth and the part allocated to display. */
 462         fixed20_12 dram_efficiency; /* 0.7 */
 463         fixed20_12 yclk, dram_channels, bandwidth;
 464         fixed20_12 a;
 465
 466         a.full = dfixed_const(1000);
 467         yclk.full = dfixed_const(wm->yclk);
 468         yclk.full = dfixed_div(yclk, a);
 469         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 470         a.full = dfixed_const(10);
 471         dram_efficiency.full = dfixed_const(7);
 472         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 473         bandwidth.full = dfixed_mul(dram_channels, yclk);
 474         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 475
 476         return dfixed_trunc(bandwidth);
 477 }
 478
 479 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 480 {
 481         /* Calculate DRAM Bandwidth and the part allocated to display. */
 482         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 483         fixed20_12 yclk, dram_channels, bandwidth;
 484         fixed20_12 a;
 485
 486         a.full = dfixed_const(1000);
 487         yclk.full = dfixed_const(wm->yclk);
 488         yclk.full = dfixed_div(yclk, a);
 489         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 490         a.full = dfixed_const(10);
 491         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 492         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 493         bandwidth.full = dfixed_mul(dram_channels, yclk);
 494         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 495
 496         return dfixed_trunc(bandwidth);
 497 }
 498
 499 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 500 {
 501         /* Calculate the display Data return Bandwidth */
 502         fixed20_12 return_efficiency; /* 0.8 */
 503         fixed20_12 sclk, bandwidth;
 504         fixed20_12 a;
 505
 506         a.full = dfixed_const(1000);
 507         sclk.full = dfixed_const(wm->sclk);
 508         sclk.full = dfixed_div(sclk, a);
 509         a.full = dfixed_const(10);
 510         return_efficiency.full = dfixed_const(8);
 511         return_efficiency.full = dfixed_div(return_efficiency, a);
 512         a.full = dfixed_const(32);
 513         bandwidth.full = dfixed_mul(a, sclk);
 514         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 515
 516         return dfixed_trunc(bandwidth);
 517 }
 518
 519 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 520 {
 521         /* Calculate the DMIF Request Bandwidth */
 522         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 523         fixed20_12 disp_clk, bandwidth;
 524         fixed20_12 a;
 525
 526         a.full = dfixed_const(1000);
 527         disp_clk.full = dfixed_const(wm->disp_clk);
 528         disp_clk.full = dfixed_div(disp_clk, a);
 529         a.full = dfixed_const(10);
 530         disp_clk_request_efficiency.full = dfixed_const(8);
 531         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 532         a.full = dfixed_const(32);
 533         bandwidth.full = dfixed_mul(a, disp_clk);
 534         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 535
 536         return dfixed_trunc(bandwidth);
 537 }
 538
 539 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 540 {
 541         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 542         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 543         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 544         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 545
 546         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 547 }
 548
 549 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 550 {
 551         /* Calculate the display mode Average Bandwidth
 552          * DisplayMode should contain the source and destination dimensions,
 553          * timing, etc.
 554          */
 555         fixed20_12 bpp;
 556         fixed20_12 line_time;
 557         fixed20_12 src_width;
 558         fixed20_12 bandwidth;
 559         fixed20_12 a;
 560
 561         a.full = dfixed_const(1000);
 562         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 563         line_time.full = dfixed_div(line_time, a);
 564         bpp.full = dfixed_const(wm->bytes_per_pixel);
 565         src_width.full = dfixed_const(wm->src_width);
 566         bandwidth.full = dfixed_mul(src_width, bpp);
 567         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 568         bandwidth.full = dfixed_div(bandwidth, line_time);
 569
 570         return dfixed_trunc(bandwidth);
 571 }
 572
 573 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 574 {
 575         /* First calcualte the latency in ns */
 576         u32 mc_latency = 2000; /* 2000 ns. */
 577         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 578         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 579         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 580         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 581         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 582                 (wm->num_heads * cursor_line_pair_return_time);
 583         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 584         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 585         fixed20_12 a, b, c;
 586
 587         if (wm->num_heads == 0)
 588                 return 0;
 589
 590         a.full = dfixed_const(2);
 591         b.full = dfixed_const(1);
 592         if ((wm->vsc.full > a.full) ||
 593             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 594             (wm->vtaps >= 5) ||
 595             ((wm->vsc.full >= a.full) && wm->interlaced))
 596                 max_src_lines_per_dst_line = 4;
 597         else
 598                 max_src_lines_per_dst_line = 2;
 599
 600         a.full = dfixed_const(available_bandwidth);
 601         b.full = dfixed_const(wm->num_heads);
 602         a.full = dfixed_div(a, b);
 603
 604         b.full = dfixed_const(1000);
 605         c.full = dfixed_const(wm->disp_clk);
 606         b.full = dfixed_div(c, b);
 607         c.full = dfixed_const(wm->bytes_per_pixel);
 608         b.full = dfixed_mul(b, c);
 609
 610         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 611
 612         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 613         b.full = dfixed_const(1000);
 614         c.full = dfixed_const(lb_fill_bw);
 615         b.full = dfixed_div(c, b);
 616         a.full = dfixed_div(a, b);
 617         line_fill_time = dfixed_trunc(a);
 618
 619         if (line_fill_time < wm->active_time)
 620                 return latency;
 621         else
 622                 return latency + (line_fill_time - wm->active_time);
 623
 624 }
 625
 626 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 627 {
 628         if (evergreen_average_bandwidth(wm) <=
 629             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 630                 return true;
 631         else
 632                 return false;
 633 };
 634
 635 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 636 {
 637         if (evergreen_average_bandwidth(wm) <=
 638             (evergreen_available_bandwidth(wm) / wm->num_heads))
 639                 return true;
 640         else
 641                 return false;
 642 };
 643
 644 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 645 {
 646         u32 lb_partitions = wm->lb_size / wm->src_width;
 647         u32 line_time = wm->active_time + wm->blank_time;
 648         u32 latency_tolerant_lines;
 649         u32 latency_hiding;
 650         fixed20_12 a;
 651
 652         a.full = dfixed_const(1);
 653         if (wm->vsc.full > a.full)
 654                 latency_tolerant_lines = 1;
 655         else {
 656                 if (lb_partitions <= (wm->vtaps + 1))
 657                         latency_tolerant_lines = 1;
 658                 else
 659                         latency_tolerant_lines = 2;
 660         }
 661
 662         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 663
 664         if (evergreen_latency_watermark(wm) <= latency_hiding)
 665                 return true;
 666         else
 667                 return false;
 668 }
 669
 670 static void evergreen_program_watermarks(struct radeon_device *rdev,
 671                                          struct radeon_crtc *radeon_crtc,
 672                                          u32 lb_size, u32 num_heads)
 673 {
 674         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 675         struct evergreen_wm_params wm;
 676         u32 pixel_period;
 677         u32 line_time = 0;
 678         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 679         u32 priority_a_mark = 0, priority_b_mark = 0;
 680         u32 priority_a_cnt = PRIORITY_OFF;
 681         u32 priority_b_cnt = PRIORITY_OFF;
 682         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 683         u32 tmp, arb_control3;
 684         fixed20_12 a, b, c;
 685
 686         if (radeon_crtc->base.enabled && num_heads && mode) {
 687                 pixel_period = 1000000 / (u32)mode->clock;
 688                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 689                 priority_a_cnt = 0;
 690                 priority_b_cnt = 0;
 691
 692                 wm.yclk = rdev->pm.current_mclk * 10;
 693                 wm.sclk = rdev->pm.current_sclk * 10;
 694                 wm.disp_clk = mode->clock;
 695                 wm.src_width = mode->crtc_hdisplay;
 696                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 697                 wm.blank_time = line_time - wm.active_time;
 698                 wm.interlaced = false;
 699                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 700                         wm.interlaced = true;
 701                 wm.vsc = radeon_crtc->vsc;
 702                 wm.vtaps = 1;
 703                 if (radeon_crtc->rmx_type != RMX_OFF)
 704                         wm.vtaps = 2;
 705                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 706                 wm.lb_size = lb_size;
 707                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 708                 wm.num_heads = num_heads;
 709
 710                 /* set for high clocks */
 711                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 712                 /* set for low clocks */
 713                 /* wm.yclk = low clk; wm.sclk = low clk */
 714                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 715
 716                 /* possibly force display priority to high */
 717                 /* should really do this at mode validation time... */
 718                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 719                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 720                     !evergreen_check_latency_hiding(&wm) ||
 721                     (rdev->disp_priority == 2)) {
 722                         DRM_INFO("force priority to high\n");
 723                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 724                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 725                 }
 726
 727                 a.full = dfixed_const(1000);
 728                 b.full = dfixed_const(mode->clock);
 729                 b.full = dfixed_div(b, a);
 730                 c.full = dfixed_const(latency_watermark_a);
 731                 c.full = dfixed_mul(c, b);
 732                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 733                 c.full = dfixed_div(c, a);
 734                 a.full = dfixed_const(16);
 735                 c.full = dfixed_div(c, a);
 736                 priority_a_mark = dfixed_trunc(c);
 737                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 738
 739                 a.full = dfixed_const(1000);
 740                 b.full = dfixed_const(mode->clock);
 741                 b.full = dfixed_div(b, a);
 742                 c.full = dfixed_const(latency_watermark_b);
 743                 c.full = dfixed_mul(c, b);
 744                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 745                 c.full = dfixed_div(c, a);
 746                 a.full = dfixed_const(16);
 747                 c.full = dfixed_div(c, a);
 748                 priority_b_mark = dfixed_trunc(c);
 749                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 750         }
 751
 752         /* select wm A */
 753         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 754         tmp = arb_control3;
 755         tmp &= ~LATENCY_WATERMARK_MASK(3);
 756         tmp |= LATENCY_WATERMARK_MASK(1);
 757         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 758         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 759                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 760                 LATENCY_HIGH_WATERMARK(line_time)));
 761         /* select wm B */
 762         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 763         tmp &= ~LATENCY_WATERMARK_MASK(3);
 764         tmp |= LATENCY_WATERMARK_MASK(2);
 765         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 766         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 767                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 768                 LATENCY_HIGH_WATERMARK(line_time)));
 769         /* restore original selection */
 770         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 771
 772         /* write the priority marks */
 773         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 774         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 775
 776 }
 777
 778 void evergreen_bandwidth_update(struct radeon_device *rdev)
 779 {
 780         struct drm_display_mode *mode0 = NULL;
 781         struct drm_display_mode *mode1 = NULL;
 782         u32 num_heads = 0, lb_size;
 783         int i;
 784
 785         radeon_update_display_priority(rdev);
 786
 787         for (i = 0; i < rdev->num_crtc; i++) {
 788                 if (rdev->mode_info.crtcs[i]->base.enabled)
 789                         num_heads++;
 790         }
 791         for (i = 0; i < rdev->num_crtc; i += 2) {
 792                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 793                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 794                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 795                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 796                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 797                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 798         }
 799 }
 800
 801 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 802 {
 803         unsigned i;
 804         u32 tmp;
 805
 806         for (i = 0; i < rdev->usec_timeout; i++) {
 807                 /* read MC_STATUS */
 808                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 809                 if (!tmp)
 810                         return 0;
 811                 udelay(1);
 812         }
 813         return -1;
 814 }
 815
 816 /*
 817  * GART
 818  */
 819 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 820 {
 821         unsigned i;
 822         u32 tmp;
 823
 824         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 825
 826         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 827         for (i = 0; i < rdev->usec_timeout; i++) {
 828                 /* read MC_STATUS */
 829                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 830                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 831                 if (tmp == 2) {
 832                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 833                         return;
 834                 }
 835                 if (tmp) {
 836                         return;
 837                 }
 838                 udelay(1);
 839         }
 840 }
 841
 842 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 843 {
 844         u32 tmp;
 845         int r;
 846
 847         if (rdev->gart.table.vram.robj == NULL) {
 848                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 849                 return -EINVAL;
 850         }
 851         r = radeon_gart_table_vram_pin(rdev);
 852         if (r)
 853                 return r;
 854         radeon_gart_restore(rdev);
 855         /* Setup L2 cache */
 856         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 857                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 858                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 859         WREG32(VM_L2_CNTL2, 0);
 860         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 861         /* Setup TLB control */
 862         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 863                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 864                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 865                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 866         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 867         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 868         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 869         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 870         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 871         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 872         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 873         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 874         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 875         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 876         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 877                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 878         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 879                         (u32)(rdev->dummy_page.addr >> 12));
 880         WREG32(VM_CONTEXT1_CNTL, 0);
 881
 882         evergreen_pcie_gart_tlb_flush(rdev);
 883         rdev->gart.ready = true;
 884         return 0;
 885 }
 886
 887 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 888 {
 889         u32 tmp;
 890         int r;
 891
 892         /* Disable all tables */
 893         WREG32(VM_CONTEXT0_CNTL, 0);
 894         WREG32(VM_CONTEXT1_CNTL, 0);
 895
 896         /* Setup L2 cache */
 897         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 898                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 899         WREG32(VM_L2_CNTL2, 0);
 900         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 901         /* Setup TLB control */
 902         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 903         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 904         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 905         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 906         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 907         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 908         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 909         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 910         if (rdev->gart.table.vram.robj) {
 911                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 912                 if (likely(r == 0)) {
 913                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 914                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 915                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 916                 }
 917         }
 918 }
 919
 920 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 921 {
 922         evergreen_pcie_gart_disable(rdev);
 923         radeon_gart_table_vram_free(rdev);
 924         radeon_gart_fini(rdev);
 925 }
 926
 927
 928 void evergreen_agp_enable(struct radeon_device *rdev)
 929 {
 930         u32 tmp;
 931
 932         /* Setup L2 cache */
 933         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 934                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 935                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 936         WREG32(VM_L2_CNTL2, 0);
 937         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 938         /* Setup TLB control */
 939         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 940                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 941                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 942                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 943         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 944         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 945         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 946         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 947         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 948         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 949         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 950         WREG32(VM_CONTEXT0_CNTL, 0);
 951         WREG32(VM_CONTEXT1_CNTL, 0);
 952 }
 953
 954 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 955 {
 956         save->vga_control[0] = RREG32(D1VGA_CONTROL);
 957         save->vga_control[1] = RREG32(D2VGA_CONTROL);
 958         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 959         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 960         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 961         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 962         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 963         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 964         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 965         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 966         if (!(rdev->flags & RADEON_IS_IGP)) {
 967                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 968                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 969                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 970                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 971         }
 972
 973         /* Stop all video */
 974         WREG32(VGA_RENDER_CONTROL, 0);
 975         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 976         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 977         if (!(rdev->flags & RADEON_IS_IGP)) {
 978                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 979                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 980                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 981                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 982         }
 983         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 984         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 985         if (!(rdev->flags & RADEON_IS_IGP)) {
 986                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 987                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 988                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 989                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 990         }
 991         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 992         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 993         if (!(rdev->flags & RADEON_IS_IGP)) {
 994                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 995                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 996                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 997                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 998         }
 999
1000         WREG32(D1VGA_CONTROL, 0);
1001         WREG32(D2VGA_CONTROL, 0);
1002         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1003         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1004         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1005         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1006 }
1007
1008 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1009 {
1010         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1011                upper_32_bits(rdev->mc.vram_start));
1012         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1013                upper_32_bits(rdev->mc.vram_start));
1014         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1015                (u32)rdev->mc.vram_start);
1016         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1017                (u32)rdev->mc.vram_start);
1018
1019         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1020                upper_32_bits(rdev->mc.vram_start));
1021         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1022                upper_32_bits(rdev->mc.vram_start));
1023         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1024                (u32)rdev->mc.vram_start);
1025         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1026                (u32)rdev->mc.vram_start);
1027
1028         if (!(rdev->flags & RADEON_IS_IGP)) {
1029                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1030                        upper_32_bits(rdev->mc.vram_start));
1031                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1032                        upper_32_bits(rdev->mc.vram_start));
1033                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1034                        (u32)rdev->mc.vram_start);
1035                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1036                        (u32)rdev->mc.vram_start);
1037
1038                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1039                        upper_32_bits(rdev->mc.vram_start));
1040                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1041                        upper_32_bits(rdev->mc.vram_start));
1042                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1043                        (u32)rdev->mc.vram_start);
1044                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1045                        (u32)rdev->mc.vram_start);
1046
1047                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1048                        upper_32_bits(rdev->mc.vram_start));
1049                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1050                        upper_32_bits(rdev->mc.vram_start));
1051                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1052                        (u32)rdev->mc.vram_start);
1053                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1054                        (u32)rdev->mc.vram_start);
1055
1056                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1057                        upper_32_bits(rdev->mc.vram_start));
1058                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1059                        upper_32_bits(rdev->mc.vram_start));
1060                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1061                        (u32)rdev->mc.vram_start);
1062                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1063                        (u32)rdev->mc.vram_start);
1064         }
1065
1066         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1067         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1068         /* Unlock host access */
1069         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1070         mdelay(1);
1071         /* Restore video state */
1072         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1073         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1074         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1075         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1076         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1077         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1078         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1079         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1080         if (!(rdev->flags & RADEON_IS_IGP)) {
1081                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1082                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1083                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1084                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1085         }
1086         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1087         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1088         if (!(rdev->flags & RADEON_IS_IGP)) {
1089                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1090                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1091                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1092                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1093         }
1094         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1095         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1096         if (!(rdev->flags & RADEON_IS_IGP)) {
1097                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1098                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1099                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1100                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1101         }
1102         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1103 }
1104
1105 void evergreen_mc_program(struct radeon_device *rdev)
1106 {
1107         struct evergreen_mc_save save;
1108         u32 tmp;
1109         int i, j;
1110
1111         /* Initialize HDP */
1112         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1113                 WREG32((0x2c14 + j), 0x00000000);
1114                 WREG32((0x2c18 + j), 0x00000000);
1115                 WREG32((0x2c1c + j), 0x00000000);
1116                 WREG32((0x2c20 + j), 0x00000000);
1117                 WREG32((0x2c24 + j), 0x00000000);
1118         }
1119         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1120
1121         evergreen_mc_stop(rdev, &save);
1122         if (evergreen_mc_wait_for_idle(rdev)) {
1123                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1124         }
1125         /* Lockout access through VGA aperture*/
1126         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1127         /* Update configuration */
1128         if (rdev->flags & RADEON_IS_AGP) {
1129                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1130                         /* VRAM before AGP */
1131                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1132                                 rdev->mc.vram_start >> 12);
1133                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1134                                 rdev->mc.gtt_end >> 12);
1135                 } else {
1136                         /* VRAM after AGP */
1137                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1138                                 rdev->mc.gtt_start >> 12);
1139                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1140                                 rdev->mc.vram_end >> 12);
1141                 }
1142         } else {
1143                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1144                         rdev->mc.vram_start >> 12);
1145                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1146                         rdev->mc.vram_end >> 12);
1147         }
1148         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1149         if (rdev->flags & RADEON_IS_IGP) {
1150                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1151                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1152                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1153                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1154         }
1155         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1156         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1157         WREG32(MC_VM_FB_LOCATION, tmp);
1158         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1159         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1160         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1161         if (rdev->flags & RADEON_IS_AGP) {
1162                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1163                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1164                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1165         } else {
1166                 WREG32(MC_VM_AGP_BASE, 0);
1167                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1168                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1169         }
1170         if (evergreen_mc_wait_for_idle(rdev)) {
1171                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1172         }
1173         evergreen_mc_resume(rdev, &save);
1174         /* we need to own VRAM, so turn off the VGA renderer here
1175          * to stop it overwriting our objects */
1176         rv515_vga_render_disable(rdev);
1177 }
1178
1179 /*
1180  * CP.
1181  */
1182 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1183 {
1184         /* set to DX10/11 mode */
1185         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1186         radeon_ring_write(rdev, 1);
1187         /* FIXME: implement */
1188         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1189         radeon_ring_write(rdev,
1190 #ifdef __BIG_ENDIAN
1191                           (2 << 0) |
1192 #endif
1193                           (ib->gpu_addr & 0xFFFFFFFC));
1194         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1195         radeon_ring_write(rdev, ib->length_dw);
1196 }
1197
1198
1199 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1200 {
1201         const __be32 *fw_data;
1202         int i;
1203
1204         if (!rdev->me_fw || !rdev->pfp_fw)
1205                 return -EINVAL;
1206
1207         r700_cp_stop(rdev);
1208         WREG32(CP_RB_CNTL,
1209 #ifdef __BIG_ENDIAN
1210                BUF_SWAP_32BIT |
1211 #endif
1212                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1213
1214         fw_data = (const __be32 *)rdev->pfp_fw->data;
1215         WREG32(CP_PFP_UCODE_ADDR, 0);
1216         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1217                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1218         WREG32(CP_PFP_UCODE_ADDR, 0);
1219
1220         fw_data = (const __be32 *)rdev->me_fw->data;
1221         WREG32(CP_ME_RAM_WADDR, 0);
1222         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1223                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1224
1225         WREG32(CP_PFP_UCODE_ADDR, 0);
1226         WREG32(CP_ME_RAM_WADDR, 0);
1227         WREG32(CP_ME_RAM_RADDR, 0);
1228         return 0;
1229 }
1230
1231 static int evergreen_cp_start(struct radeon_device *rdev)
1232 {
1233         int r, i;
1234         uint32_t cp_me;
1235
1236         r = radeon_ring_lock(rdev, 7);
1237         if (r) {
1238                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1239                 return r;
1240         }
1241         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1242         radeon_ring_write(rdev, 0x1);
1243         radeon_ring_write(rdev, 0x0);
1244         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1245         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1246         radeon_ring_write(rdev, 0);
1247         radeon_ring_write(rdev, 0);
1248         radeon_ring_unlock_commit(rdev);
1249
1250         cp_me = 0xff;
1251         WREG32(CP_ME_CNTL, cp_me);
1252
1253         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1254         if (r) {
1255                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1256                 return r;
1257         }
1258
1259         /* setup clear context state */
1260         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1261         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1262
1263         for (i = 0; i < evergreen_default_size; i++)
1264                 radeon_ring_write(rdev, evergreen_default_state[i]);
1265
1266         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1267         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1268
1269         /* set clear context state */
1270         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1271         radeon_ring_write(rdev, 0);
1272
1273         /* SQ_VTX_BASE_VTX_LOC */
1274         radeon_ring_write(rdev, 0xc0026f00);
1275         radeon_ring_write(rdev, 0x00000000);
1276         radeon_ring_write(rdev, 0x00000000);
1277         radeon_ring_write(rdev, 0x00000000);
1278
1279         /* Clear consts */
1280         radeon_ring_write(rdev, 0xc0036f00);
1281         radeon_ring_write(rdev, 0x00000bc4);
1282         radeon_ring_write(rdev, 0xffffffff);
1283         radeon_ring_write(rdev, 0xffffffff);
1284         radeon_ring_write(rdev, 0xffffffff);
1285
1286         radeon_ring_write(rdev, 0xc0026900);
1287         radeon_ring_write(rdev, 0x00000316);
1288         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1289         radeon_ring_write(rdev, 0x00000010); /*  */
1290
1291         radeon_ring_unlock_commit(rdev);
1292
1293         return 0;
1294 }
1295
1296 int evergreen_cp_resume(struct radeon_device *rdev)
1297 {
1298         u32 tmp;
1299         u32 rb_bufsz;
1300         int r;
1301
1302         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1303         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1304                                  SOFT_RESET_PA |
1305                                  SOFT_RESET_SH |
1306                                  SOFT_RESET_VGT |
1307                                  SOFT_RESET_SX));
1308         RREG32(GRBM_SOFT_RESET);
1309         mdelay(15);
1310         WREG32(GRBM_SOFT_RESET, 0);
1311         RREG32(GRBM_SOFT_RESET);
1312
1313         /* Set ring buffer size */
1314         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1315         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1316 #ifdef __BIG_ENDIAN
1317         tmp |= BUF_SWAP_32BIT;
1318 #endif
1319         WREG32(CP_RB_CNTL, tmp);
1320         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1321
1322         /* Set the write pointer delay */
1323         WREG32(CP_RB_WPTR_DELAY, 0);
1324
1325         /* Initialize the ring buffer's read and write pointers */
1326         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1327         WREG32(CP_RB_RPTR_WR, 0);
1328         WREG32(CP_RB_WPTR, 0);
1329
1330         /* set the wb address wether it's enabled or not */
1331         WREG32(CP_RB_RPTR_ADDR,
1332 #ifdef __BIG_ENDIAN
1333                RB_RPTR_SWAP(2) |
1334 #endif
1335                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1336         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1337         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1338
1339         if (rdev->wb.enabled)
1340                 WREG32(SCRATCH_UMSK, 0xff);
1341         else {
1342                 tmp |= RB_NO_UPDATE;
1343                 WREG32(SCRATCH_UMSK, 0);
1344         }
1345
1346         mdelay(1);
1347         WREG32(CP_RB_CNTL, tmp);
1348
1349         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1350         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1351
1352         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1353         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1354
1355         evergreen_cp_start(rdev);
1356         rdev->cp.ready = true;
1357         r = radeon_ring_test(rdev);
1358         if (r) {
1359                 rdev->cp.ready = false;
1360                 return r;
1361         }
1362         return 0;
1363 }
1364
1365 /*
1366  * Core functions
1367  */
1368 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1369                                                   u32 num_tile_pipes,
1370                                                   u32 num_backends,
1371                                                   u32 backend_disable_mask)
1372 {
1373         u32 backend_map = 0;
1374         u32 enabled_backends_mask = 0;
1375         u32 enabled_backends_count = 0;
1376         u32 cur_pipe;
1377         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1378         u32 cur_backend = 0;
1379         u32 i;
1380         bool force_no_swizzle;
1381
1382         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1383                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1384         if (num_tile_pipes < 1)
1385                 num_tile_pipes = 1;
1386         if (num_backends > EVERGREEN_MAX_BACKENDS)
1387                 num_backends = EVERGREEN_MAX_BACKENDS;
1388         if (num_backends < 1)
1389                 num_backends = 1;
1390
1391         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1392                 if (((backend_disable_mask >> i) & 1) == 0) {
1393                         enabled_backends_mask |= (1 << i);
1394                         ++enabled_backends_count;
1395                 }
1396                 if (enabled_backends_count == num_backends)
1397                         break;
1398         }
1399
1400         if (enabled_backends_count == 0) {
1401                 enabled_backends_mask = 1;
1402                 enabled_backends_count = 1;
1403         }
1404
1405         if (enabled_backends_count != num_backends)
1406                 num_backends = enabled_backends_count;
1407
1408         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1409         switch (rdev->family) {
1410         case CHIP_CEDAR:
1411         case CHIP_REDWOOD:
1412         case CHIP_PALM:
1413         case CHIP_TURKS:
1414         case CHIP_CAICOS:
1415                 force_no_swizzle = false;
1416                 break;
1417         case CHIP_CYPRESS:
1418         case CHIP_HEMLOCK:
1419         case CHIP_JUNIPER:
1420         case CHIP_BARTS:
1421         default:
1422                 force_no_swizzle = true;
1423                 break;
1424         }
1425         if (force_no_swizzle) {
1426                 bool last_backend_enabled = false;
1427
1428                 force_no_swizzle = false;
1429                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1430                         if (((enabled_backends_mask >> i) & 1) == 1) {
1431                                 if (last_backend_enabled)
1432                                         force_no_swizzle = true;
1433                                 last_backend_enabled = true;
1434                         } else
1435                                 last_backend_enabled = false;
1436                 }
1437         }
1438
1439         switch (num_tile_pipes) {
1440         case 1:
1441         case 3:
1442         case 5:
1443         case 7:
1444                 DRM_ERROR("odd number of pipes!\n");
1445                 break;
1446         case 2:
1447                 swizzle_pipe[0] = 0;
1448                 swizzle_pipe[1] = 1;
1449                 break;
1450         case 4:
1451                 if (force_no_swizzle) {
1452                         swizzle_pipe[0] = 0;
1453                         swizzle_pipe[1] = 1;
1454                         swizzle_pipe[2] = 2;
1455                         swizzle_pipe[3] = 3;
1456                 } else {
1457                         swizzle_pipe[0] = 0;
1458                         swizzle_pipe[1] = 2;
1459                         swizzle_pipe[2] = 1;
1460                         swizzle_pipe[3] = 3;
1461                 }
1462                 break;
1463         case 6:
1464                 if (force_no_swizzle) {
1465                         swizzle_pipe[0] = 0;
1466                         swizzle_pipe[1] = 1;
1467                         swizzle_pipe[2] = 2;
1468                         swizzle_pipe[3] = 3;
1469                         swizzle_pipe[4] = 4;
1470                         swizzle_pipe[5] = 5;
1471                 } else {
1472                         swizzle_pipe[0] = 0;
1473                         swizzle_pipe[1] = 2;
1474                         swizzle_pipe[2] = 4;
1475                         swizzle_pipe[3] = 1;
1476                         swizzle_pipe[4] = 3;
1477                         swizzle_pipe[5] = 5;
1478                 }
1479                 break;
1480         case 8:
1481                 if (force_no_swizzle) {
1482                         swizzle_pipe[0] = 0;
1483                         swizzle_pipe[1] = 1;
1484                         swizzle_pipe[2] = 2;
1485                         swizzle_pipe[3] = 3;
1486                         swizzle_pipe[4] = 4;
1487                         swizzle_pipe[5] = 5;
1488                         swizzle_pipe[6] = 6;
1489                         swizzle_pipe[7] = 7;
1490                 } else {
1491                         swizzle_pipe[0] = 0;
1492                         swizzle_pipe[1] = 2;
1493                         swizzle_pipe[2] = 4;
1494                         swizzle_pipe[3] = 6;
1495                         swizzle_pipe[4] = 1;
1496                         swizzle_pipe[5] = 3;
1497                         swizzle_pipe[6] = 5;
1498                         swizzle_pipe[7] = 7;
1499                 }
1500                 break;
1501         }
1502
1503         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1504                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1505                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1506
1507                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1508
1509                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1510         }
1511
1512         return backend_map;
1513 }
1514
1515 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1516 {
1517         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1518
1519         tmp = RREG32(MC_SHARED_CHMAP);
1520         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1521         case 0:
1522         case 1:
1523         case 2:
1524         case 3:
1525         default:
1526                 /* default mapping */
1527                 mc_shared_chremap = 0x00fac688;
1528                 break;
1529         }
1530
1531         switch (rdev->family) {
1532         case CHIP_HEMLOCK:
1533         case CHIP_CYPRESS:
1534         case CHIP_BARTS:
1535                 tcp_chan_steer_lo = 0x54763210;
1536                 tcp_chan_steer_hi = 0x0000ba98;
1537                 break;
1538         case CHIP_JUNIPER:
1539         case CHIP_REDWOOD:
1540         case CHIP_CEDAR:
1541         case CHIP_PALM:
1542         case CHIP_TURKS:
1543         case CHIP_CAICOS:
1544         default:
1545                 tcp_chan_steer_lo = 0x76543210;
1546                 tcp_chan_steer_hi = 0x0000ba98;
1547                 break;
1548         }
1549
1550         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1551         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1552         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1553 }
1554
1555 static void evergreen_gpu_init(struct radeon_device *rdev)
1556 {
1557         u32 cc_rb_backend_disable = 0;
1558         u32 cc_gc_shader_pipe_config;
1559         u32 gb_addr_config = 0;
1560         u32 mc_shared_chmap, mc_arb_ramcfg;
1561         u32 gb_backend_map;
1562         u32 grbm_gfx_index;
1563         u32 sx_debug_1;
1564         u32 smx_dc_ctl0;
1565         u32 sq_config;
1566         u32 sq_lds_resource_mgmt;
1567         u32 sq_gpr_resource_mgmt_1;
1568         u32 sq_gpr_resource_mgmt_2;
1569         u32 sq_gpr_resource_mgmt_3;
1570         u32 sq_thread_resource_mgmt;
1571         u32 sq_thread_resource_mgmt_2;
1572         u32 sq_stack_resource_mgmt_1;
1573         u32 sq_stack_resource_mgmt_2;
1574         u32 sq_stack_resource_mgmt_3;
1575         u32 vgt_cache_invalidation;
1576         u32 hdp_host_path_cntl;
1577         int i, j, num_shader_engines, ps_thread_count;
1578
1579         switch (rdev->family) {
1580         case CHIP_CYPRESS:
1581         case CHIP_HEMLOCK:
1582                 rdev->config.evergreen.num_ses = 2;
1583                 rdev->config.evergreen.max_pipes = 4;
1584                 rdev->config.evergreen.max_tile_pipes = 8;
1585                 rdev->config.evergreen.max_simds = 10;
1586                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1587                 rdev->config.evergreen.max_gprs = 256;
1588                 rdev->config.evergreen.max_threads = 248;
1589                 rdev->config.evergreen.max_gs_threads = 32;
1590                 rdev->config.evergreen.max_stack_entries = 512;
1591                 rdev->config.evergreen.sx_num_of_sets = 4;
1592                 rdev->config.evergreen.sx_max_export_size = 256;
1593                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1594                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1595                 rdev->config.evergreen.max_hw_contexts = 8;
1596                 rdev->config.evergreen.sq_num_cf_insts = 2;
1597
1598                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1599                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1600                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1601                 break;
1602         case CHIP_JUNIPER:
1603                 rdev->config.evergreen.num_ses = 1;
1604                 rdev->config.evergreen.max_pipes = 4;
1605                 rdev->config.evergreen.max_tile_pipes = 4;
1606                 rdev->config.evergreen.max_simds = 10;
1607                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1608                 rdev->config.evergreen.max_gprs = 256;
1609                 rdev->config.evergreen.max_threads = 248;
1610                 rdev->config.evergreen.max_gs_threads = 32;
1611                 rdev->config.evergreen.max_stack_entries = 512;
1612                 rdev->config.evergreen.sx_num_of_sets = 4;
1613                 rdev->config.evergreen.sx_max_export_size = 256;
1614                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1615                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1616                 rdev->config.evergreen.max_hw_contexts = 8;
1617                 rdev->config.evergreen.sq_num_cf_insts = 2;
1618
1619                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1620                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1621                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1622                 break;
1623         case CHIP_REDWOOD:
1624                 rdev->config.evergreen.num_ses = 1;
1625                 rdev->config.evergreen.max_pipes = 4;
1626                 rdev->config.evergreen.max_tile_pipes = 4;
1627                 rdev->config.evergreen.max_simds = 5;
1628                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1629                 rdev->config.evergreen.max_gprs = 256;
1630                 rdev->config.evergreen.max_threads = 248;
1631                 rdev->config.evergreen.max_gs_threads = 32;
1632                 rdev->config.evergreen.max_stack_entries = 256;
1633                 rdev->config.evergreen.sx_num_of_sets = 4;
1634                 rdev->config.evergreen.sx_max_export_size = 256;
1635                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1636                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1637                 rdev->config.evergreen.max_hw_contexts = 8;
1638                 rdev->config.evergreen.sq_num_cf_insts = 2;
1639
1640                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1641                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1642                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1643                 break;
1644         case CHIP_CEDAR:
1645         default:
1646                 rdev->config.evergreen.num_ses = 1;
1647                 rdev->config.evergreen.max_pipes = 2;
1648                 rdev->config.evergreen.max_tile_pipes = 2;
1649                 rdev->config.evergreen.max_simds = 2;
1650                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1651                 rdev->config.evergreen.max_gprs = 256;
1652                 rdev->config.evergreen.max_threads = 192;
1653                 rdev->config.evergreen.max_gs_threads = 16;
1654                 rdev->config.evergreen.max_stack_entries = 256;
1655                 rdev->config.evergreen.sx_num_of_sets = 4;
1656                 rdev->config.evergreen.sx_max_export_size = 128;
1657                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1658                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1659                 rdev->config.evergreen.max_hw_contexts = 4;
1660                 rdev->config.evergreen.sq_num_cf_insts = 1;
1661
1662                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1663                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1664                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1665                 break;
1666         case CHIP_PALM:
1667                 rdev->config.evergreen.num_ses = 1;
1668                 rdev->config.evergreen.max_pipes = 2;
1669                 rdev->config.evergreen.max_tile_pipes = 2;
1670                 rdev->config.evergreen.max_simds = 2;
1671                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1672                 rdev->config.evergreen.max_gprs = 256;
1673                 rdev->config.evergreen.max_threads = 192;
1674                 rdev->config.evergreen.max_gs_threads = 16;
1675                 rdev->config.evergreen.max_stack_entries = 256;
1676                 rdev->config.evergreen.sx_num_of_sets = 4;
1677                 rdev->config.evergreen.sx_max_export_size = 128;
1678                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1679                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1680                 rdev->config.evergreen.max_hw_contexts = 4;
1681                 rdev->config.evergreen.sq_num_cf_insts = 1;
1682
1683                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1684                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1685                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1686                 break;
1687         case CHIP_BARTS:
1688                 rdev->config.evergreen.num_ses = 2;
1689                 rdev->config.evergreen.max_pipes = 4;
1690                 rdev->config.evergreen.max_tile_pipes = 8;
1691                 rdev->config.evergreen.max_simds = 7;
1692                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1693                 rdev->config.evergreen.max_gprs = 256;
1694                 rdev->config.evergreen.max_threads = 248;
1695                 rdev->config.evergreen.max_gs_threads = 32;
1696                 rdev->config.evergreen.max_stack_entries = 512;
1697                 rdev->config.evergreen.sx_num_of_sets = 4;
1698                 rdev->config.evergreen.sx_max_export_size = 256;
1699                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1700                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1701                 rdev->config.evergreen.max_hw_contexts = 8;
1702                 rdev->config.evergreen.sq_num_cf_insts = 2;
1703
1704                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1705                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1706                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1707                 break;
1708         case CHIP_TURKS:
1709                 rdev->config.evergreen.num_ses = 1;
1710                 rdev->config.evergreen.max_pipes = 4;
1711                 rdev->config.evergreen.max_tile_pipes = 4;
1712                 rdev->config.evergreen.max_simds = 6;
1713                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1714                 rdev->config.evergreen.max_gprs = 256;
1715                 rdev->config.evergreen.max_threads = 248;
1716                 rdev->config.evergreen.max_gs_threads = 32;
1717                 rdev->config.evergreen.max_stack_entries = 256;
1718                 rdev->config.evergreen.sx_num_of_sets = 4;
1719                 rdev->config.evergreen.sx_max_export_size = 256;
1720                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1721                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1722                 rdev->config.evergreen.max_hw_contexts = 8;
1723                 rdev->config.evergreen.sq_num_cf_insts = 2;
1724
1725                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1726                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1727                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1728                 break;
1729         case CHIP_CAICOS:
1730                 rdev->config.evergreen.num_ses = 1;
1731                 rdev->config.evergreen.max_pipes = 4;
1732                 rdev->config.evergreen.max_tile_pipes = 2;
1733                 rdev->config.evergreen.max_simds = 2;
1734                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1735                 rdev->config.evergreen.max_gprs = 256;
1736                 rdev->config.evergreen.max_threads = 192;
1737                 rdev->config.evergreen.max_gs_threads = 16;
1738                 rdev->config.evergreen.max_stack_entries = 256;
1739                 rdev->config.evergreen.sx_num_of_sets = 4;
1740                 rdev->config.evergreen.sx_max_export_size = 128;
1741                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1742                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1743                 rdev->config.evergreen.max_hw_contexts = 4;
1744                 rdev->config.evergreen.sq_num_cf_insts = 1;
1745
1746                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1747                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1748                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1749                 break;
1750         }
1751
1752         /* Initialize HDP */
1753         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1754                 WREG32((0x2c14 + j), 0x00000000);
1755                 WREG32((0x2c18 + j), 0x00000000);
1756                 WREG32((0x2c1c + j), 0x00000000);
1757                 WREG32((0x2c20 + j), 0x00000000);
1758                 WREG32((0x2c24 + j), 0x00000000);
1759         }
1760
1761         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1762
1763         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1764
1765         cc_gc_shader_pipe_config |=
1766                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1767                                   & EVERGREEN_MAX_PIPES_MASK);
1768         cc_gc_shader_pipe_config |=
1769                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1770                                & EVERGREEN_MAX_SIMDS_MASK);
1771
1772         cc_rb_backend_disable =
1773                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1774                                 & EVERGREEN_MAX_BACKENDS_MASK);
1775
1776
1777         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1778         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1779
1780         switch (rdev->config.evergreen.max_tile_pipes) {
1781         case 1:
1782         default:
1783                 gb_addr_config |= NUM_PIPES(0);
1784                 break;
1785         case 2:
1786                 gb_addr_config |= NUM_PIPES(1);
1787                 break;
1788         case 4:
1789                 gb_addr_config |= NUM_PIPES(2);
1790                 break;
1791         case 8:
1792                 gb_addr_config |= NUM_PIPES(3);
1793                 break;
1794         }
1795
1796         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1797         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1798         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1799         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1800         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1801         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1802
1803         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1804                 gb_addr_config |= ROW_SIZE(2);
1805         else
1806                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1807
1808         if (rdev->ddev->pdev->device == 0x689e) {
1809                 u32 efuse_straps_4;
1810                 u32 efuse_straps_3;
1811                 u8 efuse_box_bit_131_124;
1812
1813                 WREG32(RCU_IND_INDEX, 0x204);
1814                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1815                 WREG32(RCU_IND_INDEX, 0x203);
1816                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1817                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1818
1819                 switch(efuse_box_bit_131_124) {
1820                 case 0x00:
1821                         gb_backend_map = 0x76543210;
1822                         break;
1823                 case 0x55:
1824                         gb_backend_map = 0x77553311;
1825                         break;
1826                 case 0x56:
1827                         gb_backend_map = 0x77553300;
1828                         break;
1829                 case 0x59:
1830                         gb_backend_map = 0x77552211;
1831                         break;
1832                 case 0x66:
1833                         gb_backend_map = 0x77443300;
1834                         break;
1835                 case 0x99:
1836                         gb_backend_map = 0x66552211;
1837                         break;
1838                 case 0x5a:
1839                         gb_backend_map = 0x77552200;
1840                         break;
1841                 case 0xaa:
1842                         gb_backend_map = 0x66442200;
1843                         break;
1844                 case 0x95:
1845                         gb_backend_map = 0x66553311;
1846                         break;
1847                 default:
1848                         DRM_ERROR("bad backend map, using default\n");
1849                         gb_backend_map =
1850                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1851                                                                        rdev->config.evergreen.max_tile_pipes,
1852                                                                        rdev->config.evergreen.max_backends,
1853                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1854                                                                    rdev->config.evergreen.max_backends) &
1855                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1856                         break;
1857                 }
1858         } else if (rdev->ddev->pdev->device == 0x68b9) {
1859                 u32 efuse_straps_3;
1860                 u8 efuse_box_bit_127_124;
1861
1862                 WREG32(RCU_IND_INDEX, 0x203);
1863                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1864                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1865
1866                 switch(efuse_box_bit_127_124) {
1867                 case 0x0:
1868                         gb_backend_map = 0x00003210;
1869                         break;
1870                 case 0x5:
1871                 case 0x6:
1872                 case 0x9:
1873                 case 0xa:
1874                         gb_backend_map = 0x00003311;
1875                         break;
1876                 default:
1877                         DRM_ERROR("bad backend map, using default\n");
1878                         gb_backend_map =
1879                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1880                                                                        rdev->config.evergreen.max_tile_pipes,
1881                                                                        rdev->config.evergreen.max_backends,
1882                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1883                                                                    rdev->config.evergreen.max_backends) &
1884                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1885                         break;
1886                 }
1887         } else {
1888                 switch (rdev->family) {
1889                 case CHIP_CYPRESS:
1890                 case CHIP_HEMLOCK:
1891                 case CHIP_BARTS:
1892                         gb_backend_map = 0x66442200;
1893                         break;
1894                 case CHIP_JUNIPER:
1895                         gb_backend_map = 0x00006420;
1896                         break;
1897                 default:
1898                         gb_backend_map =
1899                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1900                                                                        rdev->config.evergreen.max_tile_pipes,
1901                                                                        rdev->config.evergreen.max_backends,
1902                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1903                                                                          rdev->config.evergreen.max_backends) &
1904                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1905                 }
1906         }
1907
1908         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1909          * not have bank info, so create a custom tiling dword.
1910          * bits 3:0   num_pipes
1911          * bits 7:4   num_banks
1912          * bits 11:8  group_size
1913          * bits 15:12 row_size
1914          */
1915         rdev->config.evergreen.tile_config = 0;
1916         switch (rdev->config.evergreen.max_tile_pipes) {
1917         case 1:
1918         default:
1919                 rdev->config.evergreen.tile_config |= (0 << 0);
1920                 break;
1921         case 2:
1922                 rdev->config.evergreen.tile_config |= (1 << 0);
1923                 break;
1924         case 4:
1925                 rdev->config.evergreen.tile_config |= (2 << 0);
1926                 break;
1927         case 8:
1928                 rdev->config.evergreen.tile_config |= (3 << 0);
1929                 break;
1930         }
1931         rdev->config.evergreen.tile_config |=
1932                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1933         rdev->config.evergreen.tile_config |=
1934                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1935         rdev->config.evergreen.tile_config |=
1936                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1937
1938         WREG32(GB_BACKEND_MAP, gb_backend_map);
1939         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1940         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1941         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1942
1943         evergreen_program_channel_remap(rdev);
1944
1945         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1946         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1947
1948         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1949                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1950                 u32 sp = cc_gc_shader_pipe_config;
1951                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1952
1953                 if (i == num_shader_engines) {
1954                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1955                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1956                 }
1957
1958                 WREG32(GRBM_GFX_INDEX, gfx);
1959                 WREG32(RLC_GFX_INDEX, gfx);
1960
1961                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1962                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1963                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1964                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1965         }
1966
1967         grbm_gfx_index |= SE_BROADCAST_WRITES;
1968         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1969         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1970
1971         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1972         WREG32(CGTS_TCC_DISABLE, 0);
1973         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1974         WREG32(CGTS_USER_TCC_DISABLE, 0);
1975
1976         /* set HW defaults for 3D engine */
1977         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1978                                      ROQ_IB2_START(0x2b)));
1979
1980         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1981
1982         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1983                              SYNC_GRADIENT |
1984                              SYNC_WALKER |
1985                              SYNC_ALIGNER));
1986
1987         sx_debug_1 = RREG32(SX_DEBUG_1);
1988         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1989         WREG32(SX_DEBUG_1, sx_debug_1);
1990
1991
1992         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1993         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1994         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1995         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1996
1997         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1998                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1999                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2000
2001         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2002                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2003                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2004
2005         WREG32(VGT_NUM_INSTANCES, 1);
2006         WREG32(SPI_CONFIG_CNTL, 0);
2007         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2008         WREG32(CP_PERFMON_CNTL, 0);
2009
2010         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2011                                   FETCH_FIFO_HIWATER(0x4) |
2012                                   DONE_FIFO_HIWATER(0xe0) |
2013                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2014
2015         sq_config = RREG32(SQ_CONFIG);
2016         sq_config &= ~(PS_PRIO(3) |
2017                        VS_PRIO(3) |
2018                        GS_PRIO(3) |
2019                        ES_PRIO(3));
2020         sq_config |= (VC_ENABLE |
2021                       EXPORT_SRC_C |
2022                       PS_PRIO(0) |
2023                       VS_PRIO(1) |
2024                       GS_PRIO(2) |
2025                       ES_PRIO(3));
2026
2027         switch (rdev->family) {
2028         case CHIP_CEDAR:
2029         case CHIP_PALM:
2030         case CHIP_CAICOS:
2031                 /* no vertex cache */
2032                 sq_config &= ~VC_ENABLE;
2033                 break;
2034         default:
2035                 break;
2036         }
2037
2038         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2039
2040         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2041         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2042         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2043         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2044         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2045         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2046         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2047
2048         switch (rdev->family) {
2049         case CHIP_CEDAR:
2050         case CHIP_PALM:
2051                 ps_thread_count = 96;
2052                 break;
2053         default:
2054                 ps_thread_count = 128;
2055                 break;
2056         }
2057
2058         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2059         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2060         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2061         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2062         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2063         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2064
2065         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2066         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2067         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2068         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2069         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2070         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2071
2072         WREG32(SQ_CONFIG, sq_config);
2073         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2074         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2075         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2076         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2077         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2078         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2079         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2080         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2081         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2082         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2083
2084         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2085                                           FORCE_EOV_MAX_REZ_CNT(255)));
2086
2087         switch (rdev->family) {
2088         case CHIP_CEDAR:
2089         case CHIP_PALM:
2090         case CHIP_CAICOS:
2091                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2092                 break;
2093         default:
2094                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2095                 break;
2096         }
2097         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2098         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2099
2100         WREG32(VGT_GS_VERTEX_REUSE, 16);
2101         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2102         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2103
2104         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2105         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2106
2107         WREG32(CB_PERF_CTR0_SEL_0, 0);
2108         WREG32(CB_PERF_CTR0_SEL_1, 0);
2109         WREG32(CB_PERF_CTR1_SEL_0, 0);
2110         WREG32(CB_PERF_CTR1_SEL_1, 0);
2111         WREG32(CB_PERF_CTR2_SEL_0, 0);
2112         WREG32(CB_PERF_CTR2_SEL_1, 0);
2113         WREG32(CB_PERF_CTR3_SEL_0, 0);
2114         WREG32(CB_PERF_CTR3_SEL_1, 0);
2115
2116         /* clear render buffer base addresses */
2117         WREG32(CB_COLOR0_BASE, 0);
2118         WREG32(CB_COLOR1_BASE, 0);
2119         WREG32(CB_COLOR2_BASE, 0);
2120         WREG32(CB_COLOR3_BASE, 0);
2121         WREG32(CB_COLOR4_BASE, 0);
2122         WREG32(CB_COLOR5_BASE, 0);
2123         WREG32(CB_COLOR6_BASE, 0);
2124         WREG32(CB_COLOR7_BASE, 0);
2125         WREG32(CB_COLOR8_BASE, 0);
2126         WREG32(CB_COLOR9_BASE, 0);
2127         WREG32(CB_COLOR10_BASE, 0);
2128         WREG32(CB_COLOR11_BASE, 0);
2129
2130         /* set the shader const cache sizes to 0 */
2131         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2132                 WREG32(i, 0);
2133         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2134                 WREG32(i, 0);
2135
2136         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2137         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2138
2139         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2140
2141         udelay(50);
2142
2143 }
2144
2145 int evergreen_mc_init(struct radeon_device *rdev)
2146 {
2147         u32 tmp;
2148         int chansize, numchan;
2149
2150         /* Get VRAM informations */
2151         rdev->mc.vram_is_ddr = true;
2152         tmp = RREG32(MC_ARB_RAMCFG);
2153         if (tmp & CHANSIZE_OVERRIDE) {
2154                 chansize = 16;
2155         } else if (tmp & CHANSIZE_MASK) {
2156                 chansize = 64;
2157         } else {
2158                 chansize = 32;
2159         }
2160         tmp = RREG32(MC_SHARED_CHMAP);
2161         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2162         case 0:
2163         default:
2164                 numchan = 1;
2165                 break;
2166         case 1:
2167                 numchan = 2;
2168                 break;
2169         case 2:
2170                 numchan = 4;
2171                 break;
2172         case 3:
2173                 numchan = 8;
2174                 break;
2175         }
2176         rdev->mc.vram_width = numchan * chansize;
2177         /* Could aper size report 0 ? */
2178         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2179         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2180         /* Setup GPU memory space */
2181         if (rdev->flags & RADEON_IS_IGP) {
2182                 /* size in bytes on fusion */
2183                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2184                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2185         } else {
2186                 /* size in MB on evergreen */
2187                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2188                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2189         }
2190         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2191         r700_vram_gtt_location(rdev, &rdev->mc);
2192         radeon_update_bandwidth_info(rdev);
2193
2194         return 0;
2195 }
2196
2197 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2198 {
2199         u32 srbm_status;
2200         u32 grbm_status;
2201         u32 grbm_status_se0, grbm_status_se1;
2202         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2203         int r;
2204
2205         srbm_status = RREG32(SRBM_STATUS);
2206         grbm_status = RREG32(GRBM_STATUS);
2207         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2208         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2209         if (!(grbm_status & GUI_ACTIVE)) {
2210                 r100_gpu_lockup_update(lockup, &rdev->cp);
2211                 return false;
2212         }
2213         /* force CP activities */
2214         r = radeon_ring_lock(rdev, 2);
2215         if (!r) {
2216                 /* PACKET2 NOP */
2217                 radeon_ring_write(rdev, 0x80000000);
2218                 radeon_ring_write(rdev, 0x80000000);
2219                 radeon_ring_unlock_commit(rdev);
2220         }
2221         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2222         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2223 }
2224
2225 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2226 {
2227         struct evergreen_mc_save save;
2228         u32 grbm_reset = 0;
2229
2230         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2231                 return 0;
2232
2233         dev_info(rdev->dev, "GPU softreset \n");
2234         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2235                 RREG32(GRBM_STATUS));
2236         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2237                 RREG32(GRBM_STATUS_SE0));
2238         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2239                 RREG32(GRBM_STATUS_SE1));
2240         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2241                 RREG32(SRBM_STATUS));
2242         evergreen_mc_stop(rdev, &save);
2243         if (evergreen_mc_wait_for_idle(rdev)) {
2244                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2245         }
2246         /* Disable CP parsing/prefetching */
2247         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2248
2249         /* reset all the gfx blocks */
2250         grbm_reset = (SOFT_RESET_CP |
2251                       SOFT_RESET_CB |
2252                       SOFT_RESET_DB |
2253                       SOFT_RESET_PA |
2254                       SOFT_RESET_SC |
2255                       SOFT_RESET_SPI |
2256                       SOFT_RESET_SH |
2257                       SOFT_RESET_SX |
2258                       SOFT_RESET_TC |
2259                       SOFT_RESET_TA |
2260                       SOFT_RESET_VC |
2261                       SOFT_RESET_VGT);
2262
2263         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2264         WREG32(GRBM_SOFT_RESET, grbm_reset);
2265         (void)RREG32(GRBM_SOFT_RESET);
2266         udelay(50);
2267         WREG32(GRBM_SOFT_RESET, 0);
2268         (void)RREG32(GRBM_SOFT_RESET);
2269         /* Wait a little for things to settle down */
2270         udelay(50);
2271         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2272                 RREG32(GRBM_STATUS));
2273         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2274                 RREG32(GRBM_STATUS_SE0));
2275         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2276                 RREG32(GRBM_STATUS_SE1));
2277         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2278                 RREG32(SRBM_STATUS));
2279         evergreen_mc_resume(rdev, &save);
2280         return 0;
2281 }
2282
2283 int evergreen_asic_reset(struct radeon_device *rdev)
2284 {
2285         return evergreen_gpu_soft_reset(rdev);
2286 }
2287
2288 /* Interrupts */
2289
2290 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2291 {
2292         switch (crtc) {
2293         case 0:
2294                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2295         case 1:
2296                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2297         case 2:
2298                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2299         case 3:
2300                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2301         case 4:
2302                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2303         case 5:
2304                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2305         default:
2306                 return 0;
2307         }
2308 }
2309
2310 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2311 {
2312         u32 tmp;
2313
2314         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2315         WREG32(GRBM_INT_CNTL, 0);
2316         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2317         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2318         if (!(rdev->flags & RADEON_IS_IGP)) {
2319                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2320                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2321                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2322                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2323         }
2324
2325         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2326         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2327         if (!(rdev->flags & RADEON_IS_IGP)) {
2328                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2329                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2330                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2331                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2332         }
2333
2334         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2335         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2336
2337         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2338         WREG32(DC_HPD1_INT_CONTROL, tmp);
2339         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2340         WREG32(DC_HPD2_INT_CONTROL, tmp);
2341         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2342         WREG32(DC_HPD3_INT_CONTROL, tmp);
2343         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2344         WREG32(DC_HPD4_INT_CONTROL, tmp);
2345         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2346         WREG32(DC_HPD5_INT_CONTROL, tmp);
2347         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2348         WREG32(DC_HPD6_INT_CONTROL, tmp);
2349
2350 }
2351
2352 int evergreen_irq_set(struct radeon_device *rdev)
2353 {
2354         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2355         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2356         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2357         u32 grbm_int_cntl = 0;
2358         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2359
2360         if (!rdev->irq.installed) {
2361                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2362                 return -EINVAL;
2363         }
2364         /* don't enable anything if the ih is disabled */
2365         if (!rdev->ih.enabled) {
2366                 r600_disable_interrupts(rdev);
2367                 /* force the active interrupt state to all disabled */
2368                 evergreen_disable_interrupt_state(rdev);
2369                 return 0;
2370         }
2371
2372         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2373         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2374         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2375         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2376         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2377         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2378
2379         if (rdev->irq.sw_int) {
2380                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2381                 cp_int_cntl |= RB_INT_ENABLE;
2382                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2383         }
2384         if (rdev->irq.crtc_vblank_int[0] ||
2385             rdev->irq.pflip[0]) {
2386                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2387                 crtc1 |= VBLANK_INT_MASK;
2388         }
2389         if (rdev->irq.crtc_vblank_int[1] ||
2390             rdev->irq.pflip[1]) {
2391                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2392                 crtc2 |= VBLANK_INT_MASK;
2393         }
2394         if (rdev->irq.crtc_vblank_int[2] ||
2395             rdev->irq.pflip[2]) {
2396                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2397                 crtc3 |= VBLANK_INT_MASK;
2398         }
2399         if (rdev->irq.crtc_vblank_int[3] ||
2400             rdev->irq.pflip[3]) {
2401                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2402                 crtc4 |= VBLANK_INT_MASK;
2403         }
2404         if (rdev->irq.crtc_vblank_int[4] ||
2405             rdev->irq.pflip[4]) {
2406                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2407                 crtc5 |= VBLANK_INT_MASK;
2408         }
2409         if (rdev->irq.crtc_vblank_int[5] ||
2410             rdev->irq.pflip[5]) {
2411                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2412                 crtc6 |= VBLANK_INT_MASK;
2413         }
2414         if (rdev->irq.hpd[0]) {
2415                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2416                 hpd1 |= DC_HPDx_INT_EN;
2417         }
2418         if (rdev->irq.hpd[1]) {
2419                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2420                 hpd2 |= DC_HPDx_INT_EN;
2421         }
2422         if (rdev->irq.hpd[2]) {
2423                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2424                 hpd3 |= DC_HPDx_INT_EN;
2425         }
2426         if (rdev->irq.hpd[3]) {
2427                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2428                 hpd4 |= DC_HPDx_INT_EN;
2429         }
2430         if (rdev->irq.hpd[4]) {
2431                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2432                 hpd5 |= DC_HPDx_INT_EN;
2433         }
2434         if (rdev->irq.hpd[5]) {
2435                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2436                 hpd6 |= DC_HPDx_INT_EN;
2437         }
2438         if (rdev->irq.gui_idle) {
2439                 DRM_DEBUG("gui idle\n");
2440                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2441         }
2442
2443         WREG32(CP_INT_CNTL, cp_int_cntl);
2444         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2445
2446         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2447         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2448         if (!(rdev->flags & RADEON_IS_IGP)) {
2449                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2450                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2451                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2452                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2453         }
2454
2455         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2456         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2457         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2458         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2459         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2460         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2461
2462         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2463         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2464         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2465         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2466         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2467         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2468
2469         return 0;
2470 }
2471
2472 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2473 {
2474         u32 tmp;
2475
2476         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2477         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2478         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2479         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2480         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2481         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2482         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2483         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2484         rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2485         rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2486         rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2487         rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2488
2489         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2490                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2491         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2492                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2493         if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2494                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2495         if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2496                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2497         if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2498                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2499         if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2500                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2501
2502         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2503                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2504         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2505                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2506
2507         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2508                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2509         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2510                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2511
2512         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2513                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2514         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2515                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2516
2517         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2518                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2519         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2520                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2521
2522         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2523                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2524         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2525                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2526
2527         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2528                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2529         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2530                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2531
2532         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2533                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2534                 tmp |= DC_HPDx_INT_ACK;
2535                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2536         }
2537         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2538                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2539                 tmp |= DC_HPDx_INT_ACK;
2540                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2541         }
2542         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2543                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2544                 tmp |= DC_HPDx_INT_ACK;
2545                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2546         }
2547         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2548                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2549                 tmp |= DC_HPDx_INT_ACK;
2550                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2551         }
2552         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2553                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2554                 tmp |= DC_HPDx_INT_ACK;
2555                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2556         }
2557         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2558                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2559                 tmp |= DC_HPDx_INT_ACK;
2560                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2561         }
2562 }
2563
2564 void evergreen_irq_disable(struct radeon_device *rdev)
2565 {
2566         r600_disable_interrupts(rdev);
2567         /* Wait and acknowledge irq */
2568         mdelay(1);
2569         evergreen_irq_ack(rdev);
2570         evergreen_disable_interrupt_state(rdev);
2571 }
2572
2573 void evergreen_irq_suspend(struct radeon_device *rdev)
2574 {
2575         evergreen_irq_disable(rdev);
2576         r600_rlc_stop(rdev);
2577 }
2578
2579 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2580 {
2581         u32 wptr, tmp;
2582
2583         if (rdev->wb.enabled)
2584                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2585         else
2586                 wptr = RREG32(IH_RB_WPTR);
2587
2588         if (wptr & RB_OVERFLOW) {
2589                 /* When a ring buffer overflow happen start parsing interrupt
2590                  * from the last not overwritten vector (wptr + 16). Hopefully
2591                  * this should allow us to catchup.
2592                  */
2593                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2594                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2595                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2596                 tmp = RREG32(IH_RB_CNTL);
2597                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2598                 WREG32(IH_RB_CNTL, tmp);
2599         }
2600         return (wptr & rdev->ih.ptr_mask);
2601 }
2602
2603 int evergreen_irq_process(struct radeon_device *rdev)
2604 {
2605         u32 wptr = evergreen_get_ih_wptr(rdev);
2606         u32 rptr = rdev->ih.rptr;
2607         u32 src_id, src_data;
2608         u32 ring_index;
2609         unsigned long flags;
2610         bool queue_hotplug = false;
2611
2612         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2613         if (!rdev->ih.enabled)
2614                 return IRQ_NONE;
2615
2616         spin_lock_irqsave(&rdev->ih.lock, flags);
2617
2618         if (rptr == wptr) {
2619                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2620                 return IRQ_NONE;
2621         }
2622         if (rdev->shutdown) {
2623                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2624                 return IRQ_NONE;
2625         }
2626
2627 restart_ih:
2628         /* display interrupts */
2629         evergreen_irq_ack(rdev);
2630
2631         rdev->ih.wptr = wptr;
2632         while (rptr != wptr) {
2633                 /* wptr/rptr are in bytes! */
2634                 ring_index = rptr / 4;
2635                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2636                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2637
2638                 switch (src_id) {
2639                 case 1: /* D1 vblank/vline */
2640                         switch (src_data) {
2641                         case 0: /* D1 vblank */
2642                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2643                                         if (rdev->irq.crtc_vblank_int[0]) {
2644                                                 drm_handle_vblank(rdev->ddev, 0);
2645                                                 rdev->pm.vblank_sync = true;
2646                                                 wake_up(&rdev->irq.vblank_queue);
2647                                         }
2648                                         if (rdev->irq.pflip[0])
2649                                                 radeon_crtc_handle_flip(rdev, 0);
2650                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2651                                         DRM_DEBUG("IH: D1 vblank\n");
2652                                 }
2653                                 break;
2654                         case 1: /* D1 vline */
2655                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2656                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2657                                         DRM_DEBUG("IH: D1 vline\n");
2658                                 }
2659                                 break;
2660                         default:
2661                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2662                                 break;
2663                         }
2664                         break;
2665                 case 2: /* D2 vblank/vline */
2666                         switch (src_data) {
2667                         case 0: /* D2 vblank */
2668                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2669                                         if (rdev->irq.crtc_vblank_int[1]) {
2670                                                 drm_handle_vblank(rdev->ddev, 1);
2671                                                 rdev->pm.vblank_sync = true;
2672                                                 wake_up(&rdev->irq.vblank_queue);
2673                                         }
2674                                         if (rdev->irq.pflip[1])
2675                                                 radeon_crtc_handle_flip(rdev, 1);
2676                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2677                                         DRM_DEBUG("IH: D2 vblank\n");
2678                                 }
2679                                 break;
2680                         case 1: /* D2 vline */
2681                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2682                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2683                                         DRM_DEBUG("IH: D2 vline\n");
2684                                 }
2685                                 break;
2686                         default:
2687                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2688                                 break;
2689                         }
2690                         break;
2691                 case 3: /* D3 vblank/vline */
2692                         switch (src_data) {
2693                         case 0: /* D3 vblank */
2694                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2695                                         if (rdev->irq.crtc_vblank_int[2]) {
2696                                                 drm_handle_vblank(rdev->ddev, 2);
2697                                                 rdev->pm.vblank_sync = true;
2698                                                 wake_up(&rdev->irq.vblank_queue);
2699                                         }
2700                                         if (rdev->irq.pflip[2])
2701                                                 radeon_crtc_handle_flip(rdev, 2);
2702                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2703                                         DRM_DEBUG("IH: D3 vblank\n");
2704                                 }
2705                                 break;
2706                         case 1: /* D3 vline */
2707                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2708                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2709                                         DRM_DEBUG("IH: D3 vline\n");
2710                                 }
2711                                 break;
2712                         default:
2713                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2714                                 break;
2715                         }
2716                         break;
2717                 case 4: /* D4 vblank/vline */
2718                         switch (src_data) {
2719                         case 0: /* D4 vblank */
2720                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2721                                         if (rdev->irq.crtc_vblank_int[3]) {
2722                                                 drm_handle_vblank(rdev->ddev, 3);
2723                                                 rdev->pm.vblank_sync = true;
2724                                                 wake_up(&rdev->irq.vblank_queue);
2725                                         }
2726                                         if (rdev->irq.pflip[3])
2727                                                 radeon_crtc_handle_flip(rdev, 3);
2728                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2729                                         DRM_DEBUG("IH: D4 vblank\n");
2730                                 }
2731                                 break;
2732                         case 1: /* D4 vline */
2733                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2734                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2735                                         DRM_DEBUG("IH: D4 vline\n");
2736                                 }
2737                                 break;
2738                         default:
2739                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2740                                 break;
2741                         }
2742                         break;
2743                 case 5: /* D5 vblank/vline */
2744                         switch (src_data) {
2745                         case 0: /* D5 vblank */
2746                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2747                                         if (rdev->irq.crtc_vblank_int[4]) {
2748                                                 drm_handle_vblank(rdev->ddev, 4);
2749                                                 rdev->pm.vblank_sync = true;
2750                                                 wake_up(&rdev->irq.vblank_queue);
2751                                         }
2752                                         if (rdev->irq.pflip[4])
2753                                                 radeon_crtc_handle_flip(rdev, 4);
2754                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2755                                         DRM_DEBUG("IH: D5 vblank\n");
2756                                 }
2757                                 break;
2758                         case 1: /* D5 vline */
2759                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2760                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2761                                         DRM_DEBUG("IH: D5 vline\n");
2762                                 }
2763                                 break;
2764                         default:
2765                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2766                                 break;
2767                         }
2768                         break;
2769                 case 6: /* D6 vblank/vline */
2770                         switch (src_data) {
2771                         case 0: /* D6 vblank */
2772                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2773                                         if (rdev->irq.crtc_vblank_int[5]) {
2774                                                 drm_handle_vblank(rdev->ddev, 5);
2775                                                 rdev->pm.vblank_sync = true;
2776                                                 wake_up(&rdev->irq.vblank_queue);
2777                                         }
2778                                         if (rdev->irq.pflip[5])
2779                                                 radeon_crtc_handle_flip(rdev, 5);
2780                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2781                                         DRM_DEBUG("IH: D6 vblank\n");
2782                                 }
2783                                 break;
2784                         case 1: /* D6 vline */
2785                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2786                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2787                                         DRM_DEBUG("IH: D6 vline\n");
2788                                 }
2789                                 break;
2790                         default:
2791                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2792                                 break;
2793                         }
2794                         break;
2795                 case 42: /* HPD hotplug */
2796                         switch (src_data) {
2797                         case 0:
2798                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2799                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2800                                         queue_hotplug = true;
2801                                         DRM_DEBUG("IH: HPD1\n");
2802                                 }
2803                                 break;
2804                         case 1:
2805                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2806                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2807                                         queue_hotplug = true;
2808                                         DRM_DEBUG("IH: HPD2\n");
2809                                 }
2810                                 break;
2811                         case 2:
2812                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2813                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2814                                         queue_hotplug = true;
2815                                         DRM_DEBUG("IH: HPD3\n");
2816                                 }
2817                                 break;
2818                         case 3:
2819                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2820                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2821                                         queue_hotplug = true;
2822                                         DRM_DEBUG("IH: HPD4\n");
2823                                 }
2824                                 break;
2825                         case 4:
2826                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2827                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2828                                         queue_hotplug = true;
2829                                         DRM_DEBUG("IH: HPD5\n");
2830                                 }
2831                                 break;
2832                         case 5:
2833                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2834                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2835                                         queue_hotplug = true;
2836                                         DRM_DEBUG("IH: HPD6\n");
2837                                 }
2838                                 break;
2839                         default:
2840                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2841                                 break;
2842                         }
2843                         break;
2844                 case 176: /* CP_INT in ring buffer */
2845                 case 177: /* CP_INT in IB1 */
2846                 case 178: /* CP_INT in IB2 */
2847                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2848                         radeon_fence_process(rdev);
2849                         break;
2850                 case 181: /* CP EOP event */
2851                         DRM_DEBUG("IH: CP EOP\n");
2852                         radeon_fence_process(rdev);
2853                         break;
2854                 case 233: /* GUI IDLE */
2855                         DRM_DEBUG("IH: CP EOP\n");
2856                         rdev->pm.gui_idle = true;
2857                         wake_up(&rdev->irq.idle_queue);
2858                         break;
2859                 default:
2860                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2861                         break;
2862                 }
2863
2864                 /* wptr/rptr are in bytes! */
2865                 rptr += 16;
2866                 rptr &= rdev->ih.ptr_mask;
2867         }
2868         /* make sure wptr hasn't changed while processing */
2869         wptr = evergreen_get_ih_wptr(rdev);
2870         if (wptr != rdev->ih.wptr)
2871                 goto restart_ih;
2872         if (queue_hotplug)
2873                 schedule_work(&rdev->hotplug_work);
2874         rdev->ih.rptr = rptr;
2875         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2876         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2877         return IRQ_HANDLED;
2878 }
2879
2880 static int evergreen_startup(struct radeon_device *rdev)
2881 {
2882         int r;
2883
2884         /* enable pcie gen2 link */
2885         if (!ASIC_IS_DCE5(rdev))
2886                 evergreen_pcie_gen2_enable(rdev);
2887
2888         if (ASIC_IS_DCE5(rdev)) {
2889                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2890                         r = ni_init_microcode(rdev);
2891                         if (r) {
2892                                 DRM_ERROR("Failed to load firmware!\n");
2893                                 return r;
2894                         }
2895                 }
2896                 r = ni_mc_load_microcode(rdev);
2897                 if (r) {
2898                         DRM_ERROR("Failed to load MC firmware!\n");
2899                         return r;
2900                 }
2901         } else {
2902                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2903                         r = r600_init_microcode(rdev);
2904                         if (r) {
2905                                 DRM_ERROR("Failed to load firmware!\n");
2906                                 return r;
2907                         }
2908                 }
2909         }
2910
2911         evergreen_mc_program(rdev);
2912         if (rdev->flags & RADEON_IS_AGP) {
2913                 evergreen_agp_enable(rdev);
2914         } else {
2915                 r = evergreen_pcie_gart_enable(rdev);
2916                 if (r)
2917                         return r;
2918         }
2919         evergreen_gpu_init(rdev);
2920
2921         r = evergreen_blit_init(rdev);
2922         if (r) {
2923                 evergreen_blit_fini(rdev);
2924                 rdev->asic->copy = NULL;
2925                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2926         }
2927         /* XXX: ontario has problems blitting to gart at the moment */
2928         if (rdev->family == CHIP_PALM) {
2929                 rdev->asic->copy = NULL;
2930                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2931         }
2932
2933         /* allocate wb buffer */
2934         r = radeon_wb_init(rdev);
2935         if (r)
2936                 return r;
2937
2938         /* Enable IRQ */
2939         r = r600_irq_init(rdev);
2940         if (r) {
2941                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2942                 radeon_irq_kms_fini(rdev);
2943                 return r;
2944         }
2945         evergreen_irq_set(rdev);
2946
2947         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2948         if (r)
2949                 return r;
2950         r = evergreen_cp_load_microcode(rdev);
2951         if (r)
2952                 return r;
2953         r = evergreen_cp_resume(rdev);
2954         if (r)
2955                 return r;
2956
2957         return 0;
2958 }
2959
2960 int evergreen_resume(struct radeon_device *rdev)
2961 {
2962         int r;
2963
2964         /* reset the asic, the gfx blocks are often in a bad state
2965          * after the driver is unloaded or after a resume
2966          */
2967         if (radeon_asic_reset(rdev))
2968                 dev_warn(rdev->dev, "GPU reset failed !\n");
2969         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2970          * posting will perform necessary task to bring back GPU into good
2971          * shape.
2972          */
2973         /* post card */
2974         atom_asic_init(rdev->mode_info.atom_context);
2975
2976         r = evergreen_startup(rdev);
2977         if (r) {
2978                 DRM_ERROR("evergreen startup failed on resume\n");
2979                 return r;
2980         }
2981
2982         r = r600_ib_test(rdev);
2983         if (r) {
2984                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2985                 return r;
2986         }
2987
2988         return r;
2989
2990 }
2991
2992 int evergreen_suspend(struct radeon_device *rdev)
2993 {
2994         int r;
2995
2996         /* FIXME: we should wait for ring to be empty */
2997         r700_cp_stop(rdev);
2998         rdev->cp.ready = false;
2999         evergreen_irq_suspend(rdev);
3000         radeon_wb_disable(rdev);
3001         evergreen_pcie_gart_disable(rdev);
3002
3003         /* unpin shaders bo */
3004         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3005         if (likely(r == 0)) {
3006                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3007                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3008         }
3009
3010         return 0;
3011 }
3012
3013 int evergreen_copy_blit(struct radeon_device *rdev,
3014                         uint64_t src_offset, uint64_t dst_offset,
3015                         unsigned num_pages, struct radeon_fence *fence)
3016 {
3017         int r;
3018
3019         mutex_lock(&rdev->r600_blit.mutex);
3020         rdev->r600_blit.vb_ib = NULL;
3021         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
3022         if (r) {
3023                 if (rdev->r600_blit.vb_ib)
3024                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3025                 mutex_unlock(&rdev->r600_blit.mutex);
3026                 return r;
3027         }
3028         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3029         evergreen_blit_done_copy(rdev, fence);
3030         mutex_unlock(&rdev->r600_blit.mutex);
3031         return 0;
3032 }
3033
3034 /* Plan is to move initialization in that function and use
3035  * helper function so that radeon_device_init pretty much
3036  * do nothing more than calling asic specific function. This
3037  * should also allow to remove a bunch of callback function
3038  * like vram_info.
3039  */
3040 int evergreen_init(struct radeon_device *rdev)
3041 {
3042         int r;
3043
3044         /* This don't do much */
3045         r = radeon_gem_init(rdev);
3046         if (r)
3047                 return r;
3048         /* Read BIOS */
3049         if (!radeon_get_bios(rdev)) {
3050                 if (ASIC_IS_AVIVO(rdev))
3051                         return -EINVAL;
3052         }
3053         /* Must be an ATOMBIOS */
3054         if (!rdev->is_atom_bios) {
3055                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3056                 return -EINVAL;
3057         }
3058         r = radeon_atombios_init(rdev);
3059         if (r)
3060                 return r;
3061         /* reset the asic, the gfx blocks are often in a bad state
3062          * after the driver is unloaded or after a resume
3063          */
3064         if (radeon_asic_reset(rdev))
3065                 dev_warn(rdev->dev, "GPU reset failed !\n");
3066         /* Post card if necessary */
3067         if (!radeon_card_posted(rdev)) {
3068                 if (!rdev->bios) {
3069                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3070                         return -EINVAL;
3071                 }
3072                 DRM_INFO("GPU not posted. posting now...\n");
3073                 atom_asic_init(rdev->mode_info.atom_context);
3074         }
3075         /* Initialize scratch registers */
3076         r600_scratch_init(rdev);
3077         /* Initialize surface registers */
3078         radeon_surface_init(rdev);
3079         /* Initialize clocks */
3080         radeon_get_clock_info(rdev->ddev);
3081         /* Fence driver */
3082         r = radeon_fence_driver_init(rdev);
3083         if (r)
3084                 return r;
3085         /* initialize AGP */
3086         if (rdev->flags & RADEON_IS_AGP) {
3087                 r = radeon_agp_init(rdev);
3088                 if (r)
3089                         radeon_agp_disable(rdev);
3090         }
3091         /* initialize memory controller */
3092         r = evergreen_mc_init(rdev);
3093         if (r)
3094                 return r;
3095         /* Memory manager */
3096         r = radeon_bo_init(rdev);
3097         if (r)
3098                 return r;
3099
3100         r = radeon_irq_kms_init(rdev);
3101         if (r)
3102                 return r;
3103
3104         rdev->cp.ring_obj = NULL;
3105         r600_ring_init(rdev, 1024 * 1024);
3106
3107         rdev->ih.ring_obj = NULL;
3108         r600_ih_ring_init(rdev, 64 * 1024);
3109
3110         r = r600_pcie_gart_init(rdev);
3111         if (r)
3112                 return r;
3113
3114         rdev->accel_working = true;
3115         r = evergreen_startup(rdev);
3116         if (r) {
3117                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3118                 r700_cp_fini(rdev);
3119                 r600_irq_fini(rdev);
3120                 radeon_wb_fini(rdev);
3121                 radeon_irq_kms_fini(rdev);
3122                 evergreen_pcie_gart_fini(rdev);
3123                 rdev->accel_working = false;
3124         }
3125         if (rdev->accel_working) {
3126                 r = radeon_ib_pool_init(rdev);
3127                 if (r) {
3128                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3129                         rdev->accel_working = false;
3130                 }
3131                 r = r600_ib_test(rdev);
3132                 if (r) {
3133                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3134                         rdev->accel_working = false;
3135                 }
3136         }
3137         return 0;
3138 }
3139
3140 void evergreen_fini(struct radeon_device *rdev)
3141 {
3142         evergreen_blit_fini(rdev);
3143         r700_cp_fini(rdev);
3144         r600_irq_fini(rdev);
3145         radeon_wb_fini(rdev);
3146         radeon_irq_kms_fini(rdev);
3147         evergreen_pcie_gart_fini(rdev);
3148         radeon_gem_fini(rdev);
3149         radeon_fence_driver_fini(rdev);
3150         radeon_agp_fini(rdev);
3151         radeon_bo_fini(rdev);
3152         radeon_atombios_fini(rdev);
3153         kfree(rdev->bios);
3154         rdev->bios = NULL;
3155 }
3156
3157 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3158 {
3159         u32 link_width_cntl, speed_cntl;
3160
3161         if (radeon_pcie_gen2 == 0)
3162                 return;
3163
3164         if (rdev->flags & RADEON_IS_IGP)
3165                 return;
3166
3167         if (!(rdev->flags & RADEON_IS_PCIE))
3168                 return;
3169
3170         /* x2 cards have a special sequence */
3171         if (ASIC_IS_X2(rdev))
3172                 return;
3173
3174         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3175         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3176             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3177
3178                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3179                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3180                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3181
3182                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3183                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3184                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3185
3186                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3187                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3188                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3189
3190                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3191                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3192                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3193
3194                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3195                 speed_cntl |= LC_GEN2_EN_STRAP;
3196                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3197
3198         } else {
3199                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3200                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3201                 if (1)
3202                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3203                 else
3204                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3205                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3206         }
3207 }