drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38
  39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  40 {
  41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  42         switch (radeon_encoder->encoder_id) {
  43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
  50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  54                 return true;
  55         default:
  56                 return false;
  57         }
  58 }
  59
  60 static struct drm_connector *
  61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
  62 {
  63         struct drm_device *dev = encoder->dev;
  64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  65         struct drm_connector *connector;
  66         struct radeon_connector *radeon_connector;
  67
  68         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  69                 radeon_connector = to_radeon_connector(connector);
  70                 if (radeon_encoder->devices & radeon_connector->devices)
  71                         return connector;
  72         }
  73         return NULL;
  74 }
  75
  76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  77                                    struct drm_display_mode *mode,
  78                                    struct drm_display_mode *adjusted_mode)
  79 {
  80         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  81         struct drm_device *dev = encoder->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83
  84         /* set the active encoder to connector routing */
  85         radeon_encoder_set_active_device(encoder);
  86         drm_mode_set_crtcinfo(adjusted_mode, 0);
  87
  88         /* hw bug */
  89         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  90             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  91                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  92
  93         /* get the native mode for LVDS */
  94         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  95                 radeon_panel_mode_fixup(encoder, adjusted_mode);
  96
  97         /* get the native mode for TV */
  98         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
  99                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 100                 if (tv_dac) {
 101                         if (tv_dac->tv_std == TV_STD_NTSC ||
 102                             tv_dac->tv_std == TV_STD_NTSC_J ||
 103                             tv_dac->tv_std == TV_STD_PAL_M)
 104                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 105                         else
 106                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 107                 }
 108         }
 109
 110         if (ASIC_IS_DCE3(rdev) &&
 111             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 112              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 113                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 114                 radeon_dp_set_link_config(connector, adjusted_mode);
 115         }
 116
 117         return true;
 118 }
 119
 120 static void
 121 atombios_dac_setup(struct drm_encoder *encoder, int action)
 122 {
 123         struct drm_device *dev = encoder->dev;
 124         struct radeon_device *rdev = dev->dev_private;
 125         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 126         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 127         int index = 0;
 128         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 129
 130         memset(&args, 0, sizeof(args));
 131
 132         switch (radeon_encoder->encoder_id) {
 133         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 134         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 135                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 136                 break;
 137         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 138         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 139                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 140                 break;
 141         }
 142
 143         args.ucAction = action;
 144
 145         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 146                 args.ucDacStandard = ATOM_DAC1_PS2;
 147         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 148                 args.ucDacStandard = ATOM_DAC1_CV;
 149         else {
 150                 switch (dac_info->tv_std) {
 151                 case TV_STD_PAL:
 152                 case TV_STD_PAL_M:
 153                 case TV_STD_SCART_PAL:
 154                 case TV_STD_SECAM:
 155                 case TV_STD_PAL_CN:
 156                         args.ucDacStandard = ATOM_DAC1_PAL;
 157                         break;
 158                 case TV_STD_NTSC:
 159                 case TV_STD_NTSC_J:
 160                 case TV_STD_PAL_60:
 161                 default:
 162                         args.ucDacStandard = ATOM_DAC1_NTSC;
 163                         break;
 164                 }
 165         }
 166         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 167
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169
 170 }
 171
 172 static void
 173 atombios_tv_setup(struct drm_encoder *encoder, int action)
 174 {
 175         struct drm_device *dev = encoder->dev;
 176         struct radeon_device *rdev = dev->dev_private;
 177         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 178         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 179         int index = 0;
 180         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 181
 182         memset(&args, 0, sizeof(args));
 183
 184         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 185
 186         args.sTVEncoder.ucAction = action;
 187
 188         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 189                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 190         else {
 191                 switch (dac_info->tv_std) {
 192                 case TV_STD_NTSC:
 193                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 194                         break;
 195                 case TV_STD_PAL:
 196                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 197                         break;
 198                 case TV_STD_PAL_M:
 199                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 200                         break;
 201                 case TV_STD_PAL_60:
 202                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 203                         break;
 204                 case TV_STD_NTSC_J:
 205                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 206                         break;
 207                 case TV_STD_SCART_PAL:
 208                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 209                         break;
 210                 case TV_STD_SECAM:
 211                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 212                         break;
 213                 case TV_STD_PAL_CN:
 214                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 215                         break;
 216                 default:
 217                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 218                         break;
 219                 }
 220         }
 221
 222         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 223
 224         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 225
 226 }
 227
 228 union dvo_encoder_control {
 229         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 230         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 231         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 232 };
 233
 234 void
 235 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 236 {
 237         struct drm_device *dev = encoder->dev;
 238         struct radeon_device *rdev = dev->dev_private;
 239         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 240         union dvo_encoder_control args;
 241         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 242         uint8_t frev, crev;
 243
 244         memset(&args, 0, sizeof(args));
 245
 246         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 247                 return;
 248
 249         /* some R4xx chips have the wrong frev */
 250         if (rdev->family <= CHIP_RV410)
 251                 frev = 1;
 252
 253         switch (frev) {
 254         case 1:
 255                 switch (crev) {
 256                 case 1:
 257                         /* R4xx, R5xx */
 258                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 259
 260                         if (radeon_encoder->pixel_clock > 165000)
 261                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 262
 263                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 264                         break;
 265                 case 2:
 266                         /* RS600/690/740 */
 267                         args.dvo.sDVOEncoder.ucAction = action;
 268                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 269                         /* DFP1, CRT1, TV1 depending on the type of port */
 270                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 271
 272                         if (radeon_encoder->pixel_clock > 165000)
 273                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 274                         break;
 275                 case 3:
 276                         /* R6xx */
 277                         args.dvo_v3.ucAction = action;
 278                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 279                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 280                         break;
 281                 default:
 282                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 283                         break;
 284                 }
 285                 break;
 286         default:
 287                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 288                 break;
 289         }
 290
 291         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 292 }
 293
 294 union lvds_encoder_control {
 295         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 296         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 297 };
 298
 299 void
 300 atombios_digital_setup(struct drm_encoder *encoder, int action)
 301 {
 302         struct drm_device *dev = encoder->dev;
 303         struct radeon_device *rdev = dev->dev_private;
 304         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 305         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 306         union lvds_encoder_control args;
 307         int index = 0;
 308         int hdmi_detected = 0;
 309         uint8_t frev, crev;
 310
 311         if (!dig)
 312                 return;
 313
 314         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 315                 hdmi_detected = 1;
 316
 317         memset(&args, 0, sizeof(args));
 318
 319         switch (radeon_encoder->encoder_id) {
 320         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 321                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 322                 break;
 323         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 324         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 325                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 326                 break;
 327         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 328                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 329                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 330                 else
 331                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 332                 break;
 333         }
 334
 335         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 336                 return;
 337
 338         switch (frev) {
 339         case 1:
 340         case 2:
 341                 switch (crev) {
 342                 case 1:
 343                         args.v1.ucMisc = 0;
 344                         args.v1.ucAction = action;
 345                         if (hdmi_detected)
 346                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 347                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 348                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 349                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 350                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 351                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 352                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 353                         } else {
 354                                 if (dig->linkb)
 355                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 356                                 if (radeon_encoder->pixel_clock > 165000)
 357                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 358                                 /*if (pScrn->rgbBits == 8) */
 359                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 360                         }
 361                         break;
 362                 case 2:
 363                 case 3:
 364                         args.v2.ucMisc = 0;
 365                         args.v2.ucAction = action;
 366                         if (crev == 3) {
 367                                 if (dig->coherent_mode)
 368                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 369                         }
 370                         if (hdmi_detected)
 371                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 372                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 373                         args.v2.ucTruncate = 0;
 374                         args.v2.ucSpatial = 0;
 375                         args.v2.ucTemporal = 0;
 376                         args.v2.ucFRC = 0;
 377                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 378                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 379                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 380                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 381                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 382                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 383                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 384                                 }
 385                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 386                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 387                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 388                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 389                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 390                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 391                                 }
 392                         } else {
 393                                 if (dig->linkb)
 394                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 395                                 if (radeon_encoder->pixel_clock > 165000)
 396                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 397                         }
 398                         break;
 399                 default:
 400                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 401                         break;
 402                 }
 403                 break;
 404         default:
 405                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 406                 break;
 407         }
 408
 409         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 410 }
 411
 412 int
 413 atombios_get_encoder_mode(struct drm_encoder *encoder)
 414 {
 415         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 416         struct drm_device *dev = encoder->dev;
 417         struct radeon_device *rdev = dev->dev_private;
 418         struct drm_connector *connector;
 419         struct radeon_connector *radeon_connector;
 420         struct radeon_connector_atom_dig *dig_connector;
 421
 422         /* dp bridges are always DP */
 423         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 424                 return ATOM_ENCODER_MODE_DP;
 425
 426         /* DVO is always DVO */
 427         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
 428                 return ATOM_ENCODER_MODE_DVO;
 429
 430         connector = radeon_get_connector_for_encoder(encoder);
 431         /* if we don't have an active device yet, just use one of
 432          * the connectors tied to the encoder.
 433          */
 434         if (!connector)
 435                 connector = radeon_get_connector_for_encoder_init(encoder);
 436         radeon_connector = to_radeon_connector(connector);
 437
 438         switch (connector->connector_type) {
 439         case DRM_MODE_CONNECTOR_DVII:
 440         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 441                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 442                         /* fix me */
 443                         if (ASIC_IS_DCE4(rdev))
 444                                 return ATOM_ENCODER_MODE_DVI;
 445                         else
 446                                 return ATOM_ENCODER_MODE_HDMI;
 447                 } else if (radeon_connector->use_digital)
 448                         return ATOM_ENCODER_MODE_DVI;
 449                 else
 450                         return ATOM_ENCODER_MODE_CRT;
 451                 break;
 452         case DRM_MODE_CONNECTOR_DVID:
 453         case DRM_MODE_CONNECTOR_HDMIA:
 454         default:
 455                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 456                         /* fix me */
 457                         if (ASIC_IS_DCE4(rdev))
 458                                 return ATOM_ENCODER_MODE_DVI;
 459                         else
 460                                 return ATOM_ENCODER_MODE_HDMI;
 461                 } else
 462                         return ATOM_ENCODER_MODE_DVI;
 463                 break;
 464         case DRM_MODE_CONNECTOR_LVDS:
 465                 return ATOM_ENCODER_MODE_LVDS;
 466                 break;
 467         case DRM_MODE_CONNECTOR_DisplayPort:
 468                 dig_connector = radeon_connector->con_priv;
 469                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 470                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 471                         return ATOM_ENCODER_MODE_DP;
 472                 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 473                         /* fix me */
 474                         if (ASIC_IS_DCE4(rdev))
 475                                 return ATOM_ENCODER_MODE_DVI;
 476                         else
 477                                 return ATOM_ENCODER_MODE_HDMI;
 478                 } else
 479                         return ATOM_ENCODER_MODE_DVI;
 480                 break;
 481         case DRM_MODE_CONNECTOR_eDP:
 482                 return ATOM_ENCODER_MODE_DP;
 483         case DRM_MODE_CONNECTOR_DVIA:
 484         case DRM_MODE_CONNECTOR_VGA:
 485                 return ATOM_ENCODER_MODE_CRT;
 486                 break;
 487         case DRM_MODE_CONNECTOR_Composite:
 488         case DRM_MODE_CONNECTOR_SVIDEO:
 489         case DRM_MODE_CONNECTOR_9PinDIN:
 490                 /* fix me */
 491                 return ATOM_ENCODER_MODE_TV;
 492                 /*return ATOM_ENCODER_MODE_CV;*/
 493                 break;
 494         }
 495 }
 496
 497 /*
 498  * DIG Encoder/Transmitter Setup
 499  *
 500  * DCE 3.0/3.1
 501  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 502  * Supports up to 3 digital outputs
 503  * - 2 DIG encoder blocks.
 504  * DIG1 can drive UNIPHY link A or link B
 505  * DIG2 can drive UNIPHY link B or LVTMA
 506  *
 507  * DCE 3.2
 508  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 509  * Supports up to 5 digital outputs
 510  * - 2 DIG encoder blocks.
 511  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 512  *
 513  * DCE 4.0/5.0
 514  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 515  * Supports up to 6 digital outputs
 516  * - 6 DIG encoder blocks.
 517  * - DIG to PHY mapping is hardcoded
 518  * DIG1 drives UNIPHY0 link A, A+B
 519  * DIG2 drives UNIPHY0 link B
 520  * DIG3 drives UNIPHY1 link A, A+B
 521  * DIG4 drives UNIPHY1 link B
 522  * DIG5 drives UNIPHY2 link A, A+B
 523  * DIG6 drives UNIPHY2 link B
 524  *
 525  * DCE 4.1
 526  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 527  * Supports up to 6 digital outputs
 528  * - 2 DIG encoder blocks.
 529  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 530  *
 531  * Routing
 532  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 533  * Examples:
 534  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 535  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 536  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 537  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 538  */
 539
 540 union dig_encoder_control {
 541         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 542         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 543         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 544         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 545 };
 546
 547 void
 548 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 549 {
 550         struct drm_device *dev = encoder->dev;
 551         struct radeon_device *rdev = dev->dev_private;
 552         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 553         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 554         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 555         union dig_encoder_control args;
 556         int index = 0;
 557         uint8_t frev, crev;
 558         int dp_clock = 0;
 559         int dp_lane_count = 0;
 560         int hpd_id = RADEON_HPD_NONE;
 561         int bpc = 8;
 562
 563         if (connector) {
 564                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 565                 struct radeon_connector_atom_dig *dig_connector =
 566                         radeon_connector->con_priv;
 567
 568                 dp_clock = dig_connector->dp_clock;
 569                 dp_lane_count = dig_connector->dp_lane_count;
 570                 hpd_id = radeon_connector->hpd.hpd;
 571                 bpc = connector->display_info.bpc;
 572         }
 573
 574         /* no dig encoder assigned */
 575         if (dig->dig_encoder == -1)
 576                 return;
 577
 578         memset(&args, 0, sizeof(args));
 579
 580         if (ASIC_IS_DCE4(rdev))
 581                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 582         else {
 583                 if (dig->dig_encoder)
 584                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 585                 else
 586                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 587         }
 588
 589         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 590                 return;
 591
 592         switch (frev) {
 593         case 1:
 594                 switch (crev) {
 595                 case 1:
 596                         args.v1.ucAction = action;
 597                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 598                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 599                                 args.v3.ucPanelMode = panel_mode;
 600                         else
 601                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 602
 603                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 604                                 args.v1.ucLaneNum = dp_lane_count;
 605                         else if (radeon_encoder->pixel_clock > 165000)
 606                                 args.v1.ucLaneNum = 8;
 607                         else
 608                                 args.v1.ucLaneNum = 4;
 609
 610                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 611                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 612                         switch (radeon_encoder->encoder_id) {
 613                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 614                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 615                                 break;
 616                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 617                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 618                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 619                                 break;
 620                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 621                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 622                                 break;
 623                         }
 624                         if (dig->linkb)
 625                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 626                         else
 627                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 628                         break;
 629                 case 2:
 630                 case 3:
 631                         args.v3.ucAction = action;
 632                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 633                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 634                                 args.v3.ucPanelMode = panel_mode;
 635                         else
 636                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 637
 638                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 639                                 args.v3.ucLaneNum = dp_lane_count;
 640                         else if (radeon_encoder->pixel_clock > 165000)
 641                                 args.v3.ucLaneNum = 8;
 642                         else
 643                                 args.v3.ucLaneNum = 4;
 644
 645                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 646                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 647                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 648                         switch (bpc) {
 649                         case 0:
 650                                 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 651                                 break;
 652                         case 6:
 653                                 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 654                                 break;
 655                         case 8:
 656                         default:
 657                                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 658                                 break;
 659                         case 10:
 660                                 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 661                                 break;
 662                         case 12:
 663                                 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 664                                 break;
 665                         case 16:
 666                                 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 667                                 break;
 668                         }
 669                         break;
 670                 case 4:
 671                         args.v4.ucAction = action;
 672                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 673                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 674                                 args.v4.ucPanelMode = panel_mode;
 675                         else
 676                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 677
 678                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 679                                 args.v4.ucLaneNum = dp_lane_count;
 680                         else if (radeon_encoder->pixel_clock > 165000)
 681                                 args.v4.ucLaneNum = 8;
 682                         else
 683                                 args.v4.ucLaneNum = 4;
 684
 685                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
 686                                 if (dp_clock == 270000)
 687                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 688                                 else if (dp_clock == 540000)
 689                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 690                         }
 691                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 692                         switch (bpc) {
 693                         case 0:
 694                                 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 695                                 break;
 696                         case 6:
 697                                 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 698                                 break;
 699                         case 8:
 700                         default:
 701                                 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 702                                 break;
 703                         case 10:
 704                                 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 705                                 break;
 706                         case 12:
 707                                 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 708                                 break;
 709                         case 16:
 710                                 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 711                                 break;
 712                         }
 713                         if (hpd_id == RADEON_HPD_NONE)
 714                                 args.v4.ucHPD_ID = 0;
 715                         else
 716                                 args.v4.ucHPD_ID = hpd_id + 1;
 717                         break;
 718                 default:
 719                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 720                         break;
 721                 }
 722                 break;
 723         default:
 724                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 725                 break;
 726         }
 727
 728         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 729
 730 }
 731
 732 union dig_transmitter_control {
 733         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 734         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 735         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 736         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 737 };
 738
 739 void
 740 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 741 {
 742         struct drm_device *dev = encoder->dev;
 743         struct radeon_device *rdev = dev->dev_private;
 744         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 745         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 746         struct drm_connector *connector;
 747         union dig_transmitter_control args;
 748         int index = 0;
 749         uint8_t frev, crev;
 750         bool is_dp = false;
 751         int pll_id = 0;
 752         int dp_clock = 0;
 753         int dp_lane_count = 0;
 754         int connector_object_id = 0;
 755         int igp_lane_info = 0;
 756         int dig_encoder = dig->dig_encoder;
 757
 758         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 759                 connector = radeon_get_connector_for_encoder_init(encoder);
 760                 /* just needed to avoid bailing in the encoder check.  the encoder
 761                  * isn't used for init
 762                  */
 763                 dig_encoder = 0;
 764         } else
 765                 connector = radeon_get_connector_for_encoder(encoder);
 766
 767         if (connector) {
 768                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 769                 struct radeon_connector_atom_dig *dig_connector =
 770                         radeon_connector->con_priv;
 771
 772                 dp_clock = dig_connector->dp_clock;
 773                 dp_lane_count = dig_connector->dp_lane_count;
 774                 connector_object_id =
 775                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 776                 igp_lane_info = dig_connector->igp_lane_info;
 777         }
 778
 779         if (encoder->crtc) {
 780                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 781                 pll_id = radeon_crtc->pll_id;
 782         }
 783
 784         /* no dig encoder assigned */
 785         if (dig_encoder == -1)
 786                 return;
 787
 788         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
 789                 is_dp = true;
 790
 791         memset(&args, 0, sizeof(args));
 792
 793         switch (radeon_encoder->encoder_id) {
 794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 795                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 796                 break;
 797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 798         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 799         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 800                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 801                 break;
 802         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 803                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 804                 break;
 805         }
 806
 807         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 808                 return;
 809
 810         switch (frev) {
 811         case 1:
 812                 switch (crev) {
 813                 case 1:
 814                         args.v1.ucAction = action;
 815                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 816                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
 817                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 818                                 args.v1.asMode.ucLaneSel = lane_num;
 819                                 args.v1.asMode.ucLaneSet = lane_set;
 820                         } else {
 821                                 if (is_dp)
 822                                         args.v1.usPixelClock =
 823                                                 cpu_to_le16(dp_clock / 10);
 824                                 else if (radeon_encoder->pixel_clock > 165000)
 825                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 826                                 else
 827                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 828                         }
 829
 830                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 831
 832                         if (dig_encoder)
 833                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 834                         else
 835                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 836
 837                         if ((rdev->flags & RADEON_IS_IGP) &&
 838                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 839                                 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 840                                         if (igp_lane_info & 0x1)
 841                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 842                                         else if (igp_lane_info & 0x2)
 843                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 844                                         else if (igp_lane_info & 0x4)
 845                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 846                                         else if (igp_lane_info & 0x8)
 847                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 848                                 } else {
 849                                         if (igp_lane_info & 0x3)
 850                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 851                                         else if (igp_lane_info & 0xc)
 852                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 853                                 }
 854                         }
 855
 856                         if (dig->linkb)
 857                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 858                         else
 859                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 860
 861                         if (is_dp)
 862                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 863                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 864                                 if (dig->coherent_mode)
 865                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 866                                 if (radeon_encoder->pixel_clock > 165000)
 867                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 868                         }
 869                         break;
 870                 case 2:
 871                         args.v2.ucAction = action;
 872                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 873                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
 874                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 875                                 args.v2.asMode.ucLaneSel = lane_num;
 876                                 args.v2.asMode.ucLaneSet = lane_set;
 877                         } else {
 878                                 if (is_dp)
 879                                         args.v2.usPixelClock =
 880                                                 cpu_to_le16(dp_clock / 10);
 881                                 else if (radeon_encoder->pixel_clock > 165000)
 882                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 883                                 else
 884                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 885                         }
 886
 887                         args.v2.acConfig.ucEncoderSel = dig_encoder;
 888                         if (dig->linkb)
 889                                 args.v2.acConfig.ucLinkSel = 1;
 890
 891                         switch (radeon_encoder->encoder_id) {
 892                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 893                                 args.v2.acConfig.ucTransmitterSel = 0;
 894                                 break;
 895                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 896                                 args.v2.acConfig.ucTransmitterSel = 1;
 897                                 break;
 898                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 899                                 args.v2.acConfig.ucTransmitterSel = 2;
 900                                 break;
 901                         }
 902
 903                         if (is_dp) {
 904                                 args.v2.acConfig.fCoherentMode = 1;
 905                                 args.v2.acConfig.fDPConnector = 1;
 906                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 907                                 if (dig->coherent_mode)
 908                                         args.v2.acConfig.fCoherentMode = 1;
 909                                 if (radeon_encoder->pixel_clock > 165000)
 910                                         args.v2.acConfig.fDualLinkConnector = 1;
 911                         }
 912                         break;
 913                 case 3:
 914                         args.v3.ucAction = action;
 915                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 916                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
 917                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 918                                 args.v3.asMode.ucLaneSel = lane_num;
 919                                 args.v3.asMode.ucLaneSet = lane_set;
 920                         } else {
 921                                 if (is_dp)
 922                                         args.v3.usPixelClock =
 923                                                 cpu_to_le16(dp_clock / 10);
 924                                 else if (radeon_encoder->pixel_clock > 165000)
 925                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 926                                 else
 927                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 928                         }
 929
 930                         if (is_dp)
 931                                 args.v3.ucLaneNum = dp_lane_count;
 932                         else if (radeon_encoder->pixel_clock > 165000)
 933                                 args.v3.ucLaneNum = 8;
 934                         else
 935                                 args.v3.ucLaneNum = 4;
 936
 937                         if (dig->linkb)
 938                                 args.v3.acConfig.ucLinkSel = 1;
 939                         if (dig_encoder & 1)
 940                                 args.v3.acConfig.ucEncoderSel = 1;
 941
 942                         /* Select the PLL for the PHY
 943                          * DP PHY should be clocked from external src if there is
 944                          * one.
 945                          */
 946                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
 947                         if (is_dp && rdev->clock.dp_extclk)
 948                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
 949                         else
 950                                 args.v3.acConfig.ucRefClkSource = pll_id;
 951
 952                         switch (radeon_encoder->encoder_id) {
 953                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 954                                 args.v3.acConfig.ucTransmitterSel = 0;
 955                                 break;
 956                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 957                                 args.v3.acConfig.ucTransmitterSel = 1;
 958                                 break;
 959                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 960                                 args.v3.acConfig.ucTransmitterSel = 2;
 961                                 break;
 962                         }
 963
 964                         if (is_dp)
 965                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 966                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 967                                 if (dig->coherent_mode)
 968                                         args.v3.acConfig.fCoherentMode = 1;
 969                                 if (radeon_encoder->pixel_clock > 165000)
 970                                         args.v3.acConfig.fDualLinkConnector = 1;
 971                         }
 972                         break;
 973                 case 4:
 974                         args.v4.ucAction = action;
 975                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 976                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
 977                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 978                                 args.v4.asMode.ucLaneSel = lane_num;
 979                                 args.v4.asMode.ucLaneSet = lane_set;
 980                         } else {
 981                                 if (is_dp)
 982                                         args.v4.usPixelClock =
 983                                                 cpu_to_le16(dp_clock / 10);
 984                                 else if (radeon_encoder->pixel_clock > 165000)
 985                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 986                                 else
 987                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 988                         }
 989
 990                         if (is_dp)
 991                                 args.v4.ucLaneNum = dp_lane_count;
 992                         else if (radeon_encoder->pixel_clock > 165000)
 993                                 args.v4.ucLaneNum = 8;
 994                         else
 995                                 args.v4.ucLaneNum = 4;
 996
 997                         if (dig->linkb)
 998                                 args.v4.acConfig.ucLinkSel = 1;
 999                         if (dig_encoder & 1)
1000                                 args.v4.acConfig.ucEncoderSel = 1;
1001
1002                         /* Select the PLL for the PHY
1003                          * DP PHY should be clocked from external src if there is
1004                          * one.
1005                          */
1006                         /* On DCE5 DCPLL usually generates the DP ref clock */
1007                         if (is_dp) {
1008                                 if (rdev->clock.dp_extclk)
1009                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1010                                 else
1011                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1012                         } else
1013                                 args.v4.acConfig.ucRefClkSource = pll_id;
1014
1015                         switch (radeon_encoder->encoder_id) {
1016                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1017                                 args.v4.acConfig.ucTransmitterSel = 0;
1018                                 break;
1019                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1020                                 args.v4.acConfig.ucTransmitterSel = 1;
1021                                 break;
1022                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1023                                 args.v4.acConfig.ucTransmitterSel = 2;
1024                                 break;
1025                         }
1026
1027                         if (is_dp)
1028                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1029                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1030                                 if (dig->coherent_mode)
1031                                         args.v4.acConfig.fCoherentMode = 1;
1032                                 if (radeon_encoder->pixel_clock > 165000)
1033                                         args.v4.acConfig.fDualLinkConnector = 1;
1034                         }
1035                         break;
1036                 default:
1037                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1038                         break;
1039                 }
1040                 break;
1041         default:
1042                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1043                 break;
1044         }
1045
1046         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1047 }
1048
1049 bool
1050 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1051 {
1052         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1053         struct drm_device *dev = radeon_connector->base.dev;
1054         struct radeon_device *rdev = dev->dev_private;
1055         union dig_transmitter_control args;
1056         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1057         uint8_t frev, crev;
1058
1059         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1060                 goto done;
1061
1062         if (!ASIC_IS_DCE4(rdev))
1063                 goto done;
1064
1065         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1066             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1067                 goto done;
1068
1069         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1070                 goto done;
1071
1072         memset(&args, 0, sizeof(args));
1073
1074         args.v1.ucAction = action;
1075
1076         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1077
1078         /* wait for the panel to power up */
1079         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1080                 int i;
1081
1082                 for (i = 0; i < 300; i++) {
1083                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1084                                 return true;
1085                         mdelay(1);
1086                 }
1087                 return false;
1088         }
1089 done:
1090         return true;
1091 }
1092
1093 union external_encoder_control {
1094         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1095         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1096 };
1097
1098 static void
1099 atombios_external_encoder_setup(struct drm_encoder *encoder,
1100                                 struct drm_encoder *ext_encoder,
1101                                 int action)
1102 {
1103         struct drm_device *dev = encoder->dev;
1104         struct radeon_device *rdev = dev->dev_private;
1105         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1106         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1107         union external_encoder_control args;
1108         struct drm_connector *connector;
1109         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1110         u8 frev, crev;
1111         int dp_clock = 0;
1112         int dp_lane_count = 0;
1113         int connector_object_id = 0;
1114         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1115         int bpc = 8;
1116
1117         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1118                 connector = radeon_get_connector_for_encoder_init(encoder);
1119         else
1120                 connector = radeon_get_connector_for_encoder(encoder);
1121
1122         if (connector) {
1123                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1124                 struct radeon_connector_atom_dig *dig_connector =
1125                         radeon_connector->con_priv;
1126
1127                 dp_clock = dig_connector->dp_clock;
1128                 dp_lane_count = dig_connector->dp_lane_count;
1129                 connector_object_id =
1130                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1131                 bpc = connector->display_info.bpc;
1132         }
1133
1134         memset(&args, 0, sizeof(args));
1135
1136         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1137                 return;
1138
1139         switch (frev) {
1140         case 1:
1141                 /* no params on frev 1 */
1142                 break;
1143         case 2:
1144                 switch (crev) {
1145                 case 1:
1146                 case 2:
1147                         args.v1.sDigEncoder.ucAction = action;
1148                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1149                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1150
1151                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1152                                 if (dp_clock == 270000)
1153                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1154                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1155                         } else if (radeon_encoder->pixel_clock > 165000)
1156                                 args.v1.sDigEncoder.ucLaneNum = 8;
1157                         else
1158                                 args.v1.sDigEncoder.ucLaneNum = 4;
1159                         break;
1160                 case 3:
1161                         args.v3.sExtEncoder.ucAction = action;
1162                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1163                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1164                         else
1165                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1166                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1167
1168                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1169                                 if (dp_clock == 270000)
1170                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1171                                 else if (dp_clock == 540000)
1172                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1173                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1174                         } else if (radeon_encoder->pixel_clock > 165000)
1175                                 args.v3.sExtEncoder.ucLaneNum = 8;
1176                         else
1177                                 args.v3.sExtEncoder.ucLaneNum = 4;
1178                         switch (ext_enum) {
1179                         case GRAPH_OBJECT_ENUM_ID1:
1180                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1181                                 break;
1182                         case GRAPH_OBJECT_ENUM_ID2:
1183                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1184                                 break;
1185                         case GRAPH_OBJECT_ENUM_ID3:
1186                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1187                                 break;
1188                         }
1189                         switch (bpc) {
1190                         case 0:
1191                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1192                                 break;
1193                         case 6:
1194                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1195                                 break;
1196                         case 8:
1197                         default:
1198                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1199                                 break;
1200                         case 10:
1201                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1202                                 break;
1203                         case 12:
1204                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1205                                 break;
1206                         case 16:
1207                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1208                                 break;
1209                         }
1210                         break;
1211                 default:
1212                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1213                         return;
1214                 }
1215                 break;
1216         default:
1217                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1218                 return;
1219         }
1220         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1221 }
1222
1223 static void
1224 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1225 {
1226         struct drm_device *dev = encoder->dev;
1227         struct radeon_device *rdev = dev->dev_private;
1228         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1229         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1230         ENABLE_YUV_PS_ALLOCATION args;
1231         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1232         uint32_t temp, reg;
1233
1234         memset(&args, 0, sizeof(args));
1235
1236         if (rdev->family >= CHIP_R600)
1237                 reg = R600_BIOS_3_SCRATCH;
1238         else
1239                 reg = RADEON_BIOS_3_SCRATCH;
1240
1241         /* XXX: fix up scratch reg handling */
1242         temp = RREG32(reg);
1243         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1244                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1245                              (radeon_crtc->crtc_id << 18)));
1246         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1247                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1248         else
1249                 WREG32(reg, 0);
1250
1251         if (enable)
1252                 args.ucEnable = ATOM_ENABLE;
1253         args.ucCRTC = radeon_crtc->crtc_id;
1254
1255         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1256
1257         WREG32(reg, temp);
1258 }
1259
1260 static void
1261 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1262 {
1263         struct drm_device *dev = encoder->dev;
1264         struct radeon_device *rdev = dev->dev_private;
1265         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1266         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1267         int index = 0;
1268
1269         memset(&args, 0, sizeof(args));
1270
1271         switch (radeon_encoder->encoder_id) {
1272         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1273         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1274                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1275                 break;
1276         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1277         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1278         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1279                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1280                 break;
1281         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1282                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1283                 break;
1284         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1285                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1286                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1287                 else
1288                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1289                 break;
1290         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1291         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1292                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1293                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1294                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1295                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1296                 else
1297                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1298                 break;
1299         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1300         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1301                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1302                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1303                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1304                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1305                 else
1306                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1307                 break;
1308         default:
1309                 return;
1310         }
1311
1312         switch (mode) {
1313         case DRM_MODE_DPMS_ON:
1314                 args.ucAction = ATOM_ENABLE;
1315                 /* workaround for DVOOutputControl on some RS690 systems */
1316                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1317                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1318                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1319                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1320                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1321                 } else
1322                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1323                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1324                         args.ucAction = ATOM_LCD_BLON;
1325                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1326                 }
1327                 break;
1328         case DRM_MODE_DPMS_STANDBY:
1329         case DRM_MODE_DPMS_SUSPEND:
1330         case DRM_MODE_DPMS_OFF:
1331                 args.ucAction = ATOM_DISABLE;
1332                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1333                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1334                         args.ucAction = ATOM_LCD_BLOFF;
1335                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1336                 }
1337                 break;
1338         }
1339 }
1340
1341 static void
1342 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1343 {
1344         struct drm_device *dev = encoder->dev;
1345         struct radeon_device *rdev = dev->dev_private;
1346         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1347         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1348         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1349         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1350         struct radeon_connector *radeon_connector = NULL;
1351         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1352
1353         if (connector) {
1354                 radeon_connector = to_radeon_connector(connector);
1355                 radeon_dig_connector = radeon_connector->con_priv;
1356         }
1357
1358         switch (mode) {
1359         case DRM_MODE_DPMS_ON:
1360                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1361                         if (!connector)
1362                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1363                         else
1364                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1365
1366                         /* setup and enable the encoder */
1367                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1368                         atombios_dig_encoder_setup(encoder,
1369                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1370                                                    dig->panel_mode);
1371                         if (ext_encoder) {
1372                                 if (ASIC_IS_DCE41(rdev))
1373                                         atombios_external_encoder_setup(encoder, ext_encoder,
1374                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1375                         }
1376                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1377                 } else if (ASIC_IS_DCE4(rdev)) {
1378                         /* setup and enable the encoder */
1379                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1380                         /* enable the transmitter */
1381                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1382                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1383                 } else {
1384                         /* setup and enable the encoder and transmitter */
1385                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1386                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1387                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1388                         /* some dce3.x boards have a bug in their transmitter control table.
1389                          * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1390                          * does the same thing and more.
1391                          */
1392                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1393                             (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1394                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1395                 }
1396                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1397                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1398                                 atombios_set_edp_panel_power(connector,
1399                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1400                                 radeon_dig_connector->edp_on = true;
1401                         }
1402                         radeon_dp_link_train(encoder, connector);
1403                         if (ASIC_IS_DCE4(rdev))
1404                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1405                 }
1406                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1407                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1408                 break;
1409         case DRM_MODE_DPMS_STANDBY:
1410         case DRM_MODE_DPMS_SUSPEND:
1411         case DRM_MODE_DPMS_OFF:
1412                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1413                         /* disable the transmitter */
1414                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1415                 } else if (ASIC_IS_DCE4(rdev)) {
1416                         /* disable the transmitter */
1417                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1418                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1419                 } else {
1420                         /* disable the encoder and transmitter */
1421                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1422                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1423                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1424                 }
1425                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1426                         if (ASIC_IS_DCE4(rdev))
1427                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1428                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1429                                 atombios_set_edp_panel_power(connector,
1430                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1431                                 radeon_dig_connector->edp_on = false;
1432                         }
1433                 }
1434                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1435                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1436                 break;
1437         }
1438 }
1439
1440 static void
1441 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1442                              struct drm_encoder *ext_encoder,
1443                              int mode)
1444 {
1445         struct drm_device *dev = encoder->dev;
1446         struct radeon_device *rdev = dev->dev_private;
1447
1448         switch (mode) {
1449         case DRM_MODE_DPMS_ON:
1450         default:
1451                 if (ASIC_IS_DCE41(rdev)) {
1452                         atombios_external_encoder_setup(encoder, ext_encoder,
1453                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1454                         atombios_external_encoder_setup(encoder, ext_encoder,
1455                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1456                 } else
1457                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1458                 break;
1459         case DRM_MODE_DPMS_STANDBY:
1460         case DRM_MODE_DPMS_SUSPEND:
1461         case DRM_MODE_DPMS_OFF:
1462                 if (ASIC_IS_DCE41(rdev)) {
1463                         atombios_external_encoder_setup(encoder, ext_encoder,
1464                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1465                         atombios_external_encoder_setup(encoder, ext_encoder,
1466                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1467                 } else
1468                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1469                 break;
1470         }
1471 }
1472
1473 static void
1474 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1475 {
1476         struct drm_device *dev = encoder->dev;
1477         struct radeon_device *rdev = dev->dev_private;
1478         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1479         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1480
1481         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1482                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1483                   radeon_encoder->active_device);
1484         switch (radeon_encoder->encoder_id) {
1485         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1486         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1487         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1488         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1489         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1490         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1491         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1492         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1493                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1494                 break;
1495         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1496         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1497         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1498         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1499                 radeon_atom_encoder_dpms_dig(encoder, mode);
1500                 break;
1501         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1502                 if (ASIC_IS_DCE5(rdev)) {
1503                         switch (mode) {
1504                         case DRM_MODE_DPMS_ON:
1505                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1506                                 break;
1507                         case DRM_MODE_DPMS_STANDBY:
1508                         case DRM_MODE_DPMS_SUSPEND:
1509                         case DRM_MODE_DPMS_OFF:
1510                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1511                                 break;
1512                         }
1513                 } else if (ASIC_IS_DCE3(rdev))
1514                         radeon_atom_encoder_dpms_dig(encoder, mode);
1515                 else
1516                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1517                 break;
1518         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1519         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1520                 if (ASIC_IS_DCE5(rdev)) {
1521                         switch (mode) {
1522                         case DRM_MODE_DPMS_ON:
1523                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1524                                 break;
1525                         case DRM_MODE_DPMS_STANDBY:
1526                         case DRM_MODE_DPMS_SUSPEND:
1527                         case DRM_MODE_DPMS_OFF:
1528                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1529                                 break;
1530                         }
1531                 } else
1532                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1533                 break;
1534         default:
1535                 return;
1536         }
1537
1538         if (ext_encoder)
1539                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1540
1541         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1542
1543 }
1544
1545 union crtc_source_param {
1546         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1547         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1548 };
1549
1550 static void
1551 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1552 {
1553         struct drm_device *dev = encoder->dev;
1554         struct radeon_device *rdev = dev->dev_private;
1555         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1556         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1557         union crtc_source_param args;
1558         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1559         uint8_t frev, crev;
1560         struct radeon_encoder_atom_dig *dig;
1561
1562         memset(&args, 0, sizeof(args));
1563
1564         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1565                 return;
1566
1567         switch (frev) {
1568         case 1:
1569                 switch (crev) {
1570                 case 1:
1571                 default:
1572                         if (ASIC_IS_AVIVO(rdev))
1573                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1574                         else {
1575                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1576                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1577                                 } else {
1578                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1579                                 }
1580                         }
1581                         switch (radeon_encoder->encoder_id) {
1582                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1583                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1584                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1585                                 break;
1586                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1587                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1588                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1589                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1590                                 else
1591                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1592                                 break;
1593                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1594                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1595                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1596                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1597                                 break;
1598                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1599                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1600                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1601                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1602                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1603                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1604                                 else
1605                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1606                                 break;
1607                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1608                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1609                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1610                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1611                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1612                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1613                                 else
1614                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1615                                 break;
1616                         }
1617                         break;
1618                 case 2:
1619                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1620                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1621                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1622
1623                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1624                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1625                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1626                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1627                                 else
1628                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1629                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1630                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1631                         } else {
1632                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1633                         }
1634                         switch (radeon_encoder->encoder_id) {
1635                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1636                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1637                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1638                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1639                                 dig = radeon_encoder->enc_priv;
1640                                 switch (dig->dig_encoder) {
1641                                 case 0:
1642                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1643                                         break;
1644                                 case 1:
1645                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1646                                         break;
1647                                 case 2:
1648                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1649                                         break;
1650                                 case 3:
1651                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1652                                         break;
1653                                 case 4:
1654                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1655                                         break;
1656                                 case 5:
1657                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1658                                         break;
1659                                 }
1660                                 break;
1661                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1662                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1663                                 break;
1664                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1665                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1666                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1667                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1668                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1669                                 else
1670                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1671                                 break;
1672                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1673                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1674                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1675                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1676                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1677                                 else
1678                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1679                                 break;
1680                         }
1681                         break;
1682                 }
1683                 break;
1684         default:
1685                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1686                 return;
1687         }
1688
1689         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1690
1691         /* update scratch regs with new routing */
1692         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1693 }
1694
1695 static void
1696 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1697                               struct drm_display_mode *mode)
1698 {
1699         struct drm_device *dev = encoder->dev;
1700         struct radeon_device *rdev = dev->dev_private;
1701         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1702         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1703
1704         /* Funky macbooks */
1705         if ((dev->pdev->device == 0x71C5) &&
1706             (dev->pdev->subsystem_vendor == 0x106b) &&
1707             (dev->pdev->subsystem_device == 0x0080)) {
1708                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1709                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1710
1711                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1712                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1713
1714                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1715                 }
1716         }
1717
1718         /* set scaler clears this on some chips */
1719         if (ASIC_IS_AVIVO(rdev) &&
1720             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1721                 if (ASIC_IS_DCE4(rdev)) {
1722                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1723                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1724                                        EVERGREEN_INTERLEAVE_EN);
1725                         else
1726                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1727                 } else {
1728                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1729                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1730                                        AVIVO_D1MODE_INTERLEAVE_EN);
1731                         else
1732                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1733                 }
1734         }
1735 }
1736
1737 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1738 {
1739         struct drm_device *dev = encoder->dev;
1740         struct radeon_device *rdev = dev->dev_private;
1741         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1742         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1743         struct drm_encoder *test_encoder;
1744         struct radeon_encoder_atom_dig *dig;
1745         uint32_t dig_enc_in_use = 0;
1746
1747         /* DCE4/5 */
1748         if (ASIC_IS_DCE4(rdev)) {
1749                 dig = radeon_encoder->enc_priv;
1750                 if (ASIC_IS_DCE41(rdev)) {
1751                         /* ontario follows DCE4 */
1752                         if (rdev->family == CHIP_PALM) {
1753                                 if (dig->linkb)
1754                                         return 1;
1755                                 else
1756                                         return 0;
1757                         } else
1758                                 /* llano follows DCE3.2 */
1759                                 return radeon_crtc->crtc_id;
1760                 } else {
1761                         switch (radeon_encoder->encoder_id) {
1762                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1763                                 if (dig->linkb)
1764                                         return 1;
1765                                 else
1766                                         return 0;
1767                                 break;
1768                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1769                                 if (dig->linkb)
1770                                         return 3;
1771                                 else
1772                                         return 2;
1773                                 break;
1774                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1775                                 if (dig->linkb)
1776                                         return 5;
1777                                 else
1778                                         return 4;
1779                                 break;
1780                         }
1781                 }
1782         }
1783
1784         /* on DCE32 and encoder can driver any block so just crtc id */
1785         if (ASIC_IS_DCE32(rdev)) {
1786                 return radeon_crtc->crtc_id;
1787         }
1788
1789         /* on DCE3 - LVTMA can only be driven by DIGB */
1790         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1791                 struct radeon_encoder *radeon_test_encoder;
1792
1793                 if (encoder == test_encoder)
1794                         continue;
1795
1796                 if (!radeon_encoder_is_digital(test_encoder))
1797                         continue;
1798
1799                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1800                 dig = radeon_test_encoder->enc_priv;
1801
1802                 if (dig->dig_encoder >= 0)
1803                         dig_enc_in_use |= (1 << dig->dig_encoder);
1804         }
1805
1806         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1807                 if (dig_enc_in_use & 0x2)
1808                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1809                 return 1;
1810         }
1811         if (!(dig_enc_in_use & 1))
1812                 return 0;
1813         return 1;
1814 }
1815
1816 /* This only needs to be called once at startup */
1817 void
1818 radeon_atom_encoder_init(struct radeon_device *rdev)
1819 {
1820         struct drm_device *dev = rdev->ddev;
1821         struct drm_encoder *encoder;
1822
1823         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1824                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1825                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1826
1827                 switch (radeon_encoder->encoder_id) {
1828                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1829                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1830                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1831                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1832                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1833                         break;
1834                 default:
1835                         break;
1836                 }
1837
1838                 if (ext_encoder && ASIC_IS_DCE41(rdev))
1839                         atombios_external_encoder_setup(encoder, ext_encoder,
1840                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1841         }
1842 }
1843
1844 static void
1845 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1846                              struct drm_display_mode *mode,
1847                              struct drm_display_mode *adjusted_mode)
1848 {
1849         struct drm_device *dev = encoder->dev;
1850         struct radeon_device *rdev = dev->dev_private;
1851         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1852
1853         radeon_encoder->pixel_clock = adjusted_mode->clock;
1854
1855         /* need to call this here rather than in prepare() since we need some crtc info */
1856         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1857
1858         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1859                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1860                         atombios_yuv_setup(encoder, true);
1861                 else
1862                         atombios_yuv_setup(encoder, false);
1863         }
1864
1865         switch (radeon_encoder->encoder_id) {
1866         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1867         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1868         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1869         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1870                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1871                 break;
1872         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1873         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1874         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1875         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1876                 /* handled in dpms */
1877                 break;
1878         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1879         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1880         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1881                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1882                 break;
1883         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1884         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1885         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1886         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1887                 atombios_dac_setup(encoder, ATOM_ENABLE);
1888                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1889                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1890                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1891                         else
1892                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1893                 }
1894                 break;
1895         }
1896
1897         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1898
1899         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1900                 r600_hdmi_enable(encoder);
1901                 r600_hdmi_setmode(encoder, adjusted_mode);
1902         }
1903 }
1904
1905 static bool
1906 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1907 {
1908         struct drm_device *dev = encoder->dev;
1909         struct radeon_device *rdev = dev->dev_private;
1910         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1911         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1912
1913         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1914                                        ATOM_DEVICE_CV_SUPPORT |
1915                                        ATOM_DEVICE_CRT_SUPPORT)) {
1916                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1917                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1918                 uint8_t frev, crev;
1919
1920                 memset(&args, 0, sizeof(args));
1921
1922                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1923                         return false;
1924
1925                 args.sDacload.ucMisc = 0;
1926
1927                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1928                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1929                         args.sDacload.ucDacType = ATOM_DAC_A;
1930                 else
1931                         args.sDacload.ucDacType = ATOM_DAC_B;
1932
1933                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1934                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1935                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1936                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1937                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1938                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1939                         if (crev >= 3)
1940                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1941                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1942                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1943                         if (crev >= 3)
1944                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1945                 }
1946
1947                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1948
1949                 return true;
1950         } else
1951                 return false;
1952 }
1953
1954 static enum drm_connector_status
1955 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1956 {
1957         struct drm_device *dev = encoder->dev;
1958         struct radeon_device *rdev = dev->dev_private;
1959         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1960         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1961         uint32_t bios_0_scratch;
1962
1963         if (!atombios_dac_load_detect(encoder, connector)) {
1964                 DRM_DEBUG_KMS("detect returned false \n");
1965                 return connector_status_unknown;
1966         }
1967
1968         if (rdev->family >= CHIP_R600)
1969                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1970         else
1971                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1972
1973         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1974         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1975                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1976                         return connector_status_connected;
1977         }
1978         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1979                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1980                         return connector_status_connected;
1981         }
1982         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1983                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1984                         return connector_status_connected;
1985         }
1986         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1987                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1988                         return connector_status_connected; /* CTV */
1989                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1990                         return connector_status_connected; /* STV */
1991         }
1992         return connector_status_disconnected;
1993 }
1994
1995 static enum drm_connector_status
1996 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1997 {
1998         struct drm_device *dev = encoder->dev;
1999         struct radeon_device *rdev = dev->dev_private;
2000         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2001         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2002         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2003         u32 bios_0_scratch;
2004
2005         if (!ASIC_IS_DCE4(rdev))
2006                 return connector_status_unknown;
2007
2008         if (!ext_encoder)
2009                 return connector_status_unknown;
2010
2011         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2012                 return connector_status_unknown;
2013
2014         /* load detect on the dp bridge */
2015         atombios_external_encoder_setup(encoder, ext_encoder,
2016                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2017
2018         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2019
2020         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2021         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2022                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2023                         return connector_status_connected;
2024         }
2025         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2026                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2027                         return connector_status_connected;
2028         }
2029         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2030                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2031                         return connector_status_connected;
2032         }
2033         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2034                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2035                         return connector_status_connected; /* CTV */
2036                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2037                         return connector_status_connected; /* STV */
2038         }
2039         return connector_status_disconnected;
2040 }
2041
2042 void
2043 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2044 {
2045         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2046
2047         if (ext_encoder)
2048                 /* ddc_setup on the dp bridge */
2049                 atombios_external_encoder_setup(encoder, ext_encoder,
2050                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2051
2052 }
2053
2054 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2055 {
2056         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2057         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2058
2059         if ((radeon_encoder->active_device &
2060              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2061             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2062              ENCODER_OBJECT_ID_NONE)) {
2063                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2064                 if (dig)
2065                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2066         }
2067
2068         radeon_atom_output_lock(encoder, true);
2069
2070         if (connector) {
2071                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2072
2073                 /* select the clock/data port if it uses a router */
2074                 if (radeon_connector->router.cd_valid)
2075                         radeon_router_select_cd_port(radeon_connector);
2076
2077                 /* turn eDP panel on for mode set */
2078                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2079                         atombios_set_edp_panel_power(connector,
2080                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2081         }
2082
2083         /* this is needed for the pll/ss setup to work correctly in some cases */
2084         atombios_set_encoder_crtc_source(encoder);
2085 }
2086
2087 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2088 {
2089         /* need to call this here as we need the crtc set up */
2090         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2091         radeon_atom_output_lock(encoder, false);
2092 }
2093
2094 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2095 {
2096         struct drm_device *dev = encoder->dev;
2097         struct radeon_device *rdev = dev->dev_private;
2098         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2099         struct radeon_encoder_atom_dig *dig;
2100
2101         /* check for pre-DCE3 cards with shared encoders;
2102          * can't really use the links individually, so don't disable
2103          * the encoder if it's in use by another connector
2104          */
2105         if (!ASIC_IS_DCE3(rdev)) {
2106                 struct drm_encoder *other_encoder;
2107                 struct radeon_encoder *other_radeon_encoder;
2108
2109                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2110                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2111                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2112                             drm_helper_encoder_in_use(other_encoder))
2113                                 goto disable_done;
2114                 }
2115         }
2116
2117         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2118
2119         switch (radeon_encoder->encoder_id) {
2120         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2121         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2122         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2123         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2124                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2125                 break;
2126         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2127         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2128         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2129         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2130                 /* handled in dpms */
2131                 break;
2132         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2133         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2134         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2135                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2136                 break;
2137         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2138         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2139         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2140         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2141                 atombios_dac_setup(encoder, ATOM_DISABLE);
2142                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2143                         atombios_tv_setup(encoder, ATOM_DISABLE);
2144                 break;
2145         }
2146
2147 disable_done:
2148         if (radeon_encoder_is_digital(encoder)) {
2149                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2150                         r600_hdmi_disable(encoder);
2151                 dig = radeon_encoder->enc_priv;
2152                 dig->dig_encoder = -1;
2153         }
2154         radeon_encoder->active_device = 0;
2155 }
2156
2157 /* these are handled by the primary encoders */
2158 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2159 {
2160
2161 }
2162
2163 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2164 {
2165
2166 }
2167
2168 static void
2169 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2170                          struct drm_display_mode *mode,
2171                          struct drm_display_mode *adjusted_mode)
2172 {
2173
2174 }
2175
2176 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2177 {
2178
2179 }
2180
2181 static void
2182 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2183 {
2184
2185 }
2186
2187 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2188                                        struct drm_display_mode *mode,
2189                                        struct drm_display_mode *adjusted_mode)
2190 {
2191         return true;
2192 }
2193
2194 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2195         .dpms = radeon_atom_ext_dpms,
2196         .mode_fixup = radeon_atom_ext_mode_fixup,
2197         .prepare = radeon_atom_ext_prepare,
2198         .mode_set = radeon_atom_ext_mode_set,
2199         .commit = radeon_atom_ext_commit,
2200         .disable = radeon_atom_ext_disable,
2201         /* no detect for TMDS/LVDS yet */
2202 };
2203
2204 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2205         .dpms = radeon_atom_encoder_dpms,
2206         .mode_fixup = radeon_atom_mode_fixup,
2207         .prepare = radeon_atom_encoder_prepare,
2208         .mode_set = radeon_atom_encoder_mode_set,
2209         .commit = radeon_atom_encoder_commit,
2210         .disable = radeon_atom_encoder_disable,
2211         .detect = radeon_atom_dig_detect,
2212 };
2213
2214 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2215         .dpms = radeon_atom_encoder_dpms,
2216         .mode_fixup = radeon_atom_mode_fixup,
2217         .prepare = radeon_atom_encoder_prepare,
2218         .mode_set = radeon_atom_encoder_mode_set,
2219         .commit = radeon_atom_encoder_commit,
2220         .detect = radeon_atom_dac_detect,
2221 };
2222
2223 void radeon_enc_destroy(struct drm_encoder *encoder)
2224 {
2225         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2226         kfree(radeon_encoder->enc_priv);
2227         drm_encoder_cleanup(encoder);
2228         kfree(radeon_encoder);
2229 }
2230
2231 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2232         .destroy = radeon_enc_destroy,
2233 };
2234
2235 struct radeon_encoder_atom_dac *
2236 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2237 {
2238         struct drm_device *dev = radeon_encoder->base.dev;
2239         struct radeon_device *rdev = dev->dev_private;
2240         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2241
2242         if (!dac)
2243                 return NULL;
2244
2245         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2246         return dac;
2247 }
2248
2249 struct radeon_encoder_atom_dig *
2250 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2251 {
2252         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2253         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2254
2255         if (!dig)
2256                 return NULL;
2257
2258         /* coherent mode by default */
2259         dig->coherent_mode = true;
2260         dig->dig_encoder = -1;
2261
2262         if (encoder_enum == 2)
2263                 dig->linkb = true;
2264         else
2265                 dig->linkb = false;
2266
2267         return dig;
2268 }
2269
2270 void
2271 radeon_add_atom_encoder(struct drm_device *dev,
2272                         uint32_t encoder_enum,
2273                         uint32_t supported_device,
2274                         u16 caps)
2275 {
2276         struct radeon_device *rdev = dev->dev_private;
2277         struct drm_encoder *encoder;
2278         struct radeon_encoder *radeon_encoder;
2279
2280         /* see if we already added it */
2281         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2282                 radeon_encoder = to_radeon_encoder(encoder);
2283                 if (radeon_encoder->encoder_enum == encoder_enum) {
2284                         radeon_encoder->devices |= supported_device;
2285                         return;
2286                 }
2287
2288         }
2289
2290         /* add a new one */
2291         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2292         if (!radeon_encoder)
2293                 return;
2294
2295         encoder = &radeon_encoder->base;
2296         switch (rdev->num_crtc) {
2297         case 1:
2298                 encoder->possible_crtcs = 0x1;
2299                 break;
2300         case 2:
2301         default:
2302                 encoder->possible_crtcs = 0x3;
2303                 break;
2304         case 4:
2305                 encoder->possible_crtcs = 0xf;
2306                 break;
2307         case 6:
2308                 encoder->possible_crtcs = 0x3f;
2309                 break;
2310         }
2311
2312         radeon_encoder->enc_priv = NULL;
2313
2314         radeon_encoder->encoder_enum = encoder_enum;
2315         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2316         radeon_encoder->devices = supported_device;
2317         radeon_encoder->rmx_type = RMX_OFF;
2318         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2319         radeon_encoder->is_ext_encoder = false;
2320         radeon_encoder->caps = caps;
2321
2322         switch (radeon_encoder->encoder_id) {
2323         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2324         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2325         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2326         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2327                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2328                         radeon_encoder->rmx_type = RMX_FULL;
2329                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2330                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2331                 } else {
2332                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2333                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2334                 }
2335                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2336                 break;
2337         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2338                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2339                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2340                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2341                 break;
2342         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2343         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2344         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2345                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2346                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2347                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2348                 break;
2349         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2350         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2351         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2352         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2353         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2354         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2355         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2356                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2357                         radeon_encoder->rmx_type = RMX_FULL;
2358                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2359                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2360                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2361                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2362                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2363                 } else {
2364                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2365                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2366                 }
2367                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2368                 break;
2369         case ENCODER_OBJECT_ID_SI170B:
2370         case ENCODER_OBJECT_ID_CH7303:
2371         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2372         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2373         case ENCODER_OBJECT_ID_TITFP513:
2374         case ENCODER_OBJECT_ID_VT1623:
2375         case ENCODER_OBJECT_ID_HDMI_SI1930:
2376         case ENCODER_OBJECT_ID_TRAVIS:
2377         case ENCODER_OBJECT_ID_NUTMEG:
2378                 /* these are handled by the primary encoders */
2379                 radeon_encoder->is_ext_encoder = true;
2380                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2381                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2382                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2383                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2384                 else
2385                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2386                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2387                 break;
2388         }
2389 }