drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38
  39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  40 {
  41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  42         switch (radeon_encoder->encoder_id) {
  43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
  50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  54                 return true;
  55         default:
  56                 return false;
  57         }
  58 }
  59
  60 static struct drm_connector *
  61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
  62 {
  63         struct drm_device *dev = encoder->dev;
  64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  65         struct drm_connector *connector;
  66         struct radeon_connector *radeon_connector;
  67
  68         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  69                 radeon_connector = to_radeon_connector(connector);
  70                 if (radeon_encoder->devices & radeon_connector->devices)
  71                         return connector;
  72         }
  73         return NULL;
  74 }
  75
  76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  77                                    struct drm_display_mode *mode,
  78                                    struct drm_display_mode *adjusted_mode)
  79 {
  80         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  81         struct drm_device *dev = encoder->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83
  84         /* set the active encoder to connector routing */
  85         radeon_encoder_set_active_device(encoder);
  86         drm_mode_set_crtcinfo(adjusted_mode, 0);
  87
  88         /* hw bug */
  89         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  90             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  91                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  92
  93         /* get the native mode for LVDS */
  94         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  95                 radeon_panel_mode_fixup(encoder, adjusted_mode);
  96
  97         /* get the native mode for TV */
  98         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
  99                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 100                 if (tv_dac) {
 101                         if (tv_dac->tv_std == TV_STD_NTSC ||
 102                             tv_dac->tv_std == TV_STD_NTSC_J ||
 103                             tv_dac->tv_std == TV_STD_PAL_M)
 104                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 105                         else
 106                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 107                 }
 108         }
 109
 110         if (ASIC_IS_DCE3(rdev) &&
 111             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 112              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 113                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 114                 radeon_dp_set_link_config(connector, mode);
 115         }
 116
 117         return true;
 118 }
 119
 120 static void
 121 atombios_dac_setup(struct drm_encoder *encoder, int action)
 122 {
 123         struct drm_device *dev = encoder->dev;
 124         struct radeon_device *rdev = dev->dev_private;
 125         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 126         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 127         int index = 0;
 128         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 129
 130         memset(&args, 0, sizeof(args));
 131
 132         switch (radeon_encoder->encoder_id) {
 133         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 134         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 135                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 136                 break;
 137         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 138         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 139                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 140                 break;
 141         }
 142
 143         args.ucAction = action;
 144
 145         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 146                 args.ucDacStandard = ATOM_DAC1_PS2;
 147         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 148                 args.ucDacStandard = ATOM_DAC1_CV;
 149         else {
 150                 switch (dac_info->tv_std) {
 151                 case TV_STD_PAL:
 152                 case TV_STD_PAL_M:
 153                 case TV_STD_SCART_PAL:
 154                 case TV_STD_SECAM:
 155                 case TV_STD_PAL_CN:
 156                         args.ucDacStandard = ATOM_DAC1_PAL;
 157                         break;
 158                 case TV_STD_NTSC:
 159                 case TV_STD_NTSC_J:
 160                 case TV_STD_PAL_60:
 161                 default:
 162                         args.ucDacStandard = ATOM_DAC1_NTSC;
 163                         break;
 164                 }
 165         }
 166         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 167
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169
 170 }
 171
 172 static void
 173 atombios_tv_setup(struct drm_encoder *encoder, int action)
 174 {
 175         struct drm_device *dev = encoder->dev;
 176         struct radeon_device *rdev = dev->dev_private;
 177         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 178         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 179         int index = 0;
 180         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 181
 182         memset(&args, 0, sizeof(args));
 183
 184         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 185
 186         args.sTVEncoder.ucAction = action;
 187
 188         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 189                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 190         else {
 191                 switch (dac_info->tv_std) {
 192                 case TV_STD_NTSC:
 193                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 194                         break;
 195                 case TV_STD_PAL:
 196                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 197                         break;
 198                 case TV_STD_PAL_M:
 199                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 200                         break;
 201                 case TV_STD_PAL_60:
 202                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 203                         break;
 204                 case TV_STD_NTSC_J:
 205                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 206                         break;
 207                 case TV_STD_SCART_PAL:
 208                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 209                         break;
 210                 case TV_STD_SECAM:
 211                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 212                         break;
 213                 case TV_STD_PAL_CN:
 214                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 215                         break;
 216                 default:
 217                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 218                         break;
 219                 }
 220         }
 221
 222         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 223
 224         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 225
 226 }
 227
 228 union dvo_encoder_control {
 229         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 230         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 231         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 232 };
 233
 234 void
 235 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 236 {
 237         struct drm_device *dev = encoder->dev;
 238         struct radeon_device *rdev = dev->dev_private;
 239         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 240         union dvo_encoder_control args;
 241         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 242         uint8_t frev, crev;
 243
 244         memset(&args, 0, sizeof(args));
 245
 246         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 247                 return;
 248
 249         switch (frev) {
 250         case 1:
 251                 switch (crev) {
 252                 case 1:
 253                         /* R4xx, R5xx */
 254                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 255
 256                         if (radeon_encoder->pixel_clock > 165000)
 257                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 258
 259                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 260                         break;
 261                 case 2:
 262                         /* RS600/690/740 */
 263                         args.dvo.sDVOEncoder.ucAction = action;
 264                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 265                         /* DFP1, CRT1, TV1 depending on the type of port */
 266                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 267
 268                         if (radeon_encoder->pixel_clock > 165000)
 269                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 270                         break;
 271                 case 3:
 272                         /* R6xx */
 273                         args.dvo_v3.ucAction = action;
 274                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 275                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 276                         break;
 277                 default:
 278                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 279                         break;
 280                 }
 281                 break;
 282         default:
 283                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 284                 break;
 285         }
 286
 287         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 288 }
 289
 290 union lvds_encoder_control {
 291         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 292         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 293 };
 294
 295 void
 296 atombios_digital_setup(struct drm_encoder *encoder, int action)
 297 {
 298         struct drm_device *dev = encoder->dev;
 299         struct radeon_device *rdev = dev->dev_private;
 300         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 301         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 302         union lvds_encoder_control args;
 303         int index = 0;
 304         int hdmi_detected = 0;
 305         uint8_t frev, crev;
 306
 307         if (!dig)
 308                 return;
 309
 310         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 311                 hdmi_detected = 1;
 312
 313         memset(&args, 0, sizeof(args));
 314
 315         switch (radeon_encoder->encoder_id) {
 316         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 317                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 318                 break;
 319         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 320         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 321                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 322                 break;
 323         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 324                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 325                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 326                 else
 327                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 328                 break;
 329         }
 330
 331         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 332                 return;
 333
 334         switch (frev) {
 335         case 1:
 336         case 2:
 337                 switch (crev) {
 338                 case 1:
 339                         args.v1.ucMisc = 0;
 340                         args.v1.ucAction = action;
 341                         if (hdmi_detected)
 342                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 343                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 344                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 345                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 346                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 347                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 348                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 349                         } else {
 350                                 if (dig->linkb)
 351                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 352                                 if (radeon_encoder->pixel_clock > 165000)
 353                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 354                                 /*if (pScrn->rgbBits == 8) */
 355                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 356                         }
 357                         break;
 358                 case 2:
 359                 case 3:
 360                         args.v2.ucMisc = 0;
 361                         args.v2.ucAction = action;
 362                         if (crev == 3) {
 363                                 if (dig->coherent_mode)
 364                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 365                         }
 366                         if (hdmi_detected)
 367                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 368                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 369                         args.v2.ucTruncate = 0;
 370                         args.v2.ucSpatial = 0;
 371                         args.v2.ucTemporal = 0;
 372                         args.v2.ucFRC = 0;
 373                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 374                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 375                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 376                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 377                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 378                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 379                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 380                                 }
 381                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 382                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 383                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 384                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 385                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 386                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 387                                 }
 388                         } else {
 389                                 if (dig->linkb)
 390                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 391                                 if (radeon_encoder->pixel_clock > 165000)
 392                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 393                         }
 394                         break;
 395                 default:
 396                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 397                         break;
 398                 }
 399                 break;
 400         default:
 401                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 402                 break;
 403         }
 404
 405         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 406 }
 407
 408 int
 409 atombios_get_encoder_mode(struct drm_encoder *encoder)
 410 {
 411         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 412         struct drm_device *dev = encoder->dev;
 413         struct radeon_device *rdev = dev->dev_private;
 414         struct drm_connector *connector;
 415         struct radeon_connector *radeon_connector;
 416         struct radeon_connector_atom_dig *dig_connector;
 417
 418         /* dp bridges are always DP */
 419         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 420                 return ATOM_ENCODER_MODE_DP;
 421
 422         /* DVO is always DVO */
 423         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
 424                 return ATOM_ENCODER_MODE_DVO;
 425
 426         connector = radeon_get_connector_for_encoder(encoder);
 427         /* if we don't have an active device yet, just use one of
 428          * the connectors tied to the encoder.
 429          */
 430         if (!connector)
 431                 connector = radeon_get_connector_for_encoder_init(encoder);
 432         radeon_connector = to_radeon_connector(connector);
 433
 434         switch (connector->connector_type) {
 435         case DRM_MODE_CONNECTOR_DVII:
 436         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 437                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 438                         /* fix me */
 439                         if (ASIC_IS_DCE4(rdev))
 440                                 return ATOM_ENCODER_MODE_DVI;
 441                         else
 442                                 return ATOM_ENCODER_MODE_HDMI;
 443                 } else if (radeon_connector->use_digital)
 444                         return ATOM_ENCODER_MODE_DVI;
 445                 else
 446                         return ATOM_ENCODER_MODE_CRT;
 447                 break;
 448         case DRM_MODE_CONNECTOR_DVID:
 449         case DRM_MODE_CONNECTOR_HDMIA:
 450         default:
 451                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 452                         /* fix me */
 453                         if (ASIC_IS_DCE4(rdev))
 454                                 return ATOM_ENCODER_MODE_DVI;
 455                         else
 456                                 return ATOM_ENCODER_MODE_HDMI;
 457                 } else
 458                         return ATOM_ENCODER_MODE_DVI;
 459                 break;
 460         case DRM_MODE_CONNECTOR_LVDS:
 461                 return ATOM_ENCODER_MODE_LVDS;
 462                 break;
 463         case DRM_MODE_CONNECTOR_DisplayPort:
 464                 dig_connector = radeon_connector->con_priv;
 465                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 466                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 467                         return ATOM_ENCODER_MODE_DP;
 468                 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 469                         /* fix me */
 470                         if (ASIC_IS_DCE4(rdev))
 471                                 return ATOM_ENCODER_MODE_DVI;
 472                         else
 473                                 return ATOM_ENCODER_MODE_HDMI;
 474                 } else
 475                         return ATOM_ENCODER_MODE_DVI;
 476                 break;
 477         case DRM_MODE_CONNECTOR_eDP:
 478                 return ATOM_ENCODER_MODE_DP;
 479         case DRM_MODE_CONNECTOR_DVIA:
 480         case DRM_MODE_CONNECTOR_VGA:
 481                 return ATOM_ENCODER_MODE_CRT;
 482                 break;
 483         case DRM_MODE_CONNECTOR_Composite:
 484         case DRM_MODE_CONNECTOR_SVIDEO:
 485         case DRM_MODE_CONNECTOR_9PinDIN:
 486                 /* fix me */
 487                 return ATOM_ENCODER_MODE_TV;
 488                 /*return ATOM_ENCODER_MODE_CV;*/
 489                 break;
 490         }
 491 }
 492
 493 /*
 494  * DIG Encoder/Transmitter Setup
 495  *
 496  * DCE 3.0/3.1
 497  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 498  * Supports up to 3 digital outputs
 499  * - 2 DIG encoder blocks.
 500  * DIG1 can drive UNIPHY link A or link B
 501  * DIG2 can drive UNIPHY link B or LVTMA
 502  *
 503  * DCE 3.2
 504  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 505  * Supports up to 5 digital outputs
 506  * - 2 DIG encoder blocks.
 507  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 508  *
 509  * DCE 4.0/5.0
 510  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 511  * Supports up to 6 digital outputs
 512  * - 6 DIG encoder blocks.
 513  * - DIG to PHY mapping is hardcoded
 514  * DIG1 drives UNIPHY0 link A, A+B
 515  * DIG2 drives UNIPHY0 link B
 516  * DIG3 drives UNIPHY1 link A, A+B
 517  * DIG4 drives UNIPHY1 link B
 518  * DIG5 drives UNIPHY2 link A, A+B
 519  * DIG6 drives UNIPHY2 link B
 520  *
 521  * DCE 4.1
 522  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 523  * Supports up to 6 digital outputs
 524  * - 2 DIG encoder blocks.
 525  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 526  *
 527  * Routing
 528  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 529  * Examples:
 530  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 531  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 532  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 533  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 534  */
 535
 536 union dig_encoder_control {
 537         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 538         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 539         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 540         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 541 };
 542
 543 void
 544 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 545 {
 546         struct drm_device *dev = encoder->dev;
 547         struct radeon_device *rdev = dev->dev_private;
 548         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 549         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 550         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 551         union dig_encoder_control args;
 552         int index = 0;
 553         uint8_t frev, crev;
 554         int dp_clock = 0;
 555         int dp_lane_count = 0;
 556         int hpd_id = RADEON_HPD_NONE;
 557         int bpc = 8;
 558
 559         if (connector) {
 560                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 561                 struct radeon_connector_atom_dig *dig_connector =
 562                         radeon_connector->con_priv;
 563
 564                 dp_clock = dig_connector->dp_clock;
 565                 dp_lane_count = dig_connector->dp_lane_count;
 566                 hpd_id = radeon_connector->hpd.hpd;
 567                 bpc = connector->display_info.bpc;
 568         }
 569
 570         /* no dig encoder assigned */
 571         if (dig->dig_encoder == -1)
 572                 return;
 573
 574         memset(&args, 0, sizeof(args));
 575
 576         if (ASIC_IS_DCE4(rdev))
 577                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 578         else {
 579                 if (dig->dig_encoder)
 580                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 581                 else
 582                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 583         }
 584
 585         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 586                 return;
 587
 588         args.v1.ucAction = action;
 589         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 590         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 591                 args.v3.ucPanelMode = panel_mode;
 592         else
 593                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 594
 595         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 596                 args.v1.ucLaneNum = dp_lane_count;
 597         else if (radeon_encoder->pixel_clock > 165000)
 598                 args.v1.ucLaneNum = 8;
 599         else
 600                 args.v1.ucLaneNum = 4;
 601
 602         if (ASIC_IS_DCE5(rdev)) {
 603                 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
 604                         if (dp_clock == 270000)
 605                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 606                         else if (dp_clock == 540000)
 607                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 608                 }
 609                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 610                 switch (bpc) {
 611                 case 0:
 612                         args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 613                         break;
 614                 case 6:
 615                         args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 616                         break;
 617                 case 8:
 618                 default:
 619                         args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 620                         break;
 621                 case 10:
 622                         args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 623                         break;
 624                 case 12:
 625                         args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 626                         break;
 627                 case 16:
 628                         args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 629                         break;
 630                 }
 631                 if (hpd_id == RADEON_HPD_NONE)
 632                         args.v4.ucHPD_ID = 0;
 633                 else
 634                         args.v4.ucHPD_ID = hpd_id + 1;
 635         } else if (ASIC_IS_DCE4(rdev)) {
 636                 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 637                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 638                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 639                 switch (bpc) {
 640                 case 0:
 641                         args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 642                         break;
 643                 case 6:
 644                         args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 645                         break;
 646                 case 8:
 647                 default:
 648                         args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 649                         break;
 650                 case 10:
 651                         args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 652                         break;
 653                 case 12:
 654                         args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 655                         break;
 656                 case 16:
 657                         args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 658                         break;
 659                 }
 660         } else {
 661                 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 662                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 663                 switch (radeon_encoder->encoder_id) {
 664                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 665                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 666                         break;
 667                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 668                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 669                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 670                         break;
 671                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 672                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 673                         break;
 674                 }
 675                 if (dig->linkb)
 676                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 677                 else
 678                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 679         }
 680
 681         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 682
 683 }
 684
 685 union dig_transmitter_control {
 686         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 687         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 688         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 689         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 690 };
 691
 692 void
 693 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 694 {
 695         struct drm_device *dev = encoder->dev;
 696         struct radeon_device *rdev = dev->dev_private;
 697         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 698         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 699         struct drm_connector *connector;
 700         union dig_transmitter_control args;
 701         int index = 0;
 702         uint8_t frev, crev;
 703         bool is_dp = false;
 704         int pll_id = 0;
 705         int dp_clock = 0;
 706         int dp_lane_count = 0;
 707         int connector_object_id = 0;
 708         int igp_lane_info = 0;
 709         int dig_encoder = dig->dig_encoder;
 710
 711         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 712                 connector = radeon_get_connector_for_encoder_init(encoder);
 713                 /* just needed to avoid bailing in the encoder check.  the encoder
 714                  * isn't used for init
 715                  */
 716                 dig_encoder = 0;
 717         } else
 718                 connector = radeon_get_connector_for_encoder(encoder);
 719
 720         if (connector) {
 721                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 722                 struct radeon_connector_atom_dig *dig_connector =
 723                         radeon_connector->con_priv;
 724
 725                 dp_clock = dig_connector->dp_clock;
 726                 dp_lane_count = dig_connector->dp_lane_count;
 727                 connector_object_id =
 728                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 729                 igp_lane_info = dig_connector->igp_lane_info;
 730         }
 731
 732         /* no dig encoder assigned */
 733         if (dig_encoder == -1)
 734                 return;
 735
 736         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
 737                 is_dp = true;
 738
 739         memset(&args, 0, sizeof(args));
 740
 741         switch (radeon_encoder->encoder_id) {
 742         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 743                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 744                 break;
 745         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 746         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 747         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 748                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 749                 break;
 750         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 751                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 752                 break;
 753         }
 754
 755         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 756                 return;
 757
 758         args.v1.ucAction = action;
 759         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 760                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
 761         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 762                 args.v1.asMode.ucLaneSel = lane_num;
 763                 args.v1.asMode.ucLaneSet = lane_set;
 764         } else {
 765                 if (is_dp)
 766                         args.v1.usPixelClock =
 767                                 cpu_to_le16(dp_clock / 10);
 768                 else if (radeon_encoder->pixel_clock > 165000)
 769                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 770                 else
 771                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 772         }
 773         if (ASIC_IS_DCE4(rdev)) {
 774                 if (is_dp)
 775                         args.v3.ucLaneNum = dp_lane_count;
 776                 else if (radeon_encoder->pixel_clock > 165000)
 777                         args.v3.ucLaneNum = 8;
 778                 else
 779                         args.v3.ucLaneNum = 4;
 780
 781                 if (dig->linkb)
 782                         args.v3.acConfig.ucLinkSel = 1;
 783                 if (dig_encoder & 1)
 784                         args.v3.acConfig.ucEncoderSel = 1;
 785
 786                 /* Select the PLL for the PHY
 787                  * DP PHY should be clocked from external src if there is
 788                  * one.
 789                  */
 790                 if (encoder->crtc) {
 791                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 792                         pll_id = radeon_crtc->pll_id;
 793                 }
 794
 795                 if (ASIC_IS_DCE5(rdev)) {
 796                         /* On DCE5 DCPLL usually generates the DP ref clock */
 797                         if (is_dp) {
 798                                 if (rdev->clock.dp_extclk)
 799                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
 800                                 else
 801                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
 802                         } else
 803                                 args.v4.acConfig.ucRefClkSource = pll_id;
 804                 } else {
 805                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
 806                         if (is_dp && rdev->clock.dp_extclk)
 807                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
 808                         else
 809                                 args.v3.acConfig.ucRefClkSource = pll_id;
 810                 }
 811
 812                 switch (radeon_encoder->encoder_id) {
 813                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 814                         args.v3.acConfig.ucTransmitterSel = 0;
 815                         break;
 816                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 817                         args.v3.acConfig.ucTransmitterSel = 1;
 818                         break;
 819                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 820                         args.v3.acConfig.ucTransmitterSel = 2;
 821                         break;
 822                 }
 823
 824                 if (is_dp)
 825                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 826                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 827                         if (dig->coherent_mode)
 828                                 args.v3.acConfig.fCoherentMode = 1;
 829                         if (radeon_encoder->pixel_clock > 165000)
 830                                 args.v3.acConfig.fDualLinkConnector = 1;
 831                 }
 832         } else if (ASIC_IS_DCE32(rdev)) {
 833                 args.v2.acConfig.ucEncoderSel = dig_encoder;
 834                 if (dig->linkb)
 835                         args.v2.acConfig.ucLinkSel = 1;
 836
 837                 switch (radeon_encoder->encoder_id) {
 838                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 839                         args.v2.acConfig.ucTransmitterSel = 0;
 840                         break;
 841                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 842                         args.v2.acConfig.ucTransmitterSel = 1;
 843                         break;
 844                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 845                         args.v2.acConfig.ucTransmitterSel = 2;
 846                         break;
 847                 }
 848
 849                 if (is_dp) {
 850                         args.v2.acConfig.fCoherentMode = 1;
 851                         args.v2.acConfig.fDPConnector = 1;
 852                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 853                         if (dig->coherent_mode)
 854                                 args.v2.acConfig.fCoherentMode = 1;
 855                         if (radeon_encoder->pixel_clock > 165000)
 856                                 args.v2.acConfig.fDualLinkConnector = 1;
 857                 }
 858         } else {
 859                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 860
 861                 if (dig_encoder)
 862                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 863                 else
 864                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 865
 866                 if ((rdev->flags & RADEON_IS_IGP) &&
 867                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 868                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 869                                 if (igp_lane_info & 0x1)
 870                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 871                                 else if (igp_lane_info & 0x2)
 872                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 873                                 else if (igp_lane_info & 0x4)
 874                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 875                                 else if (igp_lane_info & 0x8)
 876                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 877                         } else {
 878                                 if (igp_lane_info & 0x3)
 879                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 880                                 else if (igp_lane_info & 0xc)
 881                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 882                         }
 883                 }
 884
 885                 if (dig->linkb)
 886                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 887                 else
 888                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 889
 890                 if (is_dp)
 891                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 892                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 893                         if (dig->coherent_mode)
 894                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 895                         if (radeon_encoder->pixel_clock > 165000)
 896                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 897                 }
 898         }
 899
 900         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 901 }
 902
 903 bool
 904 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
 905 {
 906         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 907         struct drm_device *dev = radeon_connector->base.dev;
 908         struct radeon_device *rdev = dev->dev_private;
 909         union dig_transmitter_control args;
 910         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 911         uint8_t frev, crev;
 912
 913         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
 914                 goto done;
 915
 916         if (!ASIC_IS_DCE4(rdev))
 917                 goto done;
 918
 919         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
 920             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
 921                 goto done;
 922
 923         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 924                 goto done;
 925
 926         memset(&args, 0, sizeof(args));
 927
 928         args.v1.ucAction = action;
 929
 930         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 931
 932         /* wait for the panel to power up */
 933         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
 934                 int i;
 935
 936                 for (i = 0; i < 300; i++) {
 937                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
 938                                 return true;
 939                         mdelay(1);
 940                 }
 941                 return false;
 942         }
 943 done:
 944         return true;
 945 }
 946
 947 union external_encoder_control {
 948         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
 949         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
 950 };
 951
 952 static void
 953 atombios_external_encoder_setup(struct drm_encoder *encoder,
 954                                 struct drm_encoder *ext_encoder,
 955                                 int action)
 956 {
 957         struct drm_device *dev = encoder->dev;
 958         struct radeon_device *rdev = dev->dev_private;
 959         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 960         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
 961         union external_encoder_control args;
 962         struct drm_connector *connector;
 963         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
 964         u8 frev, crev;
 965         int dp_clock = 0;
 966         int dp_lane_count = 0;
 967         int connector_object_id = 0;
 968         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 969         int bpc = 8;
 970
 971         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
 972                 connector = radeon_get_connector_for_encoder_init(encoder);
 973         else
 974                 connector = radeon_get_connector_for_encoder(encoder);
 975
 976         if (connector) {
 977                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 978                 struct radeon_connector_atom_dig *dig_connector =
 979                         radeon_connector->con_priv;
 980
 981                 dp_clock = dig_connector->dp_clock;
 982                 dp_lane_count = dig_connector->dp_lane_count;
 983                 connector_object_id =
 984                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 985                 bpc = connector->display_info.bpc;
 986         }
 987
 988         memset(&args, 0, sizeof(args));
 989
 990         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 991                 return;
 992
 993         switch (frev) {
 994         case 1:
 995                 /* no params on frev 1 */
 996                 break;
 997         case 2:
 998                 switch (crev) {
 999                 case 1:
1000                 case 2:
1001                         args.v1.sDigEncoder.ucAction = action;
1002                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1003                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1004
1005                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1006                                 if (dp_clock == 270000)
1007                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1008                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1009                         } else if (radeon_encoder->pixel_clock > 165000)
1010                                 args.v1.sDigEncoder.ucLaneNum = 8;
1011                         else
1012                                 args.v1.sDigEncoder.ucLaneNum = 4;
1013                         break;
1014                 case 3:
1015                         args.v3.sExtEncoder.ucAction = action;
1016                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1017                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1018                         else
1019                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1020                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1021
1022                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1023                                 if (dp_clock == 270000)
1024                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1025                                 else if (dp_clock == 540000)
1026                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1027                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1028                         } else if (radeon_encoder->pixel_clock > 165000)
1029                                 args.v3.sExtEncoder.ucLaneNum = 8;
1030                         else
1031                                 args.v3.sExtEncoder.ucLaneNum = 4;
1032                         switch (ext_enum) {
1033                         case GRAPH_OBJECT_ENUM_ID1:
1034                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1035                                 break;
1036                         case GRAPH_OBJECT_ENUM_ID2:
1037                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1038                                 break;
1039                         case GRAPH_OBJECT_ENUM_ID3:
1040                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1041                                 break;
1042                         }
1043                         switch (bpc) {
1044                         case 0:
1045                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1046                                 break;
1047                         case 6:
1048                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1049                                 break;
1050                         case 8:
1051                         default:
1052                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1053                                 break;
1054                         case 10:
1055                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1056                                 break;
1057                         case 12:
1058                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1059                                 break;
1060                         case 16:
1061                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1062                                 break;
1063                         }
1064                         break;
1065                 default:
1066                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1067                         return;
1068                 }
1069                 break;
1070         default:
1071                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1072                 return;
1073         }
1074         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1075 }
1076
1077 static void
1078 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1079 {
1080         struct drm_device *dev = encoder->dev;
1081         struct radeon_device *rdev = dev->dev_private;
1082         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1083         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1084         ENABLE_YUV_PS_ALLOCATION args;
1085         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1086         uint32_t temp, reg;
1087
1088         memset(&args, 0, sizeof(args));
1089
1090         if (rdev->family >= CHIP_R600)
1091                 reg = R600_BIOS_3_SCRATCH;
1092         else
1093                 reg = RADEON_BIOS_3_SCRATCH;
1094
1095         /* XXX: fix up scratch reg handling */
1096         temp = RREG32(reg);
1097         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1098                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1099                              (radeon_crtc->crtc_id << 18)));
1100         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1101                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1102         else
1103                 WREG32(reg, 0);
1104
1105         if (enable)
1106                 args.ucEnable = ATOM_ENABLE;
1107         args.ucCRTC = radeon_crtc->crtc_id;
1108
1109         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1110
1111         WREG32(reg, temp);
1112 }
1113
1114 static void
1115 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1116 {
1117         struct drm_device *dev = encoder->dev;
1118         struct radeon_device *rdev = dev->dev_private;
1119         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1120         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1121         int index = 0;
1122
1123         memset(&args, 0, sizeof(args));
1124
1125         switch (radeon_encoder->encoder_id) {
1126         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1127         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1128                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1129                 break;
1130         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1131         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1132         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1133                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1134                 break;
1135         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1136                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1137                 break;
1138         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1139                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1140                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1141                 else
1142                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1143                 break;
1144         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1145         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1146                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1147                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1148                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1149                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1150                 else
1151                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1152                 break;
1153         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1154         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1155                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1156                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1157                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1158                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1159                 else
1160                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1161                 break;
1162         default:
1163                 return;
1164         }
1165
1166         switch (mode) {
1167         case DRM_MODE_DPMS_ON:
1168                 args.ucAction = ATOM_ENABLE;
1169                 /* workaround for DVOOutputControl on some RS690 systems */
1170                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1171                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1172                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1173                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1174                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1175                 } else
1176                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1177                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1178                         args.ucAction = ATOM_LCD_BLON;
1179                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1180                 }
1181                 break;
1182         case DRM_MODE_DPMS_STANDBY:
1183         case DRM_MODE_DPMS_SUSPEND:
1184         case DRM_MODE_DPMS_OFF:
1185                 args.ucAction = ATOM_DISABLE;
1186                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1187                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1188                         args.ucAction = ATOM_LCD_BLOFF;
1189                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1190                 }
1191                 break;
1192         }
1193 }
1194
1195 static void
1196 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1197 {
1198         struct drm_device *dev = encoder->dev;
1199         struct radeon_device *rdev = dev->dev_private;
1200         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1201         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1202         struct radeon_connector *radeon_connector = NULL;
1203         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1204
1205         if (connector) {
1206                 radeon_connector = to_radeon_connector(connector);
1207                 radeon_dig_connector = radeon_connector->con_priv;
1208         }
1209
1210         switch (mode) {
1211         case DRM_MODE_DPMS_ON:
1212                 /* some early dce3.2 boards have a bug in their transmitter control table */
1213                 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1214                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1215                 else
1216                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1217                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1218                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1219                                 atombios_set_edp_panel_power(connector,
1220                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1221                                 radeon_dig_connector->edp_on = true;
1222                         }
1223                         if (ASIC_IS_DCE4(rdev))
1224                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1225                         radeon_dp_link_train(encoder, connector);
1226                         if (ASIC_IS_DCE4(rdev))
1227                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1228                 }
1229                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1230                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1231                 break;
1232         case DRM_MODE_DPMS_STANDBY:
1233         case DRM_MODE_DPMS_SUSPEND:
1234         case DRM_MODE_DPMS_OFF:
1235                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1236                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1237                         if (ASIC_IS_DCE4(rdev))
1238                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1239                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1240                                 atombios_set_edp_panel_power(connector,
1241                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1242                                 radeon_dig_connector->edp_on = false;
1243                         }
1244                 }
1245                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1246                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1247                 break;
1248         }
1249 }
1250
1251 static void
1252 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1253                              struct drm_encoder *ext_encoder,
1254                              int mode)
1255 {
1256         struct drm_device *dev = encoder->dev;
1257         struct radeon_device *rdev = dev->dev_private;
1258
1259         switch (mode) {
1260         case DRM_MODE_DPMS_ON:
1261         default:
1262                 if (ASIC_IS_DCE41(rdev)) {
1263                         atombios_external_encoder_setup(encoder, ext_encoder,
1264                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1265                         atombios_external_encoder_setup(encoder, ext_encoder,
1266                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1267                 } else
1268                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1269                 break;
1270         case DRM_MODE_DPMS_STANDBY:
1271         case DRM_MODE_DPMS_SUSPEND:
1272         case DRM_MODE_DPMS_OFF:
1273                 if (ASIC_IS_DCE41(rdev)) {
1274                         atombios_external_encoder_setup(encoder, ext_encoder,
1275                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1276                         atombios_external_encoder_setup(encoder, ext_encoder,
1277                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1278                 } else
1279                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1280                 break;
1281         }
1282 }
1283
1284 static void
1285 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1286 {
1287         struct drm_device *dev = encoder->dev;
1288         struct radeon_device *rdev = dev->dev_private;
1289         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1290         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1291
1292         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1293                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1294                   radeon_encoder->active_device);
1295         switch (radeon_encoder->encoder_id) {
1296         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1298         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1299         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1300         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1301         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1302         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1303         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1304                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1305                 break;
1306         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1307         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1308         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1309         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1310                 radeon_atom_encoder_dpms_dig(encoder, mode);
1311                 break;
1312         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1313                 if (ASIC_IS_DCE5(rdev)) {
1314                         switch (mode) {
1315                         case DRM_MODE_DPMS_ON:
1316                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1317                                 break;
1318                         case DRM_MODE_DPMS_STANDBY:
1319                         case DRM_MODE_DPMS_SUSPEND:
1320                         case DRM_MODE_DPMS_OFF:
1321                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1322                                 break;
1323                         }
1324                 } else if (ASIC_IS_DCE3(rdev))
1325                         radeon_atom_encoder_dpms_dig(encoder, mode);
1326                 else
1327                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1328                 break;
1329         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1330         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1331                 if (ASIC_IS_DCE5(rdev)) {
1332                         switch (mode) {
1333                         case DRM_MODE_DPMS_ON:
1334                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1335                                 break;
1336                         case DRM_MODE_DPMS_STANDBY:
1337                         case DRM_MODE_DPMS_SUSPEND:
1338                         case DRM_MODE_DPMS_OFF:
1339                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1340                                 break;
1341                         }
1342                 } else
1343                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1344                 break;
1345         default:
1346                 return;
1347         }
1348
1349         if (ext_encoder)
1350                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1351
1352         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1353
1354 }
1355
1356 union crtc_source_param {
1357         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1358         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1359 };
1360
1361 static void
1362 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1363 {
1364         struct drm_device *dev = encoder->dev;
1365         struct radeon_device *rdev = dev->dev_private;
1366         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1367         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1368         union crtc_source_param args;
1369         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1370         uint8_t frev, crev;
1371         struct radeon_encoder_atom_dig *dig;
1372
1373         memset(&args, 0, sizeof(args));
1374
1375         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1376                 return;
1377
1378         switch (frev) {
1379         case 1:
1380                 switch (crev) {
1381                 case 1:
1382                 default:
1383                         if (ASIC_IS_AVIVO(rdev))
1384                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1385                         else {
1386                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1387                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1388                                 } else {
1389                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1390                                 }
1391                         }
1392                         switch (radeon_encoder->encoder_id) {
1393                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1394                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1395                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1396                                 break;
1397                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1398                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1399                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1400                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1401                                 else
1402                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1403                                 break;
1404                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1405                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1406                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1407                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1408                                 break;
1409                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1410                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1411                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1412                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1413                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1414                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1415                                 else
1416                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1417                                 break;
1418                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1419                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1420                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1421                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1422                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1423                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1424                                 else
1425                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1426                                 break;
1427                         }
1428                         break;
1429                 case 2:
1430                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1431                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1432                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1433
1434                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1435                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1436                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1437                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1438                                 else
1439                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1440                         } else
1441                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1442                         switch (radeon_encoder->encoder_id) {
1443                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1444                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1445                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1446                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1447                                 dig = radeon_encoder->enc_priv;
1448                                 switch (dig->dig_encoder) {
1449                                 case 0:
1450                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1451                                         break;
1452                                 case 1:
1453                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1454                                         break;
1455                                 case 2:
1456                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1457                                         break;
1458                                 case 3:
1459                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1460                                         break;
1461                                 case 4:
1462                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1463                                         break;
1464                                 case 5:
1465                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1466                                         break;
1467                                 }
1468                                 break;
1469                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1470                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1471                                 break;
1472                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1473                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1474                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1475                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1476                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1477                                 else
1478                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1479                                 break;
1480                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1481                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1482                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1483                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1484                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1485                                 else
1486                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1487                                 break;
1488                         }
1489                         break;
1490                 }
1491                 break;
1492         default:
1493                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1494                 return;
1495         }
1496
1497         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1498
1499         /* update scratch regs with new routing */
1500         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1501 }
1502
1503 static void
1504 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1505                               struct drm_display_mode *mode)
1506 {
1507         struct drm_device *dev = encoder->dev;
1508         struct radeon_device *rdev = dev->dev_private;
1509         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1510         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1511
1512         /* Funky macbooks */
1513         if ((dev->pdev->device == 0x71C5) &&
1514             (dev->pdev->subsystem_vendor == 0x106b) &&
1515             (dev->pdev->subsystem_device == 0x0080)) {
1516                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1517                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1518
1519                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1520                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1521
1522                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1523                 }
1524         }
1525
1526         /* set scaler clears this on some chips */
1527         if (ASIC_IS_AVIVO(rdev) &&
1528             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1529                 if (ASIC_IS_DCE4(rdev)) {
1530                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1531                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1532                                        EVERGREEN_INTERLEAVE_EN);
1533                         else
1534                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1535                 } else {
1536                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1537                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1538                                        AVIVO_D1MODE_INTERLEAVE_EN);
1539                         else
1540                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1541                 }
1542         }
1543 }
1544
1545 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1546 {
1547         struct drm_device *dev = encoder->dev;
1548         struct radeon_device *rdev = dev->dev_private;
1549         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1550         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1551         struct drm_encoder *test_encoder;
1552         struct radeon_encoder_atom_dig *dig;
1553         uint32_t dig_enc_in_use = 0;
1554
1555         /* DCE4/5 */
1556         if (ASIC_IS_DCE4(rdev)) {
1557                 dig = radeon_encoder->enc_priv;
1558                 if (ASIC_IS_DCE41(rdev)) {
1559                         /* ontario follows DCE4 */
1560                         if (rdev->family == CHIP_PALM) {
1561                                 if (dig->linkb)
1562                                         return 1;
1563                                 else
1564                                         return 0;
1565                         } else
1566                                 /* llano follows DCE3.2 */
1567                                 return radeon_crtc->crtc_id;
1568                 } else {
1569                         switch (radeon_encoder->encoder_id) {
1570                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1571                                 if (dig->linkb)
1572                                         return 1;
1573                                 else
1574                                         return 0;
1575                                 break;
1576                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1577                                 if (dig->linkb)
1578                                         return 3;
1579                                 else
1580                                         return 2;
1581                                 break;
1582                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1583                                 if (dig->linkb)
1584                                         return 5;
1585                                 else
1586                                         return 4;
1587                                 break;
1588                         }
1589                 }
1590         }
1591
1592         /* on DCE32 and encoder can driver any block so just crtc id */
1593         if (ASIC_IS_DCE32(rdev)) {
1594                 return radeon_crtc->crtc_id;
1595         }
1596
1597         /* on DCE3 - LVTMA can only be driven by DIGB */
1598         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1599                 struct radeon_encoder *radeon_test_encoder;
1600
1601                 if (encoder == test_encoder)
1602                         continue;
1603
1604                 if (!radeon_encoder_is_digital(test_encoder))
1605                         continue;
1606
1607                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1608                 dig = radeon_test_encoder->enc_priv;
1609
1610                 if (dig->dig_encoder >= 0)
1611                         dig_enc_in_use |= (1 << dig->dig_encoder);
1612         }
1613
1614         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1615                 if (dig_enc_in_use & 0x2)
1616                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1617                 return 1;
1618         }
1619         if (!(dig_enc_in_use & 1))
1620                 return 0;
1621         return 1;
1622 }
1623
1624 /* This only needs to be called once at startup */
1625 void
1626 radeon_atom_encoder_init(struct radeon_device *rdev)
1627 {
1628         struct drm_device *dev = rdev->ddev;
1629         struct drm_encoder *encoder;
1630
1631         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1632                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1633                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1634
1635                 switch (radeon_encoder->encoder_id) {
1636                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1637                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1638                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1639                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1640                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1641                         break;
1642                 default:
1643                         break;
1644                 }
1645
1646                 if (ext_encoder && ASIC_IS_DCE41(rdev))
1647                         atombios_external_encoder_setup(encoder, ext_encoder,
1648                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1649         }
1650 }
1651
1652 static void
1653 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1654                              struct drm_display_mode *mode,
1655                              struct drm_display_mode *adjusted_mode)
1656 {
1657         struct drm_device *dev = encoder->dev;
1658         struct radeon_device *rdev = dev->dev_private;
1659         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1660         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1661
1662         radeon_encoder->pixel_clock = adjusted_mode->clock;
1663
1664         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1665                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1666                         atombios_yuv_setup(encoder, true);
1667                 else
1668                         atombios_yuv_setup(encoder, false);
1669         }
1670
1671         switch (radeon_encoder->encoder_id) {
1672         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1673         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1674         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1675         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1676                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1677                 break;
1678         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1679         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1680         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1681         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1682                 if (ASIC_IS_DCE4(rdev)) {
1683                         /* disable the transmitter */
1684                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1685                         /* setup and enable the encoder */
1686                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1687
1688                         /* enable the transmitter */
1689                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1690                 } else {
1691                         /* disable the encoder and transmitter */
1692                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1693                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1694
1695                         /* setup and enable the encoder and transmitter */
1696                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1697                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1698                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1699                 }
1700                 break;
1701         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1702         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1703         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1704                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1705                 break;
1706         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1707         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1708         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1709         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1710                 atombios_dac_setup(encoder, ATOM_ENABLE);
1711                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1712                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1713                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1714                         else
1715                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1716                 }
1717                 break;
1718         }
1719
1720         if (ext_encoder) {
1721                 if (ASIC_IS_DCE41(rdev))
1722                         atombios_external_encoder_setup(encoder, ext_encoder,
1723                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1724                 else
1725                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1726         }
1727
1728         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1729
1730         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1731                 r600_hdmi_enable(encoder);
1732                 r600_hdmi_setmode(encoder, adjusted_mode);
1733         }
1734 }
1735
1736 static bool
1737 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1738 {
1739         struct drm_device *dev = encoder->dev;
1740         struct radeon_device *rdev = dev->dev_private;
1741         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1742         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1743
1744         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1745                                        ATOM_DEVICE_CV_SUPPORT |
1746                                        ATOM_DEVICE_CRT_SUPPORT)) {
1747                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1748                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1749                 uint8_t frev, crev;
1750
1751                 memset(&args, 0, sizeof(args));
1752
1753                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1754                         return false;
1755
1756                 args.sDacload.ucMisc = 0;
1757
1758                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1759                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1760                         args.sDacload.ucDacType = ATOM_DAC_A;
1761                 else
1762                         args.sDacload.ucDacType = ATOM_DAC_B;
1763
1764                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1765                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1766                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1767                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1768                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1769                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1770                         if (crev >= 3)
1771                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1772                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1773                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1774                         if (crev >= 3)
1775                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1776                 }
1777
1778                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1779
1780                 return true;
1781         } else
1782                 return false;
1783 }
1784
1785 static enum drm_connector_status
1786 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1787 {
1788         struct drm_device *dev = encoder->dev;
1789         struct radeon_device *rdev = dev->dev_private;
1790         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1791         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1792         uint32_t bios_0_scratch;
1793
1794         if (!atombios_dac_load_detect(encoder, connector)) {
1795                 DRM_DEBUG_KMS("detect returned false \n");
1796                 return connector_status_unknown;
1797         }
1798
1799         if (rdev->family >= CHIP_R600)
1800                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1801         else
1802                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1803
1804         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1805         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1806                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1807                         return connector_status_connected;
1808         }
1809         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1810                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1811                         return connector_status_connected;
1812         }
1813         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1814                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1815                         return connector_status_connected;
1816         }
1817         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1818                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1819                         return connector_status_connected; /* CTV */
1820                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1821                         return connector_status_connected; /* STV */
1822         }
1823         return connector_status_disconnected;
1824 }
1825
1826 static enum drm_connector_status
1827 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1828 {
1829         struct drm_device *dev = encoder->dev;
1830         struct radeon_device *rdev = dev->dev_private;
1831         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1832         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1833         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1834         u32 bios_0_scratch;
1835
1836         if (!ASIC_IS_DCE4(rdev))
1837                 return connector_status_unknown;
1838
1839         if (!ext_encoder)
1840                 return connector_status_unknown;
1841
1842         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1843                 return connector_status_unknown;
1844
1845         /* load detect on the dp bridge */
1846         atombios_external_encoder_setup(encoder, ext_encoder,
1847                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1848
1849         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1850
1851         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1852         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1853                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1854                         return connector_status_connected;
1855         }
1856         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1857                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1858                         return connector_status_connected;
1859         }
1860         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1861                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1862                         return connector_status_connected;
1863         }
1864         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1865                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1866                         return connector_status_connected; /* CTV */
1867                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1868                         return connector_status_connected; /* STV */
1869         }
1870         return connector_status_disconnected;
1871 }
1872
1873 void
1874 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
1875 {
1876         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1877
1878         if (ext_encoder)
1879                 /* ddc_setup on the dp bridge */
1880                 atombios_external_encoder_setup(encoder, ext_encoder,
1881                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
1882
1883 }
1884
1885 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1886 {
1887         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1888         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1889
1890         if ((radeon_encoder->active_device &
1891              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
1892             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
1893              ENCODER_OBJECT_ID_NONE)) {
1894                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1895                 if (dig)
1896                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1897         }
1898
1899         radeon_atom_output_lock(encoder, true);
1900         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1901
1902         if (connector) {
1903                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1904
1905                 /* select the clock/data port if it uses a router */
1906                 if (radeon_connector->router.cd_valid)
1907                         radeon_router_select_cd_port(radeon_connector);
1908
1909                 /* turn eDP panel on for mode set */
1910                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1911                         atombios_set_edp_panel_power(connector,
1912                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1913         }
1914
1915         /* this is needed for the pll/ss setup to work correctly in some cases */
1916         atombios_set_encoder_crtc_source(encoder);
1917 }
1918
1919 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1920 {
1921         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1922         radeon_atom_output_lock(encoder, false);
1923 }
1924
1925 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1926 {
1927         struct drm_device *dev = encoder->dev;
1928         struct radeon_device *rdev = dev->dev_private;
1929         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1930         struct radeon_encoder_atom_dig *dig;
1931
1932         /* check for pre-DCE3 cards with shared encoders;
1933          * can't really use the links individually, so don't disable
1934          * the encoder if it's in use by another connector
1935          */
1936         if (!ASIC_IS_DCE3(rdev)) {
1937                 struct drm_encoder *other_encoder;
1938                 struct radeon_encoder *other_radeon_encoder;
1939
1940                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1941                         other_radeon_encoder = to_radeon_encoder(other_encoder);
1942                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1943                             drm_helper_encoder_in_use(other_encoder))
1944                                 goto disable_done;
1945                 }
1946         }
1947
1948         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1949
1950         switch (radeon_encoder->encoder_id) {
1951         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1952         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1953         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1954         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1955                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1956                 break;
1957         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1958         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1959         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1960         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1961                 if (ASIC_IS_DCE4(rdev))
1962                         /* disable the transmitter */
1963                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1964                 else {
1965                         /* disable the encoder and transmitter */
1966                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1967                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1968                 }
1969                 break;
1970         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1971         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1972         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1973                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1974                 break;
1975         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1976         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1977         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1978         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1979                 atombios_dac_setup(encoder, ATOM_DISABLE);
1980                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1981                         atombios_tv_setup(encoder, ATOM_DISABLE);
1982                 break;
1983         }
1984
1985 disable_done:
1986         if (radeon_encoder_is_digital(encoder)) {
1987                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1988                         r600_hdmi_disable(encoder);
1989                 dig = radeon_encoder->enc_priv;
1990                 dig->dig_encoder = -1;
1991         }
1992         radeon_encoder->active_device = 0;
1993 }
1994
1995 /* these are handled by the primary encoders */
1996 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1997 {
1998
1999 }
2000
2001 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2002 {
2003
2004 }
2005
2006 static void
2007 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2008                          struct drm_display_mode *mode,
2009                          struct drm_display_mode *adjusted_mode)
2010 {
2011
2012 }
2013
2014 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2015 {
2016
2017 }
2018
2019 static void
2020 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2021 {
2022
2023 }
2024
2025 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2026                                        struct drm_display_mode *mode,
2027                                        struct drm_display_mode *adjusted_mode)
2028 {
2029         return true;
2030 }
2031
2032 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2033         .dpms = radeon_atom_ext_dpms,
2034         .mode_fixup = radeon_atom_ext_mode_fixup,
2035         .prepare = radeon_atom_ext_prepare,
2036         .mode_set = radeon_atom_ext_mode_set,
2037         .commit = radeon_atom_ext_commit,
2038         .disable = radeon_atom_ext_disable,
2039         /* no detect for TMDS/LVDS yet */
2040 };
2041
2042 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2043         .dpms = radeon_atom_encoder_dpms,
2044         .mode_fixup = radeon_atom_mode_fixup,
2045         .prepare = radeon_atom_encoder_prepare,
2046         .mode_set = radeon_atom_encoder_mode_set,
2047         .commit = radeon_atom_encoder_commit,
2048         .disable = radeon_atom_encoder_disable,
2049         .detect = radeon_atom_dig_detect,
2050 };
2051
2052 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2053         .dpms = radeon_atom_encoder_dpms,
2054         .mode_fixup = radeon_atom_mode_fixup,
2055         .prepare = radeon_atom_encoder_prepare,
2056         .mode_set = radeon_atom_encoder_mode_set,
2057         .commit = radeon_atom_encoder_commit,
2058         .detect = radeon_atom_dac_detect,
2059 };
2060
2061 void radeon_enc_destroy(struct drm_encoder *encoder)
2062 {
2063         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2064         kfree(radeon_encoder->enc_priv);
2065         drm_encoder_cleanup(encoder);
2066         kfree(radeon_encoder);
2067 }
2068
2069 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2070         .destroy = radeon_enc_destroy,
2071 };
2072
2073 struct radeon_encoder_atom_dac *
2074 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2075 {
2076         struct drm_device *dev = radeon_encoder->base.dev;
2077         struct radeon_device *rdev = dev->dev_private;
2078         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2079
2080         if (!dac)
2081                 return NULL;
2082
2083         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2084         return dac;
2085 }
2086
2087 struct radeon_encoder_atom_dig *
2088 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2089 {
2090         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2091         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2092
2093         if (!dig)
2094                 return NULL;
2095
2096         /* coherent mode by default */
2097         dig->coherent_mode = true;
2098         dig->dig_encoder = -1;
2099
2100         if (encoder_enum == 2)
2101                 dig->linkb = true;
2102         else
2103                 dig->linkb = false;
2104
2105         return dig;
2106 }
2107
2108 void
2109 radeon_add_atom_encoder(struct drm_device *dev,
2110                         uint32_t encoder_enum,
2111                         uint32_t supported_device,
2112                         u16 caps)
2113 {
2114         struct radeon_device *rdev = dev->dev_private;
2115         struct drm_encoder *encoder;
2116         struct radeon_encoder *radeon_encoder;
2117
2118         /* see if we already added it */
2119         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2120                 radeon_encoder = to_radeon_encoder(encoder);
2121                 if (radeon_encoder->encoder_enum == encoder_enum) {
2122                         radeon_encoder->devices |= supported_device;
2123                         return;
2124                 }
2125
2126         }
2127
2128         /* add a new one */
2129         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2130         if (!radeon_encoder)
2131                 return;
2132
2133         encoder = &radeon_encoder->base;
2134         switch (rdev->num_crtc) {
2135         case 1:
2136                 encoder->possible_crtcs = 0x1;
2137                 break;
2138         case 2:
2139         default:
2140                 encoder->possible_crtcs = 0x3;
2141                 break;
2142         case 4:
2143                 encoder->possible_crtcs = 0xf;
2144                 break;
2145         case 6:
2146                 encoder->possible_crtcs = 0x3f;
2147                 break;
2148         }
2149
2150         radeon_encoder->enc_priv = NULL;
2151
2152         radeon_encoder->encoder_enum = encoder_enum;
2153         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2154         radeon_encoder->devices = supported_device;
2155         radeon_encoder->rmx_type = RMX_OFF;
2156         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2157         radeon_encoder->is_ext_encoder = false;
2158         radeon_encoder->caps = caps;
2159
2160         switch (radeon_encoder->encoder_id) {
2161         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2162         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2163         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2164         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2165                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2166                         radeon_encoder->rmx_type = RMX_FULL;
2167                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2168                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2169                 } else {
2170                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2171                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2172                 }
2173                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2174                 break;
2175         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2176                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2177                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2178                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2179                 break;
2180         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2181         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2182         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2183                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2184                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2185                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2186                 break;
2187         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2188         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2189         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2190         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2191         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2192         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2193         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2194                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2195                         radeon_encoder->rmx_type = RMX_FULL;
2196                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2197                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2198                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2199                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2200                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2201                 } else {
2202                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2203                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2204                 }
2205                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2206                 break;
2207         case ENCODER_OBJECT_ID_SI170B:
2208         case ENCODER_OBJECT_ID_CH7303:
2209         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2210         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2211         case ENCODER_OBJECT_ID_TITFP513:
2212         case ENCODER_OBJECT_ID_VT1623:
2213         case ENCODER_OBJECT_ID_HDMI_SI1930:
2214         case ENCODER_OBJECT_ID_TRAVIS:
2215         case ENCODER_OBJECT_ID_NUTMEG:
2216                 /* these are handled by the primary encoders */
2217                 radeon_encoder->is_ext_encoder = true;
2218                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2219                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2220                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2221                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2222                 else
2223                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2224                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2225                 break;
2226         }
2227 }