2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60 static struct drm_connector *
61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct drm_device *dev = encoder->dev;
82 struct radeon_device *rdev = dev->dev_private;
84 /* set the active encoder to connector routing */
85 radeon_encoder_set_active_device(encoder);
86 drm_mode_set_crtcinfo(adjusted_mode, 0);
89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
93 /* get the native mode for LVDS */
94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95 radeon_panel_mode_fixup(encoder, adjusted_mode);
97 /* get the native mode for TV */
98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 if (tv_dac->tv_std == TV_STD_NTSC ||
102 tv_dac->tv_std == TV_STD_NTSC_J ||
103 tv_dac->tv_std == TV_STD_PAL_M)
104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
110 if (ASIC_IS_DCE3(rdev) &&
111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114 radeon_dp_set_link_config(connector, adjusted_mode);
121 atombios_dac_setup(struct drm_encoder *encoder, int action)
123 struct drm_device *dev = encoder->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
130 memset(&args, 0, sizeof(args));
132 switch (radeon_encoder->encoder_id) {
133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
143 args.ucAction = action;
145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146 args.ucDacStandard = ATOM_DAC1_PS2;
147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148 args.ucDacStandard = ATOM_DAC1_CV;
150 switch (dac_info->tv_std) {
153 case TV_STD_SCART_PAL:
156 args.ucDacStandard = ATOM_DAC1_PAL;
162 args.ucDacStandard = ATOM_DAC1_NTSC;
166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
173 atombios_tv_setup(struct drm_encoder *encoder, int action)
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 TV_ENCODER_CONTROL_PS_ALLOCATION args;
180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
182 memset(&args, 0, sizeof(args));
184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
186 args.sTVEncoder.ucAction = action;
188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
191 switch (dac_info->tv_std) {
193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
207 case TV_STD_SCART_PAL:
208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
228 union dvo_encoder_control {
229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
235 atombios_dvo_setup(struct drm_encoder *encoder, int action)
237 struct drm_device *dev = encoder->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240 union dvo_encoder_control args;
241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
244 memset(&args, 0, sizeof(args));
246 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
249 /* some R4xx chips have the wrong frev */
250 if (rdev->family <= CHIP_RV410)
258 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
260 if (radeon_encoder->pixel_clock > 165000)
261 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
263 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
267 args.dvo.sDVOEncoder.ucAction = action;
268 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
269 /* DFP1, CRT1, TV1 depending on the type of port */
270 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
272 if (radeon_encoder->pixel_clock > 165000)
273 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
277 args.dvo_v3.ucAction = action;
278 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
279 args.dvo_v3.ucDVOConfig = 0; /* XXX */
282 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
287 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
291 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
294 union lvds_encoder_control {
295 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
296 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
300 atombios_digital_setup(struct drm_encoder *encoder, int action)
302 struct drm_device *dev = encoder->dev;
303 struct radeon_device *rdev = dev->dev_private;
304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
305 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
306 union lvds_encoder_control args;
308 int hdmi_detected = 0;
314 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
317 memset(&args, 0, sizeof(args));
319 switch (radeon_encoder->encoder_id) {
320 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
321 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
323 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
324 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
325 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
327 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
328 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
329 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
331 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
335 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
344 args.v1.ucAction = action;
346 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
347 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
348 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
349 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
350 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
351 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
352 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
355 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
356 if (radeon_encoder->pixel_clock > 165000)
357 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
358 /*if (pScrn->rgbBits == 8) */
359 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
365 args.v2.ucAction = action;
367 if (dig->coherent_mode)
368 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
371 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
372 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
373 args.v2.ucTruncate = 0;
374 args.v2.ucSpatial = 0;
375 args.v2.ucTemporal = 0;
377 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
378 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
379 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
380 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
381 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
382 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
383 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
385 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
386 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
387 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
388 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
389 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
390 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
394 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
395 if (radeon_encoder->pixel_clock > 165000)
396 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
400 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
405 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
409 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
413 atombios_get_encoder_mode(struct drm_encoder *encoder)
415 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
416 struct drm_device *dev = encoder->dev;
417 struct radeon_device *rdev = dev->dev_private;
418 struct drm_connector *connector;
419 struct radeon_connector *radeon_connector;
420 struct radeon_connector_atom_dig *dig_connector;
422 /* dp bridges are always DP */
423 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
424 return ATOM_ENCODER_MODE_DP;
426 /* DVO is always DVO */
427 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
428 return ATOM_ENCODER_MODE_DVO;
430 connector = radeon_get_connector_for_encoder(encoder);
431 /* if we don't have an active device yet, just use one of
432 * the connectors tied to the encoder.
435 connector = radeon_get_connector_for_encoder_init(encoder);
436 radeon_connector = to_radeon_connector(connector);
438 switch (connector->connector_type) {
439 case DRM_MODE_CONNECTOR_DVII:
440 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
441 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
443 if (ASIC_IS_DCE4(rdev))
444 return ATOM_ENCODER_MODE_DVI;
446 return ATOM_ENCODER_MODE_HDMI;
447 } else if (radeon_connector->use_digital)
448 return ATOM_ENCODER_MODE_DVI;
450 return ATOM_ENCODER_MODE_CRT;
452 case DRM_MODE_CONNECTOR_DVID:
453 case DRM_MODE_CONNECTOR_HDMIA:
455 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
457 if (ASIC_IS_DCE4(rdev))
458 return ATOM_ENCODER_MODE_DVI;
460 return ATOM_ENCODER_MODE_HDMI;
462 return ATOM_ENCODER_MODE_DVI;
464 case DRM_MODE_CONNECTOR_LVDS:
465 return ATOM_ENCODER_MODE_LVDS;
467 case DRM_MODE_CONNECTOR_DisplayPort:
468 dig_connector = radeon_connector->con_priv;
469 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
470 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
471 return ATOM_ENCODER_MODE_DP;
472 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
474 if (ASIC_IS_DCE4(rdev))
475 return ATOM_ENCODER_MODE_DVI;
477 return ATOM_ENCODER_MODE_HDMI;
479 return ATOM_ENCODER_MODE_DVI;
481 case DRM_MODE_CONNECTOR_eDP:
482 return ATOM_ENCODER_MODE_DP;
483 case DRM_MODE_CONNECTOR_DVIA:
484 case DRM_MODE_CONNECTOR_VGA:
485 return ATOM_ENCODER_MODE_CRT;
487 case DRM_MODE_CONNECTOR_Composite:
488 case DRM_MODE_CONNECTOR_SVIDEO:
489 case DRM_MODE_CONNECTOR_9PinDIN:
491 return ATOM_ENCODER_MODE_TV;
492 /*return ATOM_ENCODER_MODE_CV;*/
498 * DIG Encoder/Transmitter Setup
501 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
502 * Supports up to 3 digital outputs
503 * - 2 DIG encoder blocks.
504 * DIG1 can drive UNIPHY link A or link B
505 * DIG2 can drive UNIPHY link B or LVTMA
508 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
509 * Supports up to 5 digital outputs
510 * - 2 DIG encoder blocks.
511 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
514 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
515 * Supports up to 6 digital outputs
516 * - 6 DIG encoder blocks.
517 * - DIG to PHY mapping is hardcoded
518 * DIG1 drives UNIPHY0 link A, A+B
519 * DIG2 drives UNIPHY0 link B
520 * DIG3 drives UNIPHY1 link A, A+B
521 * DIG4 drives UNIPHY1 link B
522 * DIG5 drives UNIPHY2 link A, A+B
523 * DIG6 drives UNIPHY2 link B
526 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
527 * Supports up to 6 digital outputs
528 * - 2 DIG encoder blocks.
529 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
532 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
534 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
535 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
536 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
537 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
540 union dig_encoder_control {
541 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
542 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
543 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
544 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
548 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
550 struct drm_device *dev = encoder->dev;
551 struct radeon_device *rdev = dev->dev_private;
552 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
553 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
554 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
555 union dig_encoder_control args;
559 int dp_lane_count = 0;
560 int hpd_id = RADEON_HPD_NONE;
564 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
565 struct radeon_connector_atom_dig *dig_connector =
566 radeon_connector->con_priv;
568 dp_clock = dig_connector->dp_clock;
569 dp_lane_count = dig_connector->dp_lane_count;
570 hpd_id = radeon_connector->hpd.hpd;
571 bpc = connector->display_info.bpc;
574 /* no dig encoder assigned */
575 if (dig->dig_encoder == -1)
578 memset(&args, 0, sizeof(args));
580 if (ASIC_IS_DCE4(rdev))
581 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
583 if (dig->dig_encoder)
584 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
586 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
589 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
596 args.v1.ucAction = action;
597 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
598 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
599 args.v3.ucPanelMode = panel_mode;
601 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
603 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
604 args.v1.ucLaneNum = dp_lane_count;
605 else if (radeon_encoder->pixel_clock > 165000)
606 args.v1.ucLaneNum = 8;
608 args.v1.ucLaneNum = 4;
610 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
611 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
612 switch (radeon_encoder->encoder_id) {
613 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
614 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
617 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
618 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
620 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
621 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
625 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
627 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
631 args.v3.ucAction = action;
632 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
633 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
634 args.v3.ucPanelMode = panel_mode;
636 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
638 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
639 args.v3.ucLaneNum = dp_lane_count;
640 else if (radeon_encoder->pixel_clock > 165000)
641 args.v3.ucLaneNum = 8;
643 args.v3.ucLaneNum = 4;
645 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
646 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
647 args.v3.acConfig.ucDigSel = dig->dig_encoder;
650 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
653 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
657 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
660 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
663 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
666 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
671 args.v4.ucAction = action;
672 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
673 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
674 args.v4.ucPanelMode = panel_mode;
676 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
678 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
679 args.v4.ucLaneNum = dp_lane_count;
680 else if (radeon_encoder->pixel_clock > 165000)
681 args.v4.ucLaneNum = 8;
683 args.v4.ucLaneNum = 4;
685 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
686 if (dp_clock == 270000)
687 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
688 else if (dp_clock == 540000)
689 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
691 args.v4.acConfig.ucDigSel = dig->dig_encoder;
694 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
697 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
701 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
704 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
707 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
710 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
713 if (hpd_id == RADEON_HPD_NONE)
714 args.v4.ucHPD_ID = 0;
716 args.v4.ucHPD_ID = hpd_id + 1;
719 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
724 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
728 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
732 union dig_transmitter_control {
733 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
734 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
735 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
736 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
740 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
742 struct drm_device *dev = encoder->dev;
743 struct radeon_device *rdev = dev->dev_private;
744 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
745 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
746 struct drm_connector *connector;
747 union dig_transmitter_control args;
753 int dp_lane_count = 0;
754 int connector_object_id = 0;
755 int igp_lane_info = 0;
756 int dig_encoder = dig->dig_encoder;
758 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
759 connector = radeon_get_connector_for_encoder_init(encoder);
760 /* just needed to avoid bailing in the encoder check. the encoder
761 * isn't used for init
765 connector = radeon_get_connector_for_encoder(encoder);
768 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
769 struct radeon_connector_atom_dig *dig_connector =
770 radeon_connector->con_priv;
772 dp_clock = dig_connector->dp_clock;
773 dp_lane_count = dig_connector->dp_lane_count;
774 connector_object_id =
775 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
776 igp_lane_info = dig_connector->igp_lane_info;
780 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
781 pll_id = radeon_crtc->pll_id;
784 /* no dig encoder assigned */
785 if (dig_encoder == -1)
788 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
791 memset(&args, 0, sizeof(args));
793 switch (radeon_encoder->encoder_id) {
794 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
795 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
800 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
802 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
803 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
807 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
814 args.v1.ucAction = action;
815 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
816 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
817 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
818 args.v1.asMode.ucLaneSel = lane_num;
819 args.v1.asMode.ucLaneSet = lane_set;
822 args.v1.usPixelClock =
823 cpu_to_le16(dp_clock / 10);
824 else if (radeon_encoder->pixel_clock > 165000)
825 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
827 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
830 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
833 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
835 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
837 if ((rdev->flags & RADEON_IS_IGP) &&
838 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
839 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
840 if (igp_lane_info & 0x1)
841 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
842 else if (igp_lane_info & 0x2)
843 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
844 else if (igp_lane_info & 0x4)
845 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
846 else if (igp_lane_info & 0x8)
847 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
849 if (igp_lane_info & 0x3)
850 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
851 else if (igp_lane_info & 0xc)
852 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
857 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
859 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
862 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
863 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
864 if (dig->coherent_mode)
865 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
866 if (radeon_encoder->pixel_clock > 165000)
867 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
871 args.v2.ucAction = action;
872 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
873 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
874 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
875 args.v2.asMode.ucLaneSel = lane_num;
876 args.v2.asMode.ucLaneSet = lane_set;
879 args.v2.usPixelClock =
880 cpu_to_le16(dp_clock / 10);
881 else if (radeon_encoder->pixel_clock > 165000)
882 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
884 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
887 args.v2.acConfig.ucEncoderSel = dig_encoder;
889 args.v2.acConfig.ucLinkSel = 1;
891 switch (radeon_encoder->encoder_id) {
892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
893 args.v2.acConfig.ucTransmitterSel = 0;
895 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
896 args.v2.acConfig.ucTransmitterSel = 1;
898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
899 args.v2.acConfig.ucTransmitterSel = 2;
904 args.v2.acConfig.fCoherentMode = 1;
905 args.v2.acConfig.fDPConnector = 1;
906 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
907 if (dig->coherent_mode)
908 args.v2.acConfig.fCoherentMode = 1;
909 if (radeon_encoder->pixel_clock > 165000)
910 args.v2.acConfig.fDualLinkConnector = 1;
914 args.v3.ucAction = action;
915 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
916 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
917 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
918 args.v3.asMode.ucLaneSel = lane_num;
919 args.v3.asMode.ucLaneSet = lane_set;
922 args.v3.usPixelClock =
923 cpu_to_le16(dp_clock / 10);
924 else if (radeon_encoder->pixel_clock > 165000)
925 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
927 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
931 args.v3.ucLaneNum = dp_lane_count;
932 else if (radeon_encoder->pixel_clock > 165000)
933 args.v3.ucLaneNum = 8;
935 args.v3.ucLaneNum = 4;
938 args.v3.acConfig.ucLinkSel = 1;
940 args.v3.acConfig.ucEncoderSel = 1;
942 /* Select the PLL for the PHY
943 * DP PHY should be clocked from external src if there is
946 /* On DCE4, if there is an external clock, it generates the DP ref clock */
947 if (is_dp && rdev->clock.dp_extclk)
948 args.v3.acConfig.ucRefClkSource = 2; /* external src */
950 args.v3.acConfig.ucRefClkSource = pll_id;
952 switch (radeon_encoder->encoder_id) {
953 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
954 args.v3.acConfig.ucTransmitterSel = 0;
956 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
957 args.v3.acConfig.ucTransmitterSel = 1;
959 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
960 args.v3.acConfig.ucTransmitterSel = 2;
965 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
966 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
967 if (dig->coherent_mode)
968 args.v3.acConfig.fCoherentMode = 1;
969 if (radeon_encoder->pixel_clock > 165000)
970 args.v3.acConfig.fDualLinkConnector = 1;
974 args.v4.ucAction = action;
975 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
976 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
977 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
978 args.v4.asMode.ucLaneSel = lane_num;
979 args.v4.asMode.ucLaneSet = lane_set;
982 args.v4.usPixelClock =
983 cpu_to_le16(dp_clock / 10);
984 else if (radeon_encoder->pixel_clock > 165000)
985 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
987 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
991 args.v4.ucLaneNum = dp_lane_count;
992 else if (radeon_encoder->pixel_clock > 165000)
993 args.v4.ucLaneNum = 8;
995 args.v4.ucLaneNum = 4;
998 args.v4.acConfig.ucLinkSel = 1;
1000 args.v4.acConfig.ucEncoderSel = 1;
1002 /* Select the PLL for the PHY
1003 * DP PHY should be clocked from external src if there is
1006 /* On DCE5 DCPLL usually generates the DP ref clock */
1008 if (rdev->clock.dp_extclk)
1009 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1011 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1013 args.v4.acConfig.ucRefClkSource = pll_id;
1015 switch (radeon_encoder->encoder_id) {
1016 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1017 args.v4.acConfig.ucTransmitterSel = 0;
1019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1020 args.v4.acConfig.ucTransmitterSel = 1;
1022 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1023 args.v4.acConfig.ucTransmitterSel = 2;
1028 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1029 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1030 if (dig->coherent_mode)
1031 args.v4.acConfig.fCoherentMode = 1;
1032 if (radeon_encoder->pixel_clock > 165000)
1033 args.v4.acConfig.fDualLinkConnector = 1;
1037 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1042 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1046 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1050 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1052 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1053 struct drm_device *dev = radeon_connector->base.dev;
1054 struct radeon_device *rdev = dev->dev_private;
1055 union dig_transmitter_control args;
1056 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1059 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1062 if (!ASIC_IS_DCE4(rdev))
1065 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1066 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1069 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1072 memset(&args, 0, sizeof(args));
1074 args.v1.ucAction = action;
1076 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1078 /* wait for the panel to power up */
1079 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1082 for (i = 0; i < 300; i++) {
1083 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1093 union external_encoder_control {
1094 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1095 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1099 atombios_external_encoder_setup(struct drm_encoder *encoder,
1100 struct drm_encoder *ext_encoder,
1103 struct drm_device *dev = encoder->dev;
1104 struct radeon_device *rdev = dev->dev_private;
1105 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1106 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1107 union external_encoder_control args;
1108 struct drm_connector *connector;
1109 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1112 int dp_lane_count = 0;
1113 int connector_object_id = 0;
1114 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1117 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1118 connector = radeon_get_connector_for_encoder_init(encoder);
1120 connector = radeon_get_connector_for_encoder(encoder);
1123 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1124 struct radeon_connector_atom_dig *dig_connector =
1125 radeon_connector->con_priv;
1127 dp_clock = dig_connector->dp_clock;
1128 dp_lane_count = dig_connector->dp_lane_count;
1129 connector_object_id =
1130 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1131 bpc = connector->display_info.bpc;
1134 memset(&args, 0, sizeof(args));
1136 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1141 /* no params on frev 1 */
1147 args.v1.sDigEncoder.ucAction = action;
1148 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1149 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1151 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1152 if (dp_clock == 270000)
1153 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1154 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1155 } else if (radeon_encoder->pixel_clock > 165000)
1156 args.v1.sDigEncoder.ucLaneNum = 8;
1158 args.v1.sDigEncoder.ucLaneNum = 4;
1161 args.v3.sExtEncoder.ucAction = action;
1162 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1163 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1165 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1166 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1168 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1169 if (dp_clock == 270000)
1170 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1171 else if (dp_clock == 540000)
1172 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1173 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1174 } else if (radeon_encoder->pixel_clock > 165000)
1175 args.v3.sExtEncoder.ucLaneNum = 8;
1177 args.v3.sExtEncoder.ucLaneNum = 4;
1179 case GRAPH_OBJECT_ENUM_ID1:
1180 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1182 case GRAPH_OBJECT_ENUM_ID2:
1183 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1185 case GRAPH_OBJECT_ENUM_ID3:
1186 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1191 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1194 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1198 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1201 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1204 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1207 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1212 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1217 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1220 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1224 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1226 struct drm_device *dev = encoder->dev;
1227 struct radeon_device *rdev = dev->dev_private;
1228 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1229 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1230 ENABLE_YUV_PS_ALLOCATION args;
1231 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1234 memset(&args, 0, sizeof(args));
1236 if (rdev->family >= CHIP_R600)
1237 reg = R600_BIOS_3_SCRATCH;
1239 reg = RADEON_BIOS_3_SCRATCH;
1241 /* XXX: fix up scratch reg handling */
1243 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1244 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1245 (radeon_crtc->crtc_id << 18)));
1246 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1247 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1252 args.ucEnable = ATOM_ENABLE;
1253 args.ucCRTC = radeon_crtc->crtc_id;
1255 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1261 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1263 struct drm_device *dev = encoder->dev;
1264 struct radeon_device *rdev = dev->dev_private;
1265 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1266 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1269 memset(&args, 0, sizeof(args));
1271 switch (radeon_encoder->encoder_id) {
1272 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1273 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1274 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1276 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1277 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1278 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1279 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1281 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1282 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1284 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1285 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1286 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1288 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1290 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1291 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1292 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1293 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1294 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1295 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1297 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1299 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1301 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1302 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1303 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1304 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1306 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1313 case DRM_MODE_DPMS_ON:
1314 args.ucAction = ATOM_ENABLE;
1315 /* workaround for DVOOutputControl on some RS690 systems */
1316 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1317 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1318 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1319 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1320 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1323 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1324 args.ucAction = ATOM_LCD_BLON;
1325 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1328 case DRM_MODE_DPMS_STANDBY:
1329 case DRM_MODE_DPMS_SUSPEND:
1330 case DRM_MODE_DPMS_OFF:
1331 args.ucAction = ATOM_DISABLE;
1332 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1333 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1334 args.ucAction = ATOM_LCD_BLOFF;
1335 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1342 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1344 struct drm_device *dev = encoder->dev;
1345 struct radeon_device *rdev = dev->dev_private;
1346 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1347 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1348 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1349 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1350 struct radeon_connector *radeon_connector = NULL;
1351 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1354 radeon_connector = to_radeon_connector(connector);
1355 radeon_dig_connector = radeon_connector->con_priv;
1359 case DRM_MODE_DPMS_ON:
1360 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1362 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1364 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1366 /* setup and enable the encoder */
1367 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1368 atombios_dig_encoder_setup(encoder,
1369 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1372 if (ASIC_IS_DCE41(rdev))
1373 atombios_external_encoder_setup(encoder, ext_encoder,
1374 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1376 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1377 } else if (ASIC_IS_DCE4(rdev)) {
1378 /* setup and enable the encoder */
1379 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1380 /* enable the transmitter */
1381 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1382 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1384 /* setup and enable the encoder and transmitter */
1385 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1386 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1387 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1388 /* some early dce3.2 boards have a bug in their transmitter control table */
1389 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1390 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1392 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1393 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1394 atombios_set_edp_panel_power(connector,
1395 ATOM_TRANSMITTER_ACTION_POWER_ON);
1396 radeon_dig_connector->edp_on = true;
1398 radeon_dp_link_train(encoder, connector);
1399 if (ASIC_IS_DCE4(rdev))
1400 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1402 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1403 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1405 case DRM_MODE_DPMS_STANDBY:
1406 case DRM_MODE_DPMS_SUSPEND:
1407 case DRM_MODE_DPMS_OFF:
1408 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1409 /* disable the transmitter */
1410 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1411 } else if (ASIC_IS_DCE4(rdev)) {
1412 /* disable the transmitter */
1413 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1414 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1416 /* disable the encoder and transmitter */
1417 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1418 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1419 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1421 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1422 if (ASIC_IS_DCE4(rdev))
1423 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1424 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1425 atombios_set_edp_panel_power(connector,
1426 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1427 radeon_dig_connector->edp_on = false;
1430 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1431 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1437 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1438 struct drm_encoder *ext_encoder,
1441 struct drm_device *dev = encoder->dev;
1442 struct radeon_device *rdev = dev->dev_private;
1445 case DRM_MODE_DPMS_ON:
1447 if (ASIC_IS_DCE41(rdev)) {
1448 atombios_external_encoder_setup(encoder, ext_encoder,
1449 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1450 atombios_external_encoder_setup(encoder, ext_encoder,
1451 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1453 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1455 case DRM_MODE_DPMS_STANDBY:
1456 case DRM_MODE_DPMS_SUSPEND:
1457 case DRM_MODE_DPMS_OFF:
1458 if (ASIC_IS_DCE41(rdev)) {
1459 atombios_external_encoder_setup(encoder, ext_encoder,
1460 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1461 atombios_external_encoder_setup(encoder, ext_encoder,
1462 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1464 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1470 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1472 struct drm_device *dev = encoder->dev;
1473 struct radeon_device *rdev = dev->dev_private;
1474 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1475 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1477 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1478 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1479 radeon_encoder->active_device);
1480 switch (radeon_encoder->encoder_id) {
1481 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1482 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1483 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1484 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1485 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1486 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1487 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1488 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1489 radeon_atom_encoder_dpms_avivo(encoder, mode);
1491 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1492 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1493 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1494 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1495 radeon_atom_encoder_dpms_dig(encoder, mode);
1497 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1498 if (ASIC_IS_DCE5(rdev)) {
1500 case DRM_MODE_DPMS_ON:
1501 atombios_dvo_setup(encoder, ATOM_ENABLE);
1503 case DRM_MODE_DPMS_STANDBY:
1504 case DRM_MODE_DPMS_SUSPEND:
1505 case DRM_MODE_DPMS_OFF:
1506 atombios_dvo_setup(encoder, ATOM_DISABLE);
1509 } else if (ASIC_IS_DCE3(rdev))
1510 radeon_atom_encoder_dpms_dig(encoder, mode);
1512 radeon_atom_encoder_dpms_avivo(encoder, mode);
1514 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1515 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1516 if (ASIC_IS_DCE5(rdev)) {
1518 case DRM_MODE_DPMS_ON:
1519 atombios_dac_setup(encoder, ATOM_ENABLE);
1521 case DRM_MODE_DPMS_STANDBY:
1522 case DRM_MODE_DPMS_SUSPEND:
1523 case DRM_MODE_DPMS_OFF:
1524 atombios_dac_setup(encoder, ATOM_DISABLE);
1528 radeon_atom_encoder_dpms_avivo(encoder, mode);
1535 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1537 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1541 union crtc_source_param {
1542 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1543 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1547 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1549 struct drm_device *dev = encoder->dev;
1550 struct radeon_device *rdev = dev->dev_private;
1551 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1553 union crtc_source_param args;
1554 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1556 struct radeon_encoder_atom_dig *dig;
1558 memset(&args, 0, sizeof(args));
1560 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1568 if (ASIC_IS_AVIVO(rdev))
1569 args.v1.ucCRTC = radeon_crtc->crtc_id;
1571 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1572 args.v1.ucCRTC = radeon_crtc->crtc_id;
1574 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1577 switch (radeon_encoder->encoder_id) {
1578 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1580 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1582 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1583 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1584 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1585 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1587 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1589 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1590 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1591 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1592 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1594 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1596 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1597 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1598 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1599 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1601 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1603 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1605 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1606 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1607 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1608 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1610 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1615 args.v2.ucCRTC = radeon_crtc->crtc_id;
1616 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1617 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1619 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1620 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1621 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1622 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1624 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1626 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1627 switch (radeon_encoder->encoder_id) {
1628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1630 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1632 dig = radeon_encoder->enc_priv;
1633 switch (dig->dig_encoder) {
1635 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1638 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1641 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1644 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1647 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1650 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1655 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1658 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1659 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1660 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1661 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1663 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1665 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1666 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1667 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1668 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1669 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1671 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1678 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1682 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1684 /* update scratch regs with new routing */
1685 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1689 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1690 struct drm_display_mode *mode)
1692 struct drm_device *dev = encoder->dev;
1693 struct radeon_device *rdev = dev->dev_private;
1694 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1695 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1697 /* Funky macbooks */
1698 if ((dev->pdev->device == 0x71C5) &&
1699 (dev->pdev->subsystem_vendor == 0x106b) &&
1700 (dev->pdev->subsystem_device == 0x0080)) {
1701 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1702 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1704 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1705 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1707 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1711 /* set scaler clears this on some chips */
1712 if (ASIC_IS_AVIVO(rdev) &&
1713 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1714 if (ASIC_IS_DCE4(rdev)) {
1715 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1716 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1717 EVERGREEN_INTERLEAVE_EN);
1719 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1721 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1722 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1723 AVIVO_D1MODE_INTERLEAVE_EN);
1725 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1730 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1732 struct drm_device *dev = encoder->dev;
1733 struct radeon_device *rdev = dev->dev_private;
1734 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1735 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1736 struct drm_encoder *test_encoder;
1737 struct radeon_encoder_atom_dig *dig;
1738 uint32_t dig_enc_in_use = 0;
1741 if (ASIC_IS_DCE4(rdev)) {
1742 dig = radeon_encoder->enc_priv;
1743 if (ASIC_IS_DCE41(rdev)) {
1744 /* ontario follows DCE4 */
1745 if (rdev->family == CHIP_PALM) {
1751 /* llano follows DCE3.2 */
1752 return radeon_crtc->crtc_id;
1754 switch (radeon_encoder->encoder_id) {
1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1777 /* on DCE32 and encoder can driver any block so just crtc id */
1778 if (ASIC_IS_DCE32(rdev)) {
1779 return radeon_crtc->crtc_id;
1782 /* on DCE3 - LVTMA can only be driven by DIGB */
1783 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1784 struct radeon_encoder *radeon_test_encoder;
1786 if (encoder == test_encoder)
1789 if (!radeon_encoder_is_digital(test_encoder))
1792 radeon_test_encoder = to_radeon_encoder(test_encoder);
1793 dig = radeon_test_encoder->enc_priv;
1795 if (dig->dig_encoder >= 0)
1796 dig_enc_in_use |= (1 << dig->dig_encoder);
1799 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1800 if (dig_enc_in_use & 0x2)
1801 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1804 if (!(dig_enc_in_use & 1))
1809 /* This only needs to be called once at startup */
1811 radeon_atom_encoder_init(struct radeon_device *rdev)
1813 struct drm_device *dev = rdev->ddev;
1814 struct drm_encoder *encoder;
1816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1817 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1818 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1820 switch (radeon_encoder->encoder_id) {
1821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1824 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1825 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1831 if (ext_encoder && ASIC_IS_DCE41(rdev))
1832 atombios_external_encoder_setup(encoder, ext_encoder,
1833 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1838 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1839 struct drm_display_mode *mode,
1840 struct drm_display_mode *adjusted_mode)
1842 struct drm_device *dev = encoder->dev;
1843 struct radeon_device *rdev = dev->dev_private;
1844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1846 radeon_encoder->pixel_clock = adjusted_mode->clock;
1848 /* need to call this here rather than in prepare() since we need some crtc info */
1849 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1851 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1852 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1853 atombios_yuv_setup(encoder, true);
1855 atombios_yuv_setup(encoder, false);
1858 switch (radeon_encoder->encoder_id) {
1859 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1860 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1861 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1862 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1863 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1868 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1869 /* handled in dpms */
1871 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1872 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1873 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1874 atombios_dvo_setup(encoder, ATOM_ENABLE);
1876 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1877 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1878 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1880 atombios_dac_setup(encoder, ATOM_ENABLE);
1881 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1882 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1883 atombios_tv_setup(encoder, ATOM_ENABLE);
1885 atombios_tv_setup(encoder, ATOM_DISABLE);
1890 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1892 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1893 r600_hdmi_enable(encoder);
1894 r600_hdmi_setmode(encoder, adjusted_mode);
1899 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1901 struct drm_device *dev = encoder->dev;
1902 struct radeon_device *rdev = dev->dev_private;
1903 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1904 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1906 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1907 ATOM_DEVICE_CV_SUPPORT |
1908 ATOM_DEVICE_CRT_SUPPORT)) {
1909 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1910 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1913 memset(&args, 0, sizeof(args));
1915 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1918 args.sDacload.ucMisc = 0;
1920 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1921 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1922 args.sDacload.ucDacType = ATOM_DAC_A;
1924 args.sDacload.ucDacType = ATOM_DAC_B;
1926 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1927 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1928 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1929 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1930 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1931 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1933 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1934 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1935 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1937 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1947 static enum drm_connector_status
1948 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1950 struct drm_device *dev = encoder->dev;
1951 struct radeon_device *rdev = dev->dev_private;
1952 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1953 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1954 uint32_t bios_0_scratch;
1956 if (!atombios_dac_load_detect(encoder, connector)) {
1957 DRM_DEBUG_KMS("detect returned false \n");
1958 return connector_status_unknown;
1961 if (rdev->family >= CHIP_R600)
1962 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1964 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1966 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1967 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1968 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1969 return connector_status_connected;
1971 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1972 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1973 return connector_status_connected;
1975 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1976 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1977 return connector_status_connected;
1979 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1980 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1981 return connector_status_connected; /* CTV */
1982 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1983 return connector_status_connected; /* STV */
1985 return connector_status_disconnected;
1988 static enum drm_connector_status
1989 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1991 struct drm_device *dev = encoder->dev;
1992 struct radeon_device *rdev = dev->dev_private;
1993 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1994 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1995 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1998 if (!ASIC_IS_DCE4(rdev))
1999 return connector_status_unknown;
2002 return connector_status_unknown;
2004 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2005 return connector_status_unknown;
2007 /* load detect on the dp bridge */
2008 atombios_external_encoder_setup(encoder, ext_encoder,
2009 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2011 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2013 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2014 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2015 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2016 return connector_status_connected;
2018 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2019 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2020 return connector_status_connected;
2022 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2023 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2024 return connector_status_connected;
2026 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2027 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2028 return connector_status_connected; /* CTV */
2029 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2030 return connector_status_connected; /* STV */
2032 return connector_status_disconnected;
2036 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2038 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2041 /* ddc_setup on the dp bridge */
2042 atombios_external_encoder_setup(encoder, ext_encoder,
2043 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2047 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2049 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2050 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2052 if ((radeon_encoder->active_device &
2053 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2054 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2055 ENCODER_OBJECT_ID_NONE)) {
2056 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2058 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2061 radeon_atom_output_lock(encoder, true);
2064 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2066 /* select the clock/data port if it uses a router */
2067 if (radeon_connector->router.cd_valid)
2068 radeon_router_select_cd_port(radeon_connector);
2070 /* turn eDP panel on for mode set */
2071 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2072 atombios_set_edp_panel_power(connector,
2073 ATOM_TRANSMITTER_ACTION_POWER_ON);
2076 /* this is needed for the pll/ss setup to work correctly in some cases */
2077 atombios_set_encoder_crtc_source(encoder);
2080 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2082 /* need to call this here as we need the crtc set up */
2083 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2084 radeon_atom_output_lock(encoder, false);
2087 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2089 struct drm_device *dev = encoder->dev;
2090 struct radeon_device *rdev = dev->dev_private;
2091 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2092 struct radeon_encoder_atom_dig *dig;
2094 /* check for pre-DCE3 cards with shared encoders;
2095 * can't really use the links individually, so don't disable
2096 * the encoder if it's in use by another connector
2098 if (!ASIC_IS_DCE3(rdev)) {
2099 struct drm_encoder *other_encoder;
2100 struct radeon_encoder *other_radeon_encoder;
2102 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2103 other_radeon_encoder = to_radeon_encoder(other_encoder);
2104 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2105 drm_helper_encoder_in_use(other_encoder))
2110 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2112 switch (radeon_encoder->encoder_id) {
2113 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2114 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2115 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2116 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2117 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2122 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2123 /* handled in dpms */
2125 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2126 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2128 atombios_dvo_setup(encoder, ATOM_DISABLE);
2130 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2131 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2132 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2133 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2134 atombios_dac_setup(encoder, ATOM_DISABLE);
2135 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2136 atombios_tv_setup(encoder, ATOM_DISABLE);
2141 if (radeon_encoder_is_digital(encoder)) {
2142 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2143 r600_hdmi_disable(encoder);
2144 dig = radeon_encoder->enc_priv;
2145 dig->dig_encoder = -1;
2147 radeon_encoder->active_device = 0;
2150 /* these are handled by the primary encoders */
2151 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2156 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2162 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2163 struct drm_display_mode *mode,
2164 struct drm_display_mode *adjusted_mode)
2169 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2175 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2180 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2181 struct drm_display_mode *mode,
2182 struct drm_display_mode *adjusted_mode)
2187 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2188 .dpms = radeon_atom_ext_dpms,
2189 .mode_fixup = radeon_atom_ext_mode_fixup,
2190 .prepare = radeon_atom_ext_prepare,
2191 .mode_set = radeon_atom_ext_mode_set,
2192 .commit = radeon_atom_ext_commit,
2193 .disable = radeon_atom_ext_disable,
2194 /* no detect for TMDS/LVDS yet */
2197 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2198 .dpms = radeon_atom_encoder_dpms,
2199 .mode_fixup = radeon_atom_mode_fixup,
2200 .prepare = radeon_atom_encoder_prepare,
2201 .mode_set = radeon_atom_encoder_mode_set,
2202 .commit = radeon_atom_encoder_commit,
2203 .disable = radeon_atom_encoder_disable,
2204 .detect = radeon_atom_dig_detect,
2207 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2208 .dpms = radeon_atom_encoder_dpms,
2209 .mode_fixup = radeon_atom_mode_fixup,
2210 .prepare = radeon_atom_encoder_prepare,
2211 .mode_set = radeon_atom_encoder_mode_set,
2212 .commit = radeon_atom_encoder_commit,
2213 .detect = radeon_atom_dac_detect,
2216 void radeon_enc_destroy(struct drm_encoder *encoder)
2218 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2219 kfree(radeon_encoder->enc_priv);
2220 drm_encoder_cleanup(encoder);
2221 kfree(radeon_encoder);
2224 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2225 .destroy = radeon_enc_destroy,
2228 struct radeon_encoder_atom_dac *
2229 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2231 struct drm_device *dev = radeon_encoder->base.dev;
2232 struct radeon_device *rdev = dev->dev_private;
2233 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2238 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2242 struct radeon_encoder_atom_dig *
2243 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2245 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2246 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2251 /* coherent mode by default */
2252 dig->coherent_mode = true;
2253 dig->dig_encoder = -1;
2255 if (encoder_enum == 2)
2264 radeon_add_atom_encoder(struct drm_device *dev,
2265 uint32_t encoder_enum,
2266 uint32_t supported_device,
2269 struct radeon_device *rdev = dev->dev_private;
2270 struct drm_encoder *encoder;
2271 struct radeon_encoder *radeon_encoder;
2273 /* see if we already added it */
2274 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2275 radeon_encoder = to_radeon_encoder(encoder);
2276 if (radeon_encoder->encoder_enum == encoder_enum) {
2277 radeon_encoder->devices |= supported_device;
2284 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2285 if (!radeon_encoder)
2288 encoder = &radeon_encoder->base;
2289 switch (rdev->num_crtc) {
2291 encoder->possible_crtcs = 0x1;
2295 encoder->possible_crtcs = 0x3;
2298 encoder->possible_crtcs = 0xf;
2301 encoder->possible_crtcs = 0x3f;
2305 radeon_encoder->enc_priv = NULL;
2307 radeon_encoder->encoder_enum = encoder_enum;
2308 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2309 radeon_encoder->devices = supported_device;
2310 radeon_encoder->rmx_type = RMX_OFF;
2311 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2312 radeon_encoder->is_ext_encoder = false;
2313 radeon_encoder->caps = caps;
2315 switch (radeon_encoder->encoder_id) {
2316 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2317 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2318 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2319 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2320 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2321 radeon_encoder->rmx_type = RMX_FULL;
2322 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2323 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2325 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2326 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2328 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2330 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2331 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2332 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2333 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2335 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2336 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2337 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2338 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2339 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2340 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2342 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2343 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2344 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2345 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2346 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2347 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2348 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2349 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2350 radeon_encoder->rmx_type = RMX_FULL;
2351 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2352 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2353 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2354 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2355 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2357 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2358 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2360 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2362 case ENCODER_OBJECT_ID_SI170B:
2363 case ENCODER_OBJECT_ID_CH7303:
2364 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2365 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2366 case ENCODER_OBJECT_ID_TITFP513:
2367 case ENCODER_OBJECT_ID_VT1623:
2368 case ENCODER_OBJECT_ID_HDMI_SI1930:
2369 case ENCODER_OBJECT_ID_TRAVIS:
2370 case ENCODER_OBJECT_ID_NUTMEG:
2371 /* these are handled by the primary encoders */
2372 radeon_encoder->is_ext_encoder = true;
2373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2374 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2375 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2376 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2378 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2379 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);