drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.usOverscanRight = 0;
  48         args.usOverscanLeft = 0;
  49         args.usOverscanBottom = 0;
  50         args.usOverscanTop = 0;
  51         args.ucCRTC = radeon_crtc->crtc_id;
  52
  53         switch (radeon_crtc->rmx_type) {
  54         case RMX_CENTER:
  55                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  56                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  57                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  58                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  59                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  60                 break;
  61         case RMX_ASPECT:
  62                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  63                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  64
  65                 if (a1 > a2) {
  66                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  67                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  68                 } else if (a2 > a1) {
  69                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  70                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  71                 }
  72                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  73                 break;
  74         case RMX_FULL:
  75         default:
  76                 args.usOverscanRight = 0;
  77                 args.usOverscanLeft = 0;
  78                 args.usOverscanBottom = 0;
  79                 args.usOverscanTop = 0;
  80                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  81                 break;
  82         }
  83 }
  84
  85 static void atombios_scaler_setup(struct drm_crtc *crtc)
  86 {
  87         struct drm_device *dev = crtc->dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         ENABLE_SCALER_PS_ALLOCATION args;
  91         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  92
  93         /* fixme - fill in enc_priv for atom dac */
  94         enum radeon_tv_std tv_std = TV_STD_NTSC;
  95         bool is_tv = false, is_cv = false;
  96         struct drm_encoder *encoder;
  97
  98         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  99                 return;
 100
 101         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 102                 /* find tv std */
 103                 if (encoder->crtc == crtc) {
 104                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 105                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 106                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 107                                 tv_std = tv_dac->tv_std;
 108                                 is_tv = true;
 109                         }
 110                 }
 111         }
 112
 113         memset(&args, 0, sizeof(args));
 114
 115         args.ucScaler = radeon_crtc->crtc_id;
 116
 117         if (is_tv) {
 118                 switch (tv_std) {
 119                 case TV_STD_NTSC:
 120                 default:
 121                         args.ucTVStandard = ATOM_TV_NTSC;
 122                         break;
 123                 case TV_STD_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL;
 125                         break;
 126                 case TV_STD_PAL_M:
 127                         args.ucTVStandard = ATOM_TV_PALM;
 128                         break;
 129                 case TV_STD_PAL_60:
 130                         args.ucTVStandard = ATOM_TV_PAL60;
 131                         break;
 132                 case TV_STD_NTSC_J:
 133                         args.ucTVStandard = ATOM_TV_NTSCJ;
 134                         break;
 135                 case TV_STD_SCART_PAL:
 136                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 137                         break;
 138                 case TV_STD_SECAM:
 139                         args.ucTVStandard = ATOM_TV_SECAM;
 140                         break;
 141                 case TV_STD_PAL_CN:
 142                         args.ucTVStandard = ATOM_TV_PALCN;
 143                         break;
 144                 }
 145                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 146         } else if (is_cv) {
 147                 args.ucTVStandard = ATOM_TV_CV;
 148                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 149         } else {
 150                 switch (radeon_crtc->rmx_type) {
 151                 case RMX_FULL:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 case RMX_CENTER:
 155                         args.ucEnable = ATOM_SCALER_CENTER;
 156                         break;
 157                 case RMX_ASPECT:
 158                         args.ucEnable = ATOM_SCALER_EXPANSION;
 159                         break;
 160                 default:
 161                         if (ASIC_IS_AVIVO(rdev))
 162                                 args.ucEnable = ATOM_SCALER_DISABLE;
 163                         else
 164                                 args.ucEnable = ATOM_SCALER_CENTER;
 165                         break;
 166                 }
 167         }
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169         if ((is_tv || is_cv)
 170             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 171                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 172         }
 173 }
 174
 175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 176 {
 177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 178         struct drm_device *dev = crtc->dev;
 179         struct radeon_device *rdev = dev->dev_private;
 180         int index =
 181             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 182         ENABLE_CRTC_PS_ALLOCATION args;
 183
 184         memset(&args, 0, sizeof(args));
 185
 186         args.ucCRTC = radeon_crtc->crtc_id;
 187         args.ucEnable = lock;
 188
 189         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 190 }
 191
 192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 193 {
 194         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 195         struct drm_device *dev = crtc->dev;
 196         struct radeon_device *rdev = dev->dev_private;
 197         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 198         ENABLE_CRTC_PS_ALLOCATION args;
 199
 200         memset(&args, 0, sizeof(args));
 201
 202         args.ucCRTC = radeon_crtc->crtc_id;
 203         args.ucEnable = state;
 204
 205         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 206 }
 207
 208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 209 {
 210         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 211         struct drm_device *dev = crtc->dev;
 212         struct radeon_device *rdev = dev->dev_private;
 213         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 214         ENABLE_CRTC_PS_ALLOCATION args;
 215
 216         memset(&args, 0, sizeof(args));
 217
 218         args.ucCRTC = radeon_crtc->crtc_id;
 219         args.ucEnable = state;
 220
 221         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 222 }
 223
 224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 225 {
 226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 227         struct drm_device *dev = crtc->dev;
 228         struct radeon_device *rdev = dev->dev_private;
 229         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 230         BLANK_CRTC_PS_ALLOCATION args;
 231
 232         memset(&args, 0, sizeof(args));
 233
 234         args.ucCRTC = radeon_crtc->crtc_id;
 235         args.ucBlanking = state;
 236
 237         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 238 }
 239
 240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 241 {
 242         struct drm_device *dev = crtc->dev;
 243         struct radeon_device *rdev = dev->dev_private;
 244         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 245
 246         switch (mode) {
 247         case DRM_MODE_DPMS_ON:
 248                 radeon_crtc->enabled = true;
 249                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 250                 radeon_pm_compute_clocks(rdev);
 251                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 252                 if (ASIC_IS_DCE3(rdev))
 253                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 254                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 255                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 256                 radeon_crtc_load_lut(crtc);
 257                 break;
 258         case DRM_MODE_DPMS_STANDBY:
 259         case DRM_MODE_DPMS_SUSPEND:
 260         case DRM_MODE_DPMS_OFF:
 261                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 262                 atombios_blank_crtc(crtc, ATOM_ENABLE);
 263                 if (ASIC_IS_DCE3(rdev))
 264                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 265                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 266                 radeon_crtc->enabled = false;
 267                 /* adjust pm to dpms changes AFTER disabling crtcs */
 268                 radeon_pm_compute_clocks(rdev);
 269                 break;
 270         }
 271 }
 272
 273 static void
 274 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 275                              struct drm_display_mode *mode)
 276 {
 277         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 278         struct drm_device *dev = crtc->dev;
 279         struct radeon_device *rdev = dev->dev_private;
 280         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 281         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 282         u16 misc = 0;
 283
 284         memset(&args, 0, sizeof(args));
 285         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
 286         args.usH_Blanking_Time =
 287                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
 288         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
 289         args.usV_Blanking_Time =
 290             cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
 291         args.usH_SyncOffset =
 292                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
 293         args.usH_SyncWidth =
 294                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 295         args.usV_SyncOffset =
 296                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
 297         args.usV_SyncWidth =
 298                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 299         /*args.ucH_Border = mode->hborder;*/
 300         /*args.ucV_Border = mode->vborder;*/
 301
 302         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 303                 misc |= ATOM_VSYNC_POLARITY;
 304         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 305                 misc |= ATOM_HSYNC_POLARITY;
 306         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 307                 misc |= ATOM_COMPOSITESYNC;
 308         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 309                 misc |= ATOM_INTERLACE;
 310         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 311                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 312
 313         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 314         args.ucCRTC = radeon_crtc->crtc_id;
 315
 316         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 317 }
 318
 319 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 320                                      struct drm_display_mode *mode)
 321 {
 322         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 323         struct drm_device *dev = crtc->dev;
 324         struct radeon_device *rdev = dev->dev_private;
 325         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 326         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 327         u16 misc = 0;
 328
 329         memset(&args, 0, sizeof(args));
 330         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 331         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 332         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 333         args.usH_SyncWidth =
 334                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 335         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 336         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 337         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 338         args.usV_SyncWidth =
 339                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 340
 341         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 342                 misc |= ATOM_VSYNC_POLARITY;
 343         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 344                 misc |= ATOM_HSYNC_POLARITY;
 345         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 346                 misc |= ATOM_COMPOSITESYNC;
 347         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 348                 misc |= ATOM_INTERLACE;
 349         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 350                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 351
 352         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 353         args.ucCRTC = radeon_crtc->crtc_id;
 354
 355         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 356 }
 357
 358 static void atombios_disable_ss(struct drm_crtc *crtc)
 359 {
 360         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 361         struct drm_device *dev = crtc->dev;
 362         struct radeon_device *rdev = dev->dev_private;
 363         u32 ss_cntl;
 364
 365         if (ASIC_IS_DCE4(rdev)) {
 366                 switch (radeon_crtc->pll_id) {
 367                 case ATOM_PPLL1:
 368                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 369                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 370                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 371                         break;
 372                 case ATOM_PPLL2:
 373                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 374                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 375                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 376                         break;
 377                 case ATOM_DCPLL:
 378                 case ATOM_PPLL_INVALID:
 379                         return;
 380                 }
 381         } else if (ASIC_IS_AVIVO(rdev)) {
 382                 switch (radeon_crtc->pll_id) {
 383                 case ATOM_PPLL1:
 384                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 385                         ss_cntl &= ~1;
 386                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 387                         break;
 388                 case ATOM_PPLL2:
 389                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 390                         ss_cntl &= ~1;
 391                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 392                         break;
 393                 case ATOM_DCPLL:
 394                 case ATOM_PPLL_INVALID:
 395                         return;
 396                 }
 397         }
 398 }
 399
 400
 401 union atom_enable_ss {
 402         ENABLE_LVDS_SS_PARAMETERS legacy;
 403         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 404 };
 405
 406 static void atombios_enable_ss(struct drm_crtc *crtc)
 407 {
 408         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 409         struct drm_device *dev = crtc->dev;
 410         struct radeon_device *rdev = dev->dev_private;
 411         struct drm_encoder *encoder = NULL;
 412         struct radeon_encoder *radeon_encoder = NULL;
 413         struct radeon_encoder_atom_dig *dig = NULL;
 414         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 415         union atom_enable_ss args;
 416         uint16_t percentage = 0;
 417         uint8_t type = 0, step = 0, delay = 0, range = 0;
 418
 419         /* XXX add ss support for DCE4 */
 420         if (ASIC_IS_DCE4(rdev))
 421                 return;
 422
 423         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 424                 if (encoder->crtc == crtc) {
 425                         radeon_encoder = to_radeon_encoder(encoder);
 426                         /* only enable spread spectrum on LVDS */
 427                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 428                                 dig = radeon_encoder->enc_priv;
 429                                 if (dig && dig->ss) {
 430                                         percentage = dig->ss->percentage;
 431                                         type = dig->ss->type;
 432                                         step = dig->ss->step;
 433                                         delay = dig->ss->delay;
 434                                         range = dig->ss->range;
 435                                 } else
 436                                         return;
 437                         } else
 438                                 return;
 439                         break;
 440                 }
 441         }
 442
 443         if (!radeon_encoder)
 444                 return;
 445
 446         memset(&args, 0, sizeof(args));
 447         if (ASIC_IS_AVIVO(rdev)) {
 448                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 449                 args.v1.ucSpreadSpectrumType = type;
 450                 args.v1.ucSpreadSpectrumStep = step;
 451                 args.v1.ucSpreadSpectrumDelay = delay;
 452                 args.v1.ucSpreadSpectrumRange = range;
 453                 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 454                 args.v1.ucEnable = ATOM_ENABLE;
 455         } else {
 456                 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 457                 args.legacy.ucSpreadSpectrumType = type;
 458                 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
 459                 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
 460                 args.legacy.ucEnable = ATOM_ENABLE;
 461         }
 462         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 463 }
 464
 465 union adjust_pixel_clock {
 466         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 467         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 468 };
 469
 470 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 471                                struct drm_display_mode *mode,
 472                                struct radeon_pll *pll)
 473 {
 474         struct drm_device *dev = crtc->dev;
 475         struct radeon_device *rdev = dev->dev_private;
 476         struct drm_encoder *encoder = NULL;
 477         struct radeon_encoder *radeon_encoder = NULL;
 478         u32 adjusted_clock = mode->clock;
 479         int encoder_mode = 0;
 480
 481         /* reset the pll flags */
 482         pll->flags = 0;
 483
 484         /* select the PLL algo */
 485         if (ASIC_IS_AVIVO(rdev)) {
 486                 if (radeon_new_pll == 0)
 487                         pll->algo = PLL_ALGO_LEGACY;
 488                 else
 489                         pll->algo = PLL_ALGO_NEW;
 490         } else {
 491                 if (radeon_new_pll == 1)
 492                         pll->algo = PLL_ALGO_NEW;
 493                 else
 494                         pll->algo = PLL_ALGO_LEGACY;
 495         }
 496
 497         if (ASIC_IS_AVIVO(rdev)) {
 498                 if ((rdev->family == CHIP_RS600) ||
 499                     (rdev->family == CHIP_RS690) ||
 500                     (rdev->family == CHIP_RS740))
 501                         pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
 502                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 503
 504                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 505                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 506                 else
 507                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 508         } else {
 509                 pll->flags |= RADEON_PLL_LEGACY;
 510
 511                 if (mode->clock > 200000)       /* range limits??? */
 512                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 513                 else
 514                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 515
 516         }
 517
 518         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 519                 if (encoder->crtc == crtc) {
 520                         radeon_encoder = to_radeon_encoder(encoder);
 521                         encoder_mode = atombios_get_encoder_mode(encoder);
 522                         if (ASIC_IS_AVIVO(rdev)) {
 523                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 524                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 525                                         adjusted_clock = mode->clock * 2;
 526                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 527                                         pll->algo = PLL_ALGO_LEGACY;
 528                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 529                                 }
 530                         } else {
 531                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 532                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 533                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 534                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 535                         }
 536                         break;
 537                 }
 538         }
 539
 540         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 541          * accordingly based on the encoder/transmitter to work around
 542          * special hw requirements.
 543          */
 544         if (ASIC_IS_DCE3(rdev)) {
 545                 union adjust_pixel_clock args;
 546                 u8 frev, crev;
 547                 int index;
 548
 549                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 550                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 551                                            &crev))
 552                         return adjusted_clock;
 553
 554                 memset(&args, 0, sizeof(args));
 555
 556                 switch (frev) {
 557                 case 1:
 558                         switch (crev) {
 559                         case 1:
 560                         case 2:
 561                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 562                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 563                                 args.v1.ucEncodeMode = encoder_mode;
 564
 565                                 atom_execute_table(rdev->mode_info.atom_context,
 566                                                    index, (uint32_t *)&args);
 567                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 568                                 break;
 569                         case 3:
 570                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 571                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 572                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 573                                 args.v3.sInput.ucDispPllConfig = 0;
 574                                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 575                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 576
 577                                         if (encoder_mode == ATOM_ENCODER_MODE_DP)
 578                                                 args.v3.sInput.ucDispPllConfig |=
 579                                                         DISPPLL_CONFIG_COHERENT_MODE;
 580                                         else {
 581                                                 if (dig->coherent_mode)
 582                                                         args.v3.sInput.ucDispPllConfig |=
 583                                                                 DISPPLL_CONFIG_COHERENT_MODE;
 584                                                 if (mode->clock > 165000)
 585                                                         args.v3.sInput.ucDispPllConfig |=
 586                                                                 DISPPLL_CONFIG_DUAL_LINK;
 587                                         }
 588                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 589                                         /* may want to enable SS on DP/eDP eventually */
 590                                         /*args.v3.sInput.ucDispPllConfig |=
 591                                                 DISPPLL_CONFIG_SS_ENABLE;*/
 592                                         if (encoder_mode == ATOM_ENCODER_MODE_DP)
 593                                                 args.v3.sInput.ucDispPllConfig |=
 594                                                         DISPPLL_CONFIG_COHERENT_MODE;
 595                                         else {
 596                                                 if (mode->clock > 165000)
 597                                                         args.v3.sInput.ucDispPllConfig |=
 598                                                                 DISPPLL_CONFIG_DUAL_LINK;
 599                                         }
 600                                 }
 601                                 atom_execute_table(rdev->mode_info.atom_context,
 602                                                    index, (uint32_t *)&args);
 603                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 604                                 if (args.v3.sOutput.ucRefDiv) {
 605                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 606                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 607                                 }
 608                                 if (args.v3.sOutput.ucPostDiv) {
 609                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 610                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 611                                 }
 612                                 break;
 613                         default:
 614                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 615                                 return adjusted_clock;
 616                         }
 617                         break;
 618                 default:
 619                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 620                         return adjusted_clock;
 621                 }
 622         }
 623         return adjusted_clock;
 624 }
 625
 626 union set_pixel_clock {
 627         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 628         PIXEL_CLOCK_PARAMETERS v1;
 629         PIXEL_CLOCK_PARAMETERS_V2 v2;
 630         PIXEL_CLOCK_PARAMETERS_V3 v3;
 631         PIXEL_CLOCK_PARAMETERS_V5 v5;
 632 };
 633
 634 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
 635 {
 636         struct drm_device *dev = crtc->dev;
 637         struct radeon_device *rdev = dev->dev_private;
 638         u8 frev, crev;
 639         int index;
 640         union set_pixel_clock args;
 641
 642         memset(&args, 0, sizeof(args));
 643
 644         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 645         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 646                                    &crev))
 647                 return;
 648
 649         switch (frev) {
 650         case 1:
 651                 switch (crev) {
 652                 case 5:
 653                         /* if the default dcpll clock is specified,
 654                          * SetPixelClock provides the dividers
 655                          */
 656                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 657                         args.v5.usPixelClock = rdev->clock.default_dispclk;
 658                         args.v5.ucPpll = ATOM_DCPLL;
 659                         break;
 660                 default:
 661                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 662                         return;
 663                 }
 664                 break;
 665         default:
 666                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 667                 return;
 668         }
 669         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 670 }
 671
 672 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 673 {
 674         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 675         struct drm_device *dev = crtc->dev;
 676         struct radeon_device *rdev = dev->dev_private;
 677         struct drm_encoder *encoder = NULL;
 678         struct radeon_encoder *radeon_encoder = NULL;
 679         u8 frev, crev;
 680         int index;
 681         union set_pixel_clock args;
 682         u32 pll_clock = mode->clock;
 683         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 684         struct radeon_pll *pll;
 685         u32 adjusted_clock;
 686         int encoder_mode = 0;
 687
 688         memset(&args, 0, sizeof(args));
 689
 690         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 691                 if (encoder->crtc == crtc) {
 692                         radeon_encoder = to_radeon_encoder(encoder);
 693                         encoder_mode = atombios_get_encoder_mode(encoder);
 694                         break;
 695                 }
 696         }
 697
 698         if (!radeon_encoder)
 699                 return;
 700
 701         switch (radeon_crtc->pll_id) {
 702         case ATOM_PPLL1:
 703                 pll = &rdev->clock.p1pll;
 704                 break;
 705         case ATOM_PPLL2:
 706                 pll = &rdev->clock.p2pll;
 707                 break;
 708         case ATOM_DCPLL:
 709         case ATOM_PPLL_INVALID:
 710         default:
 711                 pll = &rdev->clock.dcpll;
 712                 break;
 713         }
 714
 715         /* adjust pixel clock as needed */
 716         adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
 717
 718         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 719                            &ref_div, &post_div);
 720
 721         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 722         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 723                                    &crev))
 724                 return;
 725
 726         switch (frev) {
 727         case 1:
 728                 switch (crev) {
 729                 case 1:
 730                         args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 731                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 732                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 733                         args.v1.ucFracFbDiv = frac_fb_div;
 734                         args.v1.ucPostDiv = post_div;
 735                         args.v1.ucPpll = radeon_crtc->pll_id;
 736                         args.v1.ucCRTC = radeon_crtc->crtc_id;
 737                         args.v1.ucRefDivSrc = 1;
 738                         break;
 739                 case 2:
 740                         args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
 741                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 742                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 743                         args.v2.ucFracFbDiv = frac_fb_div;
 744                         args.v2.ucPostDiv = post_div;
 745                         args.v2.ucPpll = radeon_crtc->pll_id;
 746                         args.v2.ucCRTC = radeon_crtc->crtc_id;
 747                         args.v2.ucRefDivSrc = 1;
 748                         break;
 749                 case 3:
 750                         args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
 751                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 752                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 753                         args.v3.ucFracFbDiv = frac_fb_div;
 754                         args.v3.ucPostDiv = post_div;
 755                         args.v3.ucPpll = radeon_crtc->pll_id;
 756                         args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
 757                         args.v3.ucTransmitterId = radeon_encoder->encoder_id;
 758                         args.v3.ucEncoderMode = encoder_mode;
 759                         break;
 760                 case 5:
 761                         args.v5.ucCRTC = radeon_crtc->crtc_id;
 762                         args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
 763                         args.v5.ucRefDiv = ref_div;
 764                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 765                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 766                         args.v5.ucPostDiv = post_div;
 767                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 768                         args.v5.ucTransmitterID = radeon_encoder->encoder_id;
 769                         args.v5.ucEncoderMode = encoder_mode;
 770                         args.v5.ucPpll = radeon_crtc->pll_id;
 771                         break;
 772                 default:
 773                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 774                         return;
 775                 }
 776                 break;
 777         default:
 778                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 779                 return;
 780         }
 781
 782         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 783 }
 784
 785 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 786                                    struct drm_framebuffer *old_fb)
 787 {
 788         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 789         struct drm_device *dev = crtc->dev;
 790         struct radeon_device *rdev = dev->dev_private;
 791         struct radeon_framebuffer *radeon_fb;
 792         struct drm_gem_object *obj;
 793         struct radeon_bo *rbo;
 794         uint64_t fb_location;
 795         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 796         int r;
 797
 798         /* no fb bound */
 799         if (!crtc->fb) {
 800                 DRM_DEBUG("No FB bound\n");
 801                 return 0;
 802         }
 803
 804         radeon_fb = to_radeon_framebuffer(crtc->fb);
 805
 806         /* Pin framebuffer & get tilling informations */
 807         obj = radeon_fb->obj;
 808         rbo = obj->driver_private;
 809         r = radeon_bo_reserve(rbo, false);
 810         if (unlikely(r != 0))
 811                 return r;
 812         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 813         if (unlikely(r != 0)) {
 814                 radeon_bo_unreserve(rbo);
 815                 return -EINVAL;
 816         }
 817         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 818         radeon_bo_unreserve(rbo);
 819
 820         switch (crtc->fb->bits_per_pixel) {
 821         case 8:
 822                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
 823                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
 824                 break;
 825         case 15:
 826                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 827                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
 828                 break;
 829         case 16:
 830                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 831                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
 832                 break;
 833         case 24:
 834         case 32:
 835                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
 836                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
 837                 break;
 838         default:
 839                 DRM_ERROR("Unsupported screen depth %d\n",
 840                           crtc->fb->bits_per_pixel);
 841                 return -EINVAL;
 842         }
 843
 844         switch (radeon_crtc->crtc_id) {
 845         case 0:
 846                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 847                 break;
 848         case 1:
 849                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 850                 break;
 851         case 2:
 852                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 853                 break;
 854         case 3:
 855                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 856                 break;
 857         case 4:
 858                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 859                 break;
 860         case 5:
 861                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 862                 break;
 863         default:
 864                 break;
 865         }
 866
 867         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 868                upper_32_bits(fb_location));
 869         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 870                upper_32_bits(fb_location));
 871         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 872                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 873         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 874                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 875         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 876
 877         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 878         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 879         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
 880         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 881         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 882         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 883
 884         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 885         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 886         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 887
 888         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 889                crtc->mode.vdisplay);
 890         x &= ~3;
 891         y &= ~1;
 892         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
 893                (x << 16) | y);
 894         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 895                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 896
 897         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 898                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
 899                        EVERGREEN_INTERLEAVE_EN);
 900         else
 901                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
 902
 903         if (old_fb && old_fb != crtc->fb) {
 904                 radeon_fb = to_radeon_framebuffer(old_fb);
 905                 rbo = radeon_fb->obj->driver_private;
 906                 r = radeon_bo_reserve(rbo, false);
 907                 if (unlikely(r != 0))
 908                         return r;
 909                 radeon_bo_unpin(rbo);
 910                 radeon_bo_unreserve(rbo);
 911         }
 912
 913         /* Bytes per pixel may have changed */
 914         radeon_bandwidth_update(rdev);
 915
 916         return 0;
 917 }
 918
 919 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 920                                struct drm_framebuffer *old_fb)
 921 {
 922         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 923         struct drm_device *dev = crtc->dev;
 924         struct radeon_device *rdev = dev->dev_private;
 925         struct radeon_framebuffer *radeon_fb;
 926         struct drm_gem_object *obj;
 927         struct radeon_bo *rbo;
 928         uint64_t fb_location;
 929         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 930         int r;
 931
 932         /* no fb bound */
 933         if (!crtc->fb) {
 934                 DRM_DEBUG("No FB bound\n");
 935                 return 0;
 936         }
 937
 938         radeon_fb = to_radeon_framebuffer(crtc->fb);
 939
 940         /* Pin framebuffer & get tilling informations */
 941         obj = radeon_fb->obj;
 942         rbo = obj->driver_private;
 943         r = radeon_bo_reserve(rbo, false);
 944         if (unlikely(r != 0))
 945                 return r;
 946         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 947         if (unlikely(r != 0)) {
 948                 radeon_bo_unreserve(rbo);
 949                 return -EINVAL;
 950         }
 951         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 952         radeon_bo_unreserve(rbo);
 953
 954         switch (crtc->fb->bits_per_pixel) {
 955         case 8:
 956                 fb_format =
 957                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
 958                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
 959                 break;
 960         case 15:
 961                 fb_format =
 962                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 963                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 964                 break;
 965         case 16:
 966                 fb_format =
 967                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 968                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 969                 break;
 970         case 24:
 971         case 32:
 972                 fb_format =
 973                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
 974                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 975                 break;
 976         default:
 977                 DRM_ERROR("Unsupported screen depth %d\n",
 978                           crtc->fb->bits_per_pixel);
 979                 return -EINVAL;
 980         }
 981
 982         if (tiling_flags & RADEON_TILING_MACRO)
 983                 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 984
 985         if (tiling_flags & RADEON_TILING_MICRO)
 986                 fb_format |= AVIVO_D1GRPH_TILED;
 987
 988         if (radeon_crtc->crtc_id == 0)
 989                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 990         else
 991                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 992
 993         if (rdev->family >= CHIP_RV770) {
 994                 if (radeon_crtc->crtc_id) {
 995                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 996                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 997                 } else {
 998                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 999                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1000                 }
1001         }
1002         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1003                (u32) fb_location);
1004         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1005                radeon_crtc->crtc_offset, (u32) fb_location);
1006         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1007
1008         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1009         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1010         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1011         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1012         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1013         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1014
1015         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1016         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1017         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1018
1019         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1020                crtc->mode.vdisplay);
1021         x &= ~3;
1022         y &= ~1;
1023         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1024                (x << 16) | y);
1025         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1026                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1027
1028         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1029                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1030                        AVIVO_D1MODE_INTERLEAVE_EN);
1031         else
1032                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1033
1034         if (old_fb && old_fb != crtc->fb) {
1035                 radeon_fb = to_radeon_framebuffer(old_fb);
1036                 rbo = radeon_fb->obj->driver_private;
1037                 r = radeon_bo_reserve(rbo, false);
1038                 if (unlikely(r != 0))
1039                         return r;
1040                 radeon_bo_unpin(rbo);
1041                 radeon_bo_unreserve(rbo);
1042         }
1043
1044         /* Bytes per pixel may have changed */
1045         radeon_bandwidth_update(rdev);
1046
1047         return 0;
1048 }
1049
1050 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1051                            struct drm_framebuffer *old_fb)
1052 {
1053         struct drm_device *dev = crtc->dev;
1054         struct radeon_device *rdev = dev->dev_private;
1055
1056         if (ASIC_IS_DCE4(rdev))
1057                 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1058         else if (ASIC_IS_AVIVO(rdev))
1059                 return avivo_crtc_set_base(crtc, x, y, old_fb);
1060         else
1061                 return radeon_crtc_set_base(crtc, x, y, old_fb);
1062 }
1063
1064 /* properly set additional regs when using atombios */
1065 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1066 {
1067         struct drm_device *dev = crtc->dev;
1068         struct radeon_device *rdev = dev->dev_private;
1069         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1070         u32 disp_merge_cntl;
1071
1072         switch (radeon_crtc->crtc_id) {
1073         case 0:
1074                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1075                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1076                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1077                 break;
1078         case 1:
1079                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1080                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1081                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1082                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1083                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1084                 break;
1085         }
1086 }
1087
1088 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1089 {
1090         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1091         struct drm_device *dev = crtc->dev;
1092         struct radeon_device *rdev = dev->dev_private;
1093         struct drm_encoder *test_encoder;
1094         struct drm_crtc *test_crtc;
1095         uint32_t pll_in_use = 0;
1096
1097         if (ASIC_IS_DCE4(rdev)) {
1098                 /* if crtc is driving DP and we have an ext clock, use that */
1099                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1100                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1101                                 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1102                                         if (rdev->clock.dp_extclk)
1103                                                 return ATOM_PPLL_INVALID;
1104                                 }
1105                         }
1106                 }
1107
1108                 /* otherwise, pick one of the plls */
1109                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1110                         struct radeon_crtc *radeon_test_crtc;
1111
1112                         if (crtc == test_crtc)
1113                                 continue;
1114
1115                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1116                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1117                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1118                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1119                 }
1120                 if (!(pll_in_use & 1))
1121                         return ATOM_PPLL1;
1122                 return ATOM_PPLL2;
1123         } else
1124                 return radeon_crtc->crtc_id;
1125
1126 }
1127
1128 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1129                            struct drm_display_mode *mode,
1130                            struct drm_display_mode *adjusted_mode,
1131                            int x, int y, struct drm_framebuffer *old_fb)
1132 {
1133         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1134         struct drm_device *dev = crtc->dev;
1135         struct radeon_device *rdev = dev->dev_private;
1136
1137         /* TODO color tiling */
1138
1139         atombios_disable_ss(crtc);
1140         /* always set DCPLL */
1141         if (ASIC_IS_DCE4(rdev))
1142                 atombios_crtc_set_dcpll(crtc);
1143         atombios_crtc_set_pll(crtc, adjusted_mode);
1144         atombios_enable_ss(crtc);
1145
1146         if (ASIC_IS_DCE4(rdev))
1147                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1148         else if (ASIC_IS_AVIVO(rdev))
1149                 atombios_crtc_set_timing(crtc, adjusted_mode);
1150         else {
1151                 atombios_crtc_set_timing(crtc, adjusted_mode);
1152                 if (radeon_crtc->crtc_id == 0)
1153                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1154                 radeon_legacy_atom_fixup(crtc);
1155         }
1156         atombios_crtc_set_base(crtc, x, y, old_fb);
1157         atombios_overscan_setup(crtc, mode, adjusted_mode);
1158         atombios_scaler_setup(crtc);
1159         return 0;
1160 }
1161
1162 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1163                                      struct drm_display_mode *mode,
1164                                      struct drm_display_mode *adjusted_mode)
1165 {
1166         struct drm_device *dev = crtc->dev;
1167         struct radeon_device *rdev = dev->dev_private;
1168
1169         /* adjust pm to upcoming mode change */
1170         radeon_pm_compute_clocks(rdev);
1171
1172         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1173                 return false;
1174         return true;
1175 }
1176
1177 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1178 {
1179         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1180
1181         /* pick pll */
1182         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1183
1184         atombios_lock_crtc(crtc, ATOM_ENABLE);
1185         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1186 }
1187
1188 static void atombios_crtc_commit(struct drm_crtc *crtc)
1189 {
1190         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1191         atombios_lock_crtc(crtc, ATOM_DISABLE);
1192 }
1193
1194 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1195         .dpms = atombios_crtc_dpms,
1196         .mode_fixup = atombios_crtc_mode_fixup,
1197         .mode_set = atombios_crtc_mode_set,
1198         .mode_set_base = atombios_crtc_set_base,
1199         .prepare = atombios_crtc_prepare,
1200         .commit = atombios_crtc_commit,
1201         .load_lut = radeon_crtc_load_lut,
1202 };
1203
1204 void radeon_atombios_init_crtc(struct drm_device *dev,
1205                                struct radeon_crtc *radeon_crtc)
1206 {
1207         struct radeon_device *rdev = dev->dev_private;
1208
1209         if (ASIC_IS_DCE4(rdev)) {
1210                 switch (radeon_crtc->crtc_id) {
1211                 case 0:
1212                 default:
1213                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1214                         break;
1215                 case 1:
1216                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1217                         break;
1218                 case 2:
1219                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1220                         break;
1221                 case 3:
1222                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1223                         break;
1224                 case 4:
1225                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1226                         break;
1227                 case 5:
1228                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1229                         break;
1230                 }
1231         } else {
1232                 if (radeon_crtc->crtc_id == 1)
1233                         radeon_crtc->crtc_offset =
1234                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1235                 else
1236                         radeon_crtc->crtc_offset = 0;
1237         }
1238         radeon_crtc->pll_id = -1;
1239         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1240 }