drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.usOverscanRight = 0;
  48         args.usOverscanLeft = 0;
  49         args.usOverscanBottom = 0;
  50         args.usOverscanTop = 0;
  51         args.ucCRTC = radeon_crtc->crtc_id;
  52
  53         switch (radeon_crtc->rmx_type) {
  54         case RMX_CENTER:
  55                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  56                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  57                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  58                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  59                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  60                 break;
  61         case RMX_ASPECT:
  62                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  63                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  64
  65                 if (a1 > a2) {
  66                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  67                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  68                 } else if (a2 > a1) {
  69                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  70                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  71                 }
  72                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  73                 break;
  74         case RMX_FULL:
  75         default:
  76                 args.usOverscanRight = 0;
  77                 args.usOverscanLeft = 0;
  78                 args.usOverscanBottom = 0;
  79                 args.usOverscanTop = 0;
  80                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  81                 break;
  82         }
  83 }
  84
  85 static void atombios_scaler_setup(struct drm_crtc *crtc)
  86 {
  87         struct drm_device *dev = crtc->dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         ENABLE_SCALER_PS_ALLOCATION args;
  91         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  92         /* fixme - fill in enc_priv for atom dac */
  93         enum radeon_tv_std tv_std = TV_STD_NTSC;
  94
  95         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  96                 return;
  97
  98         memset(&args, 0, sizeof(args));
  99
 100         args.ucScaler = radeon_crtc->crtc_id;
 101
 102         if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 103                 switch (tv_std) {
 104                 case TV_STD_NTSC:
 105                 default:
 106                         args.ucTVStandard = ATOM_TV_NTSC;
 107                         break;
 108                 case TV_STD_PAL:
 109                         args.ucTVStandard = ATOM_TV_PAL;
 110                         break;
 111                 case TV_STD_PAL_M:
 112                         args.ucTVStandard = ATOM_TV_PALM;
 113                         break;
 114                 case TV_STD_PAL_60:
 115                         args.ucTVStandard = ATOM_TV_PAL60;
 116                         break;
 117                 case TV_STD_NTSC_J:
 118                         args.ucTVStandard = ATOM_TV_NTSCJ;
 119                         break;
 120                 case TV_STD_SCART_PAL:
 121                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 122                         break;
 123                 case TV_STD_SECAM:
 124                         args.ucTVStandard = ATOM_TV_SECAM;
 125                         break;
 126                 case TV_STD_PAL_CN:
 127                         args.ucTVStandard = ATOM_TV_PALCN;
 128                         break;
 129                 }
 130                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 131         } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) {
 132                 args.ucTVStandard = ATOM_TV_CV;
 133                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 134         } else {
 135                 switch (radeon_crtc->rmx_type) {
 136                 case RMX_FULL:
 137                         args.ucEnable = ATOM_SCALER_EXPANSION;
 138                         break;
 139                 case RMX_CENTER:
 140                         args.ucEnable = ATOM_SCALER_CENTER;
 141                         break;
 142                 case RMX_ASPECT:
 143                         args.ucEnable = ATOM_SCALER_EXPANSION;
 144                         break;
 145                 default:
 146                         if (ASIC_IS_AVIVO(rdev))
 147                                 args.ucEnable = ATOM_SCALER_DISABLE;
 148                         else
 149                                 args.ucEnable = ATOM_SCALER_CENTER;
 150                         break;
 151                 }
 152         }
 153         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 154         if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)
 155             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {
 156                 atom_rv515_force_tv_scaler(rdev);
 157         }
 158 }
 159
 160 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 161 {
 162         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 163         struct drm_device *dev = crtc->dev;
 164         struct radeon_device *rdev = dev->dev_private;
 165         int index =
 166             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 167         ENABLE_CRTC_PS_ALLOCATION args;
 168
 169         memset(&args, 0, sizeof(args));
 170
 171         args.ucCRTC = radeon_crtc->crtc_id;
 172         args.ucEnable = lock;
 173
 174         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 175 }
 176
 177 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 178 {
 179         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 180         struct drm_device *dev = crtc->dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 183         ENABLE_CRTC_PS_ALLOCATION args;
 184
 185         memset(&args, 0, sizeof(args));
 186
 187         args.ucCRTC = radeon_crtc->crtc_id;
 188         args.ucEnable = state;
 189
 190         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 191 }
 192
 193 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 194 {
 195         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 199         ENABLE_CRTC_PS_ALLOCATION args;
 200
 201         memset(&args, 0, sizeof(args));
 202
 203         args.ucCRTC = radeon_crtc->crtc_id;
 204         args.ucEnable = state;
 205
 206         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 207 }
 208
 209 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 210 {
 211         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 212         struct drm_device *dev = crtc->dev;
 213         struct radeon_device *rdev = dev->dev_private;
 214         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 215         BLANK_CRTC_PS_ALLOCATION args;
 216
 217         memset(&args, 0, sizeof(args));
 218
 219         args.ucCRTC = radeon_crtc->crtc_id;
 220         args.ucBlanking = state;
 221
 222         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 223 }
 224
 225 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 226 {
 227         struct drm_device *dev = crtc->dev;
 228         struct radeon_device *rdev = dev->dev_private;
 229
 230         switch (mode) {
 231         case DRM_MODE_DPMS_ON:
 232                 if (ASIC_IS_DCE3(rdev))
 233                         atombios_enable_crtc_memreq(crtc, 1);
 234                 atombios_enable_crtc(crtc, 1);
 235                 atombios_blank_crtc(crtc, 0);
 236                 break;
 237         case DRM_MODE_DPMS_STANDBY:
 238         case DRM_MODE_DPMS_SUSPEND:
 239         case DRM_MODE_DPMS_OFF:
 240                 atombios_blank_crtc(crtc, 1);
 241                 atombios_enable_crtc(crtc, 0);
 242                 if (ASIC_IS_DCE3(rdev))
 243                         atombios_enable_crtc_memreq(crtc, 0);
 244                 break;
 245         }
 246
 247         if (mode != DRM_MODE_DPMS_OFF) {
 248                 radeon_crtc_load_lut(crtc);
 249         }
 250 }
 251
 252 static void
 253 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 254                              SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
 255 {
 256         struct drm_device *dev = crtc->dev;
 257         struct radeon_device *rdev = dev->dev_private;
 258         SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
 259         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 260
 261         conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
 262         conv_param.usH_Blanking_Time =
 263             cpu_to_le16(crtc_param->usH_Blanking_Time);
 264         conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
 265         conv_param.usV_Blanking_Time =
 266             cpu_to_le16(crtc_param->usV_Blanking_Time);
 267         conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
 268         conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
 269         conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
 270         conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
 271         conv_param.susModeMiscInfo.usAccess =
 272             cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
 273         conv_param.ucCRTC = crtc_param->ucCRTC;
 274
 275         printk("executing set crtc dtd timing\n");
 276         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
 277 }
 278
 279 void atombios_crtc_set_timing(struct drm_crtc *crtc,
 280                               SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
 281                               crtc_param)
 282 {
 283         struct drm_device *dev = crtc->dev;
 284         struct radeon_device *rdev = dev->dev_private;
 285         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
 286         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 287
 288         conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
 289         conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
 290         conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
 291         conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
 292         conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
 293         conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
 294         conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
 295         conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
 296         conv_param.susModeMiscInfo.usAccess =
 297             cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
 298         conv_param.ucCRTC = crtc_param->ucCRTC;
 299         conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
 300         conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
 301         conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
 302         conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
 303         conv_param.ucReserved = crtc_param->ucReserved;
 304
 305         printk("executing set crtc timing\n");
 306         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
 307 }
 308
 309 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 310 {
 311         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 312         struct drm_device *dev = crtc->dev;
 313         struct radeon_device *rdev = dev->dev_private;
 314         struct drm_encoder *encoder = NULL;
 315         struct radeon_encoder *radeon_encoder = NULL;
 316         uint8_t frev, crev;
 317         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 318         SET_PIXEL_CLOCK_PS_ALLOCATION args;
 319         PIXEL_CLOCK_PARAMETERS *spc1_ptr;
 320         PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
 321         PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
 322         uint32_t sclock = mode->clock;
 323         uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 324         struct radeon_pll *pll;
 325         int pll_flags = 0;
 326
 327         memset(&args, 0, sizeof(args));
 328
 329         if (ASIC_IS_AVIVO(rdev)) {
 330                 uint32_t ss_cntl;
 331
 332                 if ((rdev->family == CHIP_RS600) ||
 333                     (rdev->family == CHIP_RS690) ||
 334                     (rdev->family == CHIP_RS740))
 335                         pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
 336                                       RADEON_PLL_PREFER_CLOSEST_LOWER);
 337
 338                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 339                         pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 340                 else
 341                         pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 342
 343                 /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
 344                 if (radeon_crtc->crtc_id == 0) {
 345                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 346                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
 347                 } else {
 348                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 349                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
 350                 }
 351         } else {
 352                 pll_flags |= RADEON_PLL_LEGACY;
 353
 354                 if (mode->clock > 200000)       /* range limits??? */
 355                         pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 356                 else
 357                         pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 358
 359         }
 360
 361         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 362                 if (encoder->crtc == crtc) {
 363                         if (!ASIC_IS_AVIVO(rdev)) {
 364                                 if (encoder->encoder_type !=
 365                                     DRM_MODE_ENCODER_DAC)
 366                                         pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 367                                 if (!ASIC_IS_AVIVO(rdev)
 368                                     && (encoder->encoder_type ==
 369                                         DRM_MODE_ENCODER_LVDS))
 370                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 371                         }
 372                         radeon_encoder = to_radeon_encoder(encoder);
 373                 }
 374         }
 375
 376         if (radeon_crtc->crtc_id == 0)
 377                 pll = &rdev->clock.p1pll;
 378         else
 379                 pll = &rdev->clock.p2pll;
 380
 381         radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
 382                            &ref_div, &post_div, pll_flags);
 383
 384         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 385                               &crev);
 386
 387         switch (frev) {
 388         case 1:
 389                 switch (crev) {
 390                 case 1:
 391                         spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
 392                         spc1_ptr->usPixelClock = cpu_to_le16(sclock);
 393                         spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
 394                         spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
 395                         spc1_ptr->ucFracFbDiv = frac_fb_div;
 396                         spc1_ptr->ucPostDiv = post_div;
 397                         spc1_ptr->ucPpll =
 398                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 399                         spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
 400                         spc1_ptr->ucRefDivSrc = 1;
 401                         break;
 402                 case 2:
 403                         spc2_ptr =
 404                             (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
 405                         spc2_ptr->usPixelClock = cpu_to_le16(sclock);
 406                         spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
 407                         spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
 408                         spc2_ptr->ucFracFbDiv = frac_fb_div;
 409                         spc2_ptr->ucPostDiv = post_div;
 410                         spc2_ptr->ucPpll =
 411                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 412                         spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
 413                         spc2_ptr->ucRefDivSrc = 1;
 414                         break;
 415                 case 3:
 416                         if (!encoder)
 417                                 return;
 418                         spc3_ptr =
 419                             (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
 420                         spc3_ptr->usPixelClock = cpu_to_le16(sclock);
 421                         spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
 422                         spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
 423                         spc3_ptr->ucFracFbDiv = frac_fb_div;
 424                         spc3_ptr->ucPostDiv = post_div;
 425                         spc3_ptr->ucPpll =
 426                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 427                         spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
 428                         spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
 429                         spc3_ptr->ucEncoderMode =
 430                             atombios_get_encoder_mode(encoder);
 431                         break;
 432                 default:
 433                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 434                         return;
 435                 }
 436                 break;
 437         default:
 438                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 439                 return;
 440         }
 441
 442         printk("executing set pll\n");
 443         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 444 }
 445
 446 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 447                            struct drm_framebuffer *old_fb)
 448 {
 449         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 450         struct drm_device *dev = crtc->dev;
 451         struct radeon_device *rdev = dev->dev_private;
 452         struct radeon_framebuffer *radeon_fb;
 453         struct drm_gem_object *obj;
 454         struct drm_radeon_gem_object *obj_priv;
 455         uint64_t fb_location;
 456         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 457
 458         if (!crtc->fb)
 459                 return -EINVAL;
 460
 461         radeon_fb = to_radeon_framebuffer(crtc->fb);
 462
 463         obj = radeon_fb->obj;
 464         obj_priv = obj->driver_private;
 465
 466         if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {
 467                 return -EINVAL;
 468         }
 469
 470         switch (crtc->fb->bits_per_pixel) {
 471         case 15:
 472                 fb_format =
 473                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 474                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 475                 break;
 476         case 16:
 477                 fb_format =
 478                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 479                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 480                 break;
 481         case 24:
 482         case 32:
 483                 fb_format =
 484                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
 485                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 486                 break;
 487         default:
 488                 DRM_ERROR("Unsupported screen depth %d\n",
 489                           crtc->fb->bits_per_pixel);
 490                 return -EINVAL;
 491         }
 492
 493         radeon_object_get_tiling_flags(obj->driver_private,
 494                                        &tiling_flags, NULL);
 495         if (tiling_flags & RADEON_TILING_MACRO)
 496                 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 497
 498         if (tiling_flags & RADEON_TILING_MICRO)
 499                 fb_format |= AVIVO_D1GRPH_TILED;
 500
 501         if (radeon_crtc->crtc_id == 0)
 502                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 503         else
 504                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 505         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 506                (u32) fb_location);
 507         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
 508                radeon_crtc->crtc_offset, (u32) fb_location);
 509         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 510
 511         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 512         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 513         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
 514         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 515         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 516         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 517
 518         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 519         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 520         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 521
 522         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 523                crtc->mode.vdisplay);
 524         x &= ~3;
 525         y &= ~1;
 526         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
 527                (x << 16) | y);
 528         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 529                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 530
 531         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 532                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
 533                        AVIVO_D1MODE_INTERLEAVE_EN);
 534         else
 535                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
 536
 537         if (old_fb && old_fb != crtc->fb) {
 538                 radeon_fb = to_radeon_framebuffer(old_fb);
 539                 radeon_gem_object_unpin(radeon_fb->obj);
 540         }
 541         return 0;
 542 }
 543
 544 int atombios_crtc_mode_set(struct drm_crtc *crtc,
 545                            struct drm_display_mode *mode,
 546                            struct drm_display_mode *adjusted_mode,
 547                            int x, int y, struct drm_framebuffer *old_fb)
 548 {
 549         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 550         struct drm_device *dev = crtc->dev;
 551         struct radeon_device *rdev = dev->dev_private;
 552         struct drm_encoder *encoder;
 553         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
 554
 555         /* TODO color tiling */
 556         memset(&crtc_timing, 0, sizeof(crtc_timing));
 557
 558         /* TODO tv */
 559         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 560
 561         }
 562
 563         crtc_timing.ucCRTC = radeon_crtc->crtc_id;
 564         crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
 565         crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
 566         crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
 567         crtc_timing.usH_SyncWidth =
 568             adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 569
 570         crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
 571         crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
 572         crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
 573         crtc_timing.usV_SyncWidth =
 574             adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 575
 576         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 577                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
 578
 579         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 580                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
 581
 582         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
 583                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
 584
 585         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 586                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
 587
 588         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 589                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
 590
 591         atombios_crtc_set_pll(crtc, adjusted_mode);
 592         atombios_crtc_set_timing(crtc, &crtc_timing);
 593
 594         if (ASIC_IS_AVIVO(rdev))
 595                 atombios_crtc_set_base(crtc, x, y, old_fb);
 596         else {
 597                 if (radeon_crtc->crtc_id == 0) {
 598                         SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
 599                         memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
 600
 601                         /* setup FP shadow regs on R4xx */
 602                         crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
 603                         crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
 604                         crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
 605                         crtc_dtd_timing.usH_Blanking_Time =
 606                             adjusted_mode->crtc_hblank_end -
 607                             adjusted_mode->crtc_hdisplay;
 608                         crtc_dtd_timing.usV_Blanking_Time =
 609                             adjusted_mode->crtc_vblank_end -
 610                             adjusted_mode->crtc_vdisplay;
 611                         crtc_dtd_timing.usH_SyncOffset =
 612                             adjusted_mode->crtc_hsync_start -
 613                             adjusted_mode->crtc_hdisplay;
 614                         crtc_dtd_timing.usV_SyncOffset =
 615                             adjusted_mode->crtc_vsync_start -
 616                             adjusted_mode->crtc_vdisplay;
 617                         crtc_dtd_timing.usH_SyncWidth =
 618                             adjusted_mode->crtc_hsync_end -
 619                             adjusted_mode->crtc_hsync_start;
 620                         crtc_dtd_timing.usV_SyncWidth =
 621                             adjusted_mode->crtc_vsync_end -
 622                             adjusted_mode->crtc_vsync_start;
 623                         /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
 624                         /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
 625
 626                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 627                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
 628                                     ATOM_VSYNC_POLARITY;
 629
 630                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 631                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
 632                                     ATOM_HSYNC_POLARITY;
 633
 634                         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
 635                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
 636                                     ATOM_COMPOSITESYNC;
 637
 638                         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 639                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
 640                                     ATOM_INTERLACE;
 641
 642                         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 643                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
 644                                     ATOM_DOUBLE_CLOCK_MODE;
 645
 646                         atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
 647                 }
 648                 radeon_crtc_set_base(crtc, x, y, old_fb);
 649                 radeon_legacy_atom_set_surface(crtc);
 650         }
 651         atombios_overscan_setup(crtc, mode, adjusted_mode);
 652         atombios_scaler_setup(crtc);
 653         radeon_bandwidth_update(rdev);
 654         return 0;
 655 }
 656
 657 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 658                                      struct drm_display_mode *mode,
 659                                      struct drm_display_mode *adjusted_mode)
 660 {
 661         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
 662                 return false;
 663         return true;
 664 }
 665
 666 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 667 {
 668         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 669         atombios_lock_crtc(crtc, 1);
 670 }
 671
 672 static void atombios_crtc_commit(struct drm_crtc *crtc)
 673 {
 674         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 675         atombios_lock_crtc(crtc, 0);
 676 }
 677
 678 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 679         .dpms = atombios_crtc_dpms,
 680         .mode_fixup = atombios_crtc_mode_fixup,
 681         .mode_set = atombios_crtc_mode_set,
 682         .mode_set_base = atombios_crtc_set_base,
 683         .prepare = atombios_crtc_prepare,
 684         .commit = atombios_crtc_commit,
 685 };
 686
 687 void radeon_atombios_init_crtc(struct drm_device *dev,
 688                                struct radeon_crtc *radeon_crtc)
 689 {
 690         if (radeon_crtc->crtc_id == 1)
 691                 radeon_crtc->crtc_offset =
 692                     AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
 693         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 694 }