2 * Copyright 2010 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
30 nvc0_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
35 *size = ALIGN(*size, 4096);
39 ret = nouveau_bo_new(dev, NULL, *size, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
40 true, false, &gpuobj->im_backing);
42 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
46 ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
48 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
49 nouveau_bo_ref(NULL, &gpuobj->im_backing);
53 gpuobj->vinst = gpuobj->im_backing->bo.mem.start << PAGE_SHIFT;
58 nvc0_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
60 struct drm_nouveau_private *dev_priv = dev->dev_private;
62 if (gpuobj && gpuobj->im_backing) {
64 dev_priv->engine.instmem.unbind(dev, gpuobj);
65 nouveau_bo_unpin(gpuobj->im_backing);
66 nouveau_bo_ref(NULL, &gpuobj->im_backing);
67 gpuobj->im_backing = NULL;
72 nvc0_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
74 struct drm_nouveau_private *dev_priv = dev->dev_private;
75 uint32_t pte, pte_end;
78 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
81 NV_DEBUG(dev, "st=0x%lx sz=0x%lx\n",
82 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
84 pte = gpuobj->im_pramin->start >> 12;
85 pte_end = (gpuobj->im_pramin->size >> 12) + pte;
88 NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
89 gpuobj->im_pramin->start, pte, pte_end);
90 NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
92 while (pte < pte_end) {
93 nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
94 nv_wr32(dev, 0x702004 + (pte * 8), 0);
98 dev_priv->engine.instmem.flush(dev);
101 u32 chan = nv_rd32(dev, 0x1700) << 16;
102 nv_wr32(dev, 0x100cb8, (chan + 0x1000) >> 8);
103 nv_wr32(dev, 0x100cbc, 0x80000005);
106 gpuobj->im_bound = 1;
111 nvc0_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
113 struct drm_nouveau_private *dev_priv = dev->dev_private;
114 uint32_t pte, pte_end;
116 if (gpuobj->im_bound == 0)
119 pte = gpuobj->im_pramin->start >> 12;
120 pte_end = (gpuobj->im_pramin->size >> 12) + pte;
121 while (pte < pte_end) {
122 nv_wr32(dev, 0x702000 + (pte * 8), 0);
123 nv_wr32(dev, 0x702004 + (pte * 8), 0);
126 dev_priv->engine.instmem.flush(dev);
128 gpuobj->im_bound = 0;
133 nvc0_instmem_flush(struct drm_device *dev)
135 nv_wr32(dev, 0x070000, 1);
136 if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
137 NV_ERROR(dev, "PRAMIN flush timeout\n");
141 nvc0_instmem_suspend(struct drm_device *dev)
143 struct drm_nouveau_private *dev_priv = dev->dev_private;
147 dev_priv->susres.ramin_copy = vmalloc(65536);
148 if (!dev_priv->susres.ramin_copy)
150 buf = dev_priv->susres.ramin_copy;
152 for (i = 0; i < 65536; i += 4)
153 buf[i/4] = nv_rd32(dev, NV04_PRAMIN + i);
158 nvc0_instmem_resume(struct drm_device *dev)
160 struct drm_nouveau_private *dev_priv = dev->dev_private;
161 u32 *buf = dev_priv->susres.ramin_copy;
165 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
166 nv_wr32(dev, 0x001700, chan >> 16);
168 for (i = 0; i < 65536; i += 4)
169 nv_wr32(dev, NV04_PRAMIN + i, buf[i/4]);
170 vfree(dev_priv->susres.ramin_copy);
171 dev_priv->susres.ramin_copy = NULL;
173 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
177 nvc0_instmem_init(struct drm_device *dev)
179 struct drm_nouveau_private *dev_priv = dev->dev_private;
180 u64 chan, pgt3, imem, lim3 = dev_priv->ramin_size - 1;
183 dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
184 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
185 imem = 4096 + 4096 + 32768;
187 nv_wr32(dev, 0x001700, chan >> 16);
190 nv_wr32(dev, 0x700200, lower_32_bits(chan + 0x1000));
191 nv_wr32(dev, 0x700204, upper_32_bits(chan + 0x1000));
192 nv_wr32(dev, 0x700208, lower_32_bits(lim3));
193 nv_wr32(dev, 0x70020c, upper_32_bits(lim3));
195 /* point pgd -> pgt */
196 nv_wr32(dev, 0x701000, 0);
197 nv_wr32(dev, 0x701004, ((chan + 0x2000) >> 8) | 1);
199 /* point pgt -> physical vram for channel */
201 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4096, pgt3 += 8) {
202 nv_wr32(dev, 0x700000 + pgt3, ((chan + i) >> 8) | 1);
203 nv_wr32(dev, 0x700004 + pgt3, 0);
206 /* clear rest of pgt */
207 for (; i < dev_priv->ramin_size; i += 4096, pgt3 += 8) {
208 nv_wr32(dev, 0x700000 + pgt3, 0);
209 nv_wr32(dev, 0x700004 + pgt3, 0);
212 /* point bar3 at the channel */
213 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
215 /* Global PRAMIN heap */
216 ret = drm_mm_init(&dev_priv->ramin_heap, imem,
217 dev_priv->ramin_size - imem);
219 NV_ERROR(dev, "Failed to init RAMIN heap\n");
227 nvc0_instmem_takedown(struct drm_device *dev)