drivers/gpu/drm/nouveau/nvc0_graph.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "drmP.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_mm.h"
  32
  33 #include "nvc0_graph.h"
  34 #include "nvc0_grhub.fuc.h"
  35 #include "nvc0_grgpc.fuc.h"
  36
  37 static void
  38 nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
  39 {
  40         NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
  41                 nv_rd32(dev, base + 0x400));
  42         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  43                 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
  44                 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
  45         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  46                 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
  47                 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
  48 }
  49
  50 static void
  51 nvc0_graph_ctxctl_debug(struct drm_device *dev)
  52 {
  53         u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
  54         u32 gpc;
  55
  56         nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
  57         for (gpc = 0; gpc < gpcnr; gpc++)
  58                 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
  59 }
  60
  61 static int
  62 nvc0_graph_load_context(struct nouveau_channel *chan)
  63 {
  64         struct drm_device *dev = chan->dev;
  65
  66         nv_wr32(dev, 0x409840, 0x00000030);
  67         nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
  68         nv_wr32(dev, 0x409504, 0x00000003);
  69         if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
  70                 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
  71
  72         return 0;
  73 }
  74
  75 static int
  76 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
  77 {
  78         nv_wr32(dev, 0x409840, 0x00000003);
  79         nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
  80         nv_wr32(dev, 0x409504, 0x00000009);
  81         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
  82                 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
  83                 return -EBUSY;
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int
  90 nvc0_graph_construct_context(struct nouveau_channel *chan)
  91 {
  92         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  93         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
  94         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
  95         struct drm_device *dev = chan->dev;
  96         int ret, i;
  97         u32 *ctx;
  98
  99         ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
 100         if (!ctx)
 101                 return -ENOMEM;
 102
 103         if (!nouveau_ctxfw) {
 104                 nv_wr32(dev, 0x409840, 0x80000000);
 105                 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 106                 nv_wr32(dev, 0x409504, 0x00000001);
 107                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 108                         NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
 109                         nvc0_graph_ctxctl_debug(dev);
 110                         ret = -EBUSY;
 111                         goto err;
 112                 }
 113         } else {
 114                 nvc0_graph_load_context(chan);
 115
 116                 nv_wo32(grch->grctx, 0x1c, 1);
 117                 nv_wo32(grch->grctx, 0x20, 0);
 118                 nv_wo32(grch->grctx, 0x28, 0);
 119                 nv_wo32(grch->grctx, 0x2c, 0);
 120                 dev_priv->engine.instmem.flush(dev);
 121         }
 122
 123         ret = nvc0_grctx_generate(chan);
 124         if (ret)
 125                 goto err;
 126
 127         if (!nouveau_ctxfw) {
 128                 nv_wr32(dev, 0x409840, 0x80000000);
 129                 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 130                 nv_wr32(dev, 0x409504, 0x00000002);
 131                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 132                         NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
 133                         nvc0_graph_ctxctl_debug(dev);
 134                         ret = -EBUSY;
 135                         goto err;
 136                 }
 137         } else {
 138                 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
 139                 if (ret)
 140                         goto err;
 141         }
 142
 143         for (i = 0; i < priv->grctx_size; i += 4)
 144                 ctx[i / 4] = nv_ro32(grch->grctx, i);
 145
 146         priv->grctx_vals = ctx;
 147         return 0;
 148
 149 err:
 150         kfree(ctx);
 151         return ret;
 152 }
 153
 154 static int
 155 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 156 {
 157         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
 158         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
 159         struct drm_device *dev = chan->dev;
 160         struct drm_nouveau_private *dev_priv = dev->dev_private;
 161         int i = 0, gpc, tp, ret;
 162
 163         ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
 164                                  &grch->unk408004);
 165         if (ret)
 166                 return ret;
 167
 168         ret = nouveau_gpuobj_new(dev, chan, 0x8000, 256, NVOBJ_FLAG_VM,
 169                                  &grch->unk40800c);
 170         if (ret)
 171                 return ret;
 172
 173         ret = nouveau_gpuobj_new(dev, chan, 384 * 1024, 4096,
 174                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
 175                                  &grch->unk418810);
 176         if (ret)
 177                 return ret;
 178
 179         ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, NVOBJ_FLAG_VM,
 180                                  &grch->mmio);
 181         if (ret)
 182                 return ret;
 183
 184
 185         nv_wo32(grch->mmio, i++ * 4, 0x00408004);
 186         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
 187         nv_wo32(grch->mmio, i++ * 4, 0x00408008);
 188         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 189
 190         nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
 191         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
 192         nv_wo32(grch->mmio, i++ * 4, 0x00408010);
 193         nv_wo32(grch->mmio, i++ * 4, 0x80000000);
 194
 195         nv_wo32(grch->mmio, i++ * 4, 0x00418810);
 196         nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
 197         nv_wo32(grch->mmio, i++ * 4, 0x00419848);
 198         nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
 199
 200         nv_wo32(grch->mmio, i++ * 4, 0x00419004);
 201         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
 202         nv_wo32(grch->mmio, i++ * 4, 0x00419008);
 203         nv_wo32(grch->mmio, i++ * 4, 0x00000000);
 204
 205         nv_wo32(grch->mmio, i++ * 4, 0x00418808);
 206         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
 207         nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
 208         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 209
 210         if (dev_priv->chipset != 0xc1) {
 211                 u32 magic = 0x02180000;
 212                 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
 213                 nv_wo32(grch->mmio, i++ * 4, magic);
 214                 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 215                         for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 216                                 u32 reg = TP_UNIT(gpc, tp, 0x520);
 217                                 nv_wo32(grch->mmio, i++ * 4, reg);
 218                                 nv_wo32(grch->mmio, i++ * 4, magic);
 219                                 magic += 0x0324;
 220                         }
 221                 }
 222         } else {
 223                 u32 magic = 0x02180000;
 224                 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
 225                 nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218);
 226                 nv_wo32(grch->mmio, i++ * 4, 0x004064c4);
 227                 nv_wo32(grch->mmio, i++ * 4, 0x0086ffff);
 228                 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 229                         for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 230                                 u32 reg = TP_UNIT(gpc, tp, 0x520);
 231                                 nv_wo32(grch->mmio, i++ * 4, reg);
 232                                 nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic);
 233                                 magic += 0x0324;
 234                         }
 235                         for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 236                                 u32 reg = TP_UNIT(gpc, tp, 0x544);
 237                                 nv_wo32(grch->mmio, i++ * 4, reg);
 238                                 nv_wo32(grch->mmio, i++ * 4, magic);
 239                                 magic += 0x0324;
 240                         }
 241                 }
 242         }
 243
 244         grch->mmio_nr = i / 2;
 245         return 0;
 246 }
 247
 248 static int
 249 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 250 {
 251         struct drm_device *dev = chan->dev;
 252         struct drm_nouveau_private *dev_priv = dev->dev_private;
 253         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 254         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 255         struct nvc0_graph_chan *grch;
 256         struct nouveau_gpuobj *grctx;
 257         int ret, i;
 258
 259         grch = kzalloc(sizeof(*grch), GFP_KERNEL);
 260         if (!grch)
 261                 return -ENOMEM;
 262         chan->engctx[NVOBJ_ENGINE_GR] = grch;
 263
 264         ret = nouveau_gpuobj_new(dev, chan, priv->grctx_size, 256,
 265                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
 266                                  &grch->grctx);
 267         if (ret)
 268                 goto error;
 269         grctx = grch->grctx;
 270
 271         ret = nvc0_graph_create_context_mmio_list(chan);
 272         if (ret)
 273                 goto error;
 274
 275         nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
 276         nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
 277         pinstmem->flush(dev);
 278
 279         if (!priv->grctx_vals) {
 280                 ret = nvc0_graph_construct_context(chan);
 281                 if (ret)
 282                         goto error;
 283         }
 284
 285         for (i = 0; i < priv->grctx_size; i += 4)
 286                 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
 287
 288         if (!nouveau_ctxfw) {
 289                 nv_wo32(grctx, 0x00, grch->mmio_nr);
 290                 nv_wo32(grctx, 0x04, grch->mmio->linst >> 8);
 291         } else {
 292                 nv_wo32(grctx, 0xf4, 0);
 293                 nv_wo32(grctx, 0xf8, 0);
 294                 nv_wo32(grctx, 0x10, grch->mmio_nr);
 295                 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
 296                 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
 297                 nv_wo32(grctx, 0x1c, 1);
 298                 nv_wo32(grctx, 0x20, 0);
 299                 nv_wo32(grctx, 0x28, 0);
 300                 nv_wo32(grctx, 0x2c, 0);
 301         }
 302         pinstmem->flush(dev);
 303         return 0;
 304
 305 error:
 306         priv->base.context_del(chan, engine);
 307         return ret;
 308 }
 309
 310 static void
 311 nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
 312 {
 313         struct nvc0_graph_chan *grch = chan->engctx[engine];
 314
 315         nouveau_gpuobj_ref(NULL, &grch->mmio);
 316         nouveau_gpuobj_ref(NULL, &grch->unk418810);
 317         nouveau_gpuobj_ref(NULL, &grch->unk40800c);
 318         nouveau_gpuobj_ref(NULL, &grch->unk408004);
 319         nouveau_gpuobj_ref(NULL, &grch->grctx);
 320         chan->engctx[engine] = NULL;
 321 }
 322
 323 static int
 324 nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
 325                       u32 handle, u16 class)
 326 {
 327         return 0;
 328 }
 329
 330 static int
 331 nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend)
 332 {
 333         return 0;
 334 }
 335
 336 static int
 337 nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
 338                           u32 class, u32 mthd, u32 data)
 339 {
 340         nouveau_finish_page_flip(chan, NULL);
 341         return 0;
 342 }
 343
 344 static void
 345 nvc0_graph_init_obj418880(struct drm_device *dev)
 346 {
 347         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 348         int i;
 349
 350         nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
 351         nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 352         for (i = 0; i < 4; i++)
 353                 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
 354         nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
 355         nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
 356 }
 357
 358 static void
 359 nvc0_graph_init_regs(struct drm_device *dev)
 360 {
 361         nv_wr32(dev, 0x400080, 0x003083c2);
 362         nv_wr32(dev, 0x400088, 0x00006fe7);
 363         nv_wr32(dev, 0x40008c, 0x00000000);
 364         nv_wr32(dev, 0x400090, 0x00000030);
 365         nv_wr32(dev, 0x40013c, 0x013901f7);
 366         nv_wr32(dev, 0x400140, 0x00000100);
 367         nv_wr32(dev, 0x400144, 0x00000000);
 368         nv_wr32(dev, 0x400148, 0x00000110);
 369         nv_wr32(dev, 0x400138, 0x00000000);
 370         nv_wr32(dev, 0x400130, 0x00000000);
 371         nv_wr32(dev, 0x400134, 0x00000000);
 372         nv_wr32(dev, 0x400124, 0x00000002);
 373 }
 374
 375 static void
 376 nvc0_graph_init_gpc_0(struct drm_device *dev)
 377 {
 378         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 379         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tp_total);
 380         u32 data[TP_MAX / 8];
 381         u8  tpnr[GPC_MAX];
 382         int i, gpc, tpc;
 383
 384         nv_wr32(dev, TP_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
 385
 386         /*
 387          *      TP      ROP UNKVAL(magic_not_rop_nr)
 388          * 450: 4/0/0/0 2        3
 389          * 460: 3/4/0/0 4        1
 390          * 465: 3/4/4/0 4        7
 391          * 470: 3/3/4/4 5        5
 392          * 480: 3/4/4/4 6        6
 393          */
 394
 395         memset(data, 0x00, sizeof(data));
 396         memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
 397         for (i = 0, gpc = -1; i < priv->tp_total; i++) {
 398                 do {
 399                         gpc = (gpc + 1) % priv->gpc_nr;
 400                 } while (!tpnr[gpc]);
 401                 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
 402
 403                 data[i / 8] |= tpc << ((i % 8) * 4);
 404         }
 405
 406         nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
 407         nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
 408         nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
 409         nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
 410
 411         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 412                 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
 413                                                   priv->tp_nr[gpc]);
 414                 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
 415                 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918);
 416         }
 417
 418         nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918);
 419         nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800));
 420 }
 421
 422 static void
 423 nvc0_graph_init_units(struct drm_device *dev)
 424 {
 425         nv_wr32(dev, 0x409c24, 0x000f0000);
 426         nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
 427         nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
 428         nv_wr32(dev, 0x408030, 0xc0000000);
 429         nv_wr32(dev, 0x40601c, 0xc0000000);
 430         nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
 431         nv_wr32(dev, 0x406018, 0xc0000000);
 432         nv_wr32(dev, 0x405840, 0xc0000000);
 433         nv_wr32(dev, 0x405844, 0x00ffffff);
 434         nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
 435         nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
 436 }
 437
 438 static void
 439 nvc0_graph_init_gpc_1(struct drm_device *dev)
 440 {
 441         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 442         int gpc, tp;
 443
 444         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 445                 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 446                 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 447                 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 448                 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 449                 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 450                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
 451                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
 452                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
 453                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
 454                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
 455                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
 456                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
 457                 }
 458                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 459                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 460         }
 461 }
 462
 463 static void
 464 nvc0_graph_init_rop(struct drm_device *dev)
 465 {
 466         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 467         int rop;
 468
 469         for (rop = 0; rop < priv->rop_nr; rop++) {
 470                 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
 471                 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
 472                 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
 473                 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
 474         }
 475 }
 476
 477 static void
 478 nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
 479                     struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
 480 {
 481         int i;
 482
 483         nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
 484         for (i = 0; i < data->size / 4; i++)
 485                 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
 486
 487         nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
 488         for (i = 0; i < code->size / 4; i++) {
 489                 if ((i & 0x3f) == 0)
 490                         nv_wr32(dev, fuc_base + 0x0188, i >> 6);
 491                 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
 492         }
 493 }
 494
 495 static int
 496 nvc0_graph_init_ctxctl(struct drm_device *dev)
 497 {
 498         struct drm_nouveau_private *dev_priv = dev->dev_private;
 499         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 500         u32 r000260;
 501         int i;
 502
 503         if (!nouveau_ctxfw) {
 504                 /* load HUB microcode */
 505                 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 506                 nv_wr32(dev, 0x4091c0, 0x01000000);
 507                 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
 508                         nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
 509
 510                 nv_wr32(dev, 0x409180, 0x01000000);
 511                 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
 512                         if ((i & 0x3f) == 0)
 513                                 nv_wr32(dev, 0x409188, i >> 6);
 514                         nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
 515                 }
 516
 517                 /* load GPC microcode */
 518                 nv_wr32(dev, 0x41a1c0, 0x01000000);
 519                 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
 520                         nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
 521
 522                 nv_wr32(dev, 0x41a180, 0x01000000);
 523                 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
 524                         if ((i & 0x3f) == 0)
 525                                 nv_wr32(dev, 0x41a188, i >> 6);
 526                         nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
 527                 }
 528                 nv_wr32(dev, 0x000260, r000260);
 529
 530                 /* start HUB ucode running, it'll init the GPCs */
 531                 nv_wr32(dev, 0x409800, dev_priv->chipset);
 532                 nv_wr32(dev, 0x40910c, 0x00000000);
 533                 nv_wr32(dev, 0x409100, 0x00000002);
 534                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 535                         NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
 536                         nvc0_graph_ctxctl_debug(dev);
 537                         return -EBUSY;
 538                 }
 539
 540                 priv->grctx_size = nv_rd32(dev, 0x409804);
 541                 return 0;
 542         }
 543
 544         /* load fuc microcode */
 545         r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 546         nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
 547         nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
 548         nv_wr32(dev, 0x000260, r000260);
 549
 550         /* start both of them running */
 551         nv_wr32(dev, 0x409840, 0xffffffff);
 552         nv_wr32(dev, 0x41a10c, 0x00000000);
 553         nv_wr32(dev, 0x40910c, 0x00000000);
 554         nv_wr32(dev, 0x41a100, 0x00000002);
 555         nv_wr32(dev, 0x409100, 0x00000002);
 556         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
 557                 NV_INFO(dev, "0x409800 wait failed\n");
 558
 559         nv_wr32(dev, 0x409840, 0xffffffff);
 560         nv_wr32(dev, 0x409500, 0x7fffffff);
 561         nv_wr32(dev, 0x409504, 0x00000021);
 562
 563         nv_wr32(dev, 0x409840, 0xffffffff);
 564         nv_wr32(dev, 0x409500, 0x00000000);
 565         nv_wr32(dev, 0x409504, 0x00000010);
 566         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 567                 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
 568                 return -EBUSY;
 569         }
 570         priv->grctx_size = nv_rd32(dev, 0x409800);
 571
 572         nv_wr32(dev, 0x409840, 0xffffffff);
 573         nv_wr32(dev, 0x409500, 0x00000000);
 574         nv_wr32(dev, 0x409504, 0x00000016);
 575         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 576                 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
 577                 return -EBUSY;
 578         }
 579
 580         nv_wr32(dev, 0x409840, 0xffffffff);
 581         nv_wr32(dev, 0x409500, 0x00000000);
 582         nv_wr32(dev, 0x409504, 0x00000025);
 583         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 584                 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
 585                 return -EBUSY;
 586         }
 587
 588         return 0;
 589 }
 590
 591 static int
 592 nvc0_graph_init(struct drm_device *dev, int engine)
 593 {
 594         int ret;
 595
 596         nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
 597         nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
 598
 599         nvc0_graph_init_obj418880(dev);
 600         nvc0_graph_init_regs(dev);
 601         /*nvc0_graph_init_unitplemented_magics(dev);*/
 602         nvc0_graph_init_gpc_0(dev);
 603         /*nvc0_graph_init_unitplemented_c242(dev);*/
 604
 605         nv_wr32(dev, 0x400500, 0x00010001);
 606         nv_wr32(dev, 0x400100, 0xffffffff);
 607         nv_wr32(dev, 0x40013c, 0xffffffff);
 608
 609         nvc0_graph_init_units(dev);
 610         nvc0_graph_init_gpc_1(dev);
 611         nvc0_graph_init_rop(dev);
 612
 613         nv_wr32(dev, 0x400108, 0xffffffff);
 614         nv_wr32(dev, 0x400138, 0xffffffff);
 615         nv_wr32(dev, 0x400118, 0xffffffff);
 616         nv_wr32(dev, 0x400130, 0xffffffff);
 617         nv_wr32(dev, 0x40011c, 0xffffffff);
 618         nv_wr32(dev, 0x400134, 0xffffffff);
 619         nv_wr32(dev, 0x400054, 0x34ce3464);
 620
 621         ret = nvc0_graph_init_ctxctl(dev);
 622         if (ret)
 623                 return ret;
 624
 625         return 0;
 626 }
 627
 628 int
 629 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
 630 {
 631         struct drm_nouveau_private *dev_priv = dev->dev_private;
 632         struct nouveau_channel *chan;
 633         unsigned long flags;
 634         int i;
 635
 636         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 637         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 638                 chan = dev_priv->channels.ptr[i];
 639                 if (!chan || !chan->ramin)
 640                         continue;
 641
 642                 if (inst == chan->ramin->vinst)
 643                         break;
 644         }
 645         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 646         return i;
 647 }
 648
 649 static void
 650 nvc0_graph_ctxctl_isr(struct drm_device *dev)
 651 {
 652         u32 ustat = nv_rd32(dev, 0x409c18);
 653
 654         if (ustat & 0x00000001)
 655                 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
 656         if (ustat & 0x00080000)
 657                 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
 658         if (ustat & ~0x00080001)
 659                 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
 660
 661         nvc0_graph_ctxctl_debug(dev);
 662         nv_wr32(dev, 0x409c20, ustat);
 663 }
 664
 665 static void
 666 nvc0_graph_isr(struct drm_device *dev)
 667 {
 668         u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
 669         u32 chid = nvc0_graph_isr_chid(dev, inst);
 670         u32 stat = nv_rd32(dev, 0x400100);
 671         u32 addr = nv_rd32(dev, 0x400704);
 672         u32 mthd = (addr & 0x00003ffc);
 673         u32 subc = (addr & 0x00070000) >> 16;
 674         u32 data = nv_rd32(dev, 0x400708);
 675         u32 code = nv_rd32(dev, 0x400110);
 676         u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
 677
 678         if (stat & 0x00000010) {
 679                 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
 680                         NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
 681                                      "subc %d class 0x%04x mthd 0x%04x "
 682                                      "data 0x%08x\n",
 683                                 chid, inst, subc, class, mthd, data);
 684                 }
 685                 nv_wr32(dev, 0x400100, 0x00000010);
 686                 stat &= ~0x00000010;
 687         }
 688
 689         if (stat & 0x00000020) {
 690                 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
 691                              "class 0x%04x mthd 0x%04x data 0x%08x\n",
 692                         chid, inst, subc, class, mthd, data);
 693                 nv_wr32(dev, 0x400100, 0x00000020);
 694                 stat &= ~0x00000020;
 695         }
 696
 697         if (stat & 0x00100000) {
 698                 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
 699                 nouveau_enum_print(nv50_data_error_names, code);
 700                 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
 701                        "mthd 0x%04x data 0x%08x\n",
 702                        chid, inst, subc, class, mthd, data);
 703                 nv_wr32(dev, 0x400100, 0x00100000);
 704                 stat &= ~0x00100000;
 705         }
 706
 707         if (stat & 0x00200000) {
 708                 u32 trap = nv_rd32(dev, 0x400108);
 709                 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
 710                 nv_wr32(dev, 0x400108, trap);
 711                 nv_wr32(dev, 0x400100, 0x00200000);
 712                 stat &= ~0x00200000;
 713         }
 714
 715         if (stat & 0x00080000) {
 716                 nvc0_graph_ctxctl_isr(dev);
 717                 nv_wr32(dev, 0x400100, 0x00080000);
 718                 stat &= ~0x00080000;
 719         }
 720
 721         if (stat) {
 722                 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
 723                 nv_wr32(dev, 0x400100, stat);
 724         }
 725
 726         nv_wr32(dev, 0x400500, 0x00010001);
 727 }
 728
 729 static int
 730 nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
 731                      struct nvc0_graph_fuc *fuc)
 732 {
 733         struct drm_nouveau_private *dev_priv = dev->dev_private;
 734         const struct firmware *fw;
 735         char f[32];
 736         int ret;
 737
 738         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
 739         ret = request_firmware(&fw, f, &dev->pdev->dev);
 740         if (ret) {
 741                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
 742                 ret = request_firmware(&fw, f, &dev->pdev->dev);
 743                 if (ret) {
 744                         NV_ERROR(dev, "failed to load %s\n", fwname);
 745                         return ret;
 746                 }
 747         }
 748
 749         fuc->size = fw->size;
 750         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
 751         release_firmware(fw);
 752         return (fuc->data != NULL) ? 0 : -ENOMEM;
 753 }
 754
 755 static void
 756 nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
 757 {
 758         if (fuc->data) {
 759                 kfree(fuc->data);
 760                 fuc->data = NULL;
 761         }
 762 }
 763
 764 static void
 765 nvc0_graph_destroy(struct drm_device *dev, int engine)
 766 {
 767         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 768
 769         if (nouveau_ctxfw) {
 770                 nvc0_graph_destroy_fw(&priv->fuc409c);
 771                 nvc0_graph_destroy_fw(&priv->fuc409d);
 772                 nvc0_graph_destroy_fw(&priv->fuc41ac);
 773                 nvc0_graph_destroy_fw(&priv->fuc41ad);
 774         }
 775
 776         nouveau_irq_unregister(dev, 12);
 777
 778         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 779         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 780
 781         if (priv->grctx_vals)
 782                 kfree(priv->grctx_vals);
 783
 784         NVOBJ_ENGINE_DEL(dev, GR);
 785         kfree(priv);
 786 }
 787
 788 int
 789 nvc0_graph_create(struct drm_device *dev)
 790 {
 791         struct drm_nouveau_private *dev_priv = dev->dev_private;
 792         struct nvc0_graph_priv *priv;
 793         int ret, gpc, i;
 794         u32 fermi;
 795
 796         fermi = nvc0_graph_class(dev);
 797         if (!fermi) {
 798                 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
 799                 return 0;
 800         }
 801
 802         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 803         if (!priv)
 804                 return -ENOMEM;
 805
 806         priv->base.destroy = nvc0_graph_destroy;
 807         priv->base.init = nvc0_graph_init;
 808         priv->base.fini = nvc0_graph_fini;
 809         priv->base.context_new = nvc0_graph_context_new;
 810         priv->base.context_del = nvc0_graph_context_del;
 811         priv->base.object_new = nvc0_graph_object_new;
 812
 813         NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
 814         nouveau_irq_register(dev, 12, nvc0_graph_isr);
 815
 816         if (nouveau_ctxfw) {
 817                 NV_INFO(dev, "PGRAPH: using external firmware\n");
 818                 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
 819                     nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
 820                     nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
 821                     nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
 822                         ret = 0;
 823                         goto error;
 824                 }
 825         }
 826
 827         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
 828         if (ret)
 829                 goto error;
 830
 831         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
 832         if (ret)
 833                 goto error;
 834
 835         for (i = 0; i < 0x1000; i += 4) {
 836                 nv_wo32(priv->unk4188b4, i, 0x00000010);
 837                 nv_wo32(priv->unk4188b8, i, 0x00000010);
 838         }
 839
 840         priv->gpc_nr  =  nv_rd32(dev, 0x409604) & 0x0000001f;
 841         priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
 842         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 843                 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
 844                 priv->tp_total += priv->tp_nr[gpc];
 845         }
 846
 847         /*XXX: these need figuring out... */
 848         switch (dev_priv->chipset) {
 849         case 0xc0:
 850                 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
 851                         priv->magic_not_rop_nr = 0x07;
 852                 } else
 853                 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
 854                         priv->magic_not_rop_nr = 0x05;
 855                 } else
 856                 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
 857                         priv->magic_not_rop_nr = 0x06;
 858                 }
 859                 break;
 860         case 0xc3: /* 450, 4/0/0/0, 2 */
 861                 priv->magic_not_rop_nr = 0x03;
 862                 break;
 863         case 0xc4: /* 460, 3/4/0/0, 4 */
 864                 priv->magic_not_rop_nr = 0x01;
 865                 break;
 866         case 0xc1: /* 2/0/0/0, 1 */
 867                 priv->magic_not_rop_nr = 0x01;
 868                 break;
 869         case 0xc8: /* 4/4/3/4, 5 */
 870                 priv->magic_not_rop_nr = 0x06;
 871                 break;
 872         case 0xce: /* 4/4/0/0, 4 */
 873                 priv->magic_not_rop_nr = 0x03;
 874                 break;
 875         case 0xcf: /* 4/0/0/0, 3 */
 876                 priv->magic_not_rop_nr = 0x03;
 877                 break;
 878         }
 879
 880         if (!priv->magic_not_rop_nr) {
 881                 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
 882                          priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
 883                          priv->tp_nr[3], priv->rop_nr);
 884                 /* use 0xc3's values... */
 885                 priv->magic_not_rop_nr = 0x03;
 886         }
 887
 888         NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
 889         NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
 890         NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
 891         NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
 892         if (fermi >= 0x9197)
 893                 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
 894         if (fermi >= 0x9297)
 895                 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
 896         NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
 897         return 0;
 898
 899 error:
 900         nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
 901         return ret;
 902 }