2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
29 #include "nouveau_drv.h"
30 #include "nouveau_mm.h"
31 #include "nvc0_graph.h"
34 nvc0_graph_load_context(struct nouveau_channel *chan)
36 struct drm_device *dev = chan->dev;
38 nv_wr32(dev, 0x409840, 0x00000030);
39 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
40 nv_wr32(dev, 0x409504, 0x00000003);
41 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
42 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
48 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
50 nv_wr32(dev, 0x409840, 0x00000003);
51 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
52 nv_wr32(dev, 0x409504, 0x00000009);
53 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
54 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
62 nvc0_graph_construct_context(struct nouveau_channel *chan)
64 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
65 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
66 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
67 struct drm_device *dev = chan->dev;
71 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
75 nvc0_graph_load_context(chan);
77 nv_wo32(grch->grctx, 0x1c, 1);
78 nv_wo32(grch->grctx, 0x20, 0);
79 nv_wo32(grch->grctx, 0x28, 0);
80 nv_wo32(grch->grctx, 0x2c, 0);
81 dev_priv->engine.instmem.flush(dev);
83 ret = nvc0_grctx_generate(chan);
89 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
95 for (i = 0; i < priv->grctx_size; i += 4)
96 ctx[i / 4] = nv_ro32(grch->grctx, i);
98 priv->grctx_vals = ctx;
103 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
105 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
106 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
107 struct drm_device *dev = chan->dev;
108 int i = 0, gpc, tp, ret;
111 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
116 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
121 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096,
122 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
127 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
133 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
134 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
135 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
136 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
138 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
139 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
140 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
141 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
143 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
144 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
145 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
146 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
148 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
149 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
150 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
151 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
153 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
154 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
155 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
156 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
159 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
160 nv_wo32(grch->mmio, i++ * 4, magic);
161 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
162 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
163 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
164 nv_wo32(grch->mmio, i++ * 4, reg);
165 nv_wo32(grch->mmio, i++ * 4, magic);
169 grch->mmio_nr = i / 2;
174 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
176 struct drm_device *dev = chan->dev;
177 struct drm_nouveau_private *dev_priv = dev->dev_private;
178 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
179 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
180 struct nvc0_graph_chan *grch;
181 struct nouveau_gpuobj *grctx;
184 grch = kzalloc(sizeof(*grch), GFP_KERNEL);
187 chan->engctx[NVOBJ_ENGINE_GR] = grch;
189 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
190 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
196 ret = nvc0_graph_create_context_mmio_list(chan);
200 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
201 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
202 pinstmem->flush(dev);
204 if (!priv->grctx_vals) {
205 ret = nvc0_graph_construct_context(chan);
210 for (i = 0; i < priv->grctx_size; i += 4)
211 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
213 nv_wo32(grctx, 0xf4, 0);
214 nv_wo32(grctx, 0xf8, 0);
215 nv_wo32(grctx, 0x10, grch->mmio_nr);
216 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
217 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
218 nv_wo32(grctx, 0x1c, 1);
219 nv_wo32(grctx, 0x20, 0);
220 nv_wo32(grctx, 0x28, 0);
221 nv_wo32(grctx, 0x2c, 0);
222 pinstmem->flush(dev);
226 priv->base.context_del(chan, engine);
231 nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
233 struct nvc0_graph_chan *grch = chan->engctx[engine];
235 nouveau_gpuobj_ref(NULL, &grch->mmio);
236 nouveau_gpuobj_ref(NULL, &grch->unk418810);
237 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
238 nouveau_gpuobj_ref(NULL, &grch->unk408004);
239 nouveau_gpuobj_ref(NULL, &grch->grctx);
240 chan->engctx[engine] = NULL;
244 nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
245 u32 handle, u16 class)
251 nvc0_graph_fini(struct drm_device *dev, int engine)
257 nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
258 u32 class, u32 mthd, u32 data)
260 nouveau_finish_page_flip(chan, NULL);
265 nvc0_graph_init_obj418880(struct drm_device *dev)
267 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
270 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
271 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
272 for (i = 0; i < 4; i++)
273 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
274 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
275 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
279 nvc0_graph_init_regs(struct drm_device *dev)
281 nv_wr32(dev, 0x400080, 0x003083c2);
282 nv_wr32(dev, 0x400088, 0x00006fe7);
283 nv_wr32(dev, 0x40008c, 0x00000000);
284 nv_wr32(dev, 0x400090, 0x00000030);
285 nv_wr32(dev, 0x40013c, 0x013901f7);
286 nv_wr32(dev, 0x400140, 0x00000100);
287 nv_wr32(dev, 0x400144, 0x00000000);
288 nv_wr32(dev, 0x400148, 0x00000110);
289 nv_wr32(dev, 0x400138, 0x00000000);
290 nv_wr32(dev, 0x400130, 0x00000000);
291 nv_wr32(dev, 0x400134, 0x00000000);
292 nv_wr32(dev, 0x400124, 0x00000002);
296 nvc0_graph_init_gpc_0(struct drm_device *dev)
298 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
299 u32 data[TP_MAX / 8];
304 * TP ROP UNKVAL(magic_not_rop_nr)
312 * 450: 00200000 00000000001000000000000000000000
313 * 460: 00124925 00000000000100100100100100100101
314 * 465: 000ba2e9 00000000000010111010001011101001
315 * 470: 00092493 00000000000010010010010010010011
316 * 480: 00088889 00000000000010001000100010001001
319 memset(data, 0x00, sizeof(data));
320 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
321 for (i = 0, gpc = -1; i < priv->tp_total; i++) {
323 gpc = (gpc + 1) % priv->gpc_nr;
324 } while (!tpnr[gpc]);
325 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
327 data[i / 8] |= tpc << ((i % 8) * 4);
330 nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
331 nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
332 nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
333 nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
335 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
336 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
338 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
339 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
342 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
343 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
347 nvc0_graph_init_units(struct drm_device *dev)
349 nv_wr32(dev, 0x409c24, 0x000f0000);
350 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
351 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
352 nv_wr32(dev, 0x408030, 0xc0000000);
353 nv_wr32(dev, 0x40601c, 0xc0000000);
354 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
355 nv_wr32(dev, 0x406018, 0xc0000000);
356 nv_wr32(dev, 0x405840, 0xc0000000);
357 nv_wr32(dev, 0x405844, 0x00ffffff);
358 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
359 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
363 nvc0_graph_init_gpc_1(struct drm_device *dev)
365 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
368 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
369 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
370 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
371 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
372 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
373 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
374 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
375 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
376 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
377 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
378 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
379 nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
380 nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
382 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
383 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
388 nvc0_graph_init_rop(struct drm_device *dev)
390 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
393 for (rop = 0; rop < priv->rop_nr; rop++) {
394 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
395 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
396 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
397 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
402 nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
403 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
407 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
408 for (i = 0; i < data->size / 4; i++)
409 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
411 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
412 for (i = 0; i < code->size / 4; i++) {
414 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
415 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
420 nvc0_graph_init_ctxctl(struct drm_device *dev)
422 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
425 /* load fuc microcode */
426 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
427 nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
428 nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
429 nv_wr32(dev, 0x000260, r000260);
431 /* start both of them running */
432 nv_wr32(dev, 0x409840, 0xffffffff);
433 nv_wr32(dev, 0x41a10c, 0x00000000);
434 nv_wr32(dev, 0x40910c, 0x00000000);
435 nv_wr32(dev, 0x41a100, 0x00000002);
436 nv_wr32(dev, 0x409100, 0x00000002);
437 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
438 NV_INFO(dev, "0x409800 wait failed\n");
440 nv_wr32(dev, 0x409840, 0xffffffff);
441 nv_wr32(dev, 0x409500, 0x7fffffff);
442 nv_wr32(dev, 0x409504, 0x00000021);
444 nv_wr32(dev, 0x409840, 0xffffffff);
445 nv_wr32(dev, 0x409500, 0x00000000);
446 nv_wr32(dev, 0x409504, 0x00000010);
447 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
448 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
451 priv->grctx_size = nv_rd32(dev, 0x409800);
453 nv_wr32(dev, 0x409840, 0xffffffff);
454 nv_wr32(dev, 0x409500, 0x00000000);
455 nv_wr32(dev, 0x409504, 0x00000016);
456 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
457 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
461 nv_wr32(dev, 0x409840, 0xffffffff);
462 nv_wr32(dev, 0x409500, 0x00000000);
463 nv_wr32(dev, 0x409504, 0x00000025);
464 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
465 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
473 nvc0_graph_init(struct drm_device *dev, int engine)
477 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
478 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
480 nvc0_graph_init_obj418880(dev);
481 nvc0_graph_init_regs(dev);
482 /*nvc0_graph_init_unitplemented_magics(dev);*/
483 nvc0_graph_init_gpc_0(dev);
484 /*nvc0_graph_init_unitplemented_c242(dev);*/
486 nv_wr32(dev, 0x400500, 0x00010001);
487 nv_wr32(dev, 0x400100, 0xffffffff);
488 nv_wr32(dev, 0x40013c, 0xffffffff);
490 nvc0_graph_init_units(dev);
491 nvc0_graph_init_gpc_1(dev);
492 nvc0_graph_init_rop(dev);
494 nv_wr32(dev, 0x400108, 0xffffffff);
495 nv_wr32(dev, 0x400138, 0xffffffff);
496 nv_wr32(dev, 0x400118, 0xffffffff);
497 nv_wr32(dev, 0x400130, 0xffffffff);
498 nv_wr32(dev, 0x40011c, 0xffffffff);
499 nv_wr32(dev, 0x400134, 0xffffffff);
500 nv_wr32(dev, 0x400054, 0x34ce3464);
502 ret = nvc0_graph_init_ctxctl(dev);
510 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
512 struct drm_nouveau_private *dev_priv = dev->dev_private;
513 struct nouveau_channel *chan;
517 spin_lock_irqsave(&dev_priv->channels.lock, flags);
518 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
519 chan = dev_priv->channels.ptr[i];
520 if (!chan || !chan->ramin)
523 if (inst == chan->ramin->vinst)
526 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
531 nvc0_graph_isr(struct drm_device *dev)
533 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
534 u32 chid = nvc0_graph_isr_chid(dev, inst);
535 u32 stat = nv_rd32(dev, 0x400100);
536 u32 addr = nv_rd32(dev, 0x400704);
537 u32 mthd = (addr & 0x00003ffc);
538 u32 subc = (addr & 0x00070000) >> 16;
539 u32 data = nv_rd32(dev, 0x400708);
540 u32 code = nv_rd32(dev, 0x400110);
541 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
543 if (stat & 0x00000010) {
544 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
545 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
546 "subc %d class 0x%04x mthd 0x%04x "
548 chid, inst, subc, class, mthd, data);
550 nv_wr32(dev, 0x400100, 0x00000010);
554 if (stat & 0x00000020) {
555 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
556 "class 0x%04x mthd 0x%04x data 0x%08x\n",
557 chid, inst, subc, class, mthd, data);
558 nv_wr32(dev, 0x400100, 0x00000020);
562 if (stat & 0x00100000) {
563 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
564 nouveau_enum_print(nv50_data_error_names, code);
565 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
566 "mthd 0x%04x data 0x%08x\n",
567 chid, inst, subc, class, mthd, data);
568 nv_wr32(dev, 0x400100, 0x00100000);
572 if (stat & 0x00200000) {
573 u32 trap = nv_rd32(dev, 0x400108);
574 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
575 nv_wr32(dev, 0x400108, trap);
576 nv_wr32(dev, 0x400100, 0x00200000);
580 if (stat & 0x00080000) {
581 u32 ustat = nv_rd32(dev, 0x409c18);
583 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
585 nv_wr32(dev, 0x409c20, ustat);
586 nv_wr32(dev, 0x400100, 0x00080000);
591 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
592 nv_wr32(dev, 0x400100, stat);
595 nv_wr32(dev, 0x400500, 0x00010001);
599 nvc0_runk140_isr(struct drm_device *dev)
601 u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
604 u32 unit = ffs(units) - 1;
605 u32 reg = 0x140000 + unit * 0x2000;
606 u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
607 u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
609 NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
610 units &= ~(1 << unit);
615 nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
616 struct nvc0_graph_fuc *fuc)
618 struct drm_nouveau_private *dev_priv = dev->dev_private;
619 const struct firmware *fw;
623 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
624 ret = request_firmware(&fw, f, &dev->pdev->dev);
626 snprintf(f, sizeof(f), "nouveau/%s", fwname);
627 ret = request_firmware(&fw, f, &dev->pdev->dev);
629 NV_ERROR(dev, "failed to load %s\n", fwname);
634 fuc->size = fw->size;
635 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
636 release_firmware(fw);
637 return (fuc->data != NULL) ? 0 : -ENOMEM;
641 nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
650 nvc0_graph_destroy(struct drm_device *dev, int engine)
652 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
654 nvc0_graph_destroy_fw(&priv->fuc409c);
655 nvc0_graph_destroy_fw(&priv->fuc409d);
656 nvc0_graph_destroy_fw(&priv->fuc41ac);
657 nvc0_graph_destroy_fw(&priv->fuc41ad);
659 nouveau_irq_unregister(dev, 12);
660 nouveau_irq_unregister(dev, 25);
662 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
663 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
665 if (priv->grctx_vals)
666 kfree(priv->grctx_vals);
668 NVOBJ_ENGINE_DEL(dev, GR);
673 nvc0_graph_create(struct drm_device *dev)
675 struct drm_nouveau_private *dev_priv = dev->dev_private;
676 struct nvc0_graph_priv *priv;
679 switch (dev_priv->chipset) {
685 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
689 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
693 priv->base.destroy = nvc0_graph_destroy;
694 priv->base.init = nvc0_graph_init;
695 priv->base.fini = nvc0_graph_fini;
696 priv->base.context_new = nvc0_graph_context_new;
697 priv->base.context_del = nvc0_graph_context_del;
698 priv->base.object_new = nvc0_graph_object_new;
700 NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
701 nouveau_irq_register(dev, 12, nvc0_graph_isr);
702 nouveau_irq_register(dev, 25, nvc0_runk140_isr);
704 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
705 nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
706 nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
707 nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
713 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
717 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
721 for (i = 0; i < 0x1000; i += 4) {
722 nv_wo32(priv->unk4188b4, i, 0x00000010);
723 nv_wo32(priv->unk4188b8, i, 0x00000010);
726 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
727 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
728 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
729 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
730 priv->tp_total += priv->tp_nr[gpc];
733 /*XXX: these need figuring out... */
734 switch (dev_priv->chipset) {
736 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
737 priv->magic_not_rop_nr = 0x07;
738 /* filled values up to tp_total, the rest 0 */
739 priv->magicgpc918 = 0x000ba2e9;
741 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
742 priv->magic_not_rop_nr = 0x05;
743 priv->magicgpc918 = 0x00092493;
745 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
746 priv->magic_not_rop_nr = 0x06;
747 priv->magicgpc918 = 0x00088889;
750 case 0xc3: /* 450, 4/0/0/0, 2 */
751 priv->magic_not_rop_nr = 0x03;
752 priv->magicgpc918 = 0x00200000;
754 case 0xc4: /* 460, 3/4/0/0, 4 */
755 priv->magic_not_rop_nr = 0x01;
756 priv->magicgpc918 = 0x00124925;
760 if (!priv->magic_not_rop_nr) {
761 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
762 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
763 priv->tp_nr[3], priv->rop_nr);
764 /* use 0xc3's values... */
765 priv->magic_not_rop_nr = 0x03;
766 priv->magicgpc918 = 0x00200000;
769 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
770 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
771 NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
772 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
773 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
777 nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
781 MODULE_FIRMWARE("nouveau/nvc0_fuc409c");
782 MODULE_FIRMWARE("nouveau/nvc0_fuc409d");
783 MODULE_FIRMWARE("nouveau/nvc0_fuc41ac");
784 MODULE_FIRMWARE("nouveau/nvc0_fuc41ad");
785 MODULE_FIRMWARE("nouveau/nvc3_fuc409c");
786 MODULE_FIRMWARE("nouveau/nvc3_fuc409d");
787 MODULE_FIRMWARE("nouveau/nvc3_fuc41ac");
788 MODULE_FIRMWARE("nouveau/nvc3_fuc41ad");
789 MODULE_FIRMWARE("nouveau/nvc4_fuc409c");
790 MODULE_FIRMWARE("nouveau/nvc4_fuc409d");
791 MODULE_FIRMWARE("nouveau/nvc4_fuc41ac");
792 MODULE_FIRMWARE("nouveau/nvc4_fuc41ad");
793 MODULE_FIRMWARE("nouveau/fuc409c");
794 MODULE_FIRMWARE("nouveau/fuc409d");
795 MODULE_FIRMWARE("nouveau/fuc41ac");
796 MODULE_FIRMWARE("nouveau/fuc41ad");