drivers/gpu/drm/nouveau/nvc0_graph.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "drmP.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_mm.h"
  32
  33 #include "nvc0_graph.h"
  34 #include "nvc0_grhub.fuc.h"
  35 #include "nvc0_grgpc.fuc.h"
  36
  37 static void
  38 nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
  39 {
  40         NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
  41                 nv_rd32(dev, base + 0x400));
  42         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  43                 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
  44                 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
  45         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  46                 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
  47                 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
  48 }
  49
  50 static void
  51 nvc0_graph_ctxctl_debug(struct drm_device *dev)
  52 {
  53         u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
  54         u32 gpc;
  55
  56         nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
  57         for (gpc = 0; gpc < gpcnr; gpc++)
  58                 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
  59 }
  60
  61 static int
  62 nvc0_graph_load_context(struct nouveau_channel *chan)
  63 {
  64         struct drm_device *dev = chan->dev;
  65
  66         nv_wr32(dev, 0x409840, 0x00000030);
  67         nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
  68         nv_wr32(dev, 0x409504, 0x00000003);
  69         if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
  70                 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
  71
  72         return 0;
  73 }
  74
  75 static int
  76 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
  77 {
  78         nv_wr32(dev, 0x409840, 0x00000003);
  79         nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
  80         nv_wr32(dev, 0x409504, 0x00000009);
  81         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
  82                 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
  83                 return -EBUSY;
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int
  90 nvc0_graph_construct_context(struct nouveau_channel *chan)
  91 {
  92         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  93         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
  94         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
  95         struct drm_device *dev = chan->dev;
  96         int ret, i;
  97         u32 *ctx;
  98
  99         ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
 100         if (!ctx)
 101                 return -ENOMEM;
 102
 103         if (!nouveau_ctxfw) {
 104                 nv_wr32(dev, 0x409840, 0x80000000);
 105                 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 106                 nv_wr32(dev, 0x409504, 0x00000001);
 107                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 108                         NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
 109                         nvc0_graph_ctxctl_debug(dev);
 110                         ret = -EBUSY;
 111                         goto err;
 112                 }
 113         } else {
 114                 nvc0_graph_load_context(chan);
 115
 116                 nv_wo32(grch->grctx, 0x1c, 1);
 117                 nv_wo32(grch->grctx, 0x20, 0);
 118                 nv_wo32(grch->grctx, 0x28, 0);
 119                 nv_wo32(grch->grctx, 0x2c, 0);
 120                 dev_priv->engine.instmem.flush(dev);
 121         }
 122
 123         ret = nvc0_grctx_generate(chan);
 124         if (ret)
 125                 goto err;
 126
 127         if (!nouveau_ctxfw) {
 128                 nv_wr32(dev, 0x409840, 0x80000000);
 129                 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 130                 nv_wr32(dev, 0x409504, 0x00000002);
 131                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 132                         NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
 133                         nvc0_graph_ctxctl_debug(dev);
 134                         ret = -EBUSY;
 135                         goto err;
 136                 }
 137         } else {
 138                 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
 139                 if (ret)
 140                         goto err;
 141         }
 142
 143         for (i = 0; i < priv->grctx_size; i += 4)
 144                 ctx[i / 4] = nv_ro32(grch->grctx, i);
 145
 146         priv->grctx_vals = ctx;
 147         return 0;
 148
 149 err:
 150         kfree(ctx);
 151         return ret;
 152 }
 153
 154 static int
 155 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 156 {
 157         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
 158         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
 159         struct drm_device *dev = chan->dev;
 160         int i = 0, gpc, tp, ret;
 161         u32 magic;
 162
 163         ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
 164                                  &grch->unk408004);
 165         if (ret)
 166                 return ret;
 167
 168         ret = nouveau_gpuobj_new(dev, chan, 0x8000, 256, NVOBJ_FLAG_VM,
 169                                  &grch->unk40800c);
 170         if (ret)
 171                 return ret;
 172
 173         ret = nouveau_gpuobj_new(dev, chan, 384 * 1024, 4096,
 174                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
 175                                  &grch->unk418810);
 176         if (ret)
 177                 return ret;
 178
 179         ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, NVOBJ_FLAG_VM,
 180                                  &grch->mmio);
 181         if (ret)
 182                 return ret;
 183
 184
 185         nv_wo32(grch->mmio, i++ * 4, 0x00408004);
 186         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
 187         nv_wo32(grch->mmio, i++ * 4, 0x00408008);
 188         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 189
 190         nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
 191         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
 192         nv_wo32(grch->mmio, i++ * 4, 0x00408010);
 193         nv_wo32(grch->mmio, i++ * 4, 0x80000000);
 194
 195         nv_wo32(grch->mmio, i++ * 4, 0x00418810);
 196         nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
 197         nv_wo32(grch->mmio, i++ * 4, 0x00419848);
 198         nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
 199
 200         nv_wo32(grch->mmio, i++ * 4, 0x00419004);
 201         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
 202         nv_wo32(grch->mmio, i++ * 4, 0x00419008);
 203         nv_wo32(grch->mmio, i++ * 4, 0x00000000);
 204
 205         nv_wo32(grch->mmio, i++ * 4, 0x00418808);
 206         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
 207         nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
 208         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 209
 210         magic = 0x02180000;
 211         nv_wo32(grch->mmio, i++ * 4, 0x00405830);
 212         nv_wo32(grch->mmio, i++ * 4, magic);
 213         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 214                 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) {
 215                         u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
 216                         nv_wo32(grch->mmio, i++ * 4, reg);
 217                         nv_wo32(grch->mmio, i++ * 4, magic);
 218                 }
 219         }
 220
 221         grch->mmio_nr = i / 2;
 222         return 0;
 223 }
 224
 225 static int
 226 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 227 {
 228         struct drm_device *dev = chan->dev;
 229         struct drm_nouveau_private *dev_priv = dev->dev_private;
 230         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 231         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 232         struct nvc0_graph_chan *grch;
 233         struct nouveau_gpuobj *grctx;
 234         int ret, i;
 235
 236         grch = kzalloc(sizeof(*grch), GFP_KERNEL);
 237         if (!grch)
 238                 return -ENOMEM;
 239         chan->engctx[NVOBJ_ENGINE_GR] = grch;
 240
 241         ret = nouveau_gpuobj_new(dev, chan, priv->grctx_size, 256,
 242                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
 243                                  &grch->grctx);
 244         if (ret)
 245                 goto error;
 246         grctx = grch->grctx;
 247
 248         ret = nvc0_graph_create_context_mmio_list(chan);
 249         if (ret)
 250                 goto error;
 251
 252         nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
 253         nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
 254         pinstmem->flush(dev);
 255
 256         if (!priv->grctx_vals) {
 257                 ret = nvc0_graph_construct_context(chan);
 258                 if (ret)
 259                         goto error;
 260         }
 261
 262         for (i = 0; i < priv->grctx_size; i += 4)
 263                 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
 264
 265         if (!nouveau_ctxfw) {
 266                 nv_wo32(grctx, 0x00, grch->mmio_nr);
 267                 nv_wo32(grctx, 0x04, grch->mmio->linst >> 8);
 268         } else {
 269                 nv_wo32(grctx, 0xf4, 0);
 270                 nv_wo32(grctx, 0xf8, 0);
 271                 nv_wo32(grctx, 0x10, grch->mmio_nr);
 272                 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
 273                 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
 274                 nv_wo32(grctx, 0x1c, 1);
 275                 nv_wo32(grctx, 0x20, 0);
 276                 nv_wo32(grctx, 0x28, 0);
 277                 nv_wo32(grctx, 0x2c, 0);
 278         }
 279         pinstmem->flush(dev);
 280         return 0;
 281
 282 error:
 283         priv->base.context_del(chan, engine);
 284         return ret;
 285 }
 286
 287 static void
 288 nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
 289 {
 290         struct nvc0_graph_chan *grch = chan->engctx[engine];
 291
 292         nouveau_gpuobj_ref(NULL, &grch->mmio);
 293         nouveau_gpuobj_ref(NULL, &grch->unk418810);
 294         nouveau_gpuobj_ref(NULL, &grch->unk40800c);
 295         nouveau_gpuobj_ref(NULL, &grch->unk408004);
 296         nouveau_gpuobj_ref(NULL, &grch->grctx);
 297         chan->engctx[engine] = NULL;
 298 }
 299
 300 static int
 301 nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
 302                       u32 handle, u16 class)
 303 {
 304         return 0;
 305 }
 306
 307 static int
 308 nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend)
 309 {
 310         return 0;
 311 }
 312
 313 static int
 314 nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
 315                           u32 class, u32 mthd, u32 data)
 316 {
 317         nouveau_finish_page_flip(chan, NULL);
 318         return 0;
 319 }
 320
 321 static void
 322 nvc0_graph_init_obj418880(struct drm_device *dev)
 323 {
 324         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 325         int i;
 326
 327         nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
 328         nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 329         for (i = 0; i < 4; i++)
 330                 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
 331         nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
 332         nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
 333 }
 334
 335 static void
 336 nvc0_graph_init_regs(struct drm_device *dev)
 337 {
 338         nv_wr32(dev, 0x400080, 0x003083c2);
 339         nv_wr32(dev, 0x400088, 0x00006fe7);
 340         nv_wr32(dev, 0x40008c, 0x00000000);
 341         nv_wr32(dev, 0x400090, 0x00000030);
 342         nv_wr32(dev, 0x40013c, 0x013901f7);
 343         nv_wr32(dev, 0x400140, 0x00000100);
 344         nv_wr32(dev, 0x400144, 0x00000000);
 345         nv_wr32(dev, 0x400148, 0x00000110);
 346         nv_wr32(dev, 0x400138, 0x00000000);
 347         nv_wr32(dev, 0x400130, 0x00000000);
 348         nv_wr32(dev, 0x400134, 0x00000000);
 349         nv_wr32(dev, 0x400124, 0x00000002);
 350 }
 351
 352 static void
 353 nvc0_graph_init_gpc_0(struct drm_device *dev)
 354 {
 355         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 356         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tp_total);
 357         u32 data[TP_MAX / 8];
 358         u8  tpnr[GPC_MAX];
 359         int i, gpc, tpc;
 360
 361         /*
 362          *      TP      ROP UNKVAL(magic_not_rop_nr)
 363          * 450: 4/0/0/0 2        3
 364          * 460: 3/4/0/0 4        1
 365          * 465: 3/4/4/0 4        7
 366          * 470: 3/3/4/4 5        5
 367          * 480: 3/4/4/4 6        6
 368          */
 369
 370         memset(data, 0x00, sizeof(data));
 371         memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
 372         for (i = 0, gpc = -1; i < priv->tp_total; i++) {
 373                 do {
 374                         gpc = (gpc + 1) % priv->gpc_nr;
 375                 } while (!tpnr[gpc]);
 376                 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
 377
 378                 data[i / 8] |= tpc << ((i % 8) * 4);
 379         }
 380
 381         nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
 382         nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
 383         nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
 384         nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
 385
 386         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 387                 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
 388                                                   priv->tp_nr[gpc]);
 389                 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
 390                 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918);
 391         }
 392
 393         nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918);
 394         nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800));
 395 }
 396
 397 static void
 398 nvc0_graph_init_units(struct drm_device *dev)
 399 {
 400         nv_wr32(dev, 0x409c24, 0x000f0000);
 401         nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
 402         nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
 403         nv_wr32(dev, 0x408030, 0xc0000000);
 404         nv_wr32(dev, 0x40601c, 0xc0000000);
 405         nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
 406         nv_wr32(dev, 0x406018, 0xc0000000);
 407         nv_wr32(dev, 0x405840, 0xc0000000);
 408         nv_wr32(dev, 0x405844, 0x00ffffff);
 409         nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
 410         nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
 411 }
 412
 413 static void
 414 nvc0_graph_init_gpc_1(struct drm_device *dev)
 415 {
 416         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 417         int gpc, tp;
 418
 419         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 420                 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 421                 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 422                 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 423                 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 424                 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 425                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
 426                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
 427                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
 428                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
 429                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
 430                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
 431                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
 432                 }
 433                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 434                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 435         }
 436 }
 437
 438 static void
 439 nvc0_graph_init_rop(struct drm_device *dev)
 440 {
 441         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 442         int rop;
 443
 444         for (rop = 0; rop < priv->rop_nr; rop++) {
 445                 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
 446                 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
 447                 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
 448                 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
 449         }
 450 }
 451
 452 static void
 453 nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
 454                     struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
 455 {
 456         int i;
 457
 458         nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
 459         for (i = 0; i < data->size / 4; i++)
 460                 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
 461
 462         nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
 463         for (i = 0; i < code->size / 4; i++) {
 464                 if ((i & 0x3f) == 0)
 465                         nv_wr32(dev, fuc_base + 0x0188, i >> 6);
 466                 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
 467         }
 468 }
 469
 470 static int
 471 nvc0_graph_init_ctxctl(struct drm_device *dev)
 472 {
 473         struct drm_nouveau_private *dev_priv = dev->dev_private;
 474         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 475         u32 r000260;
 476         int i;
 477
 478         if (!nouveau_ctxfw) {
 479                 /* load HUB microcode */
 480                 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 481                 nv_wr32(dev, 0x4091c0, 0x01000000);
 482                 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
 483                         nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
 484
 485                 nv_wr32(dev, 0x409180, 0x01000000);
 486                 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
 487                         if ((i & 0x3f) == 0)
 488                                 nv_wr32(dev, 0x409188, i >> 6);
 489                         nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
 490                 }
 491
 492                 /* load GPC microcode */
 493                 nv_wr32(dev, 0x41a1c0, 0x01000000);
 494                 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
 495                         nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
 496
 497                 nv_wr32(dev, 0x41a180, 0x01000000);
 498                 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
 499                         if ((i & 0x3f) == 0)
 500                                 nv_wr32(dev, 0x41a188, i >> 6);
 501                         nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
 502                 }
 503                 nv_wr32(dev, 0x000260, r000260);
 504
 505                 /* start HUB ucode running, it'll init the GPCs */
 506                 nv_wr32(dev, 0x409800, dev_priv->chipset);
 507                 nv_wr32(dev, 0x40910c, 0x00000000);
 508                 nv_wr32(dev, 0x409100, 0x00000002);
 509                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 510                         NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
 511                         nvc0_graph_ctxctl_debug(dev);
 512                         return -EBUSY;
 513                 }
 514
 515                 priv->grctx_size = nv_rd32(dev, 0x409804);
 516                 return 0;
 517         }
 518
 519         /* load fuc microcode */
 520         r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 521         nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
 522         nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
 523         nv_wr32(dev, 0x000260, r000260);
 524
 525         /* start both of them running */
 526         nv_wr32(dev, 0x409840, 0xffffffff);
 527         nv_wr32(dev, 0x41a10c, 0x00000000);
 528         nv_wr32(dev, 0x40910c, 0x00000000);
 529         nv_wr32(dev, 0x41a100, 0x00000002);
 530         nv_wr32(dev, 0x409100, 0x00000002);
 531         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
 532                 NV_INFO(dev, "0x409800 wait failed\n");
 533
 534         nv_wr32(dev, 0x409840, 0xffffffff);
 535         nv_wr32(dev, 0x409500, 0x7fffffff);
 536         nv_wr32(dev, 0x409504, 0x00000021);
 537
 538         nv_wr32(dev, 0x409840, 0xffffffff);
 539         nv_wr32(dev, 0x409500, 0x00000000);
 540         nv_wr32(dev, 0x409504, 0x00000010);
 541         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 542                 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
 543                 return -EBUSY;
 544         }
 545         priv->grctx_size = nv_rd32(dev, 0x409800);
 546
 547         nv_wr32(dev, 0x409840, 0xffffffff);
 548         nv_wr32(dev, 0x409500, 0x00000000);
 549         nv_wr32(dev, 0x409504, 0x00000016);
 550         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 551                 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
 552                 return -EBUSY;
 553         }
 554
 555         nv_wr32(dev, 0x409840, 0xffffffff);
 556         nv_wr32(dev, 0x409500, 0x00000000);
 557         nv_wr32(dev, 0x409504, 0x00000025);
 558         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 559                 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
 560                 return -EBUSY;
 561         }
 562
 563         return 0;
 564 }
 565
 566 static int
 567 nvc0_graph_init(struct drm_device *dev, int engine)
 568 {
 569         int ret;
 570
 571         nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
 572         nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
 573
 574         nvc0_graph_init_obj418880(dev);
 575         nvc0_graph_init_regs(dev);
 576         /*nvc0_graph_init_unitplemented_magics(dev);*/
 577         nvc0_graph_init_gpc_0(dev);
 578         /*nvc0_graph_init_unitplemented_c242(dev);*/
 579
 580         nv_wr32(dev, 0x400500, 0x00010001);
 581         nv_wr32(dev, 0x400100, 0xffffffff);
 582         nv_wr32(dev, 0x40013c, 0xffffffff);
 583
 584         nvc0_graph_init_units(dev);
 585         nvc0_graph_init_gpc_1(dev);
 586         nvc0_graph_init_rop(dev);
 587
 588         nv_wr32(dev, 0x400108, 0xffffffff);
 589         nv_wr32(dev, 0x400138, 0xffffffff);
 590         nv_wr32(dev, 0x400118, 0xffffffff);
 591         nv_wr32(dev, 0x400130, 0xffffffff);
 592         nv_wr32(dev, 0x40011c, 0xffffffff);
 593         nv_wr32(dev, 0x400134, 0xffffffff);
 594         nv_wr32(dev, 0x400054, 0x34ce3464);
 595
 596         ret = nvc0_graph_init_ctxctl(dev);
 597         if (ret)
 598                 return ret;
 599
 600         return 0;
 601 }
 602
 603 int
 604 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
 605 {
 606         struct drm_nouveau_private *dev_priv = dev->dev_private;
 607         struct nouveau_channel *chan;
 608         unsigned long flags;
 609         int i;
 610
 611         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 612         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 613                 chan = dev_priv->channels.ptr[i];
 614                 if (!chan || !chan->ramin)
 615                         continue;
 616
 617                 if (inst == chan->ramin->vinst)
 618                         break;
 619         }
 620         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 621         return i;
 622 }
 623
 624 static void
 625 nvc0_graph_ctxctl_isr(struct drm_device *dev)
 626 {
 627         u32 ustat = nv_rd32(dev, 0x409c18);
 628
 629         if (ustat & 0x00000001)
 630                 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
 631         if (ustat & 0x00080000)
 632                 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
 633         if (ustat & ~0x00080001)
 634                 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
 635
 636         nvc0_graph_ctxctl_debug(dev);
 637         nv_wr32(dev, 0x409c20, ustat);
 638 }
 639
 640 static void
 641 nvc0_graph_isr(struct drm_device *dev)
 642 {
 643         u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
 644         u32 chid = nvc0_graph_isr_chid(dev, inst);
 645         u32 stat = nv_rd32(dev, 0x400100);
 646         u32 addr = nv_rd32(dev, 0x400704);
 647         u32 mthd = (addr & 0x00003ffc);
 648         u32 subc = (addr & 0x00070000) >> 16;
 649         u32 data = nv_rd32(dev, 0x400708);
 650         u32 code = nv_rd32(dev, 0x400110);
 651         u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
 652
 653         if (stat & 0x00000010) {
 654                 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
 655                         NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
 656                                      "subc %d class 0x%04x mthd 0x%04x "
 657                                      "data 0x%08x\n",
 658                                 chid, inst, subc, class, mthd, data);
 659                 }
 660                 nv_wr32(dev, 0x400100, 0x00000010);
 661                 stat &= ~0x00000010;
 662         }
 663
 664         if (stat & 0x00000020) {
 665                 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
 666                              "class 0x%04x mthd 0x%04x data 0x%08x\n",
 667                         chid, inst, subc, class, mthd, data);
 668                 nv_wr32(dev, 0x400100, 0x00000020);
 669                 stat &= ~0x00000020;
 670         }
 671
 672         if (stat & 0x00100000) {
 673                 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
 674                 nouveau_enum_print(nv50_data_error_names, code);
 675                 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
 676                        "mthd 0x%04x data 0x%08x\n",
 677                        chid, inst, subc, class, mthd, data);
 678                 nv_wr32(dev, 0x400100, 0x00100000);
 679                 stat &= ~0x00100000;
 680         }
 681
 682         if (stat & 0x00200000) {
 683                 u32 trap = nv_rd32(dev, 0x400108);
 684                 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
 685                 nv_wr32(dev, 0x400108, trap);
 686                 nv_wr32(dev, 0x400100, 0x00200000);
 687                 stat &= ~0x00200000;
 688         }
 689
 690         if (stat & 0x00080000) {
 691                 nvc0_graph_ctxctl_isr(dev);
 692                 nv_wr32(dev, 0x400100, 0x00080000);
 693                 stat &= ~0x00080000;
 694         }
 695
 696         if (stat) {
 697                 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
 698                 nv_wr32(dev, 0x400100, stat);
 699         }
 700
 701         nv_wr32(dev, 0x400500, 0x00010001);
 702 }
 703
 704 static int
 705 nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
 706                      struct nvc0_graph_fuc *fuc)
 707 {
 708         struct drm_nouveau_private *dev_priv = dev->dev_private;
 709         const struct firmware *fw;
 710         char f[32];
 711         int ret;
 712
 713         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
 714         ret = request_firmware(&fw, f, &dev->pdev->dev);
 715         if (ret) {
 716                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
 717                 ret = request_firmware(&fw, f, &dev->pdev->dev);
 718                 if (ret) {
 719                         NV_ERROR(dev, "failed to load %s\n", fwname);
 720                         return ret;
 721                 }
 722         }
 723
 724         fuc->size = fw->size;
 725         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
 726         release_firmware(fw);
 727         return (fuc->data != NULL) ? 0 : -ENOMEM;
 728 }
 729
 730 static void
 731 nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
 732 {
 733         if (fuc->data) {
 734                 kfree(fuc->data);
 735                 fuc->data = NULL;
 736         }
 737 }
 738
 739 static void
 740 nvc0_graph_destroy(struct drm_device *dev, int engine)
 741 {
 742         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 743
 744         if (nouveau_ctxfw) {
 745                 nvc0_graph_destroy_fw(&priv->fuc409c);
 746                 nvc0_graph_destroy_fw(&priv->fuc409d);
 747                 nvc0_graph_destroy_fw(&priv->fuc41ac);
 748                 nvc0_graph_destroy_fw(&priv->fuc41ad);
 749         }
 750
 751         nouveau_irq_unregister(dev, 12);
 752
 753         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 754         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 755
 756         if (priv->grctx_vals)
 757                 kfree(priv->grctx_vals);
 758
 759         NVOBJ_ENGINE_DEL(dev, GR);
 760         kfree(priv);
 761 }
 762
 763 int
 764 nvc0_graph_create(struct drm_device *dev)
 765 {
 766         struct drm_nouveau_private *dev_priv = dev->dev_private;
 767         struct nvc0_graph_priv *priv;
 768         int ret, gpc, i;
 769         u32 fermi;
 770
 771         fermi = nvc0_graph_class(dev);
 772         if (!fermi) {
 773                 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
 774                 return 0;
 775         }
 776
 777         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 778         if (!priv)
 779                 return -ENOMEM;
 780
 781         priv->base.destroy = nvc0_graph_destroy;
 782         priv->base.init = nvc0_graph_init;
 783         priv->base.fini = nvc0_graph_fini;
 784         priv->base.context_new = nvc0_graph_context_new;
 785         priv->base.context_del = nvc0_graph_context_del;
 786         priv->base.object_new = nvc0_graph_object_new;
 787
 788         NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
 789         nouveau_irq_register(dev, 12, nvc0_graph_isr);
 790
 791         if (nouveau_ctxfw) {
 792                 NV_INFO(dev, "PGRAPH: using external firmware\n");
 793                 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
 794                     nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
 795                     nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
 796                     nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
 797                         ret = 0;
 798                         goto error;
 799                 }
 800         }
 801
 802         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
 803         if (ret)
 804                 goto error;
 805
 806         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
 807         if (ret)
 808                 goto error;
 809
 810         for (i = 0; i < 0x1000; i += 4) {
 811                 nv_wo32(priv->unk4188b4, i, 0x00000010);
 812                 nv_wo32(priv->unk4188b8, i, 0x00000010);
 813         }
 814
 815         priv->gpc_nr  =  nv_rd32(dev, 0x409604) & 0x0000001f;
 816         priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
 817         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 818                 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
 819                 priv->tp_total += priv->tp_nr[gpc];
 820         }
 821
 822         /*XXX: these need figuring out... */
 823         switch (dev_priv->chipset) {
 824         case 0xc0:
 825                 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
 826                         priv->magic_not_rop_nr = 0x07;
 827                 } else
 828                 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
 829                         priv->magic_not_rop_nr = 0x05;
 830                 } else
 831                 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
 832                         priv->magic_not_rop_nr = 0x06;
 833                 }
 834                 break;
 835         case 0xc3: /* 450, 4/0/0/0, 2 */
 836                 priv->magic_not_rop_nr = 0x03;
 837                 break;
 838         case 0xc4: /* 460, 3/4/0/0, 4 */
 839                 priv->magic_not_rop_nr = 0x01;
 840                 break;
 841         case 0xc1: /* 2/0/0/0, 1 */
 842                 priv->magic_not_rop_nr = 0x01;
 843                 break;
 844         case 0xc8: /* 4/4/3/4, 5 */
 845                 priv->magic_not_rop_nr = 0x06;
 846                 break;
 847         case 0xce: /* 4/4/0/0, 4 */
 848                 priv->magic_not_rop_nr = 0x03;
 849                 break;
 850         case 0xcf: /* 4/0/0/0, 3 */
 851                 priv->magic_not_rop_nr = 0x03;
 852                 break;
 853         }
 854
 855         if (!priv->magic_not_rop_nr) {
 856                 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
 857                          priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
 858                          priv->tp_nr[3], priv->rop_nr);
 859                 /* use 0xc3's values... */
 860                 priv->magic_not_rop_nr = 0x03;
 861         }
 862
 863         NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
 864         NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
 865         NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
 866         NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
 867         if (fermi >= 0x9197)
 868                 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
 869         if (fermi >= 0x9297)
 870                 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
 871         NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
 872         return 0;
 873
 874 error:
 875         nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
 876         return ret;
 877 }