drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_grctx.h"
  32 #include "nouveau_dma.h"
  33 #include "nouveau_vm.h"
  34 #include "nouveau_ramht.h"
  35 #include "nv50_evo.h"
  36
  37 struct nv50_graph_engine {
  38         struct nouveau_exec_engine base;
  39         u32 ctxprog[512];
  40         u32 ctxprog_size;
  41         u32 grctx_size;
  42 };
  43
  44 static void
  45 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
  46 {
  47         const uint32_t mask = 0x00010001;
  48
  49         if (enabled)
  50                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
  51         else
  52                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
  53 }
  54
  55 static struct nouveau_channel *
  56 nv50_graph_channel(struct drm_device *dev)
  57 {
  58         struct drm_nouveau_private *dev_priv = dev->dev_private;
  59         uint32_t inst;
  60         int i;
  61
  62         /* Be sure we're not in the middle of a context switch or bad things
  63          * will happen, such as unloading the wrong pgraph context.
  64          */
  65         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
  66                 NV_ERROR(dev, "Ctxprog is still running\n");
  67
  68         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
  69         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
  70                 return NULL;
  71         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
  72
  73         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  74                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
  75
  76                 if (chan && chan->ramin && chan->ramin->vinst == inst)
  77                         return chan;
  78         }
  79
  80         return NULL;
  81 }
  82
  83 static int
  84 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
  85 {
  86         uint32_t fifo = nv_rd32(dev, 0x400500);
  87
  88         nv_wr32(dev, 0x400500, fifo & ~1);
  89         nv_wr32(dev, 0x400784, inst);
  90         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
  91         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
  92         nv_wr32(dev, 0x400040, 0xffffffff);
  93         (void)nv_rd32(dev, 0x400040);
  94         nv_wr32(dev, 0x400040, 0x00000000);
  95         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
  96
  97         if (nouveau_wait_for_idle(dev))
  98                 nv_wr32(dev, 0x40032c, inst | (1<<31));
  99         nv_wr32(dev, 0x400500, fifo);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 nv50_graph_unload_context(struct drm_device *dev)
 106 {
 107         uint32_t inst;
 108
 109         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 110         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 111                 return 0;
 112         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 113
 114         nouveau_wait_for_idle(dev);
 115         nv_wr32(dev, 0x400784, inst);
 116         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 117         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 118         nouveau_wait_for_idle(dev);
 119
 120         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 121         return 0;
 122 }
 123
 124 static void
 125 nv50_graph_init_reset(struct drm_device *dev)
 126 {
 127         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
 128
 129         NV_DEBUG(dev, "\n");
 130
 131         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
 132         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
 133 }
 134
 135 static void
 136 nv50_graph_init_intr(struct drm_device *dev)
 137 {
 138         NV_DEBUG(dev, "\n");
 139
 140         nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
 141         nv_wr32(dev, 0x400138, 0xffffffff);
 142         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
 143 }
 144
 145 static void
 146 nv50_graph_init_regs__nv(struct drm_device *dev)
 147 {
 148         struct drm_nouveau_private *dev_priv = dev->dev_private;
 149         uint32_t units = nv_rd32(dev, 0x1540);
 150         int i;
 151
 152         NV_DEBUG(dev, "\n");
 153
 154         nv_wr32(dev, 0x400804, 0xc0000000);
 155         nv_wr32(dev, 0x406800, 0xc0000000);
 156         nv_wr32(dev, 0x400c04, 0xc0000000);
 157         nv_wr32(dev, 0x401800, 0xc0000000);
 158         nv_wr32(dev, 0x405018, 0xc0000000);
 159         nv_wr32(dev, 0x402000, 0xc0000000);
 160
 161         for (i = 0; i < 16; i++) {
 162                 if (units & 1 << i) {
 163                         if (dev_priv->chipset < 0xa0) {
 164                                 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
 165                                 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
 166                                 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
 167                         } else {
 168                                 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
 169                                 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
 170                                 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
 171                         }
 172                 }
 173         }
 174
 175         nv_wr32(dev, 0x400108, 0xffffffff);
 176
 177         nv_wr32(dev, 0x400824, 0x00004000);
 178         nv_wr32(dev, 0x400500, 0x00010001);
 179 }
 180
 181 static void
 182 nv50_graph_init_zcull(struct drm_device *dev)
 183 {
 184         struct drm_nouveau_private *dev_priv = dev->dev_private;
 185         int i;
 186
 187         NV_DEBUG(dev, "\n");
 188
 189         switch (dev_priv->chipset & 0xf0) {
 190         case 0x50:
 191         case 0x80:
 192         case 0x90:
 193                 nv_wr32(dev, 0x402ca8, 0x00000800);
 194                 break;
 195         case 0xa0:
 196         default:
 197                 nv_wr32(dev, 0x402cc0, 0x00000000);
 198                 if (dev_priv->chipset == 0xa0 ||
 199                     dev_priv->chipset == 0xaa ||
 200                     dev_priv->chipset == 0xac) {
 201                         nv_wr32(dev, 0x402ca8, 0x00000802);
 202                 } else {
 203                         nv_wr32(dev, 0x402cc0, 0x00000000);
 204                         nv_wr32(dev, 0x402ca8, 0x00000002);
 205                 }
 206
 207                 break;
 208         }
 209
 210         /* zero out zcull regions */
 211         for (i = 0; i < 8; i++) {
 212                 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
 213                 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
 214                 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
 215                 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
 216         }
 217 }
 218
 219 static int
 220 nv50_graph_init_ctxctl(struct drm_device *dev)
 221 {
 222         struct nv50_graph_engine *pgraph = nv_engine(dev, NVOBJ_ENGINE_GR);
 223         int i;
 224
 225         NV_DEBUG(dev, "\n");
 226
 227         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 228         for (i = 0; i < pgraph->ctxprog_size; i++)
 229                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, pgraph->ctxprog[i]);
 230
 231         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
 232         nv_wr32(dev, 0x400320, 4);
 233         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
 234         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 235         return 0;
 236 }
 237
 238 static int
 239 nv50_graph_init(struct drm_device *dev, int engine)
 240 {
 241         int ret;
 242
 243         NV_DEBUG(dev, "\n");
 244
 245         nv50_graph_init_reset(dev);
 246         nv50_graph_init_regs__nv(dev);
 247         nv50_graph_init_zcull(dev);
 248
 249         ret = nv50_graph_init_ctxctl(dev);
 250         if (ret)
 251                 return ret;
 252
 253         nv50_graph_init_intr(dev);
 254         return 0;
 255 }
 256
 257 static int
 258 nv50_graph_fini(struct drm_device *dev, int engine)
 259 {
 260         NV_DEBUG(dev, "\n");
 261         nv50_graph_unload_context(dev);
 262         nv_wr32(dev, 0x40013c, 0x00000000);
 263         return 0;
 264 }
 265
 266 static int
 267 nv50_graph_context_new(struct nouveau_channel *chan, int engine)
 268 {
 269         struct drm_device *dev = chan->dev;
 270         struct drm_nouveau_private *dev_priv = dev->dev_private;
 271         struct nouveau_gpuobj *ramin = chan->ramin;
 272         struct nouveau_gpuobj *grctx = NULL;
 273         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 274         struct nouveau_grctx ctx = {};
 275         int hdr, ret;
 276
 277         NV_DEBUG(dev, "ch%d\n", chan->id);
 278
 279         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
 280                                  NVOBJ_FLAG_ZERO_ALLOC |
 281                                  NVOBJ_FLAG_ZERO_FREE, &grctx);
 282         if (ret)
 283                 return ret;
 284
 285         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 286         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 287         nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
 288         nv_wo32(ramin, hdr + 0x08, grctx->vinst);
 289         nv_wo32(ramin, hdr + 0x0c, 0);
 290         nv_wo32(ramin, hdr + 0x10, 0);
 291         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 292
 293         ctx.dev = chan->dev;
 294         ctx.mode = NOUVEAU_GRCTX_VALS;
 295         ctx.data = grctx;
 296         nv50_grctx_init(&ctx);
 297
 298         nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
 299
 300         dev_priv->engine.instmem.flush(dev);
 301
 302         atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
 303         chan->engctx[NVOBJ_ENGINE_GR] = grctx;
 304         return 0;
 305 }
 306
 307 static void
 308 nv50_graph_context_del(struct nouveau_channel *chan, int engine)
 309 {
 310         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 311         struct drm_device *dev = chan->dev;
 312         struct drm_nouveau_private *dev_priv = dev->dev_private;
 313         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 314         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 315         unsigned long flags;
 316
 317         NV_DEBUG(dev, "ch%d\n", chan->id);
 318
 319         if (!chan->ramin)
 320                 return;
 321
 322         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 323         pfifo->reassign(dev, false);
 324         nv50_graph_fifo_access(dev, false);
 325
 326         if (nv50_graph_channel(dev) == chan)
 327                 nv50_graph_unload_context(dev);
 328
 329         for (i = hdr; i < hdr + 24; i += 4)
 330                 nv_wo32(chan->ramin, i, 0);
 331         dev_priv->engine.instmem.flush(dev);
 332
 333         nv50_graph_fifo_access(dev, true);
 334         pfifo->reassign(dev, true);
 335         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 336
 337         nouveau_gpuobj_ref(NULL, &grctx);
 338
 339         atomic_dec(&chan->vm->engref[engine]);
 340         chan->engctx[engine] = NULL;
 341 }
 342
 343 static int
 344 nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 345                       u32 handle, u16 class)
 346 {
 347         struct drm_device *dev = chan->dev;
 348         struct drm_nouveau_private *dev_priv = dev->dev_private;
 349         struct nouveau_gpuobj *obj = NULL;
 350         int ret;
 351
 352         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 353         if (ret)
 354                 return ret;
 355         obj->engine = 1;
 356         obj->class  = class;
 357
 358         nv_wo32(obj, 0x00, class);
 359         nv_wo32(obj, 0x04, 0x00000000);
 360         nv_wo32(obj, 0x08, 0x00000000);
 361         nv_wo32(obj, 0x0c, 0x00000000);
 362         dev_priv->engine.instmem.flush(dev);
 363
 364         ret = nouveau_ramht_insert(chan, handle, obj);
 365         nouveau_gpuobj_ref(NULL, &obj);
 366         return ret;
 367 }
 368
 369 static void
 370 nv50_graph_context_switch(struct drm_device *dev)
 371 {
 372         uint32_t inst;
 373
 374         nv50_graph_unload_context(dev);
 375
 376         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 377         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 378         nv50_graph_do_load_context(dev, inst);
 379
 380         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 381                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 382 }
 383
 384 static int
 385 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
 386                            u32 class, u32 mthd, u32 data)
 387 {
 388         struct nouveau_gpuobj *gpuobj;
 389
 390         gpuobj = nouveau_ramht_find(chan, data);
 391         if (!gpuobj)
 392                 return -ENOENT;
 393
 394         if (nouveau_notifier_offset(gpuobj, NULL))
 395                 return -EINVAL;
 396
 397         chan->nvsw.vblsem = gpuobj;
 398         chan->nvsw.vblsem_offset = ~0;
 399         return 0;
 400 }
 401
 402 static int
 403 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
 404                               u32 class, u32 mthd, u32 data)
 405 {
 406         if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
 407                 return -ERANGE;
 408
 409         chan->nvsw.vblsem_offset = data >> 2;
 410         return 0;
 411 }
 412
 413 static int
 414 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
 415                                    u32 class, u32 mthd, u32 data)
 416 {
 417         chan->nvsw.vblsem_rval = data;
 418         return 0;
 419 }
 420
 421 static int
 422 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
 423                                u32 class, u32 mthd, u32 data)
 424 {
 425         struct drm_device *dev = chan->dev;
 426         struct drm_nouveau_private *dev_priv = dev->dev_private;
 427
 428         if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
 429                 return -EINVAL;
 430
 431         drm_vblank_get(dev, data);
 432
 433         chan->nvsw.vblsem_head = data;
 434         list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
 435
 436         return 0;
 437 }
 438
 439 static int
 440 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
 441                                u32 class, u32 mthd, u32 data)
 442 {
 443         nouveau_finish_page_flip(chan, NULL);
 444         return 0;
 445 }
 446
 447
 448 static void
 449 nv50_graph_tlb_flush(struct drm_device *dev, int engine)
 450 {
 451         nv50_vm_flush_engine(dev, 0);
 452 }
 453
 454 static void
 455 nv84_graph_tlb_flush(struct drm_device *dev, int engine)
 456 {
 457         struct drm_nouveau_private *dev_priv = dev->dev_private;
 458         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 459         bool idle, timeout = false;
 460         unsigned long flags;
 461         u64 start;
 462         u32 tmp;
 463
 464         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 465         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 466
 467         start = ptimer->read(dev);
 468         do {
 469                 idle = true;
 470
 471                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 472                         if ((tmp & 7) == 1)
 473                                 idle = false;
 474                 }
 475
 476                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 477                         if ((tmp & 7) == 1)
 478                                 idle = false;
 479                 }
 480
 481                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 482                         if ((tmp & 7) == 1)
 483                                 idle = false;
 484                 }
 485         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 486
 487         if (timeout) {
 488                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 489                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 490                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 491                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 492         }
 493
 494         nv50_vm_flush_engine(dev, 0);
 495
 496         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 497         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 498 }
 499
 500 static struct nouveau_enum nv50_mp_exec_error_names[] = {
 501         { 3, "STACK_UNDERFLOW", NULL },
 502         { 4, "QUADON_ACTIVE", NULL },
 503         { 8, "TIMEOUT", NULL },
 504         { 0x10, "INVALID_OPCODE", NULL },
 505         { 0x40, "BREAKPOINT", NULL },
 506         {}
 507 };
 508
 509 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 510         { 0x00000001, "NOTIFY" },
 511         { 0x00000002, "IN" },
 512         { 0x00000004, "OUT" },
 513         {}
 514 };
 515
 516 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 517         { 0x00000001, "FAULT" },
 518         {}
 519 };
 520
 521 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 522         { 0x00000001, "FAULT" },
 523         {}
 524 };
 525
 526 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 527         { 0x00000001, "FAULT" },
 528         {}
 529 };
 530
 531 /* There must be a *lot* of these. Will take some time to gather them up. */
 532 struct nouveau_enum nv50_data_error_names[] = {
 533         { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
 534         { 0x00000004, "INVALID_VALUE", NULL },
 535         { 0x00000005, "INVALID_ENUM", NULL },
 536         { 0x00000008, "INVALID_OBJECT", NULL },
 537         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 538         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 539         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 540         { 0x0000000c, "INVALID_BITFIELD", NULL },
 541         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 542         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 543         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 544         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 545         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 546         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 547         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 548         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 549         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 550         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 551         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 552         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 553         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 554         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 555         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 556         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 557         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 558         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 559         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 560         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 561         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 562         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 563         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 564         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 565         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 566         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 567         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 568         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 569         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 570         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 571         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 572         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 573         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 574         {}
 575 };
 576
 577 static struct nouveau_bitfield nv50_graph_intr[] = {
 578         { 0x00000001, "NOTIFY" },
 579         { 0x00000002, "COMPUTE_QUERY" },
 580         { 0x00000010, "ILLEGAL_MTHD" },
 581         { 0x00000020, "ILLEGAL_CLASS" },
 582         { 0x00000040, "DOUBLE_NOTIFY" },
 583         { 0x00001000, "CONTEXT_SWITCH" },
 584         { 0x00010000, "BUFFER_NOTIFY" },
 585         { 0x00100000, "DATA_ERROR" },
 586         { 0x00200000, "TRAP" },
 587         { 0x01000000, "SINGLE_STEP" },
 588         {}
 589 };
 590
 591 static void
 592 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 593 {
 594         struct drm_nouveau_private *dev_priv = dev->dev_private;
 595         uint32_t units = nv_rd32(dev, 0x1540);
 596         uint32_t addr, mp10, status, pc, oplow, ophigh;
 597         int i;
 598         int mps = 0;
 599         for (i = 0; i < 4; i++) {
 600                 if (!(units & 1 << (i+24)))
 601                         continue;
 602                 if (dev_priv->chipset < 0xa0)
 603                         addr = 0x408200 + (tpid << 12) + (i << 7);
 604                 else
 605                         addr = 0x408100 + (tpid << 11) + (i << 7);
 606                 mp10 = nv_rd32(dev, addr + 0x10);
 607                 status = nv_rd32(dev, addr + 0x14);
 608                 if (!status)
 609                         continue;
 610                 if (display) {
 611                         nv_rd32(dev, addr + 0x20);
 612                         pc = nv_rd32(dev, addr + 0x24);
 613                         oplow = nv_rd32(dev, addr + 0x70);
 614                         ophigh = nv_rd32(dev, addr + 0x74);
 615                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 616                                         "TP %d MP %d: ", tpid, i);
 617                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 618                         printk(" at %06x warp %d, opcode %08x %08x\n",
 619                                         pc&0xffffff, pc >> 24,
 620                                         oplow, ophigh);
 621                 }
 622                 nv_wr32(dev, addr + 0x10, mp10);
 623                 nv_wr32(dev, addr + 0x14, 0);
 624                 mps++;
 625         }
 626         if (!mps && display)
 627                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 628                                 "No MPs claiming errors?\n", tpid);
 629 }
 630
 631 static void
 632 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 633                 uint32_t ustatus_new, int display, const char *name)
 634 {
 635         struct drm_nouveau_private *dev_priv = dev->dev_private;
 636         int tps = 0;
 637         uint32_t units = nv_rd32(dev, 0x1540);
 638         int i, r;
 639         uint32_t ustatus_addr, ustatus;
 640         for (i = 0; i < 16; i++) {
 641                 if (!(units & (1 << i)))
 642                         continue;
 643                 if (dev_priv->chipset < 0xa0)
 644                         ustatus_addr = ustatus_old + (i << 12);
 645                 else
 646                         ustatus_addr = ustatus_new + (i << 11);
 647                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 648                 if (!ustatus)
 649                         continue;
 650                 tps++;
 651                 switch (type) {
 652                 case 6: /* texture error... unknown for now */
 653                         if (display) {
 654                                 NV_ERROR(dev, "magic set %d:\n", i);
 655                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 656                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 657                                                 nv_rd32(dev, r));
 658                         }
 659                         break;
 660                 case 7: /* MP error */
 661                         if (ustatus & 0x00010000) {
 662                                 nv50_pgraph_mp_trap(dev, i, display);
 663                                 ustatus &= ~0x00010000;
 664                         }
 665                         break;
 666                 case 8: /* TPDMA error */
 667                         {
 668                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 669                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 670                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 671                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 672                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 673                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 674                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 675                         /* 2d engine destination */
 676                         if (ustatus & 0x00000010) {
 677                                 if (display) {
 678                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 679                                                         i, e14, e10);
 680                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 681                                                         i, e0c, e18, e1c, e20, e24);
 682                                 }
 683                                 ustatus &= ~0x00000010;
 684                         }
 685                         /* Render target */
 686                         if (ustatus & 0x00000040) {
 687                                 if (display) {
 688                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 689                                                         i, e14, e10);
 690                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 691                                                         i, e0c, e18, e1c, e20, e24);
 692                                 }
 693                                 ustatus &= ~0x00000040;
 694                         }
 695                         /* CUDA memory: l[], g[] or stack. */
 696                         if (ustatus & 0x00000080) {
 697                                 if (display) {
 698                                         if (e18 & 0x80000000) {
 699                                                 /* g[] read fault? */
 700                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 701                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 702                                                 e18 &= ~0x1f000000;
 703                                         } else if (e18 & 0xc) {
 704                                                 /* g[] write fault? */
 705                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 706                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 707                                                 e18 &= ~0x00000f80;
 708                                         } else {
 709                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 710                                                                 i, e14, e10);
 711                                         }
 712                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 713                                                         i, e0c, e18, e1c, e20, e24);
 714                                 }
 715                                 ustatus &= ~0x00000080;
 716                         }
 717                         }
 718                         break;
 719                 }
 720                 if (ustatus) {
 721                         if (display)
 722                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 723                 }
 724                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 725         }
 726
 727         if (!tps && display)
 728                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 729 }
 730
 731 static int
 732 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 733 {
 734         u32 status = nv_rd32(dev, 0x400108);
 735         u32 ustatus;
 736
 737         if (!status && display) {
 738                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 739                 return 1;
 740         }
 741
 742         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 743          * COND, QUERY. If you get a trap from it, the command is still stuck
 744          * in DISPATCH and you need to do something about it. */
 745         if (status & 0x001) {
 746                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 747                 if (!ustatus && display) {
 748                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 749                 }
 750
 751                 nv_wr32(dev, 0x400500, 0x00000000);
 752
 753                 /* Known to be triggered by screwed up NOTIFY and COND... */
 754                 if (ustatus & 0x00000001) {
 755                         u32 addr = nv_rd32(dev, 0x400808);
 756                         u32 subc = (addr & 0x00070000) >> 16;
 757                         u32 mthd = (addr & 0x00001ffc);
 758                         u32 datal = nv_rd32(dev, 0x40080c);
 759                         u32 datah = nv_rd32(dev, 0x400810);
 760                         u32 class = nv_rd32(dev, 0x400814);
 761                         u32 r848 = nv_rd32(dev, 0x400848);
 762
 763                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 764                         if (display && (addr & 0x80000000)) {
 765                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 766                                              "subc %d class 0x%04x mthd 0x%04x "
 767                                              "data 0x%08x%08x "
 768                                              "400808 0x%08x 400848 0x%08x\n",
 769                                         chid, inst, subc, class, mthd, datah,
 770                                         datal, addr, r848);
 771                         } else
 772                         if (display) {
 773                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 774                         }
 775
 776                         nv_wr32(dev, 0x400808, 0);
 777                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 778                         nv_wr32(dev, 0x400848, 0);
 779                         ustatus &= ~0x00000001;
 780                 }
 781
 782                 if (ustatus & 0x00000002) {
 783                         u32 addr = nv_rd32(dev, 0x40084c);
 784                         u32 subc = (addr & 0x00070000) >> 16;
 785                         u32 mthd = (addr & 0x00001ffc);
 786                         u32 data = nv_rd32(dev, 0x40085c);
 787                         u32 class = nv_rd32(dev, 0x400814);
 788
 789                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 790                         if (display && (addr & 0x80000000)) {
 791                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 792                                              "subc %d class 0x%04x mthd 0x%04x "
 793                                              "data 0x%08x 40084c 0x%08x\n",
 794                                         chid, inst, subc, class, mthd,
 795                                         data, addr);
 796                         } else
 797                         if (display) {
 798                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 799                         }
 800
 801                         nv_wr32(dev, 0x40084c, 0);
 802                         ustatus &= ~0x00000002;
 803                 }
 804
 805                 if (ustatus && display) {
 806                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 807                                       "0x%08x)\n", ustatus);
 808                 }
 809
 810                 nv_wr32(dev, 0x400804, 0xc0000000);
 811                 nv_wr32(dev, 0x400108, 0x001);
 812                 status &= ~0x001;
 813                 if (!status)
 814                         return 0;
 815         }
 816
 817         /* M2MF: Memory to memory copy engine. */
 818         if (status & 0x002) {
 819                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 820                 if (display) {
 821                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 822                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 823                         printk("\n");
 824                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 825                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 826                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 827
 828                 }
 829
 830                 /* No sane way found yet -- just reset the bugger. */
 831                 nv_wr32(dev, 0x400040, 2);
 832                 nv_wr32(dev, 0x400040, 0);
 833                 nv_wr32(dev, 0x406800, 0xc0000000);
 834                 nv_wr32(dev, 0x400108, 0x002);
 835                 status &= ~0x002;
 836         }
 837
 838         /* VFETCH: Fetches data from vertex buffers. */
 839         if (status & 0x004) {
 840                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 841                 if (display) {
 842                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 843                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 844                         printk("\n");
 845                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 846                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 847                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 848                 }
 849
 850                 nv_wr32(dev, 0x400c04, 0xc0000000);
 851                 nv_wr32(dev, 0x400108, 0x004);
 852                 status &= ~0x004;
 853         }
 854
 855         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 856         if (status & 0x008) {
 857                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 858                 if (display) {
 859                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 860                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 861                         printk("\n");
 862                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 863                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 864                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 865
 866                 }
 867
 868                 /* No sane way found yet -- just reset the bugger. */
 869                 nv_wr32(dev, 0x400040, 0x80);
 870                 nv_wr32(dev, 0x400040, 0);
 871                 nv_wr32(dev, 0x401800, 0xc0000000);
 872                 nv_wr32(dev, 0x400108, 0x008);
 873                 status &= ~0x008;
 874         }
 875
 876         /* CCACHE: Handles code and c[] caches and fills them. */
 877         if (status & 0x010) {
 878                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 879                 if (display) {
 880                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 881                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 882                         printk("\n");
 883                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 884                                      " %08x %08x %08x\n",
 885                                 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
 886                                 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
 887                                 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
 888                                 nv_rd32(dev, 0x40501c));
 889
 890                 }
 891
 892                 nv_wr32(dev, 0x405018, 0xc0000000);
 893                 nv_wr32(dev, 0x400108, 0x010);
 894                 status &= ~0x010;
 895         }
 896
 897         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 898          * remaining, so try to handle it anyway. Perhaps related to that
 899          * unknown DMA slot on tesla? */
 900         if (status & 0x20) {
 901                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 902                 if (display)
 903                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 904                 nv_wr32(dev, 0x402000, 0xc0000000);
 905                 /* no status modifiction on purpose */
 906         }
 907
 908         /* TEXTURE: CUDA texturing units */
 909         if (status & 0x040) {
 910                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 911                                     "PGRAPH - TRAP_TEXTURE");
 912                 nv_wr32(dev, 0x400108, 0x040);
 913                 status &= ~0x040;
 914         }
 915
 916         /* MP: CUDA execution engines. */
 917         if (status & 0x080) {
 918                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 919                                     "PGRAPH - TRAP_MP");
 920                 nv_wr32(dev, 0x400108, 0x080);
 921                 status &= ~0x080;
 922         }
 923
 924         /* TPDMA:  Handles TP-initiated uncached memory accesses:
 925          * l[], g[], stack, 2d surfaces, render targets. */
 926         if (status & 0x100) {
 927                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
 928                                     "PGRAPH - TRAP_TPDMA");
 929                 nv_wr32(dev, 0x400108, 0x100);
 930                 status &= ~0x100;
 931         }
 932
 933         if (status) {
 934                 if (display)
 935                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
 936                 nv_wr32(dev, 0x400108, status);
 937         }
 938
 939         return 1;
 940 }
 941
 942 int
 943 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 944 {
 945         struct drm_nouveau_private *dev_priv = dev->dev_private;
 946         struct nouveau_channel *chan;
 947         unsigned long flags;
 948         int i;
 949
 950         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 951         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 952                 chan = dev_priv->channels.ptr[i];
 953                 if (!chan || !chan->ramin)
 954                         continue;
 955
 956                 if (inst == chan->ramin->vinst)
 957                         break;
 958         }
 959         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 960         return i;
 961 }
 962
 963 static void
 964 nv50_graph_isr(struct drm_device *dev)
 965 {
 966         u32 stat;
 967
 968         while ((stat = nv_rd32(dev, 0x400100))) {
 969                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
 970                 u32 chid = nv50_graph_isr_chid(dev, inst);
 971                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 972                 u32 subc = (addr & 0x00070000) >> 16;
 973                 u32 mthd = (addr & 0x00001ffc);
 974                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 975                 u32 class = nv_rd32(dev, 0x400814);
 976                 u32 show = stat;
 977
 978                 if (stat & 0x00000010) {
 979                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
 980                                                        mthd, data))
 981                                 show &= ~0x00000010;
 982                 }
 983
 984                 if (stat & 0x00001000) {
 985                         nv_wr32(dev, 0x400500, 0x00000000);
 986                         nv_wr32(dev, 0x400100, 0x00001000);
 987                         nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
 988                         nv50_graph_context_switch(dev);
 989                         stat &= ~0x00001000;
 990                         show &= ~0x00001000;
 991                 }
 992
 993                 show = (show && nouveau_ratelimit()) ? show : 0;
 994
 995                 if (show & 0x00100000) {
 996                         u32 ecode = nv_rd32(dev, 0x400110);
 997                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
 998                         nouveau_enum_print(nv50_data_error_names, ecode);
 999                         printk("\n");
1000                 }
1001
1002                 if (stat & 0x00200000) {
1003                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1004                                 show &= ~0x00200000;
1005                 }
1006
1007                 nv_wr32(dev, 0x400100, stat);
1008                 nv_wr32(dev, 0x400500, 0x00010001);
1009
1010                 if (show) {
1011                         NV_INFO(dev, "PGRAPH -");
1012                         nouveau_bitfield_print(nv50_graph_intr, show);
1013                         printk("\n");
1014                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1015                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
1016                                 chid, inst, subc, class, mthd, data);
1017                         nv50_fb_vm_trap(dev, 1);
1018                 }
1019         }
1020
1021         if (nv_rd32(dev, 0x400824) & (1 << 31))
1022                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1023 }
1024
1025 static void
1026 nv50_graph_destroy(struct drm_device *dev, int engine)
1027 {
1028         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
1029
1030         NVOBJ_ENGINE_DEL(dev, GR);
1031
1032         nouveau_irq_unregister(dev, 12);
1033         kfree(pgraph);
1034 }
1035
1036 int
1037 nv50_graph_create(struct drm_device *dev)
1038 {
1039         struct drm_nouveau_private *dev_priv = dev->dev_private;
1040         struct nv50_graph_engine *pgraph;
1041         struct nouveau_grctx ctx = {};
1042         int ret;
1043
1044         pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
1045         if (!pgraph)
1046                 return -ENOMEM;
1047
1048         ctx.dev = dev;
1049         ctx.mode = NOUVEAU_GRCTX_PROG;
1050         ctx.data = pgraph->ctxprog;
1051         ctx.ctxprog_max = ARRAY_SIZE(pgraph->ctxprog);
1052
1053         ret = nv50_grctx_init(&ctx);
1054         if (ret) {
1055                 NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
1056                 kfree(pgraph);
1057                 return 0;
1058         }
1059
1060         pgraph->grctx_size = ctx.ctxvals_pos * 4;
1061         pgraph->ctxprog_size = ctx.ctxprog_len;
1062
1063         pgraph->base.destroy = nv50_graph_destroy;
1064         pgraph->base.init = nv50_graph_init;
1065         pgraph->base.fini = nv50_graph_fini;
1066         pgraph->base.context_new = nv50_graph_context_new;
1067         pgraph->base.context_del = nv50_graph_context_del;
1068         pgraph->base.object_new = nv50_graph_object_new;
1069         if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
1070                 pgraph->base.tlb_flush = nv50_graph_tlb_flush;
1071         else
1072                 pgraph->base.tlb_flush = nv84_graph_tlb_flush;
1073
1074         nouveau_irq_register(dev, 12, nv50_graph_isr);
1075
1076         /* NVSW really doesn't live here... */
1077         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
1078         NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
1079         NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
1080         NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
1081         NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
1082         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
1083
1084         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
1085         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
1086         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
1087         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
1088
1089         /* tesla */
1090         if (dev_priv->chipset == 0x50)
1091                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
1092         else
1093         if (dev_priv->chipset < 0xa0)
1094                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
1095         else {
1096                 switch (dev_priv->chipset) {
1097                 case 0xa0:
1098                 case 0xaa:
1099                 case 0xac:
1100                         NVOBJ_CLASS(dev, 0x8397, GR);
1101                         break;
1102                 case 0xa3:
1103                 case 0xa5:
1104                 case 0xa8:
1105                         NVOBJ_CLASS(dev, 0x8597, GR);
1106                         break;
1107                 case 0xaf:
1108                         NVOBJ_CLASS(dev, 0x8697, GR);
1109                         break;
1110                 }
1111         }
1112
1113         /* compute */
1114         NVOBJ_CLASS(dev, 0x50c0, GR);
1115         if (dev_priv->chipset  > 0xa0 &&
1116             dev_priv->chipset != 0xaa &&
1117             dev_priv->chipset != 0xac)
1118                 NVOBJ_CLASS(dev, 0x85c0, GR);
1119
1120         return 0;
1121 }