drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_grctx.h"
  32 #include "nouveau_dma.h"
  33 #include "nouveau_vm.h"
  34 #include "nv50_evo.h"
  35
  36 static int  nv50_graph_register(struct drm_device *);
  37 static void nv50_graph_isr(struct drm_device *);
  38
  39 static void
  40 nv50_graph_init_reset(struct drm_device *dev)
  41 {
  42         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
  43
  44         NV_DEBUG(dev, "\n");
  45
  46         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
  47         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
  48 }
  49
  50 static void
  51 nv50_graph_init_intr(struct drm_device *dev)
  52 {
  53         NV_DEBUG(dev, "\n");
  54
  55         nouveau_irq_register(dev, 12, nv50_graph_isr);
  56         nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
  57         nv_wr32(dev, 0x400138, 0xffffffff);
  58         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
  59 }
  60
  61 static void
  62 nv50_graph_init_regs__nv(struct drm_device *dev)
  63 {
  64         struct drm_nouveau_private *dev_priv = dev->dev_private;
  65         uint32_t units = nv_rd32(dev, 0x1540);
  66         int i;
  67
  68         NV_DEBUG(dev, "\n");
  69
  70         nv_wr32(dev, 0x400804, 0xc0000000);
  71         nv_wr32(dev, 0x406800, 0xc0000000);
  72         nv_wr32(dev, 0x400c04, 0xc0000000);
  73         nv_wr32(dev, 0x401800, 0xc0000000);
  74         nv_wr32(dev, 0x405018, 0xc0000000);
  75         nv_wr32(dev, 0x402000, 0xc0000000);
  76
  77         for (i = 0; i < 16; i++) {
  78                 if (units & 1 << i) {
  79                         if (dev_priv->chipset < 0xa0) {
  80                                 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
  81                                 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
  82                                 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
  83                         } else {
  84                                 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
  85                                 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
  86                                 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
  87                         }
  88                 }
  89         }
  90
  91         nv_wr32(dev, 0x400108, 0xffffffff);
  92
  93         nv_wr32(dev, 0x400824, 0x00004000);
  94         nv_wr32(dev, 0x400500, 0x00010001);
  95 }
  96
  97 static void
  98 nv50_graph_init_regs(struct drm_device *dev)
  99 {
 100         NV_DEBUG(dev, "\n");
 101
 102         nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
 103                                 (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
 104         nv_wr32(dev, 0x402ca8, 0x800);
 105 }
 106
 107 static int
 108 nv50_graph_init_ctxctl(struct drm_device *dev)
 109 {
 110         struct drm_nouveau_private *dev_priv = dev->dev_private;
 111         struct nouveau_grctx ctx = {};
 112         uint32_t *cp;
 113         int i;
 114
 115         NV_DEBUG(dev, "\n");
 116
 117         cp = kmalloc(512 * 4, GFP_KERNEL);
 118         if (!cp) {
 119                 NV_ERROR(dev, "failed to allocate ctxprog\n");
 120                 dev_priv->engine.graph.accel_blocked = true;
 121                 return 0;
 122         }
 123
 124         ctx.dev = dev;
 125         ctx.mode = NOUVEAU_GRCTX_PROG;
 126         ctx.data = cp;
 127         ctx.ctxprog_max = 512;
 128         if (!nv50_grctx_init(&ctx)) {
 129                 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 130
 131                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 132                 for (i = 0; i < ctx.ctxprog_len; i++)
 133                         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 134         } else {
 135                 dev_priv->engine.graph.accel_blocked = true;
 136         }
 137         kfree(cp);
 138
 139         nv_wr32(dev, 0x400320, 4);
 140         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
 141         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 142         return 0;
 143 }
 144
 145 int
 146 nv50_graph_init(struct drm_device *dev)
 147 {
 148         int ret;
 149
 150         NV_DEBUG(dev, "\n");
 151
 152         nv50_graph_init_reset(dev);
 153         nv50_graph_init_regs__nv(dev);
 154         nv50_graph_init_regs(dev);
 155
 156         ret = nv50_graph_init_ctxctl(dev);
 157         if (ret)
 158                 return ret;
 159
 160         ret = nv50_graph_register(dev);
 161         if (ret)
 162                 return ret;
 163         nv50_graph_init_intr(dev);
 164         return 0;
 165 }
 166
 167 void
 168 nv50_graph_takedown(struct drm_device *dev)
 169 {
 170         NV_DEBUG(dev, "\n");
 171         nv_wr32(dev, 0x40013c, 0x00000000);
 172         nouveau_irq_unregister(dev, 12);
 173 }
 174
 175 void
 176 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
 177 {
 178         const uint32_t mask = 0x00010001;
 179
 180         if (enabled)
 181                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
 182         else
 183                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
 184 }
 185
 186 struct nouveau_channel *
 187 nv50_graph_channel(struct drm_device *dev)
 188 {
 189         struct drm_nouveau_private *dev_priv = dev->dev_private;
 190         uint32_t inst;
 191         int i;
 192
 193         /* Be sure we're not in the middle of a context switch or bad things
 194          * will happen, such as unloading the wrong pgraph context.
 195          */
 196         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
 197                 NV_ERROR(dev, "Ctxprog is still running\n");
 198
 199         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 200         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 201                 return NULL;
 202         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
 203
 204         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 205                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 206
 207                 if (chan && chan->ramin && chan->ramin->vinst == inst)
 208                         return chan;
 209         }
 210
 211         return NULL;
 212 }
 213
 214 int
 215 nv50_graph_create_context(struct nouveau_channel *chan)
 216 {
 217         struct drm_device *dev = chan->dev;
 218         struct drm_nouveau_private *dev_priv = dev->dev_private;
 219         struct nouveau_gpuobj *ramin = chan->ramin;
 220         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 221         struct nouveau_grctx ctx = {};
 222         int hdr, ret;
 223
 224         NV_DEBUG(dev, "ch%d\n", chan->id);
 225
 226         ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
 227                                  NVOBJ_FLAG_ZERO_ALLOC |
 228                                  NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
 229         if (ret)
 230                 return ret;
 231
 232         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 233         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 234         nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
 235                                    pgraph->grctx_size - 1);
 236         nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
 237         nv_wo32(ramin, hdr + 0x0c, 0);
 238         nv_wo32(ramin, hdr + 0x10, 0);
 239         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 240
 241         ctx.dev = chan->dev;
 242         ctx.mode = NOUVEAU_GRCTX_VALS;
 243         ctx.data = chan->ramin_grctx;
 244         nv50_grctx_init(&ctx);
 245
 246         nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
 247
 248         dev_priv->engine.instmem.flush(dev);
 249         atomic_inc(&chan->vm->pgraph_refs);
 250         return 0;
 251 }
 252
 253 void
 254 nv50_graph_destroy_context(struct nouveau_channel *chan)
 255 {
 256         struct drm_device *dev = chan->dev;
 257         struct drm_nouveau_private *dev_priv = dev->dev_private;
 258         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 259         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 260         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 261         unsigned long flags;
 262
 263         NV_DEBUG(dev, "ch%d\n", chan->id);
 264
 265         if (!chan->ramin)
 266                 return;
 267
 268         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 269         pfifo->reassign(dev, false);
 270         pgraph->fifo_access(dev, false);
 271
 272         if (pgraph->channel(dev) == chan)
 273                 pgraph->unload_context(dev);
 274
 275         for (i = hdr; i < hdr + 24; i += 4)
 276                 nv_wo32(chan->ramin, i, 0);
 277         dev_priv->engine.instmem.flush(dev);
 278
 279         pgraph->fifo_access(dev, true);
 280         pfifo->reassign(dev, true);
 281         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 282
 283         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
 284
 285         atomic_dec(&chan->vm->pgraph_refs);
 286 }
 287
 288 static int
 289 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
 290 {
 291         uint32_t fifo = nv_rd32(dev, 0x400500);
 292
 293         nv_wr32(dev, 0x400500, fifo & ~1);
 294         nv_wr32(dev, 0x400784, inst);
 295         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
 296         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
 297         nv_wr32(dev, 0x400040, 0xffffffff);
 298         (void)nv_rd32(dev, 0x400040);
 299         nv_wr32(dev, 0x400040, 0x00000000);
 300         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
 301
 302         if (nouveau_wait_for_idle(dev))
 303                 nv_wr32(dev, 0x40032c, inst | (1<<31));
 304         nv_wr32(dev, 0x400500, fifo);
 305
 306         return 0;
 307 }
 308
 309 int
 310 nv50_graph_load_context(struct nouveau_channel *chan)
 311 {
 312         uint32_t inst = chan->ramin->vinst >> 12;
 313
 314         NV_DEBUG(chan->dev, "ch%d\n", chan->id);
 315         return nv50_graph_do_load_context(chan->dev, inst);
 316 }
 317
 318 int
 319 nv50_graph_unload_context(struct drm_device *dev)
 320 {
 321         uint32_t inst;
 322
 323         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 324         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 325                 return 0;
 326         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 327
 328         nouveau_wait_for_idle(dev);
 329         nv_wr32(dev, 0x400784, inst);
 330         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 331         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 332         nouveau_wait_for_idle(dev);
 333
 334         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 335         return 0;
 336 }
 337
 338 static void
 339 nv50_graph_context_switch(struct drm_device *dev)
 340 {
 341         uint32_t inst;
 342
 343         nv50_graph_unload_context(dev);
 344
 345         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 346         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 347         nv50_graph_do_load_context(dev, inst);
 348
 349         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 350                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 351 }
 352
 353 static int
 354 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
 355                            u32 class, u32 mthd, u32 data)
 356 {
 357         struct nouveau_gpuobj *gpuobj;
 358
 359         gpuobj = nouveau_ramht_find(chan, data);
 360         if (!gpuobj)
 361                 return -ENOENT;
 362
 363         if (nouveau_notifier_offset(gpuobj, NULL))
 364                 return -EINVAL;
 365
 366         chan->nvsw.vblsem = gpuobj;
 367         chan->nvsw.vblsem_offset = ~0;
 368         return 0;
 369 }
 370
 371 static int
 372 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
 373                               u32 class, u32 mthd, u32 data)
 374 {
 375         if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
 376                 return -ERANGE;
 377
 378         chan->nvsw.vblsem_offset = data >> 2;
 379         return 0;
 380 }
 381
 382 static int
 383 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
 384                                    u32 class, u32 mthd, u32 data)
 385 {
 386         chan->nvsw.vblsem_rval = data;
 387         return 0;
 388 }
 389
 390 static int
 391 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
 392                                u32 class, u32 mthd, u32 data)
 393 {
 394         struct drm_device *dev = chan->dev;
 395         struct drm_nouveau_private *dev_priv = dev->dev_private;
 396
 397         if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
 398                 return -EINVAL;
 399
 400         drm_vblank_get(dev, data);
 401
 402         chan->nvsw.vblsem_head = data;
 403         list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
 404
 405         return 0;
 406 }
 407
 408 static int
 409 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
 410                                u32 class, u32 mthd, u32 data)
 411 {
 412         struct nouveau_page_flip_state s;
 413
 414         if (!nouveau_finish_page_flip(chan, &s)) {
 415                 /* XXX - Do something here */
 416         }
 417
 418         return 0;
 419 }
 420
 421 static int
 422 nv50_graph_register(struct drm_device *dev)
 423 {
 424         struct drm_nouveau_private *dev_priv = dev->dev_private;
 425
 426         if (dev_priv->engine.graph.registered)
 427                 return 0;
 428
 429         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
 430         NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
 431         NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
 432         NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
 433         NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
 434         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
 435
 436         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 437         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 438         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 439
 440         /* tesla */
 441         if (dev_priv->chipset == 0x50)
 442                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 443         else
 444         if (dev_priv->chipset < 0xa0)
 445                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 446         else {
 447                 switch (dev_priv->chipset) {
 448                 case 0xa0:
 449                 case 0xaa:
 450                 case 0xac:
 451                         NVOBJ_CLASS(dev, 0x8397, GR);
 452                         break;
 453                 case 0xa3:
 454                 case 0xa5:
 455                 case 0xa8:
 456                         NVOBJ_CLASS(dev, 0x8597, GR);
 457                         break;
 458                 case 0xaf:
 459                         NVOBJ_CLASS(dev, 0x8697, GR);
 460                         break;
 461                 }
 462         }
 463
 464         /* compute */
 465         NVOBJ_CLASS(dev, 0x50c0, GR);
 466         if (dev_priv->chipset  > 0xa0 &&
 467             dev_priv->chipset != 0xaa &&
 468             dev_priv->chipset != 0xac)
 469                 NVOBJ_CLASS(dev, 0x85c0, GR);
 470
 471         dev_priv->engine.graph.registered = true;
 472         return 0;
 473 }
 474
 475 void
 476 nv50_graph_tlb_flush(struct drm_device *dev)
 477 {
 478         nv50_vm_flush_engine(dev, 0);
 479 }
 480
 481 void
 482 nv86_graph_tlb_flush(struct drm_device *dev)
 483 {
 484         struct drm_nouveau_private *dev_priv = dev->dev_private;
 485         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 486         bool idle, timeout = false;
 487         unsigned long flags;
 488         u64 start;
 489         u32 tmp;
 490
 491         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 492         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 493
 494         start = ptimer->read(dev);
 495         do {
 496                 idle = true;
 497
 498                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 499                         if ((tmp & 7) == 1)
 500                                 idle = false;
 501                 }
 502
 503                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 504                         if ((tmp & 7) == 1)
 505                                 idle = false;
 506                 }
 507
 508                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 509                         if ((tmp & 7) == 1)
 510                                 idle = false;
 511                 }
 512         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 513
 514         if (timeout) {
 515                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 516                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 517                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 518                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 519         }
 520
 521         nv50_vm_flush_engine(dev, 0);
 522
 523         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 524         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 525 }
 526
 527 static struct nouveau_enum nv50_mp_exec_error_names[] =
 528 {
 529         { 3, "STACK_UNDERFLOW" },
 530         { 4, "QUADON_ACTIVE" },
 531         { 8, "TIMEOUT" },
 532         { 0x10, "INVALID_OPCODE" },
 533         { 0x40, "BREAKPOINT" },
 534         {}
 535 };
 536
 537 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 538         { 0x00000001, "NOTIFY" },
 539         { 0x00000002, "IN" },
 540         { 0x00000004, "OUT" },
 541         {}
 542 };
 543
 544 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 545         { 0x00000001, "FAULT" },
 546         {}
 547 };
 548
 549 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 550         { 0x00000001, "FAULT" },
 551         {}
 552 };
 553
 554 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 555         { 0x00000001, "FAULT" },
 556         {}
 557 };
 558
 559 /* There must be a *lot* of these. Will take some time to gather them up. */
 560 struct nouveau_enum nv50_data_error_names[] = {
 561         { 0x00000003, "INVALID_QUERY_OR_TEXTURE" },
 562         { 0x00000004, "INVALID_VALUE" },
 563         { 0x00000005, "INVALID_ENUM" },
 564         { 0x00000008, "INVALID_OBJECT" },
 565         { 0x00000009, "READ_ONLY_OBJECT" },
 566         { 0x0000000a, "SUPERVISOR_OBJECT" },
 567         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT" },
 568         { 0x0000000c, "INVALID_BITFIELD" },
 569         { 0x0000000d, "BEGIN_END_ACTIVE" },
 570         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT" },
 571         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP" },
 572         { 0x00000010, "RT_DOUBLE_BIND" },
 573         { 0x00000011, "RT_TYPES_MISMATCH" },
 574         { 0x00000012, "RT_LINEAR_WITH_ZETA" },
 575         { 0x00000015, "FP_TOO_FEW_REGS" },
 576         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH" },
 577         { 0x00000017, "RT_LINEAR_WITH_MSAA" },
 578         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT" },
 579         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT" },
 580         { 0x0000001a, "RT_INVALID_ALIGNMENT" },
 581         { 0x0000001b, "SAMPLER_OVER_LIMIT" },
 582         { 0x0000001c, "TEXTURE_OVER_LIMIT" },
 583         { 0x0000001e, "GP_TOO_MANY_OUTPUTS" },
 584         { 0x0000001f, "RT_BPP128_WITH_MS8" },
 585         { 0x00000021, "Z_OUT_OF_BOUNDS" },
 586         { 0x00000023, "XY_OUT_OF_BOUNDS" },
 587         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED" },
 588         { 0x00000028, "CP_NO_REG_SPACE_STRIPED" },
 589         { 0x00000029, "CP_NO_REG_SPACE_PACKED" },
 590         { 0x0000002a, "CP_NOT_ENOUGH_WARPS" },
 591         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH" },
 592         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS" },
 593         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS" },
 594         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH" },
 595         { 0x00000031, "ENG2D_FORMAT_MISMATCH" },
 596         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP" },
 597         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT" },
 598         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT" },
 599         { 0x00000046, "LAYER_ID_NEEDS_GP" },
 600         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT" },
 601         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT" },
 602         {}
 603 };
 604
 605 static struct nouveau_bitfield nv50_graph_intr[] = {
 606         { 0x00000001, "NOTIFY" },
 607         { 0x00000002, "COMPUTE_QUERY" },
 608         { 0x00000010, "ILLEGAL_MTHD" },
 609         { 0x00000020, "ILLEGAL_CLASS" },
 610         { 0x00000040, "DOUBLE_NOTIFY" },
 611         { 0x00001000, "CONTEXT_SWITCH" },
 612         { 0x00010000, "BUFFER_NOTIFY" },
 613         { 0x00100000, "DATA_ERROR" },
 614         { 0x00200000, "TRAP" },
 615         { 0x01000000, "SINGLE_STEP" },
 616         {}
 617 };
 618
 619 static void
 620 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 621 {
 622         struct drm_nouveau_private *dev_priv = dev->dev_private;
 623         uint32_t units = nv_rd32(dev, 0x1540);
 624         uint32_t addr, mp10, status, pc, oplow, ophigh;
 625         int i;
 626         int mps = 0;
 627         for (i = 0; i < 4; i++) {
 628                 if (!(units & 1 << (i+24)))
 629                         continue;
 630                 if (dev_priv->chipset < 0xa0)
 631                         addr = 0x408200 + (tpid << 12) + (i << 7);
 632                 else
 633                         addr = 0x408100 + (tpid << 11) + (i << 7);
 634                 mp10 = nv_rd32(dev, addr + 0x10);
 635                 status = nv_rd32(dev, addr + 0x14);
 636                 if (!status)
 637                         continue;
 638                 if (display) {
 639                         nv_rd32(dev, addr + 0x20);
 640                         pc = nv_rd32(dev, addr + 0x24);
 641                         oplow = nv_rd32(dev, addr + 0x70);
 642                         ophigh= nv_rd32(dev, addr + 0x74);
 643                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 644                                         "TP %d MP %d: ", tpid, i);
 645                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 646                         printk(" at %06x warp %d, opcode %08x %08x\n",
 647                                         pc&0xffffff, pc >> 24,
 648                                         oplow, ophigh);
 649                 }
 650                 nv_wr32(dev, addr + 0x10, mp10);
 651                 nv_wr32(dev, addr + 0x14, 0);
 652                 mps++;
 653         }
 654         if (!mps && display)
 655                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 656                                 "No MPs claiming errors?\n", tpid);
 657 }
 658
 659 static void
 660 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 661                 uint32_t ustatus_new, int display, const char *name)
 662 {
 663         struct drm_nouveau_private *dev_priv = dev->dev_private;
 664         int tps = 0;
 665         uint32_t units = nv_rd32(dev, 0x1540);
 666         int i, r;
 667         uint32_t ustatus_addr, ustatus;
 668         for (i = 0; i < 16; i++) {
 669                 if (!(units & (1 << i)))
 670                         continue;
 671                 if (dev_priv->chipset < 0xa0)
 672                         ustatus_addr = ustatus_old + (i << 12);
 673                 else
 674                         ustatus_addr = ustatus_new + (i << 11);
 675                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 676                 if (!ustatus)
 677                         continue;
 678                 tps++;
 679                 switch (type) {
 680                 case 6: /* texture error... unknown for now */
 681                         nv50_fb_vm_trap(dev, display, name);
 682                         if (display) {
 683                                 NV_ERROR(dev, "magic set %d:\n", i);
 684                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 685                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 686                                                 nv_rd32(dev, r));
 687                         }
 688                         break;
 689                 case 7: /* MP error */
 690                         if (ustatus & 0x00010000) {
 691                                 nv50_pgraph_mp_trap(dev, i, display);
 692                                 ustatus &= ~0x00010000;
 693                         }
 694                         break;
 695                 case 8: /* TPDMA error */
 696                         {
 697                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 698                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 699                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 700                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 701                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 702                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 703                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 704                         nv50_fb_vm_trap(dev, display, name);
 705                         /* 2d engine destination */
 706                         if (ustatus & 0x00000010) {
 707                                 if (display) {
 708                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 709                                                         i, e14, e10);
 710                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 711                                                         i, e0c, e18, e1c, e20, e24);
 712                                 }
 713                                 ustatus &= ~0x00000010;
 714                         }
 715                         /* Render target */
 716                         if (ustatus & 0x00000040) {
 717                                 if (display) {
 718                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 719                                                         i, e14, e10);
 720                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 721                                                         i, e0c, e18, e1c, e20, e24);
 722                                 }
 723                                 ustatus &= ~0x00000040;
 724                         }
 725                         /* CUDA memory: l[], g[] or stack. */
 726                         if (ustatus & 0x00000080) {
 727                                 if (display) {
 728                                         if (e18 & 0x80000000) {
 729                                                 /* g[] read fault? */
 730                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 731                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 732                                                 e18 &= ~0x1f000000;
 733                                         } else if (e18 & 0xc) {
 734                                                 /* g[] write fault? */
 735                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 736                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 737                                                 e18 &= ~0x00000f80;
 738                                         } else {
 739                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 740                                                                 i, e14, e10);
 741                                         }
 742                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 743                                                         i, e0c, e18, e1c, e20, e24);
 744                                 }
 745                                 ustatus &= ~0x00000080;
 746                         }
 747                         }
 748                         break;
 749                 }
 750                 if (ustatus) {
 751                         if (display)
 752                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 753                 }
 754                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 755         }
 756
 757         if (!tps && display)
 758                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 759 }
 760
 761 static int
 762 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 763 {
 764         u32 status = nv_rd32(dev, 0x400108);
 765         u32 ustatus;
 766
 767         if (!status && display) {
 768                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 769                 return 1;
 770         }
 771
 772         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 773          * COND, QUERY. If you get a trap from it, the command is still stuck
 774          * in DISPATCH and you need to do something about it. */
 775         if (status & 0x001) {
 776                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 777                 if (!ustatus && display) {
 778                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 779                 }
 780
 781                 nv_wr32(dev, 0x400500, 0x00000000);
 782
 783                 /* Known to be triggered by screwed up NOTIFY and COND... */
 784                 if (ustatus & 0x00000001) {
 785                         u32 addr = nv_rd32(dev, 0x400808);
 786                         u32 subc = (addr & 0x00070000) >> 16;
 787                         u32 mthd = (addr & 0x00001ffc);
 788                         u32 datal = nv_rd32(dev, 0x40080c);
 789                         u32 datah = nv_rd32(dev, 0x400810);
 790                         u32 class = nv_rd32(dev, 0x400814);
 791                         u32 r848 = nv_rd32(dev, 0x400848);
 792
 793                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 794                         if (display && (addr & 0x80000000)) {
 795                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 796                                              "subc %d class 0x%04x mthd 0x%04x "
 797                                              "data 0x%08x%08x "
 798                                              "400808 0x%08x 400848 0x%08x\n",
 799                                         chid, inst, subc, class, mthd, datah,
 800                                         datal, addr, r848);
 801                         } else
 802                         if (display) {
 803                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 804                         }
 805
 806                         nv_wr32(dev, 0x400808, 0);
 807                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 808                         nv_wr32(dev, 0x400848, 0);
 809                         ustatus &= ~0x00000001;
 810                 }
 811
 812                 if (ustatus & 0x00000002) {
 813                         u32 addr = nv_rd32(dev, 0x40084c);
 814                         u32 subc = (addr & 0x00070000) >> 16;
 815                         u32 mthd = (addr & 0x00001ffc);
 816                         u32 data = nv_rd32(dev, 0x40085c);
 817                         u32 class = nv_rd32(dev, 0x400814);
 818
 819                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 820                         if (display && (addr & 0x80000000)) {
 821                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 822                                              "subc %d class 0x%04x mthd 0x%04x "
 823                                              "data 0x%08x 40084c 0x%08x\n",
 824                                         chid, inst, subc, class, mthd,
 825                                         data, addr);
 826                         } else
 827                         if (display) {
 828                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 829                         }
 830
 831                         nv_wr32(dev, 0x40084c, 0);
 832                         ustatus &= ~0x00000002;
 833                 }
 834
 835                 if (ustatus && display) {
 836                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 837                                       "0x%08x)\n", ustatus);
 838                 }
 839
 840                 nv_wr32(dev, 0x400804, 0xc0000000);
 841                 nv_wr32(dev, 0x400108, 0x001);
 842                 status &= ~0x001;
 843                 if (!status)
 844                         return 0;
 845         }
 846
 847         /* M2MF: Memory to memory copy engine. */
 848         if (status & 0x002) {
 849                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 850                 if (display) {
 851                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 852                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 853                         printk("\n");
 854                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 855                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 856                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 857
 858                 }
 859
 860                 /* No sane way found yet -- just reset the bugger. */
 861                 nv_wr32(dev, 0x400040, 2);
 862                 nv_wr32(dev, 0x400040, 0);
 863                 nv_wr32(dev, 0x406800, 0xc0000000);
 864                 nv_wr32(dev, 0x400108, 0x002);
 865                 status &= ~0x002;
 866         }
 867
 868         /* VFETCH: Fetches data from vertex buffers. */
 869         if (status & 0x004) {
 870                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 871                 if (display) {
 872                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 873                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 874                         printk("\n");
 875                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 876                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 877                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 878                 }
 879
 880                 nv_wr32(dev, 0x400c04, 0xc0000000);
 881                 nv_wr32(dev, 0x400108, 0x004);
 882                 status &= ~0x004;
 883         }
 884
 885         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 886         if (status & 0x008) {
 887                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 888                 if (display) {
 889                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 890                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 891                         printk("\n");
 892                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 893                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 894                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 895
 896                 }
 897
 898                 /* No sane way found yet -- just reset the bugger. */
 899                 nv_wr32(dev, 0x400040, 0x80);
 900                 nv_wr32(dev, 0x400040, 0);
 901                 nv_wr32(dev, 0x401800, 0xc0000000);
 902                 nv_wr32(dev, 0x400108, 0x008);
 903                 status &= ~0x008;
 904         }
 905
 906         /* CCACHE: Handles code and c[] caches and fills them. */
 907         if (status & 0x010) {
 908                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 909                 if (display) {
 910                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 911                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 912                         printk("\n");
 913                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 914                                      " %08x %08x %08x\n",
 915                                 nv_rd32(dev, 0x405800), nv_rd32(dev, 0x405804),
 916                                 nv_rd32(dev, 0x405808), nv_rd32(dev, 0x40580c),
 917                                 nv_rd32(dev, 0x405810), nv_rd32(dev, 0x405814),
 918                                 nv_rd32(dev, 0x40581c));
 919
 920                 }
 921
 922                 nv_wr32(dev, 0x405018, 0xc0000000);
 923                 nv_wr32(dev, 0x400108, 0x010);
 924                 status &= ~0x010;
 925         }
 926
 927         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 928          * remaining, so try to handle it anyway. Perhaps related to that
 929          * unknown DMA slot on tesla? */
 930         if (status & 0x20) {
 931                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 932                 if (display)
 933                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 934                 nv_wr32(dev, 0x402000, 0xc0000000);
 935                 /* no status modifiction on purpose */
 936         }
 937
 938         /* TEXTURE: CUDA texturing units */
 939         if (status & 0x040) {
 940                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 941                                     "PGRAPH - TRAP_TEXTURE");
 942                 nv_wr32(dev, 0x400108, 0x040);
 943                 status &= ~0x040;
 944         }
 945
 946         /* MP: CUDA execution engines. */
 947         if (status & 0x080) {
 948                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 949                                     "PGRAPH - TRAP_MP");
 950                 nv_wr32(dev, 0x400108, 0x080);
 951                 status &= ~0x080;
 952         }
 953
 954         /* TPDMA:  Handles TP-initiated uncached memory accesses:
 955          * l[], g[], stack, 2d surfaces, render targets. */
 956         if (status & 0x100) {
 957                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
 958                                     "PGRAPH - TRAP_TPDMA");
 959                 nv_wr32(dev, 0x400108, 0x100);
 960                 status &= ~0x100;
 961         }
 962
 963         if (status) {
 964                 if (display)
 965                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
 966                 nv_wr32(dev, 0x400108, status);
 967         }
 968
 969         return 1;
 970 }
 971
 972 static int
 973 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 974 {
 975         struct drm_nouveau_private *dev_priv = dev->dev_private;
 976         struct nouveau_channel *chan;
 977         unsigned long flags;
 978         int i;
 979
 980         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 981         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 982                 chan = dev_priv->channels.ptr[i];
 983                 if (!chan || !chan->ramin)
 984                         continue;
 985
 986                 if (inst == chan->ramin->vinst)
 987                         break;
 988         }
 989         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 990         return i;
 991 }
 992
 993 static void
 994 nv50_graph_isr(struct drm_device *dev)
 995 {
 996         u32 stat;
 997
 998         while ((stat = nv_rd32(dev, 0x400100))) {
 999                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
1000                 u32 chid = nv50_graph_isr_chid(dev, inst);
1001                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1002                 u32 subc = (addr & 0x00070000) >> 16;
1003                 u32 mthd = (addr & 0x00001ffc);
1004                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1005                 u32 class = nv_rd32(dev, 0x400814);
1006                 u32 show = stat;
1007
1008                 if (stat & 0x00000010) {
1009                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
1010                                                        mthd, data))
1011                                 show &= ~0x00000010;
1012                 }
1013
1014                 if (stat & 0x00001000) {
1015                         nv_wr32(dev, 0x400500, 0x00000000);
1016                         nv_wr32(dev, 0x400100, 0x00001000);
1017                         nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
1018                         nv50_graph_context_switch(dev);
1019                         stat &= ~0x00001000;
1020                         show &= ~0x00001000;
1021                 }
1022
1023                 show = (show && nouveau_ratelimit()) ? show : 0;
1024
1025                 if (show & 0x00100000) {
1026                         u32 ecode = nv_rd32(dev, 0x400110);
1027                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
1028                         nouveau_enum_print(nv50_data_error_names, ecode);
1029                         printk("\n");
1030                 }
1031
1032                 if (stat & 0x00200000) {
1033                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1034                                 show &= ~0x00200000;
1035                 }
1036
1037                 nv_wr32(dev, 0x400100, stat);
1038                 nv_wr32(dev, 0x400500, 0x00010001);
1039
1040                 if (show) {
1041                         NV_INFO(dev, "PGRAPH -");
1042                         nouveau_bitfield_print(nv50_graph_intr, show);
1043                         printk("\n");
1044                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1045                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
1046                                 chid, inst, subc, class, mthd, data);
1047                 }
1048         }
1049
1050         if (nv_rd32(dev, 0x400824) & (1 << 31))
1051                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1052 }