drivers/gpu/drm/nouveau/nv17_tv.c

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_crtc.h"
  33 #include "nouveau_hw.h"
  34 #include "nv17_tv.h"
  35
  36 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
  37 {
  38         struct drm_device *dev = encoder->dev;
  39         struct drm_nouveau_private *dev_priv = dev->dev_private;
  40         uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
  41         uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
  42                 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
  43         uint32_t sample = 0;
  44         int head;
  45
  46 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
  47         testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
  48         if (dev_priv->vbios->tvdactestval)
  49                 testval = dev_priv->vbios->tvdactestval;
  50
  51         dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
  52         head = (dacclk & 0x100) >> 8;
  53
  54         /* Save the previous state. */
  55         gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
  56         gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
  57         fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
  58         fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
  59         fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
  60         fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
  61         test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
  62         ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
  63         ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
  64         ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
  65
  66         /* Prepare the DAC for load detection.  */
  67         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true);
  68         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true);
  69
  70         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
  71         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
  72         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
  73         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
  74                       NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
  75                       NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
  76                       NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
  77                       NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
  78                       NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
  79
  80         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
  81
  82         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  83                       (dacclk & ~0xff) | 0x22);
  84         msleep(1);
  85         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  86                       (dacclk & ~0xff) | 0x21);
  87
  88         NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
  89         NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
  90
  91         /* Sample pin 0x4 (usually S-video luma). */
  92         NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
  93         msleep(20);
  94         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
  95                 & 0x4 << 28;
  96
  97         /* Sample the remaining pins. */
  98         NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
  99         msleep(20);
 100         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
 101                 & 0xa << 28;
 102
 103         /* Restore the previous state. */
 104         NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
 105         NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
 106         NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
 107         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
 108         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
 109         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
 110         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
 111         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
 112         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
 113         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1);
 114         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0);
 115
 116         return sample;
 117 }
 118
 119 static enum drm_connector_status
 120 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 121 {
 122         struct drm_device *dev = encoder->dev;
 123         struct drm_nouveau_private *dev_priv = dev->dev_private;
 124         struct drm_mode_config *conf = &dev->mode_config;
 125         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 126         struct dcb_entry *dcb = tv_enc->base.dcb;
 127
 128         if (dev_priv->chipset == 0x42 ||
 129             dev_priv->chipset == 0x43)
 130                 tv_enc->pin_mask = nv42_tv_sample_load(encoder) >> 28 & 0xe;
 131         else
 132                 tv_enc->pin_mask = nv17_dac_sample_load(encoder) >> 28 & 0xe;
 133
 134         switch (tv_enc->pin_mask) {
 135         case 0x2:
 136         case 0x4:
 137                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
 138                 break;
 139         case 0xc:
 140                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
 141                 break;
 142         case 0xe:
 143                 if (dcb->tvconf.has_component_output)
 144                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
 145                 else
 146                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
 147                 break;
 148         default:
 149                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 150                 break;
 151         }
 152
 153         drm_connector_property_set_value(connector,
 154                                          conf->tv_subconnector_property,
 155                                          tv_enc->subconnector);
 156
 157         if (tv_enc->subconnector) {
 158                 NV_INFO(dev, "Load detected on output %c\n",
 159                         '@' + ffs(dcb->or));
 160                 return connector_status_connected;
 161         } else {
 162                 return connector_status_disconnected;
 163         }
 164 }
 165
 166 static const struct {
 167         int hdisplay;
 168         int vdisplay;
 169 } modes[] = {
 170         { 640, 400 },
 171         { 640, 480 },
 172         { 720, 480 },
 173         { 720, 576 },
 174         { 800, 600 },
 175         { 1024, 768 },
 176         { 1280, 720 },
 177         { 1280, 1024 },
 178         { 1920, 1080 }
 179 };
 180
 181 static int nv17_tv_get_modes(struct drm_encoder *encoder,
 182                              struct drm_connector *connector)
 183 {
 184         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 185         struct drm_display_mode *mode;
 186         struct drm_display_mode *output_mode;
 187         int n = 0;
 188         int i;
 189
 190         if (tv_norm->kind != CTV_ENC_MODE) {
 191                 struct drm_display_mode *tv_mode;
 192
 193                 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
 194                         mode = drm_mode_duplicate(encoder->dev, tv_mode);
 195
 196                         mode->clock = tv_norm->tv_enc_mode.vrefresh *
 197                                                 mode->htotal / 1000 *
 198                                                 mode->vtotal / 1000;
 199
 200                         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 201                                 mode->clock *= 2;
 202
 203                         if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
 204                             mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
 205                                 mode->type |= DRM_MODE_TYPE_PREFERRED;
 206
 207                         drm_mode_probed_add(connector, mode);
 208                         n++;
 209                 }
 210                 return n;
 211         }
 212
 213         /* tv_norm->kind == CTV_ENC_MODE */
 214         output_mode = &tv_norm->ctv_enc_mode.mode;
 215         for (i = 0; i < ARRAY_SIZE(modes); i++) {
 216                 if (modes[i].hdisplay > output_mode->hdisplay ||
 217                     modes[i].vdisplay > output_mode->vdisplay)
 218                         continue;
 219
 220                 if (modes[i].hdisplay == output_mode->hdisplay &&
 221                     modes[i].vdisplay == output_mode->vdisplay) {
 222                         mode = drm_mode_duplicate(encoder->dev, output_mode);
 223                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 224                 } else {
 225                         mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
 226                                 modes[i].vdisplay, 60, false,
 227                                 output_mode->flags & DRM_MODE_FLAG_INTERLACE,
 228                                 false);
 229                 }
 230
 231                 /* CVT modes are sometimes unsuitable... */
 232                 if (output_mode->hdisplay <= 720
 233                     || output_mode->hdisplay >= 1920) {
 234                         mode->htotal = output_mode->htotal;
 235                         mode->hsync_start = (mode->hdisplay + (mode->htotal
 236                                              - mode->hdisplay) * 9 / 10) & ~7;
 237                         mode->hsync_end = mode->hsync_start + 8;
 238                 }
 239                 if (output_mode->vdisplay >= 1024) {
 240                         mode->vtotal = output_mode->vtotal;
 241                         mode->vsync_start = output_mode->vsync_start;
 242                         mode->vsync_end = output_mode->vsync_end;
 243                 }
 244
 245                 mode->type |= DRM_MODE_TYPE_DRIVER;
 246                 drm_mode_probed_add(connector, mode);
 247                 n++;
 248         }
 249         return n;
 250 }
 251
 252 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
 253                               struct drm_display_mode *mode)
 254 {
 255         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 256
 257         if (tv_norm->kind == CTV_ENC_MODE) {
 258                 struct drm_display_mode *output_mode =
 259                                                 &tv_norm->ctv_enc_mode.mode;
 260
 261                 if (mode->clock > 400000)
 262                         return MODE_CLOCK_HIGH;
 263
 264                 if (mode->hdisplay > output_mode->hdisplay ||
 265                     mode->vdisplay > output_mode->vdisplay)
 266                         return MODE_BAD;
 267
 268                 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
 269                     (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
 270                         return MODE_NO_INTERLACE;
 271
 272                 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 273                         return MODE_NO_DBLESCAN;
 274
 275         } else {
 276                 const int vsync_tolerance = 600;
 277
 278                 if (mode->clock > 70000)
 279                         return MODE_CLOCK_HIGH;
 280
 281                 if (abs(drm_mode_vrefresh(mode) * 1000 -
 282                         tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
 283                         return MODE_VSYNC;
 284
 285                 /* The encoder takes care of the actual interlacing */
 286                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 287                         return MODE_NO_INTERLACE;
 288         }
 289
 290         return MODE_OK;
 291 }
 292
 293 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
 294                                struct drm_display_mode *mode,
 295                                struct drm_display_mode *adjusted_mode)
 296 {
 297         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 298
 299         if (tv_norm->kind == CTV_ENC_MODE)
 300                 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
 301         else
 302                 adjusted_mode->clock = 90000;
 303
 304         return true;
 305 }
 306
 307 static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
 308 {
 309         struct drm_device *dev = encoder->dev;
 310         struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
 311         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 312
 313         if (nouveau_encoder(encoder)->last_dpms == mode)
 314                 return;
 315         nouveau_encoder(encoder)->last_dpms = mode;
 316
 317         NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
 318                  mode, nouveau_encoder(encoder)->dcb->index);
 319
 320         regs->ptv_200 &= ~1;
 321
 322         if (tv_norm->kind == CTV_ENC_MODE) {
 323                 nv04_dfp_update_fp_control(encoder, mode);
 324
 325         } else {
 326                 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
 327
 328                 if (mode == DRM_MODE_DPMS_ON)
 329                         regs->ptv_200 |= 1;
 330         }
 331
 332         nv_load_ptv(dev, regs, 200);
 333
 334         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
 335         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
 336
 337         nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
 338 }
 339
 340 static void nv17_tv_prepare(struct drm_encoder *encoder)
 341 {
 342         struct drm_device *dev = encoder->dev;
 343         struct drm_nouveau_private *dev_priv = dev->dev_private;
 344         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 345         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 346         int head = nouveau_crtc(encoder->crtc)->index;
 347         uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
 348                                                         NV_CIO_CRE_LCD__INDEX];
 349         uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
 350                                         nv04_dac_output_offset(encoder);
 351         uint32_t dacclk;
 352
 353         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 354
 355         nv04_dfp_disable(dev, head);
 356
 357         /* Unbind any FP encoders from this head if we need the FP
 358          * stuff enabled. */
 359         if (tv_norm->kind == CTV_ENC_MODE) {
 360                 struct drm_encoder *enc;
 361
 362                 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
 363                         struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
 364
 365                         if ((dcb->type == OUTPUT_TMDS ||
 366                              dcb->type == OUTPUT_LVDS) &&
 367                              !enc->crtc &&
 368                              nv04_dfp_get_bound_head(dev, dcb) == head) {
 369                                 nv04_dfp_bind_head(dev, dcb, head ^ 1,
 370                                                 dev_priv->VBIOS.fp.dual_link);
 371                         }
 372                 }
 373
 374         }
 375
 376         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
 377          * at LCD__INDEX which we don't alter
 378          */
 379         if (!(*cr_lcd & 0x44)) {
 380                 if (tv_norm->kind == CTV_ENC_MODE)
 381                         *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
 382                 else
 383                         *cr_lcd = 0;
 384         }
 385
 386         /* Set the DACCLK register */
 387         dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
 388
 389         if (dev_priv->card_type == NV_40)
 390                 dacclk |= 0x1a << 16;
 391
 392         if (tv_norm->kind == CTV_ENC_MODE) {
 393                 dacclk |=  0x20;
 394
 395                 if (head)
 396                         dacclk |= 0x100;
 397                 else
 398                         dacclk &= ~0x100;
 399
 400         } else {
 401                 dacclk |= 0x10;
 402
 403         }
 404
 405         NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
 406 }
 407
 408 static void nv17_tv_mode_set(struct drm_encoder *encoder,
 409                              struct drm_display_mode *drm_mode,
 410                              struct drm_display_mode *adjusted_mode)
 411 {
 412         struct drm_device *dev = encoder->dev;
 413         struct drm_nouveau_private *dev_priv = dev->dev_private;
 414         int head = nouveau_crtc(encoder->crtc)->index;
 415         struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
 416         struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
 417         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 418         int i;
 419
 420         regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
 421         regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
 422         regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
 423         regs->tv_setup = 1;
 424         regs->ramdac_8c0 = 0x0;
 425
 426         if (tv_norm->kind == TV_ENC_MODE) {
 427                 tv_regs->ptv_200 = 0x13111100;
 428                 if (head)
 429                         tv_regs->ptv_200 |= 0x10;
 430
 431                 tv_regs->ptv_20c = 0x808010;
 432                 tv_regs->ptv_304 = 0x2d00000;
 433                 tv_regs->ptv_600 = 0x0;
 434                 tv_regs->ptv_60c = 0x0;
 435                 tv_regs->ptv_610 = 0x1e00000;
 436
 437                 if (tv_norm->tv_enc_mode.vdisplay == 576) {
 438                         tv_regs->ptv_508 = 0x1200000;
 439                         tv_regs->ptv_614 = 0x33;
 440
 441                 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 442                         tv_regs->ptv_508 = 0xf00000;
 443                         tv_regs->ptv_614 = 0x13;
 444                 }
 445
 446                 if (dev_priv->card_type >= NV_30) {
 447                         tv_regs->ptv_500 = 0xe8e0;
 448                         tv_regs->ptv_504 = 0x1710;
 449                         tv_regs->ptv_604 = 0x0;
 450                         tv_regs->ptv_608 = 0x0;
 451                 } else {
 452                         if (tv_norm->tv_enc_mode.vdisplay == 576) {
 453                                 tv_regs->ptv_604 = 0x20;
 454                                 tv_regs->ptv_608 = 0x10;
 455                                 tv_regs->ptv_500 = 0x19710;
 456                                 tv_regs->ptv_504 = 0x68f0;
 457
 458                         } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 459                                 tv_regs->ptv_604 = 0x10;
 460                                 tv_regs->ptv_608 = 0x20;
 461                                 tv_regs->ptv_500 = 0x4b90;
 462                                 tv_regs->ptv_504 = 0x1b480;
 463                         }
 464                 }
 465
 466                 for (i = 0; i < 0x40; i++)
 467                         tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
 468
 469         } else {
 470                 struct drm_display_mode *output_mode =
 471                                                 &tv_norm->ctv_enc_mode.mode;
 472
 473                 /* The registers in PRAMDAC+0xc00 control some timings and CSC
 474                  * parameters for the CTV encoder (It's only used for "HD" TV
 475                  * modes, I don't think I have enough working to guess what
 476                  * they exactly mean...), it's probably connected at the
 477                  * output of the FP encoder, but it also needs the analog
 478                  * encoder in its OR enabled and routed to the head it's
 479                  * using. It's enabled with the DACCLK register, bits [5:4].
 480                  */
 481                 for (i = 0; i < 38; i++)
 482                         regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
 483
 484                 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 485                 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 486                 regs->fp_horiz_regs[FP_SYNC_START] =
 487                                                 output_mode->hsync_start - 1;
 488                 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 489                 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
 490                         max((output_mode->hdisplay-600)/40 - 1, 1);
 491
 492                 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 493                 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 494                 regs->fp_vert_regs[FP_SYNC_START] =
 495                                                 output_mode->vsync_start - 1;
 496                 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 497                 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
 498
 499                 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 500                         NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
 501                         NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 502
 503                 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 504                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 505                 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 506                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 507
 508                 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 509                         NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 510                         NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 511                         NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 512                         NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 513                         NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 514                         NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 515
 516                 regs->fp_debug_2 = 0;
 517
 518                 regs->fp_margin_color = 0x801080;
 519
 520         }
 521 }
 522
 523 static void nv17_tv_commit(struct drm_encoder *encoder)
 524 {
 525         struct drm_device *dev = encoder->dev;
 526         struct drm_nouveau_private *dev_priv = dev->dev_private;
 527         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 528         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 529         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 530
 531         if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
 532                 nv17_tv_update_rescaler(encoder);
 533                 nv17_tv_update_properties(encoder);
 534         } else {
 535                 nv17_ctv_update_rescaler(encoder);
 536         }
 537
 538         nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
 539
 540         /* This could use refinement for flatpanels, but it should work */
 541         if (dev_priv->chipset < 0x44)
 542                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 543                                         nv04_dac_output_offset(encoder),
 544                                         0xf0000000);
 545         else
 546                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 547                                         nv04_dac_output_offset(encoder),
 548                                         0x00100000);
 549
 550         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 551
 552         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 553                 drm_get_connector_name(
 554                         &nouveau_encoder_connector_get(nv_encoder)->base),
 555                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 556 }
 557
 558 static void nv17_tv_save(struct drm_encoder *encoder)
 559 {
 560         struct drm_device *dev = encoder->dev;
 561         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 562
 563         nouveau_encoder(encoder)->restore.output =
 564                                         NVReadRAMDAC(dev, 0,
 565                                         NV_PRAMDAC_DACCLK +
 566                                         nv04_dac_output_offset(encoder));
 567
 568         nv17_tv_state_save(dev, &tv_enc->saved_state);
 569
 570         tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
 571 }
 572
 573 static void nv17_tv_restore(struct drm_encoder *encoder)
 574 {
 575         struct drm_device *dev = encoder->dev;
 576
 577         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
 578                                 nv04_dac_output_offset(encoder),
 579                                 nouveau_encoder(encoder)->restore.output);
 580
 581         nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
 582 }
 583
 584 static int nv17_tv_create_resources(struct drm_encoder *encoder,
 585                                     struct drm_connector *connector)
 586 {
 587         struct drm_device *dev = encoder->dev;
 588         struct drm_mode_config *conf = &dev->mode_config;
 589         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 590         struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
 591         int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
 592                                                         NUM_LD_TV_NORMS;
 593         int i;
 594
 595         if (nouveau_tv_norm) {
 596                 for (i = 0; i < num_tv_norms; i++) {
 597                         if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
 598                                 tv_enc->tv_norm = i;
 599                                 break;
 600                         }
 601                 }
 602
 603                 if (i == num_tv_norms)
 604                         NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
 605                                 nouveau_tv_norm);
 606         }
 607
 608         drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
 609
 610         drm_connector_attach_property(connector,
 611                                         conf->tv_select_subconnector_property,
 612                                         tv_enc->select_subconnector);
 613         drm_connector_attach_property(connector,
 614                                         conf->tv_subconnector_property,
 615                                         tv_enc->subconnector);
 616         drm_connector_attach_property(connector,
 617                                         conf->tv_mode_property,
 618                                         tv_enc->tv_norm);
 619         drm_connector_attach_property(connector,
 620                                         conf->tv_flicker_reduction_property,
 621                                         tv_enc->flicker);
 622         drm_connector_attach_property(connector,
 623                                         conf->tv_saturation_property,
 624                                         tv_enc->saturation);
 625         drm_connector_attach_property(connector,
 626                                         conf->tv_hue_property,
 627                                         tv_enc->hue);
 628         drm_connector_attach_property(connector,
 629                                         conf->tv_overscan_property,
 630                                         tv_enc->overscan);
 631
 632         return 0;
 633 }
 634
 635 static int nv17_tv_set_property(struct drm_encoder *encoder,
 636                                 struct drm_connector *connector,
 637                                 struct drm_property *property,
 638                                 uint64_t val)
 639 {
 640         struct drm_mode_config *conf = &encoder->dev->mode_config;
 641         struct drm_crtc *crtc = encoder->crtc;
 642         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 643         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 644         bool modes_changed = false;
 645
 646         if (property == conf->tv_overscan_property) {
 647                 tv_enc->overscan = val;
 648                 if (encoder->crtc) {
 649                         if (tv_norm->kind == CTV_ENC_MODE)
 650                                 nv17_ctv_update_rescaler(encoder);
 651                         else
 652                                 nv17_tv_update_rescaler(encoder);
 653                 }
 654
 655         } else if (property == conf->tv_saturation_property) {
 656                 if (tv_norm->kind != TV_ENC_MODE)
 657                         return -EINVAL;
 658
 659                 tv_enc->saturation = val;
 660                 nv17_tv_update_properties(encoder);
 661
 662         } else if (property == conf->tv_hue_property) {
 663                 if (tv_norm->kind != TV_ENC_MODE)
 664                         return -EINVAL;
 665
 666                 tv_enc->hue = val;
 667                 nv17_tv_update_properties(encoder);
 668
 669         } else if (property == conf->tv_flicker_reduction_property) {
 670                 if (tv_norm->kind != TV_ENC_MODE)
 671                         return -EINVAL;
 672
 673                 tv_enc->flicker = val;
 674                 if (encoder->crtc)
 675                         nv17_tv_update_rescaler(encoder);
 676
 677         } else if (property == conf->tv_mode_property) {
 678                 if (connector->dpms != DRM_MODE_DPMS_OFF)
 679                         return -EINVAL;
 680
 681                 tv_enc->tv_norm = val;
 682
 683                 modes_changed = true;
 684
 685         } else if (property == conf->tv_select_subconnector_property) {
 686                 if (tv_norm->kind != TV_ENC_MODE)
 687                         return -EINVAL;
 688
 689                 tv_enc->select_subconnector = val;
 690                 nv17_tv_update_properties(encoder);
 691
 692         } else {
 693                 return -EINVAL;
 694         }
 695
 696         if (modes_changed) {
 697                 drm_helper_probe_single_connector_modes(connector, 0, 0);
 698
 699                 /* Disable the crtc to ensure a full modeset is
 700                  * performed whenever it's turned on again. */
 701                 if (crtc) {
 702                         struct drm_mode_set modeset = {
 703                                 .crtc = crtc,
 704                         };
 705
 706                         crtc->funcs->set_config(&modeset);
 707                 }
 708         }
 709
 710         return 0;
 711 }
 712
 713 static void nv17_tv_destroy(struct drm_encoder *encoder)
 714 {
 715         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 716
 717         NV_DEBUG_KMS(encoder->dev, "\n");
 718
 719         drm_encoder_cleanup(encoder);
 720         kfree(tv_enc);
 721 }
 722
 723 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
 724         .dpms = nv17_tv_dpms,
 725         .save = nv17_tv_save,
 726         .restore = nv17_tv_restore,
 727         .mode_fixup = nv17_tv_mode_fixup,
 728         .prepare = nv17_tv_prepare,
 729         .commit = nv17_tv_commit,
 730         .mode_set = nv17_tv_mode_set,
 731         .detect = nv17_tv_detect,
 732 };
 733
 734 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
 735         .get_modes = nv17_tv_get_modes,
 736         .mode_valid = nv17_tv_mode_valid,
 737         .create_resources = nv17_tv_create_resources,
 738         .set_property = nv17_tv_set_property,
 739 };
 740
 741 static struct drm_encoder_funcs nv17_tv_funcs = {
 742         .destroy = nv17_tv_destroy,
 743 };
 744
 745 int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry)
 746 {
 747         struct drm_encoder *encoder;
 748         struct nv17_tv_encoder *tv_enc = NULL;
 749
 750         tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
 751         if (!tv_enc)
 752                 return -ENOMEM;
 753
 754         tv_enc->overscan = 50;
 755         tv_enc->flicker = 50;
 756         tv_enc->saturation = 50;
 757         tv_enc->hue = 0;
 758         tv_enc->tv_norm = TV_NORM_PAL;
 759         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 760         tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
 761         tv_enc->pin_mask = 0;
 762
 763         encoder = to_drm_encoder(&tv_enc->base);
 764
 765         tv_enc->base.dcb = entry;
 766         tv_enc->base.or = ffs(entry->or) - 1;
 767
 768         drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
 769         drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
 770         to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
 771
 772         encoder->possible_crtcs = entry->heads;
 773         encoder->possible_clones = 0;
 774
 775         return 0;
 776 }