drivers/gpu/drm/nouveau/nv04_instmem.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3 #include "nouveau_drv.h"
   4 #include "nouveau_ramht.h"
   5
   6 /* returns the size of fifo context */
   7 static int
   8 nouveau_fifo_ctx_size(struct drm_device *dev)
   9 {
  10         struct drm_nouveau_private *dev_priv = dev->dev_private;
  11
  12         if (dev_priv->chipset >= 0x40)
  13                 return 128;
  14         else
  15         if (dev_priv->chipset >= 0x17)
  16                 return 64;
  17
  18         return 32;
  19 }
  20
  21 int nv04_instmem_init(struct drm_device *dev)
  22 {
  23         struct drm_nouveau_private *dev_priv = dev->dev_private;
  24         struct nouveau_gpuobj *ramht = NULL;
  25         u32 offset, length;
  26         int ret;
  27
  28         /* RAMIN always available */
  29         dev_priv->ramin_available = true;
  30
  31         /* Setup shared RAMHT */
  32         ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096,
  33                                       NVOBJ_FLAG_ZERO_ALLOC, &ramht);
  34         if (ret)
  35                 return ret;
  36
  37         ret = nouveau_ramht_new(dev, ramht, &dev_priv->ramht);
  38         nouveau_gpuobj_ref(NULL, &ramht);
  39         if (ret)
  40                 return ret;
  41
  42         /* And RAMRO */
  43         ret = nouveau_gpuobj_new_fake(dev, 0x11200, ~0, 512,
  44                                       NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramro);
  45         if (ret)
  46                 return ret;
  47
  48         /* And RAMFC */
  49         length = dev_priv->engine.fifo.channels * nouveau_fifo_ctx_size(dev);
  50         switch (dev_priv->card_type) {
  51         case NV_40:
  52                 offset = 0x20000;
  53                 break;
  54         default:
  55                 offset = 0x11400;
  56                 break;
  57         }
  58
  59         ret = nouveau_gpuobj_new_fake(dev, offset, ~0, length,
  60                                       NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramfc);
  61         if (ret)
  62                 return ret;
  63
  64         /* Only allow space after RAMFC to be used for object allocation */
  65         offset += length;
  66
  67         /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
  68          * on certain NV4x chipsets as well as RAMFC.  When 0x2230 == 0
  69          * ("new style" control) the upper 16-bits of 0x2220 points at this
  70          * other mysterious table that's clobbering important things.
  71          *
  72          * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
  73          * smashed to pieces on us, so reserve 0x30000-0x40000 too..
  74          */
  75         if (dev_priv->card_type >= NV_40) {
  76                 if (offset < 0x40000)
  77                         offset = 0x40000;
  78         }
  79
  80         ret = drm_mm_init(&dev_priv->ramin_heap, offset,
  81                           dev_priv->ramin_rsvd_vram - offset);
  82         if (ret) {
  83                 NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret);
  84                 return ret;
  85         }
  86
  87         return 0;
  88 }
  89
  90 void
  91 nv04_instmem_takedown(struct drm_device *dev)
  92 {
  93         struct drm_nouveau_private *dev_priv = dev->dev_private;
  94
  95         nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);
  96         nouveau_gpuobj_ref(NULL, &dev_priv->ramro);
  97         nouveau_gpuobj_ref(NULL, &dev_priv->ramfc);
  98
  99         if (drm_mm_initialized(&dev_priv->ramin_heap))
 100                 drm_mm_takedown(&dev_priv->ramin_heap);
 101 }
 102
 103 int
 104 nv04_instmem_suspend(struct drm_device *dev)
 105 {
 106         return 0;
 107 }
 108
 109 void
 110 nv04_instmem_resume(struct drm_device *dev)
 111 {
 112 }
 113
 114 int
 115 nv04_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
 116 {
 117         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
 118         struct drm_mm_node *ramin = NULL;
 119
 120         do {
 121                 if (drm_mm_pre_get(&dev_priv->ramin_heap))
 122                         return -ENOMEM;
 123
 124                 spin_lock(&dev_priv->ramin_lock);
 125                 ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0);
 126                 if (ramin == NULL) {
 127                         spin_unlock(&dev_priv->ramin_lock);
 128                         return -ENOMEM;
 129                 }
 130
 131                 ramin = drm_mm_get_block_atomic(ramin, size, align);
 132                 spin_unlock(&dev_priv->ramin_lock);
 133         } while (ramin == NULL);
 134
 135         gpuobj->node  = ramin;
 136         gpuobj->vinst = ramin->start;
 137         return 0;
 138 }
 139
 140 void
 141 nv04_instmem_put(struct nouveau_gpuobj *gpuobj)
 142 {
 143         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
 144
 145         spin_lock(&dev_priv->ramin_lock);
 146         drm_mm_put_block(gpuobj->node);
 147         gpuobj->node = NULL;
 148         spin_unlock(&dev_priv->ramin_lock);
 149 }
 150
 151 int
 152 nv04_instmem_map(struct nouveau_gpuobj *gpuobj)
 153 {
 154         gpuobj->pinst = gpuobj->vinst;
 155         return 0;
 156 }
 157
 158 void
 159 nv04_instmem_unmap(struct nouveau_gpuobj *gpuobj)
 160 {
 161 }
 162
 163 void
 164 nv04_instmem_flush(struct drm_device *dev)
 165 {
 166 }