drivers/gpu/drm/nouveau/nv04_graph.c

   1 /*
   2  * Copyright 2007 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drm.h"
  28 #include "nouveau_drv.h"
  29
  30 static uint32_t nv04_graph_ctx_regs[] = {
  31         0x0040053c,
  32         0x00400544,
  33         0x00400540,
  34         0x00400548,
  35         NV04_PGRAPH_CTX_SWITCH1,
  36         NV04_PGRAPH_CTX_SWITCH2,
  37         NV04_PGRAPH_CTX_SWITCH3,
  38         NV04_PGRAPH_CTX_SWITCH4,
  39         NV04_PGRAPH_CTX_CACHE1,
  40         NV04_PGRAPH_CTX_CACHE2,
  41         NV04_PGRAPH_CTX_CACHE3,
  42         NV04_PGRAPH_CTX_CACHE4,
  43         0x00400184,
  44         0x004001a4,
  45         0x004001c4,
  46         0x004001e4,
  47         0x00400188,
  48         0x004001a8,
  49         0x004001c8,
  50         0x004001e8,
  51         0x0040018c,
  52         0x004001ac,
  53         0x004001cc,
  54         0x004001ec,
  55         0x00400190,
  56         0x004001b0,
  57         0x004001d0,
  58         0x004001f0,
  59         0x00400194,
  60         0x004001b4,
  61         0x004001d4,
  62         0x004001f4,
  63         0x00400198,
  64         0x004001b8,
  65         0x004001d8,
  66         0x004001f8,
  67         0x0040019c,
  68         0x004001bc,
  69         0x004001dc,
  70         0x004001fc,
  71         0x00400174,
  72         NV04_PGRAPH_DMA_START_0,
  73         NV04_PGRAPH_DMA_START_1,
  74         NV04_PGRAPH_DMA_LENGTH,
  75         NV04_PGRAPH_DMA_MISC,
  76         NV04_PGRAPH_DMA_PITCH,
  77         NV04_PGRAPH_BOFFSET0,
  78         NV04_PGRAPH_BBASE0,
  79         NV04_PGRAPH_BLIMIT0,
  80         NV04_PGRAPH_BOFFSET1,
  81         NV04_PGRAPH_BBASE1,
  82         NV04_PGRAPH_BLIMIT1,
  83         NV04_PGRAPH_BOFFSET2,
  84         NV04_PGRAPH_BBASE2,
  85         NV04_PGRAPH_BLIMIT2,
  86         NV04_PGRAPH_BOFFSET3,
  87         NV04_PGRAPH_BBASE3,
  88         NV04_PGRAPH_BLIMIT3,
  89         NV04_PGRAPH_BOFFSET4,
  90         NV04_PGRAPH_BBASE4,
  91         NV04_PGRAPH_BLIMIT4,
  92         NV04_PGRAPH_BOFFSET5,
  93         NV04_PGRAPH_BBASE5,
  94         NV04_PGRAPH_BLIMIT5,
  95         NV04_PGRAPH_BPITCH0,
  96         NV04_PGRAPH_BPITCH1,
  97         NV04_PGRAPH_BPITCH2,
  98         NV04_PGRAPH_BPITCH3,
  99         NV04_PGRAPH_BPITCH4,
 100         NV04_PGRAPH_SURFACE,
 101         NV04_PGRAPH_STATE,
 102         NV04_PGRAPH_BSWIZZLE2,
 103         NV04_PGRAPH_BSWIZZLE5,
 104         NV04_PGRAPH_BPIXEL,
 105         NV04_PGRAPH_NOTIFY,
 106         NV04_PGRAPH_PATT_COLOR0,
 107         NV04_PGRAPH_PATT_COLOR1,
 108         NV04_PGRAPH_PATT_COLORRAM+0x00,
 109         NV04_PGRAPH_PATT_COLORRAM+0x04,
 110         NV04_PGRAPH_PATT_COLORRAM+0x08,
 111         NV04_PGRAPH_PATT_COLORRAM+0x0c,
 112         NV04_PGRAPH_PATT_COLORRAM+0x10,
 113         NV04_PGRAPH_PATT_COLORRAM+0x14,
 114         NV04_PGRAPH_PATT_COLORRAM+0x18,
 115         NV04_PGRAPH_PATT_COLORRAM+0x1c,
 116         NV04_PGRAPH_PATT_COLORRAM+0x20,
 117         NV04_PGRAPH_PATT_COLORRAM+0x24,
 118         NV04_PGRAPH_PATT_COLORRAM+0x28,
 119         NV04_PGRAPH_PATT_COLORRAM+0x2c,
 120         NV04_PGRAPH_PATT_COLORRAM+0x30,
 121         NV04_PGRAPH_PATT_COLORRAM+0x34,
 122         NV04_PGRAPH_PATT_COLORRAM+0x38,
 123         NV04_PGRAPH_PATT_COLORRAM+0x3c,
 124         NV04_PGRAPH_PATT_COLORRAM+0x40,
 125         NV04_PGRAPH_PATT_COLORRAM+0x44,
 126         NV04_PGRAPH_PATT_COLORRAM+0x48,
 127         NV04_PGRAPH_PATT_COLORRAM+0x4c,
 128         NV04_PGRAPH_PATT_COLORRAM+0x50,
 129         NV04_PGRAPH_PATT_COLORRAM+0x54,
 130         NV04_PGRAPH_PATT_COLORRAM+0x58,
 131         NV04_PGRAPH_PATT_COLORRAM+0x5c,
 132         NV04_PGRAPH_PATT_COLORRAM+0x60,
 133         NV04_PGRAPH_PATT_COLORRAM+0x64,
 134         NV04_PGRAPH_PATT_COLORRAM+0x68,
 135         NV04_PGRAPH_PATT_COLORRAM+0x6c,
 136         NV04_PGRAPH_PATT_COLORRAM+0x70,
 137         NV04_PGRAPH_PATT_COLORRAM+0x74,
 138         NV04_PGRAPH_PATT_COLORRAM+0x78,
 139         NV04_PGRAPH_PATT_COLORRAM+0x7c,
 140         NV04_PGRAPH_PATT_COLORRAM+0x80,
 141         NV04_PGRAPH_PATT_COLORRAM+0x84,
 142         NV04_PGRAPH_PATT_COLORRAM+0x88,
 143         NV04_PGRAPH_PATT_COLORRAM+0x8c,
 144         NV04_PGRAPH_PATT_COLORRAM+0x90,
 145         NV04_PGRAPH_PATT_COLORRAM+0x94,
 146         NV04_PGRAPH_PATT_COLORRAM+0x98,
 147         NV04_PGRAPH_PATT_COLORRAM+0x9c,
 148         NV04_PGRAPH_PATT_COLORRAM+0xa0,
 149         NV04_PGRAPH_PATT_COLORRAM+0xa4,
 150         NV04_PGRAPH_PATT_COLORRAM+0xa8,
 151         NV04_PGRAPH_PATT_COLORRAM+0xac,
 152         NV04_PGRAPH_PATT_COLORRAM+0xb0,
 153         NV04_PGRAPH_PATT_COLORRAM+0xb4,
 154         NV04_PGRAPH_PATT_COLORRAM+0xb8,
 155         NV04_PGRAPH_PATT_COLORRAM+0xbc,
 156         NV04_PGRAPH_PATT_COLORRAM+0xc0,
 157         NV04_PGRAPH_PATT_COLORRAM+0xc4,
 158         NV04_PGRAPH_PATT_COLORRAM+0xc8,
 159         NV04_PGRAPH_PATT_COLORRAM+0xcc,
 160         NV04_PGRAPH_PATT_COLORRAM+0xd0,
 161         NV04_PGRAPH_PATT_COLORRAM+0xd4,
 162         NV04_PGRAPH_PATT_COLORRAM+0xd8,
 163         NV04_PGRAPH_PATT_COLORRAM+0xdc,
 164         NV04_PGRAPH_PATT_COLORRAM+0xe0,
 165         NV04_PGRAPH_PATT_COLORRAM+0xe4,
 166         NV04_PGRAPH_PATT_COLORRAM+0xe8,
 167         NV04_PGRAPH_PATT_COLORRAM+0xec,
 168         NV04_PGRAPH_PATT_COLORRAM+0xf0,
 169         NV04_PGRAPH_PATT_COLORRAM+0xf4,
 170         NV04_PGRAPH_PATT_COLORRAM+0xf8,
 171         NV04_PGRAPH_PATT_COLORRAM+0xfc,
 172         NV04_PGRAPH_PATTERN,
 173         0x0040080c,
 174         NV04_PGRAPH_PATTERN_SHAPE,
 175         0x00400600,
 176         NV04_PGRAPH_ROP3,
 177         NV04_PGRAPH_CHROMA,
 178         NV04_PGRAPH_BETA_AND,
 179         NV04_PGRAPH_BETA_PREMULT,
 180         NV04_PGRAPH_CONTROL0,
 181         NV04_PGRAPH_CONTROL1,
 182         NV04_PGRAPH_CONTROL2,
 183         NV04_PGRAPH_BLEND,
 184         NV04_PGRAPH_STORED_FMT,
 185         NV04_PGRAPH_SOURCE_COLOR,
 186         0x00400560,
 187         0x00400568,
 188         0x00400564,
 189         0x0040056c,
 190         0x00400400,
 191         0x00400480,
 192         0x00400404,
 193         0x00400484,
 194         0x00400408,
 195         0x00400488,
 196         0x0040040c,
 197         0x0040048c,
 198         0x00400410,
 199         0x00400490,
 200         0x00400414,
 201         0x00400494,
 202         0x00400418,
 203         0x00400498,
 204         0x0040041c,
 205         0x0040049c,
 206         0x00400420,
 207         0x004004a0,
 208         0x00400424,
 209         0x004004a4,
 210         0x00400428,
 211         0x004004a8,
 212         0x0040042c,
 213         0x004004ac,
 214         0x00400430,
 215         0x004004b0,
 216         0x00400434,
 217         0x004004b4,
 218         0x00400438,
 219         0x004004b8,
 220         0x0040043c,
 221         0x004004bc,
 222         0x00400440,
 223         0x004004c0,
 224         0x00400444,
 225         0x004004c4,
 226         0x00400448,
 227         0x004004c8,
 228         0x0040044c,
 229         0x004004cc,
 230         0x00400450,
 231         0x004004d0,
 232         0x00400454,
 233         0x004004d4,
 234         0x00400458,
 235         0x004004d8,
 236         0x0040045c,
 237         0x004004dc,
 238         0x00400460,
 239         0x004004e0,
 240         0x00400464,
 241         0x004004e4,
 242         0x00400468,
 243         0x004004e8,
 244         0x0040046c,
 245         0x004004ec,
 246         0x00400470,
 247         0x004004f0,
 248         0x00400474,
 249         0x004004f4,
 250         0x00400478,
 251         0x004004f8,
 252         0x0040047c,
 253         0x004004fc,
 254         0x00400534,
 255         0x00400538,
 256         0x00400514,
 257         0x00400518,
 258         0x0040051c,
 259         0x00400520,
 260         0x00400524,
 261         0x00400528,
 262         0x0040052c,
 263         0x00400530,
 264         0x00400d00,
 265         0x00400d40,
 266         0x00400d80,
 267         0x00400d04,
 268         0x00400d44,
 269         0x00400d84,
 270         0x00400d08,
 271         0x00400d48,
 272         0x00400d88,
 273         0x00400d0c,
 274         0x00400d4c,
 275         0x00400d8c,
 276         0x00400d10,
 277         0x00400d50,
 278         0x00400d90,
 279         0x00400d14,
 280         0x00400d54,
 281         0x00400d94,
 282         0x00400d18,
 283         0x00400d58,
 284         0x00400d98,
 285         0x00400d1c,
 286         0x00400d5c,
 287         0x00400d9c,
 288         0x00400d20,
 289         0x00400d60,
 290         0x00400da0,
 291         0x00400d24,
 292         0x00400d64,
 293         0x00400da4,
 294         0x00400d28,
 295         0x00400d68,
 296         0x00400da8,
 297         0x00400d2c,
 298         0x00400d6c,
 299         0x00400dac,
 300         0x00400d30,
 301         0x00400d70,
 302         0x00400db0,
 303         0x00400d34,
 304         0x00400d74,
 305         0x00400db4,
 306         0x00400d38,
 307         0x00400d78,
 308         0x00400db8,
 309         0x00400d3c,
 310         0x00400d7c,
 311         0x00400dbc,
 312         0x00400590,
 313         0x00400594,
 314         0x00400598,
 315         0x0040059c,
 316         0x004005a8,
 317         0x004005ac,
 318         0x004005b0,
 319         0x004005b4,
 320         0x004005c0,
 321         0x004005c4,
 322         0x004005c8,
 323         0x004005cc,
 324         0x004005d0,
 325         0x004005d4,
 326         0x004005d8,
 327         0x004005dc,
 328         0x004005e0,
 329         NV04_PGRAPH_PASSTHRU_0,
 330         NV04_PGRAPH_PASSTHRU_1,
 331         NV04_PGRAPH_PASSTHRU_2,
 332         NV04_PGRAPH_DVD_COLORFMT,
 333         NV04_PGRAPH_SCALED_FORMAT,
 334         NV04_PGRAPH_MISC24_0,
 335         NV04_PGRAPH_MISC24_1,
 336         NV04_PGRAPH_MISC24_2,
 337         0x00400500,
 338         0x00400504,
 339         NV04_PGRAPH_VALID1,
 340         NV04_PGRAPH_VALID2,
 341         NV04_PGRAPH_DEBUG_3
 342 };
 343
 344 struct graph_state {
 345         int nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
 346 };
 347
 348 struct nouveau_channel *
 349 nv04_graph_channel(struct drm_device *dev)
 350 {
 351         struct drm_nouveau_private *dev_priv = dev->dev_private;
 352         int chid = dev_priv->engine.fifo.channels;
 353
 354         if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000)
 355                 chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24;
 356
 357         if (chid >= dev_priv->engine.fifo.channels)
 358                 return NULL;
 359
 360         return dev_priv->fifos[chid];
 361 }
 362
 363 void
 364 nv04_graph_context_switch(struct drm_device *dev)
 365 {
 366         struct drm_nouveau_private *dev_priv = dev->dev_private;
 367         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 368         struct nouveau_channel *chan = NULL;
 369         int chid;
 370
 371         pgraph->fifo_access(dev, false);
 372         nouveau_wait_for_idle(dev);
 373
 374         /* If previous context is valid, we need to save it */
 375         pgraph->unload_context(dev);
 376
 377         /* Load context for next channel */
 378         chid = dev_priv->engine.fifo.channel_id(dev);
 379         chan = dev_priv->fifos[chid];
 380         if (chan)
 381                 nv04_graph_load_context(chan);
 382
 383         pgraph->fifo_access(dev, true);
 384 }
 385
 386 static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
 387 {
 388         int i;
 389
 390         for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
 391                 if (nv04_graph_ctx_regs[i] == reg)
 392                         return &ctx->nv04[i];
 393         }
 394
 395         return NULL;
 396 }
 397
 398 int nv04_graph_create_context(struct nouveau_channel *chan)
 399 {
 400         struct graph_state *pgraph_ctx;
 401         NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
 402
 403         chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
 404                                                 GFP_KERNEL);
 405         if (pgraph_ctx == NULL)
 406                 return -ENOMEM;
 407
 408         *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
 409
 410         return 0;
 411 }
 412
 413 void nv04_graph_destroy_context(struct nouveau_channel *chan)
 414 {
 415         struct graph_state *pgraph_ctx = chan->pgraph_ctx;
 416
 417         kfree(pgraph_ctx);
 418         chan->pgraph_ctx = NULL;
 419 }
 420
 421 int nv04_graph_load_context(struct nouveau_channel *chan)
 422 {
 423         struct drm_device *dev = chan->dev;
 424         struct graph_state *pgraph_ctx = chan->pgraph_ctx;
 425         uint32_t tmp;
 426         int i;
 427
 428         for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
 429                 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
 430
 431         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
 432
 433         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
 434         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
 435
 436         tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
 437         nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
 438
 439         return 0;
 440 }
 441
 442 int
 443 nv04_graph_unload_context(struct drm_device *dev)
 444 {
 445         struct drm_nouveau_private *dev_priv = dev->dev_private;
 446         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 447         struct nouveau_channel *chan = NULL;
 448         struct graph_state *ctx;
 449         uint32_t tmp;
 450         int i;
 451
 452         chan = pgraph->channel(dev);
 453         if (!chan)
 454                 return 0;
 455         ctx = chan->pgraph_ctx;
 456
 457         for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
 458                 ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
 459
 460         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
 461         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
 462         tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
 463         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
 464         return 0;
 465 }
 466
 467 int nv04_graph_init(struct drm_device *dev)
 468 {
 469         struct drm_nouveau_private *dev_priv = dev->dev_private;
 470         uint32_t tmp;
 471
 472         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 473                         ~NV_PMC_ENABLE_PGRAPH);
 474         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 475                          NV_PMC_ENABLE_PGRAPH);
 476
 477         /* Enable PGRAPH interrupts */
 478         nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
 479         nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 480
 481         nv_wr32(dev, NV04_PGRAPH_VALID1, 0);
 482         nv_wr32(dev, NV04_PGRAPH_VALID2, 0);
 483         /*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF);
 484         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
 485         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
 486         /*1231C000 blob, 001 haiku*/
 487         //*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
 488         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
 489         /*0x72111100 blob , 01 haiku*/
 490         /*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
 491         nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
 492         /*haiku same*/
 493
 494         /*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
 495         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
 496         /*haiku and blob 10d4*/
 497
 498         nv_wr32(dev, NV04_PGRAPH_STATE        , 0xFFFFFFFF);
 499         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL  , 0x10000100);
 500         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
 501         tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
 502         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
 503
 504         /* These don't belong here, they're part of a per-channel context */
 505         nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
 506         nv_wr32(dev, NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
 507
 508         return 0;
 509 }
 510
 511 void nv04_graph_takedown(struct drm_device *dev)
 512 {
 513 }
 514
 515 void
 516 nv04_graph_fifo_access(struct drm_device *dev, bool enabled)
 517 {
 518         if (enabled)
 519                 nv_wr32(dev, NV04_PGRAPH_FIFO,
 520                                         nv_rd32(dev, NV04_PGRAPH_FIFO) | 1);
 521         else
 522                 nv_wr32(dev, NV04_PGRAPH_FIFO,
 523                                         nv_rd32(dev, NV04_PGRAPH_FIFO) & ~1);
 524 }
 525
 526 static int
 527 nv04_graph_mthd_set_ref(struct nouveau_channel *chan, int grclass,
 528                         int mthd, uint32_t data)
 529 {
 530         chan->fence.last_sequence_irq = data;
 531         nouveau_fence_handler(chan->dev, chan->id);
 532         return 0;
 533 }
 534
 535 /*
 536  * Software methods, why they are needed, and how they all work:
 537  *
 538  * NV04 and NV05 keep most of the state in PGRAPH context itself, but some
 539  * 2d engine settings are kept inside the grobjs themselves. The grobjs are
 540  * 3 words long on both. grobj format on NV04 is:
 541  *
 542  * word 0:
 543  *  - bits 0-7: class
 544  *  - bit 12: color key active
 545  *  - bit 13: clip rect active
 546  *  - bit 14: if set, destination surface is swizzled and taken from buffer 5
 547  *            [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
 548  *            from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
 549  *            NV03_CONTEXT_SURFACE_DST].
 550  *  - bits 15-17: 2d operation [aka patch config]
 551  *  - bit 24: patch valid [enables rendering using this object]
 552  *  - bit 25: surf3d valid [for tex_tri and multitex_tri only]
 553  * word 1:
 554  *  - bits 0-1: mono format
 555  *  - bits 8-13: color format
 556  *  - bits 16-31: DMA_NOTIFY instance
 557  * word 2:
 558  *  - bits 0-15: DMA_A instance
 559  *  - bits 16-31: DMA_B instance
 560  *
 561  * On NV05 it's:
 562  *
 563  * word 0:
 564  *  - bits 0-7: class
 565  *  - bit 12: color key active
 566  *  - bit 13: clip rect active
 567  *  - bit 14: if set, destination surface is swizzled and taken from buffer 5
 568  *            [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
 569  *            from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
 570  *            NV03_CONTEXT_SURFACE_DST].
 571  *  - bits 15-17: 2d operation [aka patch config]
 572  *  - bits 20-22: dither mode
 573  *  - bit 24: patch valid [enables rendering using this object]
 574  *  - bit 25: surface_dst/surface_color/surf2d/surf3d valid
 575  *  - bit 26: surface_src/surface_zeta valid
 576  *  - bit 27: pattern valid
 577  *  - bit 28: rop valid
 578  *  - bit 29: beta1 valid
 579  *  - bit 30: beta4 valid
 580  * word 1:
 581  *  - bits 0-1: mono format
 582  *  - bits 8-13: color format
 583  *  - bits 16-31: DMA_NOTIFY instance
 584  * word 2:
 585  *  - bits 0-15: DMA_A instance
 586  *  - bits 16-31: DMA_B instance
 587  *
 588  * NV05 will set/unset the relevant valid bits when you poke the relevant
 589  * object-binding methods with object of the proper type, or with the NULL
 590  * type. It'll only allow rendering using the grobj if all needed objects
 591  * are bound. The needed set of objects depends on selected operation: for
 592  * example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
 593  *
 594  * NV04 doesn't have these methods implemented at all, and doesn't have the
 595  * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
 596  * is set. So we have to emulate them in software, internally keeping the
 597  * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
 598  * but the last word isn't actually used for anything, we abuse it for this
 599  * purpose.
 600  *
 601  * Actually, NV05 can optionally check bit 24 too, but we disable this since
 602  * there's no use for it.
 603  *
 604  * For unknown reasons, NV04 implements surf3d binding in hardware as an
 605  * exception. Also for unknown reasons, NV04 doesn't implement the clipping
 606  * methods on the surf3d object, so we have to emulate them too.
 607  */
 608
 609 static void
 610 nv04_graph_set_ctx1(struct nouveau_channel *chan, uint32_t mask, uint32_t value)
 611 {
 612         struct drm_device *dev = chan->dev;
 613         uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
 614         int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
 615         uint32_t tmp;
 616
 617         tmp  = nv_ri32(dev, instance);
 618         tmp &= ~mask;
 619         tmp |= value;
 620
 621         nv_wi32(dev, instance, tmp);
 622         nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
 623         nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
 624 }
 625
 626 static void
 627 nv04_graph_set_ctx_val(struct nouveau_channel *chan, uint32_t mask, uint32_t value)
 628 {
 629         struct drm_device *dev = chan->dev;
 630         uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
 631         uint32_t tmp, ctx1;
 632         int class, op, valid = 1;
 633
 634         ctx1 = nv_ri32(dev, instance);
 635         class = ctx1 & 0xff;
 636         op = (ctx1 >> 15) & 7;
 637         tmp  = nv_ri32(dev, instance + 0xc);
 638         tmp &= ~mask;
 639         tmp |= value;
 640         nv_wi32(dev, instance + 0xc, tmp);
 641
 642         /* check for valid surf2d/surf_dst/surf_color */
 643         if (!(tmp & 0x02000000))
 644                 valid = 0;
 645         /* check for valid surf_src/surf_zeta */
 646         if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
 647                 valid = 0;
 648
 649         switch (op) {
 650         /* SRCCOPY_AND, SRCCOPY: no extra objects required */
 651         case 0:
 652         case 3:
 653                 break;
 654         /* ROP_AND: requires pattern and rop */
 655         case 1:
 656                 if (!(tmp & 0x18000000))
 657                         valid = 0;
 658                 break;
 659         /* BLEND_AND: requires beta1 */
 660         case 2:
 661                 if (!(tmp & 0x20000000))
 662                         valid = 0;
 663                 break;
 664         /* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
 665         case 4:
 666         case 5:
 667                 if (!(tmp & 0x40000000))
 668                         valid = 0;
 669                 break;
 670         }
 671
 672         nv04_graph_set_ctx1(chan, 0x01000000, valid << 24);
 673 }
 674
 675 static int
 676 nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
 677                               int mthd, uint32_t data)
 678 {
 679         if (data > 5)
 680                 return 1;
 681         /* Old versions of the objects only accept first three operations. */
 682         if (data > 2 && grclass < 0x40)
 683                 return 1;
 684         nv04_graph_set_ctx1(chan, 0x00038000, data << 15);
 685         /* changing operation changes set of objects needed for validation */
 686         nv04_graph_set_ctx_val(chan, 0, 0);
 687         return 0;
 688 }
 689
 690 static int
 691 nv04_graph_mthd_surf3d_clip_h(struct nouveau_channel *chan, int grclass,
 692                               int mthd, uint32_t data)
 693 {
 694         uint32_t min = data & 0xffff, max;
 695         uint32_t w = data >> 16;
 696         if (min & 0x8000)
 697                 /* too large */
 698                 return 1;
 699         if (w & 0x8000)
 700                 /* yes, it accepts negative for some reason. */
 701                 w |= 0xffff0000;
 702         max = min + w;
 703         max &= 0x3ffff;
 704         nv_wr32(chan->dev, 0x40053c, min);
 705         nv_wr32(chan->dev, 0x400544, max);
 706         return 0;
 707 }
 708
 709 static int
 710 nv04_graph_mthd_surf3d_clip_v(struct nouveau_channel *chan, int grclass,
 711                               int mthd, uint32_t data)
 712 {
 713         uint32_t min = data & 0xffff, max;
 714         uint32_t w = data >> 16;
 715         if (min & 0x8000)
 716                 /* too large */
 717                 return 1;
 718         if (w & 0x8000)
 719                 /* yes, it accepts negative for some reason. */
 720                 w |= 0xffff0000;
 721         max = min + w;
 722         max &= 0x3ffff;
 723         nv_wr32(chan->dev, 0x400540, min);
 724         nv_wr32(chan->dev, 0x400548, max);
 725         return 0;
 726 }
 727
 728 static int
 729 nv04_graph_mthd_bind_surf2d(struct nouveau_channel *chan, int grclass,
 730                               int mthd, uint32_t data)
 731 {
 732         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 733         case 0x30:
 734                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 735                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 736                 return 0;
 737         case 0x42:
 738                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 739                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 740                 return 0;
 741         }
 742         return 1;
 743 }
 744
 745 static int
 746 nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_channel *chan, int grclass,
 747                               int mthd, uint32_t data)
 748 {
 749         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 750         case 0x30:
 751                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 752                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 753                 return 0;
 754         case 0x42:
 755                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 756                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 757                 return 0;
 758         case 0x52:
 759                 nv04_graph_set_ctx1(chan, 0x00004000, 0x00004000);
 760                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 761                 return 0;
 762         }
 763         return 1;
 764 }
 765
 766 static int
 767 nv04_graph_mthd_bind_nv01_patt(struct nouveau_channel *chan, int grclass,
 768                               int mthd, uint32_t data)
 769 {
 770         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 771         case 0x30:
 772                 nv04_graph_set_ctx_val(chan, 0x08000000, 0);
 773                 return 0;
 774         case 0x18:
 775                 nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
 776                 return 0;
 777         }
 778         return 1;
 779 }
 780
 781 static int
 782 nv04_graph_mthd_bind_nv04_patt(struct nouveau_channel *chan, int grclass,
 783                               int mthd, uint32_t data)
 784 {
 785         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 786         case 0x30:
 787                 nv04_graph_set_ctx_val(chan, 0x08000000, 0);
 788                 return 0;
 789         case 0x44:
 790                 nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
 791                 return 0;
 792         }
 793         return 1;
 794 }
 795
 796 static int
 797 nv04_graph_mthd_bind_rop(struct nouveau_channel *chan, int grclass,
 798                               int mthd, uint32_t data)
 799 {
 800         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 801         case 0x30:
 802                 nv04_graph_set_ctx_val(chan, 0x10000000, 0);
 803                 return 0;
 804         case 0x43:
 805                 nv04_graph_set_ctx_val(chan, 0x10000000, 0x10000000);
 806                 return 0;
 807         }
 808         return 1;
 809 }
 810
 811 static int
 812 nv04_graph_mthd_bind_beta1(struct nouveau_channel *chan, int grclass,
 813                               int mthd, uint32_t data)
 814 {
 815         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 816         case 0x30:
 817                 nv04_graph_set_ctx_val(chan, 0x20000000, 0);
 818                 return 0;
 819         case 0x12:
 820                 nv04_graph_set_ctx_val(chan, 0x20000000, 0x20000000);
 821                 return 0;
 822         }
 823         return 1;
 824 }
 825
 826 static int
 827 nv04_graph_mthd_bind_beta4(struct nouveau_channel *chan, int grclass,
 828                               int mthd, uint32_t data)
 829 {
 830         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 831         case 0x30:
 832                 nv04_graph_set_ctx_val(chan, 0x40000000, 0);
 833                 return 0;
 834         case 0x72:
 835                 nv04_graph_set_ctx_val(chan, 0x40000000, 0x40000000);
 836                 return 0;
 837         }
 838         return 1;
 839 }
 840
 841 static int
 842 nv04_graph_mthd_bind_surf_dst(struct nouveau_channel *chan, int grclass,
 843                               int mthd, uint32_t data)
 844 {
 845         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 846         case 0x30:
 847                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 848                 return 0;
 849         case 0x58:
 850                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 851                 return 0;
 852         }
 853         return 1;
 854 }
 855
 856 static int
 857 nv04_graph_mthd_bind_surf_src(struct nouveau_channel *chan, int grclass,
 858                               int mthd, uint32_t data)
 859 {
 860         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 861         case 0x30:
 862                 nv04_graph_set_ctx_val(chan, 0x04000000, 0);
 863                 return 0;
 864         case 0x59:
 865                 nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
 866                 return 0;
 867         }
 868         return 1;
 869 }
 870
 871 static int
 872 nv04_graph_mthd_bind_surf_color(struct nouveau_channel *chan, int grclass,
 873                               int mthd, uint32_t data)
 874 {
 875         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 876         case 0x30:
 877                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 878                 return 0;
 879         case 0x5a:
 880                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 881                 return 0;
 882         }
 883         return 1;
 884 }
 885
 886 static int
 887 nv04_graph_mthd_bind_surf_zeta(struct nouveau_channel *chan, int grclass,
 888                               int mthd, uint32_t data)
 889 {
 890         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 891         case 0x30:
 892                 nv04_graph_set_ctx_val(chan, 0x04000000, 0);
 893                 return 0;
 894         case 0x5b:
 895                 nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
 896                 return 0;
 897         }
 898         return 1;
 899 }
 900
 901 static int
 902 nv04_graph_mthd_bind_clip(struct nouveau_channel *chan, int grclass,
 903                               int mthd, uint32_t data)
 904 {
 905         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 906         case 0x30:
 907                 nv04_graph_set_ctx1(chan, 0x2000, 0);
 908                 return 0;
 909         case 0x19:
 910                 nv04_graph_set_ctx1(chan, 0x2000, 0x2000);
 911                 return 0;
 912         }
 913         return 1;
 914 }
 915
 916 static int
 917 nv04_graph_mthd_bind_chroma(struct nouveau_channel *chan, int grclass,
 918                               int mthd, uint32_t data)
 919 {
 920         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 921         case 0x30:
 922                 nv04_graph_set_ctx1(chan, 0x1000, 0);
 923                 return 0;
 924         /* Yes, for some reason even the old versions of objects
 925          * accept 0x57 and not 0x17. Consistency be damned.
 926          */
 927         case 0x57:
 928                 nv04_graph_set_ctx1(chan, 0x1000, 0x1000);
 929                 return 0;
 930         }
 931         return 1;
 932 }
 933
 934 static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
 935         { 0x0150, nv04_graph_mthd_set_ref },
 936         {}
 937 };
 938
 939 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_gdirect[] = {
 940         { 0x0184, nv04_graph_mthd_bind_nv01_patt },
 941         { 0x0188, nv04_graph_mthd_bind_rop },
 942         { 0x018c, nv04_graph_mthd_bind_beta1 },
 943         { 0x0190, nv04_graph_mthd_bind_surf_dst },
 944         { 0x02fc, nv04_graph_mthd_set_operation },
 945         {},
 946 };
 947
 948 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_gdirect[] = {
 949         { 0x0188, nv04_graph_mthd_bind_nv04_patt },
 950         { 0x018c, nv04_graph_mthd_bind_rop },
 951         { 0x0190, nv04_graph_mthd_bind_beta1 },
 952         { 0x0194, nv04_graph_mthd_bind_beta4 },
 953         { 0x0198, nv04_graph_mthd_bind_surf2d },
 954         { 0x02fc, nv04_graph_mthd_set_operation },
 955         {},
 956 };
 957
 958 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv01_imageblit[] = {
 959         { 0x0184, nv04_graph_mthd_bind_chroma },
 960         { 0x0188, nv04_graph_mthd_bind_clip },
 961         { 0x018c, nv04_graph_mthd_bind_nv01_patt },
 962         { 0x0190, nv04_graph_mthd_bind_rop },
 963         { 0x0194, nv04_graph_mthd_bind_beta1 },
 964         { 0x0198, nv04_graph_mthd_bind_surf_dst },
 965         { 0x019c, nv04_graph_mthd_bind_surf_src },
 966         { 0x02fc, nv04_graph_mthd_set_operation },
 967         {},
 968 };
 969
 970 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_imageblit_ifc[] = {
 971         { 0x0184, nv04_graph_mthd_bind_chroma },
 972         { 0x0188, nv04_graph_mthd_bind_clip },
 973         { 0x018c, nv04_graph_mthd_bind_nv04_patt },
 974         { 0x0190, nv04_graph_mthd_bind_rop },
 975         { 0x0194, nv04_graph_mthd_bind_beta1 },
 976         { 0x0198, nv04_graph_mthd_bind_beta4 },
 977         { 0x019c, nv04_graph_mthd_bind_surf2d },
 978         { 0x02fc, nv04_graph_mthd_set_operation },
 979         {},
 980 };
 981
 982 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_iifc[] = {
 983         { 0x0188, nv04_graph_mthd_bind_chroma },
 984         { 0x018c, nv04_graph_mthd_bind_clip },
 985         { 0x0190, nv04_graph_mthd_bind_nv04_patt },
 986         { 0x0194, nv04_graph_mthd_bind_rop },
 987         { 0x0198, nv04_graph_mthd_bind_beta1 },
 988         { 0x019c, nv04_graph_mthd_bind_beta4 },
 989         { 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
 990         { 0x03e4, nv04_graph_mthd_set_operation },
 991         {},
 992 };
 993
 994 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv01_ifc[] = {
 995         { 0x0184, nv04_graph_mthd_bind_chroma },
 996         { 0x0188, nv04_graph_mthd_bind_clip },
 997         { 0x018c, nv04_graph_mthd_bind_nv01_patt },
 998         { 0x0190, nv04_graph_mthd_bind_rop },
 999         { 0x0194, nv04_graph_mthd_bind_beta1 },
1000         { 0x0198, nv04_graph_mthd_bind_surf_dst },
1001         { 0x02fc, nv04_graph_mthd_set_operation },
1002         {},
1003 };
1004
1005 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_sifc[] = {
1006         { 0x0184, nv04_graph_mthd_bind_chroma },
1007         { 0x0188, nv04_graph_mthd_bind_nv01_patt },
1008         { 0x018c, nv04_graph_mthd_bind_rop },
1009         { 0x0190, nv04_graph_mthd_bind_beta1 },
1010         { 0x0194, nv04_graph_mthd_bind_surf_dst },
1011         { 0x02fc, nv04_graph_mthd_set_operation },
1012         {},
1013 };
1014
1015 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_sifc[] = {
1016         { 0x0184, nv04_graph_mthd_bind_chroma },
1017         { 0x0188, nv04_graph_mthd_bind_nv04_patt },
1018         { 0x018c, nv04_graph_mthd_bind_rop },
1019         { 0x0190, nv04_graph_mthd_bind_beta1 },
1020         { 0x0194, nv04_graph_mthd_bind_beta4 },
1021         { 0x0198, nv04_graph_mthd_bind_surf2d },
1022         { 0x02fc, nv04_graph_mthd_set_operation },
1023         {},
1024 };
1025
1026 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_sifm[] = {
1027         { 0x0188, nv04_graph_mthd_bind_nv01_patt },
1028         { 0x018c, nv04_graph_mthd_bind_rop },
1029         { 0x0190, nv04_graph_mthd_bind_beta1 },
1030         { 0x0194, nv04_graph_mthd_bind_surf_dst },
1031         { 0x0304, nv04_graph_mthd_set_operation },
1032         {},
1033 };
1034
1035 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_sifm[] = {
1036         { 0x0188, nv04_graph_mthd_bind_nv04_patt },
1037         { 0x018c, nv04_graph_mthd_bind_rop },
1038         { 0x0190, nv04_graph_mthd_bind_beta1 },
1039         { 0x0194, nv04_graph_mthd_bind_beta4 },
1040         { 0x0198, nv04_graph_mthd_bind_surf2d_swzsurf },
1041         { 0x0304, nv04_graph_mthd_set_operation },
1042         {},
1043 };
1044
1045 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv01_shape[] = {
1046         { 0x0184, nv04_graph_mthd_bind_clip },
1047         { 0x0188, nv04_graph_mthd_bind_nv01_patt },
1048         { 0x018c, nv04_graph_mthd_bind_rop },
1049         { 0x0190, nv04_graph_mthd_bind_beta1 },
1050         { 0x0194, nv04_graph_mthd_bind_surf_dst },
1051         { 0x02fc, nv04_graph_mthd_set_operation },
1052         {},
1053 };
1054
1055 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_shape[] = {
1056         { 0x0184, nv04_graph_mthd_bind_clip },
1057         { 0x0188, nv04_graph_mthd_bind_nv04_patt },
1058         { 0x018c, nv04_graph_mthd_bind_rop },
1059         { 0x0190, nv04_graph_mthd_bind_beta1 },
1060         { 0x0194, nv04_graph_mthd_bind_beta4 },
1061         { 0x0198, nv04_graph_mthd_bind_surf2d },
1062         { 0x02fc, nv04_graph_mthd_set_operation },
1063         {},
1064 };
1065
1066 static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_tex_tri[] = {
1067         { 0x0188, nv04_graph_mthd_bind_clip },
1068         { 0x018c, nv04_graph_mthd_bind_surf_color },
1069         { 0x0190, nv04_graph_mthd_bind_surf_zeta },
1070         {},
1071 };
1072
1073 static struct nouveau_pgraph_object_method nv04_graph_mthds_surf3d[] = {
1074         { 0x02f8, nv04_graph_mthd_surf3d_clip_h },
1075         { 0x02fc, nv04_graph_mthd_surf3d_clip_v },
1076         {},
1077 };
1078
1079 struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
1080         { 0x0038, false, NULL }, /* dvd subpicture */
1081         { 0x0039, false, NULL }, /* m2mf */
1082         { 0x004b, false, nv04_graph_mthds_nv03_gdirect }, /* nv03 gdirect */
1083         { 0x004a, false, nv04_graph_mthds_nv04_gdirect }, /* nv04 gdirect */
1084         { 0x001f, false, nv04_graph_mthds_nv01_imageblit }, /* nv01 imageblit */
1085         { 0x005f, false, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 imageblit */
1086         { 0x0060, false, nv04_graph_mthds_nv04_iifc }, /* nv04 iifc */
1087         { 0x0064, false, NULL }, /* nv05 iifc */
1088         { 0x0021, false, nv04_graph_mthds_nv01_ifc }, /* nv01 ifc */
1089         { 0x0061, false, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 ifc */
1090         { 0x0065, false, NULL }, /* nv05 ifc */
1091         { 0x0036, false, nv04_graph_mthds_nv03_sifc }, /* nv03 sifc */
1092         { 0x0076, false, nv04_graph_mthds_nv04_sifc }, /* nv04 sifc */
1093         { 0x0066, false, NULL }, /* nv05 sifc */
1094         { 0x0037, false, nv04_graph_mthds_nv03_sifm }, /* nv03 sifm */
1095         { 0x0077, false, nv04_graph_mthds_nv04_sifm }, /* nv04 sifm */
1096         { 0x0030, false, NULL }, /* null */
1097         { 0x0042, false, NULL }, /* surf2d */
1098         { 0x0043, false, NULL }, /* rop */
1099         { 0x0012, false, NULL }, /* beta1 */
1100         { 0x0072, false, NULL }, /* beta4 */
1101         { 0x0019, false, NULL }, /* cliprect */
1102         { 0x0018, false, NULL }, /* nv01 pattern */
1103         { 0x0044, false, NULL }, /* nv04 pattern */
1104         { 0x0052, false, NULL }, /* swzsurf */
1105         { 0x0053, false, nv04_graph_mthds_surf3d }, /* surf3d */
1106         { 0x0048, false, nv04_graph_mthds_nv03_tex_tri }, /* nv03 tex_tri */
1107         { 0x0054, false, NULL }, /* tex_tri */
1108         { 0x0055, false, NULL }, /* multitex_tri */
1109         { 0x0017, false, NULL }, /* nv01 chroma */
1110         { 0x0057, false, NULL }, /* nv04 chroma */
1111         { 0x0058, false, NULL }, /* surf_dst */
1112         { 0x0059, false, NULL }, /* surf_src */
1113         { 0x005a, false, NULL }, /* surf_color */
1114         { 0x005b, false, NULL }, /* surf_zeta */
1115         { 0x001c, false, nv04_graph_mthds_nv01_shape }, /* nv01 line */
1116         { 0x005c, false, nv04_graph_mthds_nv04_shape }, /* nv04 line */
1117         { 0x001d, false, nv04_graph_mthds_nv01_shape }, /* nv01 tri */
1118         { 0x005d, false, nv04_graph_mthds_nv04_shape }, /* nv04 tri */
1119         { 0x001e, false, nv04_graph_mthds_nv01_shape }, /* nv01 rect */
1120         { 0x005e, false, nv04_graph_mthds_nv04_shape }, /* nv04 rect */
1121         { 0x506e, true, nv04_graph_mthds_sw },
1122         {}
1123 };
1124