drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nv50_display.h"
  38
  39 static void nouveau_stub_takedown(struct drm_device *dev) {}
  40
  41 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  42 {
  43         struct drm_nouveau_private *dev_priv = dev->dev_private;
  44         struct nouveau_engine *engine = &dev_priv->engine;
  45
  46         switch (dev_priv->chipset & 0xf0) {
  47         case 0x00:
  48                 engine->instmem.init            = nv04_instmem_init;
  49                 engine->instmem.takedown        = nv04_instmem_takedown;
  50                 engine->instmem.suspend         = nv04_instmem_suspend;
  51                 engine->instmem.resume          = nv04_instmem_resume;
  52                 engine->instmem.populate        = nv04_instmem_populate;
  53                 engine->instmem.clear           = nv04_instmem_clear;
  54                 engine->instmem.bind            = nv04_instmem_bind;
  55                 engine->instmem.unbind          = nv04_instmem_unbind;
  56                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  57                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  58                 engine->mc.init                 = nv04_mc_init;
  59                 engine->mc.takedown             = nv04_mc_takedown;
  60                 engine->timer.init              = nv04_timer_init;
  61                 engine->timer.read              = nv04_timer_read;
  62                 engine->timer.takedown          = nv04_timer_takedown;
  63                 engine->fb.init                 = nv04_fb_init;
  64                 engine->fb.takedown             = nv04_fb_takedown;
  65                 engine->graph.grclass           = nv04_graph_grclass;
  66                 engine->graph.init              = nv04_graph_init;
  67                 engine->graph.takedown          = nv04_graph_takedown;
  68                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  69                 engine->graph.channel           = nv04_graph_channel;
  70                 engine->graph.create_context    = nv04_graph_create_context;
  71                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  72                 engine->graph.load_context      = nv04_graph_load_context;
  73                 engine->graph.unload_context    = nv04_graph_unload_context;
  74                 engine->fifo.channels           = 16;
  75                 engine->fifo.init               = nv04_fifo_init;
  76                 engine->fifo.takedown           = nouveau_stub_takedown;
  77                 engine->fifo.disable            = nv04_fifo_disable;
  78                 engine->fifo.enable             = nv04_fifo_enable;
  79                 engine->fifo.reassign           = nv04_fifo_reassign;
  80                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
  81                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  82                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  83                 engine->fifo.create_context     = nv04_fifo_create_context;
  84                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  85                 engine->fifo.load_context       = nv04_fifo_load_context;
  86                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  87                 break;
  88         case 0x10:
  89                 engine->instmem.init            = nv04_instmem_init;
  90                 engine->instmem.takedown        = nv04_instmem_takedown;
  91                 engine->instmem.suspend         = nv04_instmem_suspend;
  92                 engine->instmem.resume          = nv04_instmem_resume;
  93                 engine->instmem.populate        = nv04_instmem_populate;
  94                 engine->instmem.clear           = nv04_instmem_clear;
  95                 engine->instmem.bind            = nv04_instmem_bind;
  96                 engine->instmem.unbind          = nv04_instmem_unbind;
  97                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  98                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  99                 engine->mc.init                 = nv04_mc_init;
 100                 engine->mc.takedown             = nv04_mc_takedown;
 101                 engine->timer.init              = nv04_timer_init;
 102                 engine->timer.read              = nv04_timer_read;
 103                 engine->timer.takedown          = nv04_timer_takedown;
 104                 engine->fb.init                 = nv10_fb_init;
 105                 engine->fb.takedown             = nv10_fb_takedown;
 106                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 107                 engine->graph.grclass           = nv10_graph_grclass;
 108                 engine->graph.init              = nv10_graph_init;
 109                 engine->graph.takedown          = nv10_graph_takedown;
 110                 engine->graph.channel           = nv10_graph_channel;
 111                 engine->graph.create_context    = nv10_graph_create_context;
 112                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 113                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 114                 engine->graph.load_context      = nv10_graph_load_context;
 115                 engine->graph.unload_context    = nv10_graph_unload_context;
 116                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 117                 engine->fifo.channels           = 32;
 118                 engine->fifo.init               = nv10_fifo_init;
 119                 engine->fifo.takedown           = nouveau_stub_takedown;
 120                 engine->fifo.disable            = nv04_fifo_disable;
 121                 engine->fifo.enable             = nv04_fifo_enable;
 122                 engine->fifo.reassign           = nv04_fifo_reassign;
 123                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 124                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 125                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 126                 engine->fifo.create_context     = nv10_fifo_create_context;
 127                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 128                 engine->fifo.load_context       = nv10_fifo_load_context;
 129                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 130                 break;
 131         case 0x20:
 132                 engine->instmem.init            = nv04_instmem_init;
 133                 engine->instmem.takedown        = nv04_instmem_takedown;
 134                 engine->instmem.suspend         = nv04_instmem_suspend;
 135                 engine->instmem.resume          = nv04_instmem_resume;
 136                 engine->instmem.populate        = nv04_instmem_populate;
 137                 engine->instmem.clear           = nv04_instmem_clear;
 138                 engine->instmem.bind            = nv04_instmem_bind;
 139                 engine->instmem.unbind          = nv04_instmem_unbind;
 140                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 141                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 142                 engine->mc.init                 = nv04_mc_init;
 143                 engine->mc.takedown             = nv04_mc_takedown;
 144                 engine->timer.init              = nv04_timer_init;
 145                 engine->timer.read              = nv04_timer_read;
 146                 engine->timer.takedown          = nv04_timer_takedown;
 147                 engine->fb.init                 = nv10_fb_init;
 148                 engine->fb.takedown             = nv10_fb_takedown;
 149                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 150                 engine->graph.grclass           = nv20_graph_grclass;
 151                 engine->graph.init              = nv20_graph_init;
 152                 engine->graph.takedown          = nv20_graph_takedown;
 153                 engine->graph.channel           = nv10_graph_channel;
 154                 engine->graph.create_context    = nv20_graph_create_context;
 155                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 156                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 157                 engine->graph.load_context      = nv20_graph_load_context;
 158                 engine->graph.unload_context    = nv20_graph_unload_context;
 159                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 160                 engine->fifo.channels           = 32;
 161                 engine->fifo.init               = nv10_fifo_init;
 162                 engine->fifo.takedown           = nouveau_stub_takedown;
 163                 engine->fifo.disable            = nv04_fifo_disable;
 164                 engine->fifo.enable             = nv04_fifo_enable;
 165                 engine->fifo.reassign           = nv04_fifo_reassign;
 166                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 167                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 168                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 169                 engine->fifo.create_context     = nv10_fifo_create_context;
 170                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 171                 engine->fifo.load_context       = nv10_fifo_load_context;
 172                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 173                 break;
 174         case 0x30:
 175                 engine->instmem.init            = nv04_instmem_init;
 176                 engine->instmem.takedown        = nv04_instmem_takedown;
 177                 engine->instmem.suspend         = nv04_instmem_suspend;
 178                 engine->instmem.resume          = nv04_instmem_resume;
 179                 engine->instmem.populate        = nv04_instmem_populate;
 180                 engine->instmem.clear           = nv04_instmem_clear;
 181                 engine->instmem.bind            = nv04_instmem_bind;
 182                 engine->instmem.unbind          = nv04_instmem_unbind;
 183                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 184                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 185                 engine->mc.init                 = nv04_mc_init;
 186                 engine->mc.takedown             = nv04_mc_takedown;
 187                 engine->timer.init              = nv04_timer_init;
 188                 engine->timer.read              = nv04_timer_read;
 189                 engine->timer.takedown          = nv04_timer_takedown;
 190                 engine->fb.init                 = nv10_fb_init;
 191                 engine->fb.takedown             = nv10_fb_takedown;
 192                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 193                 engine->graph.grclass           = nv30_graph_grclass;
 194                 engine->graph.init              = nv30_graph_init;
 195                 engine->graph.takedown          = nv20_graph_takedown;
 196                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 197                 engine->graph.channel           = nv10_graph_channel;
 198                 engine->graph.create_context    = nv20_graph_create_context;
 199                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 200                 engine->graph.load_context      = nv20_graph_load_context;
 201                 engine->graph.unload_context    = nv20_graph_unload_context;
 202                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 203                 engine->fifo.channels           = 32;
 204                 engine->fifo.init               = nv10_fifo_init;
 205                 engine->fifo.takedown           = nouveau_stub_takedown;
 206                 engine->fifo.disable            = nv04_fifo_disable;
 207                 engine->fifo.enable             = nv04_fifo_enable;
 208                 engine->fifo.reassign           = nv04_fifo_reassign;
 209                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 210                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 211                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 212                 engine->fifo.create_context     = nv10_fifo_create_context;
 213                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 214                 engine->fifo.load_context       = nv10_fifo_load_context;
 215                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 216                 break;
 217         case 0x40:
 218         case 0x60:
 219                 engine->instmem.init            = nv04_instmem_init;
 220                 engine->instmem.takedown        = nv04_instmem_takedown;
 221                 engine->instmem.suspend         = nv04_instmem_suspend;
 222                 engine->instmem.resume          = nv04_instmem_resume;
 223                 engine->instmem.populate        = nv04_instmem_populate;
 224                 engine->instmem.clear           = nv04_instmem_clear;
 225                 engine->instmem.bind            = nv04_instmem_bind;
 226                 engine->instmem.unbind          = nv04_instmem_unbind;
 227                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 228                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 229                 engine->mc.init                 = nv40_mc_init;
 230                 engine->mc.takedown             = nv40_mc_takedown;
 231                 engine->timer.init              = nv04_timer_init;
 232                 engine->timer.read              = nv04_timer_read;
 233                 engine->timer.takedown          = nv04_timer_takedown;
 234                 engine->fb.init                 = nv40_fb_init;
 235                 engine->fb.takedown             = nv40_fb_takedown;
 236                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 237                 engine->graph.grclass           = nv40_graph_grclass;
 238                 engine->graph.init              = nv40_graph_init;
 239                 engine->graph.takedown          = nv40_graph_takedown;
 240                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 241                 engine->graph.channel           = nv40_graph_channel;
 242                 engine->graph.create_context    = nv40_graph_create_context;
 243                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 244                 engine->graph.load_context      = nv40_graph_load_context;
 245                 engine->graph.unload_context    = nv40_graph_unload_context;
 246                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 247                 engine->fifo.channels           = 32;
 248                 engine->fifo.init               = nv40_fifo_init;
 249                 engine->fifo.takedown           = nouveau_stub_takedown;
 250                 engine->fifo.disable            = nv04_fifo_disable;
 251                 engine->fifo.enable             = nv04_fifo_enable;
 252                 engine->fifo.reassign           = nv04_fifo_reassign;
 253                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 254                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 255                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 256                 engine->fifo.create_context     = nv40_fifo_create_context;
 257                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 258                 engine->fifo.load_context       = nv40_fifo_load_context;
 259                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 260                 break;
 261         case 0x50:
 262         case 0x80: /* gotta love NVIDIA's consistency.. */
 263         case 0x90:
 264         case 0xA0:
 265                 engine->instmem.init            = nv50_instmem_init;
 266                 engine->instmem.takedown        = nv50_instmem_takedown;
 267                 engine->instmem.suspend         = nv50_instmem_suspend;
 268                 engine->instmem.resume          = nv50_instmem_resume;
 269                 engine->instmem.populate        = nv50_instmem_populate;
 270                 engine->instmem.clear           = nv50_instmem_clear;
 271                 engine->instmem.bind            = nv50_instmem_bind;
 272                 engine->instmem.unbind          = nv50_instmem_unbind;
 273                 engine->instmem.prepare_access  = nv50_instmem_prepare_access;
 274                 engine->instmem.finish_access   = nv50_instmem_finish_access;
 275                 engine->mc.init                 = nv50_mc_init;
 276                 engine->mc.takedown             = nv50_mc_takedown;
 277                 engine->timer.init              = nv04_timer_init;
 278                 engine->timer.read              = nv04_timer_read;
 279                 engine->timer.takedown          = nv04_timer_takedown;
 280                 engine->fb.init                 = nv50_fb_init;
 281                 engine->fb.takedown             = nv50_fb_takedown;
 282                 engine->graph.grclass           = nv50_graph_grclass;
 283                 engine->graph.init              = nv50_graph_init;
 284                 engine->graph.takedown          = nv50_graph_takedown;
 285                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 286                 engine->graph.channel           = nv50_graph_channel;
 287                 engine->graph.create_context    = nv50_graph_create_context;
 288                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 289                 engine->graph.load_context      = nv50_graph_load_context;
 290                 engine->graph.unload_context    = nv50_graph_unload_context;
 291                 engine->fifo.channels           = 128;
 292                 engine->fifo.init               = nv50_fifo_init;
 293                 engine->fifo.takedown           = nv50_fifo_takedown;
 294                 engine->fifo.disable            = nv04_fifo_disable;
 295                 engine->fifo.enable             = nv04_fifo_enable;
 296                 engine->fifo.reassign           = nv04_fifo_reassign;
 297                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 298                 engine->fifo.create_context     = nv50_fifo_create_context;
 299                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 300                 engine->fifo.load_context       = nv50_fifo_load_context;
 301                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 302                 break;
 303         default:
 304                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 305                 return 1;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static unsigned int
 312 nouveau_vga_set_decode(void *priv, bool state)
 313 {
 314         struct drm_device *dev = priv;
 315         struct drm_nouveau_private *dev_priv = dev->dev_private;
 316
 317         if (dev_priv->chipset >= 0x40)
 318                 nv_wr32(dev, 0x88054, state);
 319         else
 320                 nv_wr32(dev, 0x1854, state);
 321
 322         if (state)
 323                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 324                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 325         else
 326                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 327 }
 328
 329 static int
 330 nouveau_card_init_channel(struct drm_device *dev)
 331 {
 332         struct drm_nouveau_private *dev_priv = dev->dev_private;
 333         struct nouveau_gpuobj *gpuobj;
 334         int ret;
 335
 336         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 337                                     (struct drm_file *)-2,
 338                                     NvDmaFB, NvDmaTT);
 339         if (ret)
 340                 return ret;
 341
 342         gpuobj = NULL;
 343         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 344                                      0, dev_priv->vram_size,
 345                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 346                                      &gpuobj);
 347         if (ret)
 348                 goto out_err;
 349
 350         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
 351                                      gpuobj, NULL);
 352         if (ret)
 353                 goto out_err;
 354
 355         gpuobj = NULL;
 356         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 357                                           dev_priv->gart_info.aper_size,
 358                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 359         if (ret)
 360                 goto out_err;
 361
 362         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
 363                                      gpuobj, NULL);
 364         if (ret)
 365                 goto out_err;
 366
 367         return 0;
 368 out_err:
 369         nouveau_gpuobj_del(dev, &gpuobj);
 370         nouveau_channel_free(dev_priv->channel);
 371         dev_priv->channel = NULL;
 372         return ret;
 373 }
 374
 375 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 376                                          enum vga_switcheroo_state state)
 377 {
 378         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 379         if (state == VGA_SWITCHEROO_ON) {
 380                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 381                 nouveau_pci_resume(pdev);
 382         } else {
 383                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 384                 nouveau_pci_suspend(pdev, pmm);
 385         }
 386 }
 387
 388 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 389 {
 390         struct drm_device *dev = pci_get_drvdata(pdev);
 391         bool can_switch;
 392
 393         spin_lock(&dev->count_lock);
 394         can_switch = (dev->open_count == 0);
 395         spin_unlock(&dev->count_lock);
 396         return can_switch;
 397 }
 398
 399 int
 400 nouveau_card_init(struct drm_device *dev)
 401 {
 402         struct drm_nouveau_private *dev_priv = dev->dev_private;
 403         struct nouveau_engine *engine;
 404         int ret;
 405
 406         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 407
 408         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
 409                 return 0;
 410
 411         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 412         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 413                                        nouveau_switcheroo_can_switch);
 414
 415         /* Initialise internal driver API hooks */
 416         ret = nouveau_init_engine_ptrs(dev);
 417         if (ret)
 418                 goto out;
 419         engine = &dev_priv->engine;
 420         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 421         spin_lock_init(&dev_priv->context_switch_lock);
 422
 423         /* Parse BIOS tables / Run init tables if card not POSTed */
 424         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 425                 ret = nouveau_bios_init(dev);
 426                 if (ret)
 427                         goto out;
 428         }
 429
 430         ret = nouveau_mem_detect(dev);
 431         if (ret)
 432                 goto out_bios;
 433
 434         ret = nouveau_gpuobj_early_init(dev);
 435         if (ret)
 436                 goto out_bios;
 437
 438         /* Initialise instance memory, must happen before mem_init so we
 439          * know exactly how much VRAM we're able to use for "normal"
 440          * purposes.
 441          */
 442         ret = engine->instmem.init(dev);
 443         if (ret)
 444                 goto out_gpuobj_early;
 445
 446         /* Setup the memory manager */
 447         ret = nouveau_mem_init(dev);
 448         if (ret)
 449                 goto out_instmem;
 450
 451         ret = nouveau_gpuobj_init(dev);
 452         if (ret)
 453                 goto out_mem;
 454
 455         /* PMC */
 456         ret = engine->mc.init(dev);
 457         if (ret)
 458                 goto out_gpuobj;
 459
 460         /* PTIMER */
 461         ret = engine->timer.init(dev);
 462         if (ret)
 463                 goto out_mc;
 464
 465         /* PFB */
 466         ret = engine->fb.init(dev);
 467         if (ret)
 468                 goto out_timer;
 469
 470         if (nouveau_noaccel)
 471                 engine->graph.accel_blocked = true;
 472         else {
 473                 /* PGRAPH */
 474                 ret = engine->graph.init(dev);
 475                 if (ret)
 476                         goto out_fb;
 477
 478                 /* PFIFO */
 479                 ret = engine->fifo.init(dev);
 480                 if (ret)
 481                         goto out_graph;
 482         }
 483
 484         /* this call irq_preinstall, register irq handler and
 485          * call irq_postinstall
 486          */
 487         ret = drm_irq_install(dev);
 488         if (ret)
 489                 goto out_fifo;
 490
 491         ret = drm_vblank_init(dev, 0);
 492         if (ret)
 493                 goto out_irq;
 494
 495         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 496
 497         if (!engine->graph.accel_blocked) {
 498                 ret = nouveau_card_init_channel(dev);
 499                 if (ret)
 500                         goto out_irq;
 501         }
 502
 503         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 504                 if (dev_priv->card_type >= NV_50)
 505                         ret = nv50_display_create(dev);
 506                 else
 507                         ret = nv04_display_create(dev);
 508                 if (ret)
 509                         goto out_channel;
 510         }
 511
 512         ret = nouveau_backlight_init(dev);
 513         if (ret)
 514                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 515
 516         dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
 517
 518         if (drm_core_check_feature(dev, DRIVER_MODESET))
 519                 drm_helper_initial_config(dev);
 520
 521         return 0;
 522
 523 out_channel:
 524         if (dev_priv->channel) {
 525                 nouveau_channel_free(dev_priv->channel);
 526                 dev_priv->channel = NULL;
 527         }
 528 out_irq:
 529         drm_irq_uninstall(dev);
 530 out_fifo:
 531         if (!nouveau_noaccel)
 532                 engine->fifo.takedown(dev);
 533 out_graph:
 534         if (!nouveau_noaccel)
 535                 engine->graph.takedown(dev);
 536 out_fb:
 537         engine->fb.takedown(dev);
 538 out_timer:
 539         engine->timer.takedown(dev);
 540 out_mc:
 541         engine->mc.takedown(dev);
 542 out_gpuobj:
 543         nouveau_gpuobj_takedown(dev);
 544 out_mem:
 545         nouveau_sgdma_takedown(dev);
 546         nouveau_mem_close(dev);
 547 out_instmem:
 548         engine->instmem.takedown(dev);
 549 out_gpuobj_early:
 550         nouveau_gpuobj_late_takedown(dev);
 551 out_bios:
 552         nouveau_bios_takedown(dev);
 553 out:
 554         vga_client_register(dev->pdev, NULL, NULL, NULL);
 555         return ret;
 556 }
 557
 558 static void nouveau_card_takedown(struct drm_device *dev)
 559 {
 560         struct drm_nouveau_private *dev_priv = dev->dev_private;
 561         struct nouveau_engine *engine = &dev_priv->engine;
 562
 563         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 564
 565         if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
 566                 nouveau_backlight_exit(dev);
 567
 568                 if (dev_priv->channel) {
 569                         nouveau_channel_free(dev_priv->channel);
 570                         dev_priv->channel = NULL;
 571                 }
 572
 573                 if (!nouveau_noaccel) {
 574                         engine->fifo.takedown(dev);
 575                         engine->graph.takedown(dev);
 576                 }
 577                 engine->fb.takedown(dev);
 578                 engine->timer.takedown(dev);
 579                 engine->mc.takedown(dev);
 580
 581                 mutex_lock(&dev->struct_mutex);
 582                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 583                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 584                 mutex_unlock(&dev->struct_mutex);
 585                 nouveau_sgdma_takedown(dev);
 586
 587                 nouveau_gpuobj_takedown(dev);
 588                 nouveau_mem_close(dev);
 589                 engine->instmem.takedown(dev);
 590
 591                 if (drm_core_check_feature(dev, DRIVER_MODESET))
 592                         drm_irq_uninstall(dev);
 593
 594                 nouveau_gpuobj_late_takedown(dev);
 595                 nouveau_bios_takedown(dev);
 596
 597                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 598
 599                 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 600         }
 601 }
 602
 603 /* here a client dies, release the stuff that was allocated for its
 604  * file_priv */
 605 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 606 {
 607         nouveau_channel_cleanup(dev, file_priv);
 608 }
 609
 610 /* first module load, setup the mmio/fb mapping */
 611 /* KMS: we need mmio at load time, not when the first drm client opens. */
 612 int nouveau_firstopen(struct drm_device *dev)
 613 {
 614         return 0;
 615 }
 616
 617 /* if we have an OF card, copy vbios to RAMIN */
 618 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 619 {
 620 #if defined(__powerpc__)
 621         int size, i;
 622         const uint32_t *bios;
 623         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 624         if (!dn) {
 625                 NV_INFO(dev, "Unable to get the OF node\n");
 626                 return;
 627         }
 628
 629         bios = of_get_property(dn, "NVDA,BMP", &size);
 630         if (bios) {
 631                 for (i = 0; i < size; i += 4)
 632                         nv_wi32(dev, i, bios[i/4]);
 633                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 634         } else {
 635                 NV_INFO(dev, "Unable to get the OF bios\n");
 636         }
 637 #endif
 638 }
 639
 640 int nouveau_load(struct drm_device *dev, unsigned long flags)
 641 {
 642         struct drm_nouveau_private *dev_priv;
 643         uint32_t reg0;
 644         resource_size_t mmio_start_offs;
 645
 646         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 647         if (!dev_priv)
 648                 return -ENOMEM;
 649         dev->dev_private = dev_priv;
 650         dev_priv->dev = dev;
 651
 652         dev_priv->flags = flags & NOUVEAU_FLAGS;
 653         dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 654
 655         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 656                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 657
 658         dev_priv->wq = create_workqueue("nouveau");
 659         if (!dev_priv->wq)
 660                 return -EINVAL;
 661
 662         /* resource 0 is mmio regs */
 663         /* resource 1 is linear FB */
 664         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 665         /* resource 6 is bios */
 666
 667         /* map the mmio regs */
 668         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 669         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 670         if (!dev_priv->mmio) {
 671                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 672                          "Please report your setup to " DRIVER_EMAIL "\n");
 673                 return -EINVAL;
 674         }
 675         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 676                                         (unsigned long long)mmio_start_offs);
 677
 678 #ifdef __BIG_ENDIAN
 679         /* Put the card in BE mode if it's not */
 680         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 681                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 682
 683         DRM_MEMORYBARRIER();
 684 #endif
 685
 686         /* Time to determine the card architecture */
 687         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 688
 689         /* We're dealing with >=NV10 */
 690         if ((reg0 & 0x0f000000) > 0) {
 691                 /* Bit 27-20 contain the architecture in hex */
 692                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 693         /* NV04 or NV05 */
 694         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 695                 if (reg0 & 0x00f00000)
 696                         dev_priv->chipset = 0x05;
 697                 else
 698                         dev_priv->chipset = 0x04;
 699         } else
 700                 dev_priv->chipset = 0xff;
 701
 702         switch (dev_priv->chipset & 0xf0) {
 703         case 0x00:
 704         case 0x10:
 705         case 0x20:
 706         case 0x30:
 707                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 708                 break;
 709         case 0x40:
 710         case 0x60:
 711                 dev_priv->card_type = NV_40;
 712                 break;
 713         case 0x50:
 714         case 0x80:
 715         case 0x90:
 716         case 0xa0:
 717                 dev_priv->card_type = NV_50;
 718                 break;
 719         default:
 720                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 721                 return -EINVAL;
 722         }
 723
 724         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 725                 dev_priv->card_type, reg0);
 726
 727         /* map larger RAMIN aperture on NV40 cards */
 728         dev_priv->ramin  = NULL;
 729         if (dev_priv->card_type >= NV_40) {
 730                 int ramin_bar = 2;
 731                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 732                         ramin_bar = 3;
 733
 734                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 735                 dev_priv->ramin = ioremap(
 736                                 pci_resource_start(dev->pdev, ramin_bar),
 737                                 dev_priv->ramin_size);
 738                 if (!dev_priv->ramin) {
 739                         NV_ERROR(dev, "Failed to init RAMIN mapping, "
 740                                       "limited instance memory available\n");
 741                 }
 742         }
 743
 744         /* On older cards (or if the above failed), create a map covering
 745          * the BAR0 PRAMIN aperture */
 746         if (!dev_priv->ramin) {
 747                 dev_priv->ramin_size = 1 * 1024 * 1024;
 748                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 749                                                         dev_priv->ramin_size);
 750                 if (!dev_priv->ramin) {
 751                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 752                         return -ENOMEM;
 753                 }
 754         }
 755
 756         nouveau_OF_copy_vbios_to_ramin(dev);
 757
 758         /* Special flags */
 759         if (dev->pci_device == 0x01a0)
 760                 dev_priv->flags |= NV_NFORCE;
 761         else if (dev->pci_device == 0x01f0)
 762                 dev_priv->flags |= NV_NFORCE2;
 763
 764         /* For kernel modesetting, init card now and bring up fbcon */
 765         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 766                 int ret = nouveau_card_init(dev);
 767                 if (ret)
 768                         return ret;
 769         }
 770
 771         return 0;
 772 }
 773
 774 static void nouveau_close(struct drm_device *dev)
 775 {
 776         struct drm_nouveau_private *dev_priv = dev->dev_private;
 777
 778         /* In the case of an error dev_priv may not be allocated yet */
 779         if (dev_priv)
 780                 nouveau_card_takedown(dev);
 781 }
 782
 783 /* KMS: we need mmio at load time, not when the first drm client opens. */
 784 void nouveau_lastclose(struct drm_device *dev)
 785 {
 786         if (drm_core_check_feature(dev, DRIVER_MODESET))
 787                 return;
 788
 789         nouveau_close(dev);
 790 }
 791
 792 int nouveau_unload(struct drm_device *dev)
 793 {
 794         struct drm_nouveau_private *dev_priv = dev->dev_private;
 795
 796         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 797                 if (dev_priv->card_type >= NV_50)
 798                         nv50_display_destroy(dev);
 799                 else
 800                         nv04_display_destroy(dev);
 801                 nouveau_close(dev);
 802         }
 803
 804         iounmap(dev_priv->mmio);
 805         iounmap(dev_priv->ramin);
 806
 807         kfree(dev_priv);
 808         dev->dev_private = NULL;
 809         return 0;
 810 }
 811
 812 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 813                                                 struct drm_file *file_priv)
 814 {
 815         struct drm_nouveau_private *dev_priv = dev->dev_private;
 816         struct drm_nouveau_getparam *getparam = data;
 817
 818         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 819
 820         switch (getparam->param) {
 821         case NOUVEAU_GETPARAM_CHIPSET_ID:
 822                 getparam->value = dev_priv->chipset;
 823                 break;
 824         case NOUVEAU_GETPARAM_PCI_VENDOR:
 825                 getparam->value = dev->pci_vendor;
 826                 break;
 827         case NOUVEAU_GETPARAM_PCI_DEVICE:
 828                 getparam->value = dev->pci_device;
 829                 break;
 830         case NOUVEAU_GETPARAM_BUS_TYPE:
 831                 if (drm_device_is_agp(dev))
 832                         getparam->value = NV_AGP;
 833                 else if (drm_device_is_pcie(dev))
 834                         getparam->value = NV_PCIE;
 835                 else
 836                         getparam->value = NV_PCI;
 837                 break;
 838         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 839                 getparam->value = dev_priv->fb_phys;
 840                 break;
 841         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 842                 getparam->value = dev_priv->gart_info.aper_base;
 843                 break;
 844         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
 845                 if (dev->sg) {
 846                         getparam->value = (unsigned long)dev->sg->virtual;
 847                 } else {
 848                         NV_ERROR(dev, "Requested PCIGART address, "
 849                                         "while no PCIGART was created\n");
 850                         return -EINVAL;
 851                 }
 852                 break;
 853         case NOUVEAU_GETPARAM_FB_SIZE:
 854                 getparam->value = dev_priv->fb_available_size;
 855                 break;
 856         case NOUVEAU_GETPARAM_AGP_SIZE:
 857                 getparam->value = dev_priv->gart_info.aper_size;
 858                 break;
 859         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
 860                 getparam->value = dev_priv->vm_vram_base;
 861                 break;
 862         case NOUVEAU_GETPARAM_GRAPH_UNITS:
 863                 /* NV40 and NV50 versions are quite different, but register
 864                  * address is the same. User is supposed to know the card
 865                  * family anyway... */
 866                 if (dev_priv->chipset >= 0x40) {
 867                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
 868                         break;
 869                 }
 870                 /* FALLTHRU */
 871         default:
 872                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
 873                 return -EINVAL;
 874         }
 875
 876         return 0;
 877 }
 878
 879 int
 880 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
 881                        struct drm_file *file_priv)
 882 {
 883         struct drm_nouveau_setparam *setparam = data;
 884
 885         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 886
 887         switch (setparam->param) {
 888         default:
 889                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
 890                 return -EINVAL;
 891         }
 892
 893         return 0;
 894 }
 895
 896 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 897 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 898                         uint32_t reg, uint32_t mask, uint32_t val)
 899 {
 900         struct drm_nouveau_private *dev_priv = dev->dev_private;
 901         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 902         uint64_t start = ptimer->read(dev);
 903
 904         do {
 905                 if ((nv_rd32(dev, reg) & mask) == val)
 906                         return true;
 907         } while (ptimer->read(dev) - start < timeout);
 908
 909         return false;
 910 }
 911
 912 /* Waits for PGRAPH to go completely idle */
 913 bool nouveau_wait_for_idle(struct drm_device *dev)
 914 {
 915         if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
 916                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
 917                          nv_rd32(dev, NV04_PGRAPH_STATUS));
 918                 return false;
 919         }
 920
 921         return true;
 922 }
 923