drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.get             = nv04_instmem_get;
  57                 engine->instmem.put             = nv04_instmem_put;
  58                 engine->instmem.map             = nv04_instmem_map;
  59                 engine->instmem.unmap           = nv04_instmem_unmap;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->fifo.channels           = 16;
  69                 engine->fifo.init               = nv04_fifo_init;
  70                 engine->fifo.takedown           = nv04_fifo_fini;
  71                 engine->fifo.disable            = nv04_fifo_disable;
  72                 engine->fifo.enable             = nv04_fifo_enable;
  73                 engine->fifo.reassign           = nv04_fifo_reassign;
  74                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  75                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  76                 engine->fifo.create_context     = nv04_fifo_create_context;
  77                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  78                 engine->fifo.load_context       = nv04_fifo_load_context;
  79                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  80                 engine->display.early_init      = nv04_display_early_init;
  81                 engine->display.late_takedown   = nv04_display_late_takedown;
  82                 engine->display.create          = nv04_display_create;
  83                 engine->display.init            = nv04_display_init;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->gpio.init               = nouveau_stub_init;
  86                 engine->gpio.takedown           = nouveau_stub_takedown;
  87                 engine->gpio.get                = NULL;
  88                 engine->gpio.set                = NULL;
  89                 engine->gpio.irq_enable         = NULL;
  90                 engine->pm.clock_get            = nv04_pm_clock_get;
  91                 engine->pm.clock_pre            = nv04_pm_clock_pre;
  92                 engine->pm.clock_set            = nv04_pm_clock_set;
  93                 engine->vram.init               = nouveau_mem_detect;
  94                 engine->vram.takedown           = nouveau_stub_takedown;
  95                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  96                 break;
  97         case 0x10:
  98                 engine->instmem.init            = nv04_instmem_init;
  99                 engine->instmem.takedown        = nv04_instmem_takedown;
 100                 engine->instmem.suspend         = nv04_instmem_suspend;
 101                 engine->instmem.resume          = nv04_instmem_resume;
 102                 engine->instmem.get             = nv04_instmem_get;
 103                 engine->instmem.put             = nv04_instmem_put;
 104                 engine->instmem.map             = nv04_instmem_map;
 105                 engine->instmem.unmap           = nv04_instmem_unmap;
 106                 engine->instmem.flush           = nv04_instmem_flush;
 107                 engine->mc.init                 = nv04_mc_init;
 108                 engine->mc.takedown             = nv04_mc_takedown;
 109                 engine->timer.init              = nv04_timer_init;
 110                 engine->timer.read              = nv04_timer_read;
 111                 engine->timer.takedown          = nv04_timer_takedown;
 112                 engine->fb.init                 = nv10_fb_init;
 113                 engine->fb.takedown             = nv10_fb_takedown;
 114                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 115                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 116                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 117                 engine->fifo.channels           = 32;
 118                 engine->fifo.init               = nv10_fifo_init;
 119                 engine->fifo.takedown           = nv04_fifo_fini;
 120                 engine->fifo.disable            = nv04_fifo_disable;
 121                 engine->fifo.enable             = nv04_fifo_enable;
 122                 engine->fifo.reassign           = nv04_fifo_reassign;
 123                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 124                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 125                 engine->fifo.create_context     = nv10_fifo_create_context;
 126                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 127                 engine->fifo.load_context       = nv10_fifo_load_context;
 128                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 129                 engine->display.early_init      = nv04_display_early_init;
 130                 engine->display.late_takedown   = nv04_display_late_takedown;
 131                 engine->display.create          = nv04_display_create;
 132                 engine->display.init            = nv04_display_init;
 133                 engine->display.destroy         = nv04_display_destroy;
 134                 engine->gpio.init               = nouveau_stub_init;
 135                 engine->gpio.takedown           = nouveau_stub_takedown;
 136                 engine->gpio.get                = nv10_gpio_get;
 137                 engine->gpio.set                = nv10_gpio_set;
 138                 engine->gpio.irq_enable         = NULL;
 139                 engine->pm.clock_get            = nv04_pm_clock_get;
 140                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 141                 engine->pm.clock_set            = nv04_pm_clock_set;
 142                 engine->vram.init               = nouveau_mem_detect;
 143                 engine->vram.takedown           = nouveau_stub_takedown;
 144                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 145                 break;
 146         case 0x20:
 147                 engine->instmem.init            = nv04_instmem_init;
 148                 engine->instmem.takedown        = nv04_instmem_takedown;
 149                 engine->instmem.suspend         = nv04_instmem_suspend;
 150                 engine->instmem.resume          = nv04_instmem_resume;
 151                 engine->instmem.get             = nv04_instmem_get;
 152                 engine->instmem.put             = nv04_instmem_put;
 153                 engine->instmem.map             = nv04_instmem_map;
 154                 engine->instmem.unmap           = nv04_instmem_unmap;
 155                 engine->instmem.flush           = nv04_instmem_flush;
 156                 engine->mc.init                 = nv04_mc_init;
 157                 engine->mc.takedown             = nv04_mc_takedown;
 158                 engine->timer.init              = nv04_timer_init;
 159                 engine->timer.read              = nv04_timer_read;
 160                 engine->timer.takedown          = nv04_timer_takedown;
 161                 engine->fb.init                 = nv10_fb_init;
 162                 engine->fb.takedown             = nv10_fb_takedown;
 163                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 164                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 165                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 166                 engine->fifo.channels           = 32;
 167                 engine->fifo.init               = nv10_fifo_init;
 168                 engine->fifo.takedown           = nv04_fifo_fini;
 169                 engine->fifo.disable            = nv04_fifo_disable;
 170                 engine->fifo.enable             = nv04_fifo_enable;
 171                 engine->fifo.reassign           = nv04_fifo_reassign;
 172                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 173                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 174                 engine->fifo.create_context     = nv10_fifo_create_context;
 175                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 176                 engine->fifo.load_context       = nv10_fifo_load_context;
 177                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 178                 engine->display.early_init      = nv04_display_early_init;
 179                 engine->display.late_takedown   = nv04_display_late_takedown;
 180                 engine->display.create          = nv04_display_create;
 181                 engine->display.init            = nv04_display_init;
 182                 engine->display.destroy         = nv04_display_destroy;
 183                 engine->gpio.init               = nouveau_stub_init;
 184                 engine->gpio.takedown           = nouveau_stub_takedown;
 185                 engine->gpio.get                = nv10_gpio_get;
 186                 engine->gpio.set                = nv10_gpio_set;
 187                 engine->gpio.irq_enable         = NULL;
 188                 engine->pm.clock_get            = nv04_pm_clock_get;
 189                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 190                 engine->pm.clock_set            = nv04_pm_clock_set;
 191                 engine->vram.init               = nouveau_mem_detect;
 192                 engine->vram.takedown           = nouveau_stub_takedown;
 193                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 194                 break;
 195         case 0x30:
 196                 engine->instmem.init            = nv04_instmem_init;
 197                 engine->instmem.takedown        = nv04_instmem_takedown;
 198                 engine->instmem.suspend         = nv04_instmem_suspend;
 199                 engine->instmem.resume          = nv04_instmem_resume;
 200                 engine->instmem.get             = nv04_instmem_get;
 201                 engine->instmem.put             = nv04_instmem_put;
 202                 engine->instmem.map             = nv04_instmem_map;
 203                 engine->instmem.unmap           = nv04_instmem_unmap;
 204                 engine->instmem.flush           = nv04_instmem_flush;
 205                 engine->mc.init                 = nv04_mc_init;
 206                 engine->mc.takedown             = nv04_mc_takedown;
 207                 engine->timer.init              = nv04_timer_init;
 208                 engine->timer.read              = nv04_timer_read;
 209                 engine->timer.takedown          = nv04_timer_takedown;
 210                 engine->fb.init                 = nv30_fb_init;
 211                 engine->fb.takedown             = nv30_fb_takedown;
 212                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 213                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 214                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 215                 engine->fifo.channels           = 32;
 216                 engine->fifo.init               = nv10_fifo_init;
 217                 engine->fifo.takedown           = nv04_fifo_fini;
 218                 engine->fifo.disable            = nv04_fifo_disable;
 219                 engine->fifo.enable             = nv04_fifo_enable;
 220                 engine->fifo.reassign           = nv04_fifo_reassign;
 221                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 222                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 223                 engine->fifo.create_context     = nv10_fifo_create_context;
 224                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 225                 engine->fifo.load_context       = nv10_fifo_load_context;
 226                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 227                 engine->display.early_init      = nv04_display_early_init;
 228                 engine->display.late_takedown   = nv04_display_late_takedown;
 229                 engine->display.create          = nv04_display_create;
 230                 engine->display.init            = nv04_display_init;
 231                 engine->display.destroy         = nv04_display_destroy;
 232                 engine->gpio.init               = nouveau_stub_init;
 233                 engine->gpio.takedown           = nouveau_stub_takedown;
 234                 engine->gpio.get                = nv10_gpio_get;
 235                 engine->gpio.set                = nv10_gpio_set;
 236                 engine->gpio.irq_enable         = NULL;
 237                 engine->pm.clock_get            = nv04_pm_clock_get;
 238                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 239                 engine->pm.clock_set            = nv04_pm_clock_set;
 240                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 241                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 242                 engine->vram.init               = nouveau_mem_detect;
 243                 engine->vram.takedown           = nouveau_stub_takedown;
 244                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 245                 break;
 246         case 0x40:
 247         case 0x60:
 248                 engine->instmem.init            = nv04_instmem_init;
 249                 engine->instmem.takedown        = nv04_instmem_takedown;
 250                 engine->instmem.suspend         = nv04_instmem_suspend;
 251                 engine->instmem.resume          = nv04_instmem_resume;
 252                 engine->instmem.get             = nv04_instmem_get;
 253                 engine->instmem.put             = nv04_instmem_put;
 254                 engine->instmem.map             = nv04_instmem_map;
 255                 engine->instmem.unmap           = nv04_instmem_unmap;
 256                 engine->instmem.flush           = nv04_instmem_flush;
 257                 engine->mc.init                 = nv40_mc_init;
 258                 engine->mc.takedown             = nv40_mc_takedown;
 259                 engine->timer.init              = nv04_timer_init;
 260                 engine->timer.read              = nv04_timer_read;
 261                 engine->timer.takedown          = nv04_timer_takedown;
 262                 engine->fb.init                 = nv40_fb_init;
 263                 engine->fb.takedown             = nv40_fb_takedown;
 264                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 265                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 266                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 267                 engine->fifo.channels           = 32;
 268                 engine->fifo.init               = nv40_fifo_init;
 269                 engine->fifo.takedown           = nv04_fifo_fini;
 270                 engine->fifo.disable            = nv04_fifo_disable;
 271                 engine->fifo.enable             = nv04_fifo_enable;
 272                 engine->fifo.reassign           = nv04_fifo_reassign;
 273                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 274                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 275                 engine->fifo.create_context     = nv40_fifo_create_context;
 276                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 277                 engine->fifo.load_context       = nv40_fifo_load_context;
 278                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 279                 engine->display.early_init      = nv04_display_early_init;
 280                 engine->display.late_takedown   = nv04_display_late_takedown;
 281                 engine->display.create          = nv04_display_create;
 282                 engine->display.init            = nv04_display_init;
 283                 engine->display.destroy         = nv04_display_destroy;
 284                 engine->gpio.init               = nouveau_stub_init;
 285                 engine->gpio.takedown           = nouveau_stub_takedown;
 286                 engine->gpio.get                = nv10_gpio_get;
 287                 engine->gpio.set                = nv10_gpio_set;
 288                 engine->gpio.irq_enable         = NULL;
 289                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 290                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 291                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 292                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 293                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 294                 engine->pm.temp_get             = nv40_temp_get;
 295                 engine->vram.init               = nouveau_mem_detect;
 296                 engine->vram.takedown           = nouveau_stub_takedown;
 297                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 298                 break;
 299         case 0x50:
 300         case 0x80: /* gotta love NVIDIA's consistency.. */
 301         case 0x90:
 302         case 0xa0:
 303                 engine->instmem.init            = nv50_instmem_init;
 304                 engine->instmem.takedown        = nv50_instmem_takedown;
 305                 engine->instmem.suspend         = nv50_instmem_suspend;
 306                 engine->instmem.resume          = nv50_instmem_resume;
 307                 engine->instmem.get             = nv50_instmem_get;
 308                 engine->instmem.put             = nv50_instmem_put;
 309                 engine->instmem.map             = nv50_instmem_map;
 310                 engine->instmem.unmap           = nv50_instmem_unmap;
 311                 if (dev_priv->chipset == 0x50)
 312                         engine->instmem.flush   = nv50_instmem_flush;
 313                 else
 314                         engine->instmem.flush   = nv84_instmem_flush;
 315                 engine->mc.init                 = nv50_mc_init;
 316                 engine->mc.takedown             = nv50_mc_takedown;
 317                 engine->timer.init              = nv04_timer_init;
 318                 engine->timer.read              = nv04_timer_read;
 319                 engine->timer.takedown          = nv04_timer_takedown;
 320                 engine->fb.init                 = nv50_fb_init;
 321                 engine->fb.takedown             = nv50_fb_takedown;
 322                 engine->fifo.channels           = 128;
 323                 engine->fifo.init               = nv50_fifo_init;
 324                 engine->fifo.takedown           = nv50_fifo_takedown;
 325                 engine->fifo.disable            = nv04_fifo_disable;
 326                 engine->fifo.enable             = nv04_fifo_enable;
 327                 engine->fifo.reassign           = nv04_fifo_reassign;
 328                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 329                 engine->fifo.create_context     = nv50_fifo_create_context;
 330                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 331                 engine->fifo.load_context       = nv50_fifo_load_context;
 332                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 333                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 334                 engine->display.early_init      = nv50_display_early_init;
 335                 engine->display.late_takedown   = nv50_display_late_takedown;
 336                 engine->display.create          = nv50_display_create;
 337                 engine->display.init            = nv50_display_init;
 338                 engine->display.destroy         = nv50_display_destroy;
 339                 engine->gpio.init               = nv50_gpio_init;
 340                 engine->gpio.takedown           = nv50_gpio_fini;
 341                 engine->gpio.get                = nv50_gpio_get;
 342                 engine->gpio.set                = nv50_gpio_set;
 343                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 344                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 345                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 346                 switch (dev_priv->chipset) {
 347                 case 0x84:
 348                 case 0x86:
 349                 case 0x92:
 350                 case 0x94:
 351                 case 0x96:
 352                 case 0x98:
 353                 case 0xa0:
 354                 case 0xaa:
 355                 case 0xac:
 356                 case 0x50:
 357                         engine->pm.clock_get    = nv50_pm_clock_get;
 358                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 359                         engine->pm.clock_set    = nv50_pm_clock_set;
 360                         break;
 361                 default:
 362                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 363                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 364                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 365                         break;
 366                 }
 367                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 368                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 369                 if (dev_priv->chipset >= 0x84)
 370                         engine->pm.temp_get     = nv84_temp_get;
 371                 else
 372                         engine->pm.temp_get     = nv40_temp_get;
 373                 engine->vram.init               = nv50_vram_init;
 374                 engine->vram.takedown           = nv50_vram_fini;
 375                 engine->vram.get                = nv50_vram_new;
 376                 engine->vram.put                = nv50_vram_del;
 377                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 378                 break;
 379         case 0xc0:
 380                 engine->instmem.init            = nvc0_instmem_init;
 381                 engine->instmem.takedown        = nvc0_instmem_takedown;
 382                 engine->instmem.suspend         = nvc0_instmem_suspend;
 383                 engine->instmem.resume          = nvc0_instmem_resume;
 384                 engine->instmem.get             = nv50_instmem_get;
 385                 engine->instmem.put             = nv50_instmem_put;
 386                 engine->instmem.map             = nv50_instmem_map;
 387                 engine->instmem.unmap           = nv50_instmem_unmap;
 388                 engine->instmem.flush           = nv84_instmem_flush;
 389                 engine->mc.init                 = nv50_mc_init;
 390                 engine->mc.takedown             = nv50_mc_takedown;
 391                 engine->timer.init              = nv04_timer_init;
 392                 engine->timer.read              = nv04_timer_read;
 393                 engine->timer.takedown          = nv04_timer_takedown;
 394                 engine->fb.init                 = nvc0_fb_init;
 395                 engine->fb.takedown             = nvc0_fb_takedown;
 396                 engine->fifo.channels           = 128;
 397                 engine->fifo.init               = nvc0_fifo_init;
 398                 engine->fifo.takedown           = nvc0_fifo_takedown;
 399                 engine->fifo.disable            = nvc0_fifo_disable;
 400                 engine->fifo.enable             = nvc0_fifo_enable;
 401                 engine->fifo.reassign           = nvc0_fifo_reassign;
 402                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 403                 engine->fifo.create_context     = nvc0_fifo_create_context;
 404                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 405                 engine->fifo.load_context       = nvc0_fifo_load_context;
 406                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 407                 engine->display.early_init      = nv50_display_early_init;
 408                 engine->display.late_takedown   = nv50_display_late_takedown;
 409                 engine->display.create          = nv50_display_create;
 410                 engine->display.init            = nv50_display_init;
 411                 engine->display.destroy         = nv50_display_destroy;
 412                 engine->gpio.init               = nv50_gpio_init;
 413                 engine->gpio.takedown           = nouveau_stub_takedown;
 414                 engine->gpio.get                = nv50_gpio_get;
 415                 engine->gpio.set                = nv50_gpio_set;
 416                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 417                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 418                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 419                 engine->vram.init               = nvc0_vram_init;
 420                 engine->vram.takedown           = nv50_vram_fini;
 421                 engine->vram.get                = nvc0_vram_new;
 422                 engine->vram.put                = nv50_vram_del;
 423                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 424                 engine->pm.temp_get             = nv84_temp_get;
 425                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 428                 break;
 429         case 0xd0:
 430                 engine->instmem.init            = nvc0_instmem_init;
 431                 engine->instmem.takedown        = nvc0_instmem_takedown;
 432                 engine->instmem.suspend         = nvc0_instmem_suspend;
 433                 engine->instmem.resume          = nvc0_instmem_resume;
 434                 engine->instmem.get             = nv50_instmem_get;
 435                 engine->instmem.put             = nv50_instmem_put;
 436                 engine->instmem.map             = nv50_instmem_map;
 437                 engine->instmem.unmap           = nv50_instmem_unmap;
 438                 engine->instmem.flush           = nv84_instmem_flush;
 439                 engine->mc.init                 = nv50_mc_init;
 440                 engine->mc.takedown             = nv50_mc_takedown;
 441                 engine->timer.init              = nv04_timer_init;
 442                 engine->timer.read              = nv04_timer_read;
 443                 engine->timer.takedown          = nv04_timer_takedown;
 444                 engine->fb.init                 = nvc0_fb_init;
 445                 engine->fb.takedown             = nvc0_fb_takedown;
 446                 engine->fifo.channels           = 128;
 447                 engine->fifo.init               = nvc0_fifo_init;
 448                 engine->fifo.takedown           = nvc0_fifo_takedown;
 449                 engine->fifo.disable            = nvc0_fifo_disable;
 450                 engine->fifo.enable             = nvc0_fifo_enable;
 451                 engine->fifo.reassign           = nvc0_fifo_reassign;
 452                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 453                 engine->fifo.create_context     = nvc0_fifo_create_context;
 454                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 455                 engine->fifo.load_context       = nvc0_fifo_load_context;
 456                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 457                 engine->display.early_init      = nouveau_stub_init;
 458                 engine->display.late_takedown   = nouveau_stub_takedown;
 459                 engine->display.create          = nvd0_display_create;
 460                 engine->display.init            = nvd0_display_init;
 461                 engine->display.destroy         = nvd0_display_destroy;
 462                 engine->gpio.init               = nv50_gpio_init;
 463                 engine->gpio.takedown           = nouveau_stub_takedown;
 464                 engine->gpio.get                = nvd0_gpio_get;
 465                 engine->gpio.set                = nvd0_gpio_set;
 466                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 467                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 468                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 469                 engine->vram.init               = nvc0_vram_init;
 470                 engine->vram.takedown           = nv50_vram_fini;
 471                 engine->vram.get                = nvc0_vram_new;
 472                 engine->vram.put                = nv50_vram_del;
 473                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 474                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 475                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 476                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 477                 break;
 478         default:
 479                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 480                 return 1;
 481         }
 482
 483         /* headless mode */
 484         if (nouveau_modeset == 2) {
 485                 engine->display.early_init = nouveau_stub_init;
 486                 engine->display.late_takedown = nouveau_stub_takedown;
 487                 engine->display.create = nouveau_stub_init;
 488                 engine->display.init = nouveau_stub_init;
 489                 engine->display.destroy = nouveau_stub_takedown;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static unsigned int
 496 nouveau_vga_set_decode(void *priv, bool state)
 497 {
 498         struct drm_device *dev = priv;
 499         struct drm_nouveau_private *dev_priv = dev->dev_private;
 500
 501         if (dev_priv->chipset >= 0x40)
 502                 nv_wr32(dev, 0x88054, state);
 503         else
 504                 nv_wr32(dev, 0x1854, state);
 505
 506         if (state)
 507                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 508                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 509         else
 510                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 511 }
 512
 513 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 514                                          enum vga_switcheroo_state state)
 515 {
 516         struct drm_device *dev = pci_get_drvdata(pdev);
 517         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 518         if (state == VGA_SWITCHEROO_ON) {
 519                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 520                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 521                 nouveau_pci_resume(pdev);
 522                 drm_kms_helper_poll_enable(dev);
 523                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 524         } else {
 525                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 526                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 527                 drm_kms_helper_poll_disable(dev);
 528                 nouveau_pci_suspend(pdev, pmm);
 529                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 530         }
 531 }
 532
 533 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 534 {
 535         struct drm_device *dev = pci_get_drvdata(pdev);
 536         nouveau_fbcon_output_poll_changed(dev);
 537 }
 538
 539 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 540 {
 541         struct drm_device *dev = pci_get_drvdata(pdev);
 542         bool can_switch;
 543
 544         spin_lock(&dev->count_lock);
 545         can_switch = (dev->open_count == 0);
 546         spin_unlock(&dev->count_lock);
 547         return can_switch;
 548 }
 549
 550 int
 551 nouveau_card_init(struct drm_device *dev)
 552 {
 553         struct drm_nouveau_private *dev_priv = dev->dev_private;
 554         struct nouveau_engine *engine;
 555         int ret, e = 0;
 556
 557         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 558         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 559                                        nouveau_switcheroo_reprobe,
 560                                        nouveau_switcheroo_can_switch);
 561
 562         /* Initialise internal driver API hooks */
 563         ret = nouveau_init_engine_ptrs(dev);
 564         if (ret)
 565                 goto out;
 566         engine = &dev_priv->engine;
 567         spin_lock_init(&dev_priv->channels.lock);
 568         spin_lock_init(&dev_priv->tile.lock);
 569         spin_lock_init(&dev_priv->context_switch_lock);
 570         spin_lock_init(&dev_priv->vm_lock);
 571
 572         /* Make the CRTCs and I2C buses accessible */
 573         ret = engine->display.early_init(dev);
 574         if (ret)
 575                 goto out;
 576
 577         /* Parse BIOS tables / Run init tables if card not POSTed */
 578         ret = nouveau_bios_init(dev);
 579         if (ret)
 580                 goto out_display_early;
 581
 582         /* workaround an odd issue on nvc1 by disabling the device's
 583          * nosnoop capability.  hopefully won't cause issues until a
 584          * better fix is found - assuming there is one...
 585          */
 586         if (dev_priv->chipset == 0xc1) {
 587                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 588         }
 589
 590         nouveau_pm_init(dev);
 591
 592         ret = engine->vram.init(dev);
 593         if (ret)
 594                 goto out_bios;
 595
 596         ret = nouveau_gpuobj_init(dev);
 597         if (ret)
 598                 goto out_vram;
 599
 600         ret = engine->instmem.init(dev);
 601         if (ret)
 602                 goto out_gpuobj;
 603
 604         ret = nouveau_mem_vram_init(dev);
 605         if (ret)
 606                 goto out_instmem;
 607
 608         ret = nouveau_mem_gart_init(dev);
 609         if (ret)
 610                 goto out_ttmvram;
 611
 612         /* PMC */
 613         ret = engine->mc.init(dev);
 614         if (ret)
 615                 goto out_gart;
 616
 617         /* PGPIO */
 618         ret = engine->gpio.init(dev);
 619         if (ret)
 620                 goto out_mc;
 621
 622         /* PTIMER */
 623         ret = engine->timer.init(dev);
 624         if (ret)
 625                 goto out_gpio;
 626
 627         /* PFB */
 628         ret = engine->fb.init(dev);
 629         if (ret)
 630                 goto out_timer;
 631
 632         if (!dev_priv->noaccel) {
 633                 switch (dev_priv->card_type) {
 634                 case NV_04:
 635                         nv04_graph_create(dev);
 636                         break;
 637                 case NV_10:
 638                         nv10_graph_create(dev);
 639                         break;
 640                 case NV_20:
 641                 case NV_30:
 642                         nv20_graph_create(dev);
 643                         break;
 644                 case NV_40:
 645                         nv40_graph_create(dev);
 646                         break;
 647                 case NV_50:
 648                         nv50_graph_create(dev);
 649                         break;
 650                 case NV_C0:
 651                         nvc0_graph_create(dev);
 652                         break;
 653                 default:
 654                         break;
 655                 }
 656
 657                 switch (dev_priv->chipset) {
 658                 case 0x84:
 659                 case 0x86:
 660                 case 0x92:
 661                 case 0x94:
 662                 case 0x96:
 663                 case 0xa0:
 664                         nv84_crypt_create(dev);
 665                         break;
 666                 }
 667
 668                 switch (dev_priv->card_type) {
 669                 case NV_50:
 670                         switch (dev_priv->chipset) {
 671                         case 0xa3:
 672                         case 0xa5:
 673                         case 0xa8:
 674                         case 0xaf:
 675                                 nva3_copy_create(dev);
 676                                 break;
 677                         }
 678                         break;
 679                 case NV_C0:
 680                         nvc0_copy_create(dev, 0);
 681                         nvc0_copy_create(dev, 1);
 682                         break;
 683                 default:
 684                         break;
 685                 }
 686
 687                 if (dev_priv->card_type == NV_40 ||
 688                     dev_priv->chipset == 0x31 ||
 689                     dev_priv->chipset == 0x34 ||
 690                     dev_priv->chipset == 0x36)
 691                         nv31_mpeg_create(dev);
 692                 else
 693                 if (dev_priv->card_type == NV_50 &&
 694                     (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
 695                         nv50_mpeg_create(dev);
 696
 697                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 698                         if (dev_priv->eng[e]) {
 699                                 ret = dev_priv->eng[e]->init(dev, e);
 700                                 if (ret)
 701                                         goto out_engine;
 702                         }
 703                 }
 704
 705                 /* PFIFO */
 706                 ret = engine->fifo.init(dev);
 707                 if (ret)
 708                         goto out_engine;
 709         }
 710
 711         ret = nouveau_irq_init(dev);
 712         if (ret)
 713                 goto out_fifo;
 714
 715         /* initialise general modesetting */
 716         drm_mode_config_init(dev);
 717         drm_mode_create_scaling_mode_property(dev);
 718         drm_mode_create_dithering_property(dev);
 719         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 720         dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1);
 721         dev->mode_config.min_width = 0;
 722         dev->mode_config.min_height = 0;
 723         if (dev_priv->card_type < NV_10) {
 724                 dev->mode_config.max_width = 2048;
 725                 dev->mode_config.max_height = 2048;
 726         } else
 727         if (dev_priv->card_type < NV_50) {
 728                 dev->mode_config.max_width = 4096;
 729                 dev->mode_config.max_height = 4096;
 730         } else {
 731                 dev->mode_config.max_width = 8192;
 732                 dev->mode_config.max_height = 8192;
 733         }
 734
 735         ret = engine->display.create(dev);
 736         if (ret)
 737                 goto out_irq;
 738
 739         nouveau_backlight_init(dev);
 740
 741         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 742                 ret = nouveau_fence_init(dev);
 743                 if (ret)
 744                         goto out_disp;
 745
 746                 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
 747                                             NvDmaFB, NvDmaTT);
 748                 if (ret)
 749                         goto out_fence;
 750
 751                 mutex_unlock(&dev_priv->channel->mutex);
 752         }
 753
 754         if (dev->mode_config.num_crtc) {
 755                 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 756                 if (ret)
 757                         goto out_chan;
 758
 759                 nouveau_fbcon_init(dev);
 760                 drm_kms_helper_poll_init(dev);
 761         }
 762
 763         return 0;
 764
 765 out_chan:
 766         nouveau_channel_put_unlocked(&dev_priv->channel);
 767 out_fence:
 768         nouveau_fence_fini(dev);
 769 out_disp:
 770         nouveau_backlight_exit(dev);
 771         engine->display.destroy(dev);
 772 out_irq:
 773         nouveau_irq_fini(dev);
 774 out_fifo:
 775         if (!dev_priv->noaccel)
 776                 engine->fifo.takedown(dev);
 777 out_engine:
 778         if (!dev_priv->noaccel) {
 779                 for (e = e - 1; e >= 0; e--) {
 780                         if (!dev_priv->eng[e])
 781                                 continue;
 782                         dev_priv->eng[e]->fini(dev, e, false);
 783                         dev_priv->eng[e]->destroy(dev,e );
 784                 }
 785         }
 786
 787         engine->fb.takedown(dev);
 788 out_timer:
 789         engine->timer.takedown(dev);
 790 out_gpio:
 791         engine->gpio.takedown(dev);
 792 out_mc:
 793         engine->mc.takedown(dev);
 794 out_gart:
 795         nouveau_mem_gart_fini(dev);
 796 out_ttmvram:
 797         nouveau_mem_vram_fini(dev);
 798 out_instmem:
 799         engine->instmem.takedown(dev);
 800 out_gpuobj:
 801         nouveau_gpuobj_takedown(dev);
 802 out_vram:
 803         engine->vram.takedown(dev);
 804 out_bios:
 805         nouveau_pm_fini(dev);
 806         nouveau_bios_takedown(dev);
 807 out_display_early:
 808         engine->display.late_takedown(dev);
 809 out:
 810         vga_client_register(dev->pdev, NULL, NULL, NULL);
 811         return ret;
 812 }
 813
 814 static void nouveau_card_takedown(struct drm_device *dev)
 815 {
 816         struct drm_nouveau_private *dev_priv = dev->dev_private;
 817         struct nouveau_engine *engine = &dev_priv->engine;
 818         int e;
 819
 820         if (dev->mode_config.num_crtc) {
 821                 drm_kms_helper_poll_fini(dev);
 822                 nouveau_fbcon_fini(dev);
 823                 drm_vblank_cleanup(dev);
 824         }
 825
 826         if (dev_priv->channel) {
 827                 nouveau_channel_put_unlocked(&dev_priv->channel);
 828                 nouveau_fence_fini(dev);
 829         }
 830
 831         nouveau_backlight_exit(dev);
 832         engine->display.destroy(dev);
 833         drm_mode_config_cleanup(dev);
 834
 835         if (!dev_priv->noaccel) {
 836                 engine->fifo.takedown(dev);
 837                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 838                         if (dev_priv->eng[e]) {
 839                                 dev_priv->eng[e]->fini(dev, e, false);
 840                                 dev_priv->eng[e]->destroy(dev,e );
 841                         }
 842                 }
 843         }
 844         engine->fb.takedown(dev);
 845         engine->timer.takedown(dev);
 846         engine->gpio.takedown(dev);
 847         engine->mc.takedown(dev);
 848         engine->display.late_takedown(dev);
 849
 850         if (dev_priv->vga_ram) {
 851                 nouveau_bo_unpin(dev_priv->vga_ram);
 852                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 853         }
 854
 855         mutex_lock(&dev->struct_mutex);
 856         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 857         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 858         mutex_unlock(&dev->struct_mutex);
 859         nouveau_mem_gart_fini(dev);
 860         nouveau_mem_vram_fini(dev);
 861
 862         engine->instmem.takedown(dev);
 863         nouveau_gpuobj_takedown(dev);
 864         engine->vram.takedown(dev);
 865
 866         nouveau_irq_fini(dev);
 867
 868         nouveau_pm_fini(dev);
 869         nouveau_bios_takedown(dev);
 870
 871         vga_client_register(dev->pdev, NULL, NULL, NULL);
 872 }
 873
 874 int
 875 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 876 {
 877         struct drm_nouveau_private *dev_priv = dev->dev_private;
 878         struct nouveau_fpriv *fpriv;
 879         int ret;
 880
 881         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 882         if (unlikely(!fpriv))
 883                 return -ENOMEM;
 884
 885         spin_lock_init(&fpriv->lock);
 886         INIT_LIST_HEAD(&fpriv->channels);
 887
 888         if (dev_priv->card_type == NV_50) {
 889                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 890                                      &fpriv->vm);
 891                 if (ret) {
 892                         kfree(fpriv);
 893                         return ret;
 894                 }
 895         } else
 896         if (dev_priv->card_type >= NV_C0) {
 897                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 898                                      &fpriv->vm);
 899                 if (ret) {
 900                         kfree(fpriv);
 901                         return ret;
 902                 }
 903         }
 904
 905         file_priv->driver_priv = fpriv;
 906         return 0;
 907 }
 908
 909 /* here a client dies, release the stuff that was allocated for its
 910  * file_priv */
 911 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 912 {
 913         nouveau_channel_cleanup(dev, file_priv);
 914 }
 915
 916 void
 917 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 918 {
 919         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 920         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 921         kfree(fpriv);
 922 }
 923
 924 /* first module load, setup the mmio/fb mapping */
 925 /* KMS: we need mmio at load time, not when the first drm client opens. */
 926 int nouveau_firstopen(struct drm_device *dev)
 927 {
 928         return 0;
 929 }
 930
 931 /* if we have an OF card, copy vbios to RAMIN */
 932 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 933 {
 934 #if defined(__powerpc__)
 935         int size, i;
 936         const uint32_t *bios;
 937         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 938         if (!dn) {
 939                 NV_INFO(dev, "Unable to get the OF node\n");
 940                 return;
 941         }
 942
 943         bios = of_get_property(dn, "NVDA,BMP", &size);
 944         if (bios) {
 945                 for (i = 0; i < size; i += 4)
 946                         nv_wi32(dev, i, bios[i/4]);
 947                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 948         } else {
 949                 NV_INFO(dev, "Unable to get the OF bios\n");
 950         }
 951 #endif
 952 }
 953
 954 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 955 {
 956         struct pci_dev *pdev = dev->pdev;
 957         struct apertures_struct *aper = alloc_apertures(3);
 958         if (!aper)
 959                 return NULL;
 960
 961         aper->ranges[0].base = pci_resource_start(pdev, 1);
 962         aper->ranges[0].size = pci_resource_len(pdev, 1);
 963         aper->count = 1;
 964
 965         if (pci_resource_len(pdev, 2)) {
 966                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 967                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 968                 aper->count++;
 969         }
 970
 971         if (pci_resource_len(pdev, 3)) {
 972                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 973                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 974                 aper->count++;
 975         }
 976
 977         return aper;
 978 }
 979
 980 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 981 {
 982         struct drm_nouveau_private *dev_priv = dev->dev_private;
 983         bool primary = false;
 984         dev_priv->apertures = nouveau_get_apertures(dev);
 985         if (!dev_priv->apertures)
 986                 return -ENOMEM;
 987
 988 #ifdef CONFIG_X86
 989         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 990 #endif
 991
 992         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 993         return 0;
 994 }
 995
 996 int nouveau_load(struct drm_device *dev, unsigned long flags)
 997 {
 998         struct drm_nouveau_private *dev_priv;
 999         uint32_t reg0, strap;
1000         resource_size_t mmio_start_offs;
1001         int ret;
1002
1003         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1004         if (!dev_priv) {
1005                 ret = -ENOMEM;
1006                 goto err_out;
1007         }
1008         dev->dev_private = dev_priv;
1009         dev_priv->dev = dev;
1010
1011         dev_priv->flags = flags & NOUVEAU_FLAGS;
1012
1013         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1014                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1015
1016         /* resource 0 is mmio regs */
1017         /* resource 1 is linear FB */
1018         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
1019         /* resource 6 is bios */
1020
1021         /* map the mmio regs */
1022         mmio_start_offs = pci_resource_start(dev->pdev, 0);
1023         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
1024         if (!dev_priv->mmio) {
1025                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1026                          "Please report your setup to " DRIVER_EMAIL "\n");
1027                 ret = -EINVAL;
1028                 goto err_priv;
1029         }
1030         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1031                                         (unsigned long long)mmio_start_offs);
1032
1033 #ifdef __BIG_ENDIAN
1034         /* Put the card in BE mode if it's not */
1035         if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1036                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1037
1038         DRM_MEMORYBARRIER();
1039 #endif
1040
1041         /* Time to determine the card architecture */
1042         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1043
1044         /* We're dealing with >=NV10 */
1045         if ((reg0 & 0x0f000000) > 0) {
1046                 /* Bit 27-20 contain the architecture in hex */
1047                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1048         /* NV04 or NV05 */
1049         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1050                 if (reg0 & 0x00f00000)
1051                         dev_priv->chipset = 0x05;
1052                 else
1053                         dev_priv->chipset = 0x04;
1054         } else
1055                 dev_priv->chipset = 0xff;
1056
1057         switch (dev_priv->chipset & 0xf0) {
1058         case 0x00:
1059         case 0x10:
1060         case 0x20:
1061         case 0x30:
1062                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1063                 break;
1064         case 0x40:
1065         case 0x60:
1066                 dev_priv->card_type = NV_40;
1067                 break;
1068         case 0x50:
1069         case 0x80:
1070         case 0x90:
1071         case 0xa0:
1072                 dev_priv->card_type = NV_50;
1073                 break;
1074         case 0xc0:
1075                 dev_priv->card_type = NV_C0;
1076                 break;
1077         case 0xd0:
1078                 dev_priv->card_type = NV_D0;
1079                 break;
1080         default:
1081                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1082                 ret = -EINVAL;
1083                 goto err_mmio;
1084         }
1085
1086         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1087                 dev_priv->card_type, reg0);
1088
1089         /* determine frequency of timing crystal */
1090         strap = nv_rd32(dev, 0x101000);
1091         if ( dev_priv->chipset < 0x17 ||
1092             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1093                 strap &= 0x00000040;
1094         else
1095                 strap &= 0x00400040;
1096
1097         switch (strap) {
1098         case 0x00000000: dev_priv->crystal = 13500; break;
1099         case 0x00000040: dev_priv->crystal = 14318; break;
1100         case 0x00400000: dev_priv->crystal = 27000; break;
1101         case 0x00400040: dev_priv->crystal = 25000; break;
1102         }
1103
1104         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1105
1106         /* Determine whether we'll attempt acceleration or not, some
1107          * cards are disabled by default here due to them being known
1108          * non-functional, or never been tested due to lack of hw.
1109          */
1110         dev_priv->noaccel = !!nouveau_noaccel;
1111         if (nouveau_noaccel == -1) {
1112                 switch (dev_priv->chipset) {
1113 #if 0
1114                 case 0xXX: /* known broken */
1115                         NV_INFO(dev, "acceleration disabled by default, pass "
1116                                      "noaccel=0 to force enable\n");
1117                         dev_priv->noaccel = true;
1118                         break;
1119 #endif
1120                 default:
1121                         dev_priv->noaccel = false;
1122                         break;
1123                 }
1124         }
1125
1126         ret = nouveau_remove_conflicting_drivers(dev);
1127         if (ret)
1128                 goto err_mmio;
1129
1130         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1131         if (dev_priv->card_type >= NV_40) {
1132                 int ramin_bar = 2;
1133                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1134                         ramin_bar = 3;
1135
1136                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1137                 dev_priv->ramin =
1138                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1139                                 dev_priv->ramin_size);
1140                 if (!dev_priv->ramin) {
1141                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1142                         ret = -ENOMEM;
1143                         goto err_mmio;
1144                 }
1145         } else {
1146                 dev_priv->ramin_size = 1 * 1024 * 1024;
1147                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1148                                           dev_priv->ramin_size);
1149                 if (!dev_priv->ramin) {
1150                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1151                         ret = -ENOMEM;
1152                         goto err_mmio;
1153                 }
1154         }
1155
1156         nouveau_OF_copy_vbios_to_ramin(dev);
1157
1158         /* Special flags */
1159         if (dev->pci_device == 0x01a0)
1160                 dev_priv->flags |= NV_NFORCE;
1161         else if (dev->pci_device == 0x01f0)
1162                 dev_priv->flags |= NV_NFORCE2;
1163
1164         /* For kernel modesetting, init card now and bring up fbcon */
1165         ret = nouveau_card_init(dev);
1166         if (ret)
1167                 goto err_ramin;
1168
1169         return 0;
1170
1171 err_ramin:
1172         iounmap(dev_priv->ramin);
1173 err_mmio:
1174         iounmap(dev_priv->mmio);
1175 err_priv:
1176         kfree(dev_priv);
1177         dev->dev_private = NULL;
1178 err_out:
1179         return ret;
1180 }
1181
1182 void nouveau_lastclose(struct drm_device *dev)
1183 {
1184         vga_switcheroo_process_delayed_switch();
1185 }
1186
1187 int nouveau_unload(struct drm_device *dev)
1188 {
1189         struct drm_nouveau_private *dev_priv = dev->dev_private;
1190
1191         nouveau_card_takedown(dev);
1192
1193         iounmap(dev_priv->mmio);
1194         iounmap(dev_priv->ramin);
1195
1196         kfree(dev_priv);
1197         dev->dev_private = NULL;
1198         return 0;
1199 }
1200
1201 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1202                                                 struct drm_file *file_priv)
1203 {
1204         struct drm_nouveau_private *dev_priv = dev->dev_private;
1205         struct drm_nouveau_getparam *getparam = data;
1206
1207         switch (getparam->param) {
1208         case NOUVEAU_GETPARAM_CHIPSET_ID:
1209                 getparam->value = dev_priv->chipset;
1210                 break;
1211         case NOUVEAU_GETPARAM_PCI_VENDOR:
1212                 getparam->value = dev->pci_vendor;
1213                 break;
1214         case NOUVEAU_GETPARAM_PCI_DEVICE:
1215                 getparam->value = dev->pci_device;
1216                 break;
1217         case NOUVEAU_GETPARAM_BUS_TYPE:
1218                 if (drm_pci_device_is_agp(dev))
1219                         getparam->value = NV_AGP;
1220                 else if (pci_is_pcie(dev->pdev))
1221                         getparam->value = NV_PCIE;
1222                 else
1223                         getparam->value = NV_PCI;
1224                 break;
1225         case NOUVEAU_GETPARAM_FB_SIZE:
1226                 getparam->value = dev_priv->fb_available_size;
1227                 break;
1228         case NOUVEAU_GETPARAM_AGP_SIZE:
1229                 getparam->value = dev_priv->gart_info.aper_size;
1230                 break;
1231         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1232                 getparam->value = 0; /* deprecated */
1233                 break;
1234         case NOUVEAU_GETPARAM_PTIMER_TIME:
1235                 getparam->value = dev_priv->engine.timer.read(dev);
1236                 break;
1237         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1238                 getparam->value = 1;
1239                 break;
1240         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1241                 getparam->value = dev_priv->card_type < NV_D0;
1242                 break;
1243         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1244                 /* NV40 and NV50 versions are quite different, but register
1245                  * address is the same. User is supposed to know the card
1246                  * family anyway... */
1247                 if (dev_priv->chipset >= 0x40) {
1248                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1249                         break;
1250                 }
1251                 /* FALLTHRU */
1252         default:
1253                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1254                 return -EINVAL;
1255         }
1256
1257         return 0;
1258 }
1259
1260 int
1261 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1262                        struct drm_file *file_priv)
1263 {
1264         struct drm_nouveau_setparam *setparam = data;
1265
1266         switch (setparam->param) {
1267         default:
1268                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1269                 return -EINVAL;
1270         }
1271
1272         return 0;
1273 }
1274
1275 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1276 bool
1277 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1278                 uint32_t reg, uint32_t mask, uint32_t val)
1279 {
1280         struct drm_nouveau_private *dev_priv = dev->dev_private;
1281         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1282         uint64_t start = ptimer->read(dev);
1283
1284         do {
1285                 if ((nv_rd32(dev, reg) & mask) == val)
1286                         return true;
1287         } while (ptimer->read(dev) - start < timeout);
1288
1289         return false;
1290 }
1291
1292 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1293 bool
1294 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1295                 uint32_t reg, uint32_t mask, uint32_t val)
1296 {
1297         struct drm_nouveau_private *dev_priv = dev->dev_private;
1298         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1299         uint64_t start = ptimer->read(dev);
1300
1301         do {
1302                 if ((nv_rd32(dev, reg) & mask) != val)
1303                         return true;
1304         } while (ptimer->read(dev) - start < timeout);
1305
1306         return false;
1307 }
1308
1309 /* Wait until cond(data) == true, up until timeout has hit */
1310 bool
1311 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1312                 bool (*cond)(void *), void *data)
1313 {
1314         struct drm_nouveau_private *dev_priv = dev->dev_private;
1315         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1316         u64 start = ptimer->read(dev);
1317
1318         do {
1319                 if (cond(data) == true)
1320                         return true;
1321         } while (ptimer->read(dev) - start < timeout);
1322
1323         return false;
1324 }
1325
1326 /* Waits for PGRAPH to go completely idle */
1327 bool nouveau_wait_for_idle(struct drm_device *dev)
1328 {
1329         struct drm_nouveau_private *dev_priv = dev->dev_private;
1330         uint32_t mask = ~0;
1331
1332         if (dev_priv->card_type == NV_40)
1333                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1334
1335         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1336                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1337                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1338                 return false;
1339         }
1340
1341         return true;
1342 }
1343