drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.get             = nv04_instmem_get;
  57                 engine->instmem.put             = nv04_instmem_put;
  58                 engine->instmem.map             = nv04_instmem_map;
  59                 engine->instmem.unmap           = nv04_instmem_unmap;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->graph.init              = nv04_graph_init;
  69                 engine->graph.takedown          = nv04_graph_takedown;
  70                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  71                 engine->graph.channel           = nv04_graph_channel;
  72                 engine->graph.create_context    = nv04_graph_create_context;
  73                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  74                 engine->graph.load_context      = nv04_graph_load_context;
  75                 engine->graph.unload_context    = nv04_graph_unload_context;
  76                 engine->fifo.channels           = 16;
  77                 engine->fifo.init               = nv04_fifo_init;
  78                 engine->fifo.takedown           = nv04_fifo_fini;
  79                 engine->fifo.disable            = nv04_fifo_disable;
  80                 engine->fifo.enable             = nv04_fifo_enable;
  81                 engine->fifo.reassign           = nv04_fifo_reassign;
  82                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  83                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  84                 engine->fifo.create_context     = nv04_fifo_create_context;
  85                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  86                 engine->fifo.load_context       = nv04_fifo_load_context;
  87                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  88                 engine->display.early_init      = nv04_display_early_init;
  89                 engine->display.late_takedown   = nv04_display_late_takedown;
  90                 engine->display.create          = nv04_display_create;
  91                 engine->display.init            = nv04_display_init;
  92                 engine->display.destroy         = nv04_display_destroy;
  93                 engine->gpio.init               = nouveau_stub_init;
  94                 engine->gpio.takedown           = nouveau_stub_takedown;
  95                 engine->gpio.get                = NULL;
  96                 engine->gpio.set                = NULL;
  97                 engine->gpio.irq_enable         = NULL;
  98                 engine->pm.clock_get            = nv04_pm_clock_get;
  99                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 100                 engine->pm.clock_set            = nv04_pm_clock_set;
 101                 engine->crypt.init              = nouveau_stub_init;
 102                 engine->crypt.takedown          = nouveau_stub_takedown;
 103                 engine->vram.init               = nouveau_mem_detect;
 104                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 105                 break;
 106         case 0x10:
 107                 engine->instmem.init            = nv04_instmem_init;
 108                 engine->instmem.takedown        = nv04_instmem_takedown;
 109                 engine->instmem.suspend         = nv04_instmem_suspend;
 110                 engine->instmem.resume          = nv04_instmem_resume;
 111                 engine->instmem.get             = nv04_instmem_get;
 112                 engine->instmem.put             = nv04_instmem_put;
 113                 engine->instmem.map             = nv04_instmem_map;
 114                 engine->instmem.unmap           = nv04_instmem_unmap;
 115                 engine->instmem.flush           = nv04_instmem_flush;
 116                 engine->mc.init                 = nv04_mc_init;
 117                 engine->mc.takedown             = nv04_mc_takedown;
 118                 engine->timer.init              = nv04_timer_init;
 119                 engine->timer.read              = nv04_timer_read;
 120                 engine->timer.takedown          = nv04_timer_takedown;
 121                 engine->fb.init                 = nv10_fb_init;
 122                 engine->fb.takedown             = nv10_fb_takedown;
 123                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 124                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 125                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 126                 engine->graph.init              = nv10_graph_init;
 127                 engine->graph.takedown          = nv10_graph_takedown;
 128                 engine->graph.channel           = nv10_graph_channel;
 129                 engine->graph.create_context    = nv10_graph_create_context;
 130                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 131                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 132                 engine->graph.load_context      = nv10_graph_load_context;
 133                 engine->graph.unload_context    = nv10_graph_unload_context;
 134                 engine->graph.set_tile_region   = nv10_graph_set_tile_region;
 135                 engine->fifo.channels           = 32;
 136                 engine->fifo.init               = nv10_fifo_init;
 137                 engine->fifo.takedown           = nv04_fifo_fini;
 138                 engine->fifo.disable            = nv04_fifo_disable;
 139                 engine->fifo.enable             = nv04_fifo_enable;
 140                 engine->fifo.reassign           = nv04_fifo_reassign;
 141                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 142                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 143                 engine->fifo.create_context     = nv10_fifo_create_context;
 144                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 145                 engine->fifo.load_context       = nv10_fifo_load_context;
 146                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 147                 engine->display.early_init      = nv04_display_early_init;
 148                 engine->display.late_takedown   = nv04_display_late_takedown;
 149                 engine->display.create          = nv04_display_create;
 150                 engine->display.init            = nv04_display_init;
 151                 engine->display.destroy         = nv04_display_destroy;
 152                 engine->gpio.init               = nouveau_stub_init;
 153                 engine->gpio.takedown           = nouveau_stub_takedown;
 154                 engine->gpio.get                = nv10_gpio_get;
 155                 engine->gpio.set                = nv10_gpio_set;
 156                 engine->gpio.irq_enable         = NULL;
 157                 engine->pm.clock_get            = nv04_pm_clock_get;
 158                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 159                 engine->pm.clock_set            = nv04_pm_clock_set;
 160                 engine->crypt.init              = nouveau_stub_init;
 161                 engine->crypt.takedown          = nouveau_stub_takedown;
 162                 engine->vram.init               = nouveau_mem_detect;
 163                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 164                 break;
 165         case 0x20:
 166                 engine->instmem.init            = nv04_instmem_init;
 167                 engine->instmem.takedown        = nv04_instmem_takedown;
 168                 engine->instmem.suspend         = nv04_instmem_suspend;
 169                 engine->instmem.resume          = nv04_instmem_resume;
 170                 engine->instmem.get             = nv04_instmem_get;
 171                 engine->instmem.put             = nv04_instmem_put;
 172                 engine->instmem.map             = nv04_instmem_map;
 173                 engine->instmem.unmap           = nv04_instmem_unmap;
 174                 engine->instmem.flush           = nv04_instmem_flush;
 175                 engine->mc.init                 = nv04_mc_init;
 176                 engine->mc.takedown             = nv04_mc_takedown;
 177                 engine->timer.init              = nv04_timer_init;
 178                 engine->timer.read              = nv04_timer_read;
 179                 engine->timer.takedown          = nv04_timer_takedown;
 180                 engine->fb.init                 = nv10_fb_init;
 181                 engine->fb.takedown             = nv10_fb_takedown;
 182                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 183                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 184                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 185                 engine->graph.init              = nv20_graph_init;
 186                 engine->graph.takedown          = nv20_graph_takedown;
 187                 engine->graph.channel           = nv10_graph_channel;
 188                 engine->graph.create_context    = nv20_graph_create_context;
 189                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 190                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 191                 engine->graph.load_context      = nv20_graph_load_context;
 192                 engine->graph.unload_context    = nv20_graph_unload_context;
 193                 engine->graph.set_tile_region   = nv20_graph_set_tile_region;
 194                 engine->fifo.channels           = 32;
 195                 engine->fifo.init               = nv10_fifo_init;
 196                 engine->fifo.takedown           = nv04_fifo_fini;
 197                 engine->fifo.disable            = nv04_fifo_disable;
 198                 engine->fifo.enable             = nv04_fifo_enable;
 199                 engine->fifo.reassign           = nv04_fifo_reassign;
 200                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 201                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 202                 engine->fifo.create_context     = nv10_fifo_create_context;
 203                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 204                 engine->fifo.load_context       = nv10_fifo_load_context;
 205                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 206                 engine->display.early_init      = nv04_display_early_init;
 207                 engine->display.late_takedown   = nv04_display_late_takedown;
 208                 engine->display.create          = nv04_display_create;
 209                 engine->display.init            = nv04_display_init;
 210                 engine->display.destroy         = nv04_display_destroy;
 211                 engine->gpio.init               = nouveau_stub_init;
 212                 engine->gpio.takedown           = nouveau_stub_takedown;
 213                 engine->gpio.get                = nv10_gpio_get;
 214                 engine->gpio.set                = nv10_gpio_set;
 215                 engine->gpio.irq_enable         = NULL;
 216                 engine->pm.clock_get            = nv04_pm_clock_get;
 217                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 218                 engine->pm.clock_set            = nv04_pm_clock_set;
 219                 engine->crypt.init              = nouveau_stub_init;
 220                 engine->crypt.takedown          = nouveau_stub_takedown;
 221                 engine->vram.init               = nouveau_mem_detect;
 222                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 223                 break;
 224         case 0x30:
 225                 engine->instmem.init            = nv04_instmem_init;
 226                 engine->instmem.takedown        = nv04_instmem_takedown;
 227                 engine->instmem.suspend         = nv04_instmem_suspend;
 228                 engine->instmem.resume          = nv04_instmem_resume;
 229                 engine->instmem.get             = nv04_instmem_get;
 230                 engine->instmem.put             = nv04_instmem_put;
 231                 engine->instmem.map             = nv04_instmem_map;
 232                 engine->instmem.unmap           = nv04_instmem_unmap;
 233                 engine->instmem.flush           = nv04_instmem_flush;
 234                 engine->mc.init                 = nv04_mc_init;
 235                 engine->mc.takedown             = nv04_mc_takedown;
 236                 engine->timer.init              = nv04_timer_init;
 237                 engine->timer.read              = nv04_timer_read;
 238                 engine->timer.takedown          = nv04_timer_takedown;
 239                 engine->fb.init                 = nv30_fb_init;
 240                 engine->fb.takedown             = nv30_fb_takedown;
 241                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 242                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 243                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 244                 engine->graph.init              = nv30_graph_init;
 245                 engine->graph.takedown          = nv20_graph_takedown;
 246                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 247                 engine->graph.channel           = nv10_graph_channel;
 248                 engine->graph.create_context    = nv20_graph_create_context;
 249                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 250                 engine->graph.load_context      = nv20_graph_load_context;
 251                 engine->graph.unload_context    = nv20_graph_unload_context;
 252                 engine->graph.set_tile_region   = nv20_graph_set_tile_region;
 253                 engine->fifo.channels           = 32;
 254                 engine->fifo.init               = nv10_fifo_init;
 255                 engine->fifo.takedown           = nv04_fifo_fini;
 256                 engine->fifo.disable            = nv04_fifo_disable;
 257                 engine->fifo.enable             = nv04_fifo_enable;
 258                 engine->fifo.reassign           = nv04_fifo_reassign;
 259                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 260                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 261                 engine->fifo.create_context     = nv10_fifo_create_context;
 262                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 263                 engine->fifo.load_context       = nv10_fifo_load_context;
 264                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 265                 engine->display.early_init      = nv04_display_early_init;
 266                 engine->display.late_takedown   = nv04_display_late_takedown;
 267                 engine->display.create          = nv04_display_create;
 268                 engine->display.init            = nv04_display_init;
 269                 engine->display.destroy         = nv04_display_destroy;
 270                 engine->gpio.init               = nouveau_stub_init;
 271                 engine->gpio.takedown           = nouveau_stub_takedown;
 272                 engine->gpio.get                = nv10_gpio_get;
 273                 engine->gpio.set                = nv10_gpio_set;
 274                 engine->gpio.irq_enable         = NULL;
 275                 engine->pm.clock_get            = nv04_pm_clock_get;
 276                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 277                 engine->pm.clock_set            = nv04_pm_clock_set;
 278                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 279                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 280                 engine->crypt.init              = nouveau_stub_init;
 281                 engine->crypt.takedown          = nouveau_stub_takedown;
 282                 engine->vram.init               = nouveau_mem_detect;
 283                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 284                 break;
 285         case 0x40:
 286         case 0x60:
 287                 engine->instmem.init            = nv04_instmem_init;
 288                 engine->instmem.takedown        = nv04_instmem_takedown;
 289                 engine->instmem.suspend         = nv04_instmem_suspend;
 290                 engine->instmem.resume          = nv04_instmem_resume;
 291                 engine->instmem.get             = nv04_instmem_get;
 292                 engine->instmem.put             = nv04_instmem_put;
 293                 engine->instmem.map             = nv04_instmem_map;
 294                 engine->instmem.unmap           = nv04_instmem_unmap;
 295                 engine->instmem.flush           = nv04_instmem_flush;
 296                 engine->mc.init                 = nv40_mc_init;
 297                 engine->mc.takedown             = nv40_mc_takedown;
 298                 engine->timer.init              = nv04_timer_init;
 299                 engine->timer.read              = nv04_timer_read;
 300                 engine->timer.takedown          = nv04_timer_takedown;
 301                 engine->fb.init                 = nv40_fb_init;
 302                 engine->fb.takedown             = nv40_fb_takedown;
 303                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 304                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 305                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 306                 engine->graph.init              = nv40_graph_init;
 307                 engine->graph.takedown          = nv40_graph_takedown;
 308                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 309                 engine->graph.channel           = nv40_graph_channel;
 310                 engine->graph.create_context    = nv40_graph_create_context;
 311                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 312                 engine->graph.load_context      = nv40_graph_load_context;
 313                 engine->graph.unload_context    = nv40_graph_unload_context;
 314                 engine->graph.set_tile_region   = nv40_graph_set_tile_region;
 315                 engine->fifo.channels           = 32;
 316                 engine->fifo.init               = nv40_fifo_init;
 317                 engine->fifo.takedown           = nv04_fifo_fini;
 318                 engine->fifo.disable            = nv04_fifo_disable;
 319                 engine->fifo.enable             = nv04_fifo_enable;
 320                 engine->fifo.reassign           = nv04_fifo_reassign;
 321                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 322                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 323                 engine->fifo.create_context     = nv40_fifo_create_context;
 324                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 325                 engine->fifo.load_context       = nv40_fifo_load_context;
 326                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 327                 engine->display.early_init      = nv04_display_early_init;
 328                 engine->display.late_takedown   = nv04_display_late_takedown;
 329                 engine->display.create          = nv04_display_create;
 330                 engine->display.init            = nv04_display_init;
 331                 engine->display.destroy         = nv04_display_destroy;
 332                 engine->gpio.init               = nouveau_stub_init;
 333                 engine->gpio.takedown           = nouveau_stub_takedown;
 334                 engine->gpio.get                = nv10_gpio_get;
 335                 engine->gpio.set                = nv10_gpio_set;
 336                 engine->gpio.irq_enable         = NULL;
 337                 engine->pm.clock_get            = nv04_pm_clock_get;
 338                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 339                 engine->pm.clock_set            = nv04_pm_clock_set;
 340                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 341                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 342                 engine->pm.temp_get             = nv40_temp_get;
 343                 engine->crypt.init              = nouveau_stub_init;
 344                 engine->crypt.takedown          = nouveau_stub_takedown;
 345                 engine->vram.init               = nouveau_mem_detect;
 346                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 347                 break;
 348         case 0x50:
 349         case 0x80: /* gotta love NVIDIA's consistency.. */
 350         case 0x90:
 351         case 0xA0:
 352                 engine->instmem.init            = nv50_instmem_init;
 353                 engine->instmem.takedown        = nv50_instmem_takedown;
 354                 engine->instmem.suspend         = nv50_instmem_suspend;
 355                 engine->instmem.resume          = nv50_instmem_resume;
 356                 engine->instmem.get             = nv50_instmem_get;
 357                 engine->instmem.put             = nv50_instmem_put;
 358                 engine->instmem.map             = nv50_instmem_map;
 359                 engine->instmem.unmap           = nv50_instmem_unmap;
 360                 if (dev_priv->chipset == 0x50)
 361                         engine->instmem.flush   = nv50_instmem_flush;
 362                 else
 363                         engine->instmem.flush   = nv84_instmem_flush;
 364                 engine->mc.init                 = nv50_mc_init;
 365                 engine->mc.takedown             = nv50_mc_takedown;
 366                 engine->timer.init              = nv04_timer_init;
 367                 engine->timer.read              = nv04_timer_read;
 368                 engine->timer.takedown          = nv04_timer_takedown;
 369                 engine->fb.init                 = nv50_fb_init;
 370                 engine->fb.takedown             = nv50_fb_takedown;
 371                 engine->graph.init              = nv50_graph_init;
 372                 engine->graph.takedown          = nv50_graph_takedown;
 373                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 374                 engine->graph.channel           = nv50_graph_channel;
 375                 engine->graph.create_context    = nv50_graph_create_context;
 376                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 377                 engine->graph.load_context      = nv50_graph_load_context;
 378                 engine->graph.unload_context    = nv50_graph_unload_context;
 379                 if (dev_priv->chipset == 0x50 ||
 380                     dev_priv->chipset == 0xac)
 381                         engine->graph.tlb_flush = nv50_graph_tlb_flush;
 382                 else
 383                         engine->graph.tlb_flush = nv84_graph_tlb_flush;
 384                 engine->fifo.channels           = 128;
 385                 engine->fifo.init               = nv50_fifo_init;
 386                 engine->fifo.takedown           = nv50_fifo_takedown;
 387                 engine->fifo.disable            = nv04_fifo_disable;
 388                 engine->fifo.enable             = nv04_fifo_enable;
 389                 engine->fifo.reassign           = nv04_fifo_reassign;
 390                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 391                 engine->fifo.create_context     = nv50_fifo_create_context;
 392                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 393                 engine->fifo.load_context       = nv50_fifo_load_context;
 394                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 395                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 396                 engine->display.early_init      = nv50_display_early_init;
 397                 engine->display.late_takedown   = nv50_display_late_takedown;
 398                 engine->display.create          = nv50_display_create;
 399                 engine->display.init            = nv50_display_init;
 400                 engine->display.destroy         = nv50_display_destroy;
 401                 engine->gpio.init               = nv50_gpio_init;
 402                 engine->gpio.takedown           = nv50_gpio_fini;
 403                 engine->gpio.get                = nv50_gpio_get;
 404                 engine->gpio.set                = nv50_gpio_set;
 405                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 406                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 407                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 408                 switch (dev_priv->chipset) {
 409                 case 0x84:
 410                 case 0x86:
 411                 case 0x92:
 412                 case 0x94:
 413                 case 0x96:
 414                 case 0x98:
 415                 case 0xa0:
 416                 case 0xaa:
 417                 case 0xac:
 418                 case 0x50:
 419                         engine->pm.clock_get    = nv50_pm_clock_get;
 420                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 421                         engine->pm.clock_set    = nv50_pm_clock_set;
 422                         break;
 423                 default:
 424                         engine->pm.clock_get    = nva3_pm_clock_get;
 425                         engine->pm.clock_pre    = nva3_pm_clock_pre;
 426                         engine->pm.clock_set    = nva3_pm_clock_set;
 427                         break;
 428                 }
 429                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 430                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 431                 if (dev_priv->chipset >= 0x84)
 432                         engine->pm.temp_get     = nv84_temp_get;
 433                 else
 434                         engine->pm.temp_get     = nv40_temp_get;
 435                 switch (dev_priv->chipset) {
 436                 case 0x84:
 437                 case 0x86:
 438                 case 0x92:
 439                 case 0x94:
 440                 case 0x96:
 441                 case 0xa0:
 442                         engine->crypt.init      = nv84_crypt_init;
 443                         engine->crypt.takedown  = nv84_crypt_fini;
 444                         engine->crypt.create_context = nv84_crypt_create_context;
 445                         engine->crypt.destroy_context = nv84_crypt_destroy_context;
 446                         engine->crypt.tlb_flush = nv84_crypt_tlb_flush;
 447                         break;
 448                 default:
 449                         engine->crypt.init      = nouveau_stub_init;
 450                         engine->crypt.takedown  = nouveau_stub_takedown;
 451                         break;
 452                 }
 453                 engine->vram.init               = nv50_vram_init;
 454                 engine->vram.get                = nv50_vram_new;
 455                 engine->vram.put                = nv50_vram_del;
 456                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 457                 break;
 458         case 0xC0:
 459                 engine->instmem.init            = nvc0_instmem_init;
 460                 engine->instmem.takedown        = nvc0_instmem_takedown;
 461                 engine->instmem.suspend         = nvc0_instmem_suspend;
 462                 engine->instmem.resume          = nvc0_instmem_resume;
 463                 engine->instmem.get             = nv50_instmem_get;
 464                 engine->instmem.put             = nv50_instmem_put;
 465                 engine->instmem.map             = nv50_instmem_map;
 466                 engine->instmem.unmap           = nv50_instmem_unmap;
 467                 engine->instmem.flush           = nv84_instmem_flush;
 468                 engine->mc.init                 = nv50_mc_init;
 469                 engine->mc.takedown             = nv50_mc_takedown;
 470                 engine->timer.init              = nv04_timer_init;
 471                 engine->timer.read              = nv04_timer_read;
 472                 engine->timer.takedown          = nv04_timer_takedown;
 473                 engine->fb.init                 = nvc0_fb_init;
 474                 engine->fb.takedown             = nvc0_fb_takedown;
 475                 engine->graph.init              = nvc0_graph_init;
 476                 engine->graph.takedown          = nvc0_graph_takedown;
 477                 engine->graph.fifo_access       = nvc0_graph_fifo_access;
 478                 engine->graph.channel           = nvc0_graph_channel;
 479                 engine->graph.create_context    = nvc0_graph_create_context;
 480                 engine->graph.destroy_context   = nvc0_graph_destroy_context;
 481                 engine->graph.load_context      = nvc0_graph_load_context;
 482                 engine->graph.unload_context    = nvc0_graph_unload_context;
 483                 engine->fifo.channels           = 128;
 484                 engine->fifo.init               = nvc0_fifo_init;
 485                 engine->fifo.takedown           = nvc0_fifo_takedown;
 486                 engine->fifo.disable            = nvc0_fifo_disable;
 487                 engine->fifo.enable             = nvc0_fifo_enable;
 488                 engine->fifo.reassign           = nvc0_fifo_reassign;
 489                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 490                 engine->fifo.create_context     = nvc0_fifo_create_context;
 491                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 492                 engine->fifo.load_context       = nvc0_fifo_load_context;
 493                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 494                 engine->display.early_init      = nv50_display_early_init;
 495                 engine->display.late_takedown   = nv50_display_late_takedown;
 496                 engine->display.create          = nv50_display_create;
 497                 engine->display.init            = nv50_display_init;
 498                 engine->display.destroy         = nv50_display_destroy;
 499                 engine->gpio.init               = nv50_gpio_init;
 500                 engine->gpio.takedown           = nouveau_stub_takedown;
 501                 engine->gpio.get                = nv50_gpio_get;
 502                 engine->gpio.set                = nv50_gpio_set;
 503                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 504                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 505                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 506                 engine->crypt.init              = nouveau_stub_init;
 507                 engine->crypt.takedown          = nouveau_stub_takedown;
 508                 engine->vram.init               = nvc0_vram_init;
 509                 engine->vram.get                = nvc0_vram_new;
 510                 engine->vram.put                = nv50_vram_del;
 511                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 512                 break;
 513         default:
 514                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 515                 return 1;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static unsigned int
 522 nouveau_vga_set_decode(void *priv, bool state)
 523 {
 524         struct drm_device *dev = priv;
 525         struct drm_nouveau_private *dev_priv = dev->dev_private;
 526
 527         if (dev_priv->chipset >= 0x40)
 528                 nv_wr32(dev, 0x88054, state);
 529         else
 530                 nv_wr32(dev, 0x1854, state);
 531
 532         if (state)
 533                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 534                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 535         else
 536                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 537 }
 538
 539 static int
 540 nouveau_card_init_channel(struct drm_device *dev)
 541 {
 542         struct drm_nouveau_private *dev_priv = dev->dev_private;
 543         int ret;
 544
 545         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 546                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 547         if (ret)
 548                 return ret;
 549
 550         mutex_unlock(&dev_priv->channel->mutex);
 551         return 0;
 552 }
 553
 554 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 555                                          enum vga_switcheroo_state state)
 556 {
 557         struct drm_device *dev = pci_get_drvdata(pdev);
 558         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 559         if (state == VGA_SWITCHEROO_ON) {
 560                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 561                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 562                 nouveau_pci_resume(pdev);
 563                 drm_kms_helper_poll_enable(dev);
 564                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 565         } else {
 566                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 567                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 568                 drm_kms_helper_poll_disable(dev);
 569                 nouveau_pci_suspend(pdev, pmm);
 570                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 571         }
 572 }
 573
 574 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 575 {
 576         struct drm_device *dev = pci_get_drvdata(pdev);
 577         nouveau_fbcon_output_poll_changed(dev);
 578 }
 579
 580 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 581 {
 582         struct drm_device *dev = pci_get_drvdata(pdev);
 583         bool can_switch;
 584
 585         spin_lock(&dev->count_lock);
 586         can_switch = (dev->open_count == 0);
 587         spin_unlock(&dev->count_lock);
 588         return can_switch;
 589 }
 590
 591 int
 592 nouveau_card_init(struct drm_device *dev)
 593 {
 594         struct drm_nouveau_private *dev_priv = dev->dev_private;
 595         struct nouveau_engine *engine;
 596         int ret;
 597
 598         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 599         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 600                                        nouveau_switcheroo_reprobe,
 601                                        nouveau_switcheroo_can_switch);
 602
 603         /* Initialise internal driver API hooks */
 604         ret = nouveau_init_engine_ptrs(dev);
 605         if (ret)
 606                 goto out;
 607         engine = &dev_priv->engine;
 608         spin_lock_init(&dev_priv->channels.lock);
 609         spin_lock_init(&dev_priv->tile.lock);
 610         spin_lock_init(&dev_priv->context_switch_lock);
 611
 612         /* Make the CRTCs and I2C buses accessible */
 613         ret = engine->display.early_init(dev);
 614         if (ret)
 615                 goto out;
 616
 617         /* Parse BIOS tables / Run init tables if card not POSTed */
 618         ret = nouveau_bios_init(dev);
 619         if (ret)
 620                 goto out_display_early;
 621
 622         nouveau_pm_init(dev);
 623
 624         ret = nouveau_mem_vram_init(dev);
 625         if (ret)
 626                 goto out_bios;
 627
 628         ret = nouveau_gpuobj_init(dev);
 629         if (ret)
 630                 goto out_vram;
 631
 632         ret = engine->instmem.init(dev);
 633         if (ret)
 634                 goto out_gpuobj;
 635
 636         ret = nouveau_mem_gart_init(dev);
 637         if (ret)
 638                 goto out_instmem;
 639
 640         /* PMC */
 641         ret = engine->mc.init(dev);
 642         if (ret)
 643                 goto out_gart;
 644
 645         /* PGPIO */
 646         ret = engine->gpio.init(dev);
 647         if (ret)
 648                 goto out_mc;
 649
 650         /* PTIMER */
 651         ret = engine->timer.init(dev);
 652         if (ret)
 653                 goto out_gpio;
 654
 655         /* PFB */
 656         ret = engine->fb.init(dev);
 657         if (ret)
 658                 goto out_timer;
 659
 660         if (nouveau_noaccel)
 661                 engine->graph.accel_blocked = true;
 662         else {
 663                 /* PGRAPH */
 664                 ret = engine->graph.init(dev);
 665                 if (ret)
 666                         goto out_fb;
 667
 668                 /* PCRYPT */
 669                 ret = engine->crypt.init(dev);
 670                 if (ret)
 671                         goto out_graph;
 672
 673                 /* PFIFO */
 674                 ret = engine->fifo.init(dev);
 675                 if (ret)
 676                         goto out_crypt;
 677         }
 678
 679         ret = engine->display.create(dev);
 680         if (ret)
 681                 goto out_fifo;
 682
 683         ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
 684         if (ret)
 685                 goto out_vblank;
 686
 687         ret = nouveau_irq_init(dev);
 688         if (ret)
 689                 goto out_vblank;
 690
 691         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 692
 693         if (!engine->graph.accel_blocked) {
 694                 ret = nouveau_fence_init(dev);
 695                 if (ret)
 696                         goto out_irq;
 697
 698                 ret = nouveau_card_init_channel(dev);
 699                 if (ret)
 700                         goto out_fence;
 701         }
 702
 703         nouveau_fbcon_init(dev);
 704         drm_kms_helper_poll_init(dev);
 705         return 0;
 706
 707 out_fence:
 708         nouveau_fence_fini(dev);
 709 out_irq:
 710         nouveau_irq_fini(dev);
 711 out_vblank:
 712         drm_vblank_cleanup(dev);
 713         engine->display.destroy(dev);
 714 out_fifo:
 715         if (!nouveau_noaccel)
 716                 engine->fifo.takedown(dev);
 717 out_crypt:
 718         if (!nouveau_noaccel)
 719                 engine->crypt.takedown(dev);
 720 out_graph:
 721         if (!nouveau_noaccel)
 722                 engine->graph.takedown(dev);
 723 out_fb:
 724         engine->fb.takedown(dev);
 725 out_timer:
 726         engine->timer.takedown(dev);
 727 out_gpio:
 728         engine->gpio.takedown(dev);
 729 out_mc:
 730         engine->mc.takedown(dev);
 731 out_gart:
 732         nouveau_mem_gart_fini(dev);
 733 out_instmem:
 734         engine->instmem.takedown(dev);
 735 out_gpuobj:
 736         nouveau_gpuobj_takedown(dev);
 737 out_vram:
 738         nouveau_mem_vram_fini(dev);
 739 out_bios:
 740         nouveau_pm_fini(dev);
 741         nouveau_bios_takedown(dev);
 742 out_display_early:
 743         engine->display.late_takedown(dev);
 744 out:
 745         vga_client_register(dev->pdev, NULL, NULL, NULL);
 746         return ret;
 747 }
 748
 749 static void nouveau_card_takedown(struct drm_device *dev)
 750 {
 751         struct drm_nouveau_private *dev_priv = dev->dev_private;
 752         struct nouveau_engine *engine = &dev_priv->engine;
 753
 754         if (!engine->graph.accel_blocked) {
 755                 nouveau_fence_fini(dev);
 756                 nouveau_channel_put_unlocked(&dev_priv->channel);
 757         }
 758
 759         if (!nouveau_noaccel) {
 760                 engine->fifo.takedown(dev);
 761                 engine->crypt.takedown(dev);
 762                 engine->graph.takedown(dev);
 763         }
 764         engine->fb.takedown(dev);
 765         engine->timer.takedown(dev);
 766         engine->gpio.takedown(dev);
 767         engine->mc.takedown(dev);
 768         engine->display.late_takedown(dev);
 769
 770         mutex_lock(&dev->struct_mutex);
 771         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 772         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 773         mutex_unlock(&dev->struct_mutex);
 774         nouveau_mem_gart_fini(dev);
 775
 776         engine->instmem.takedown(dev);
 777         nouveau_gpuobj_takedown(dev);
 778         nouveau_mem_vram_fini(dev);
 779
 780         nouveau_irq_fini(dev);
 781         drm_vblank_cleanup(dev);
 782
 783         nouveau_pm_fini(dev);
 784         nouveau_bios_takedown(dev);
 785
 786         vga_client_register(dev->pdev, NULL, NULL, NULL);
 787 }
 788
 789 /* here a client dies, release the stuff that was allocated for its
 790  * file_priv */
 791 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 792 {
 793         nouveau_channel_cleanup(dev, file_priv);
 794 }
 795
 796 /* first module load, setup the mmio/fb mapping */
 797 /* KMS: we need mmio at load time, not when the first drm client opens. */
 798 int nouveau_firstopen(struct drm_device *dev)
 799 {
 800         return 0;
 801 }
 802
 803 /* if we have an OF card, copy vbios to RAMIN */
 804 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 805 {
 806 #if defined(__powerpc__)
 807         int size, i;
 808         const uint32_t *bios;
 809         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 810         if (!dn) {
 811                 NV_INFO(dev, "Unable to get the OF node\n");
 812                 return;
 813         }
 814
 815         bios = of_get_property(dn, "NVDA,BMP", &size);
 816         if (bios) {
 817                 for (i = 0; i < size; i += 4)
 818                         nv_wi32(dev, i, bios[i/4]);
 819                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 820         } else {
 821                 NV_INFO(dev, "Unable to get the OF bios\n");
 822         }
 823 #endif
 824 }
 825
 826 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 827 {
 828         struct pci_dev *pdev = dev->pdev;
 829         struct apertures_struct *aper = alloc_apertures(3);
 830         if (!aper)
 831                 return NULL;
 832
 833         aper->ranges[0].base = pci_resource_start(pdev, 1);
 834         aper->ranges[0].size = pci_resource_len(pdev, 1);
 835         aper->count = 1;
 836
 837         if (pci_resource_len(pdev, 2)) {
 838                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 839                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 840                 aper->count++;
 841         }
 842
 843         if (pci_resource_len(pdev, 3)) {
 844                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 845                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 846                 aper->count++;
 847         }
 848
 849         return aper;
 850 }
 851
 852 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 853 {
 854         struct drm_nouveau_private *dev_priv = dev->dev_private;
 855         bool primary = false;
 856         dev_priv->apertures = nouveau_get_apertures(dev);
 857         if (!dev_priv->apertures)
 858                 return -ENOMEM;
 859
 860 #ifdef CONFIG_X86
 861         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 862 #endif
 863
 864         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 865         return 0;
 866 }
 867
 868 int nouveau_load(struct drm_device *dev, unsigned long flags)
 869 {
 870         struct drm_nouveau_private *dev_priv;
 871         uint32_t reg0;
 872         resource_size_t mmio_start_offs;
 873         int ret;
 874
 875         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 876         if (!dev_priv) {
 877                 ret = -ENOMEM;
 878                 goto err_out;
 879         }
 880         dev->dev_private = dev_priv;
 881         dev_priv->dev = dev;
 882
 883         dev_priv->flags = flags & NOUVEAU_FLAGS;
 884
 885         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 886                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 887
 888         /* resource 0 is mmio regs */
 889         /* resource 1 is linear FB */
 890         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 891         /* resource 6 is bios */
 892
 893         /* map the mmio regs */
 894         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 895         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 896         if (!dev_priv->mmio) {
 897                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 898                          "Please report your setup to " DRIVER_EMAIL "\n");
 899                 ret = -EINVAL;
 900                 goto err_priv;
 901         }
 902         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 903                                         (unsigned long long)mmio_start_offs);
 904
 905 #ifdef __BIG_ENDIAN
 906         /* Put the card in BE mode if it's not */
 907         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 908                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 909
 910         DRM_MEMORYBARRIER();
 911 #endif
 912
 913         /* Time to determine the card architecture */
 914         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 915
 916         /* We're dealing with >=NV10 */
 917         if ((reg0 & 0x0f000000) > 0) {
 918                 /* Bit 27-20 contain the architecture in hex */
 919                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 920         /* NV04 or NV05 */
 921         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 922                 if (reg0 & 0x00f00000)
 923                         dev_priv->chipset = 0x05;
 924                 else
 925                         dev_priv->chipset = 0x04;
 926         } else
 927                 dev_priv->chipset = 0xff;
 928
 929         switch (dev_priv->chipset & 0xf0) {
 930         case 0x00:
 931         case 0x10:
 932         case 0x20:
 933         case 0x30:
 934                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 935                 break;
 936         case 0x40:
 937         case 0x60:
 938                 dev_priv->card_type = NV_40;
 939                 break;
 940         case 0x50:
 941         case 0x80:
 942         case 0x90:
 943         case 0xa0:
 944                 dev_priv->card_type = NV_50;
 945                 break;
 946         case 0xc0:
 947                 dev_priv->card_type = NV_C0;
 948                 break;
 949         default:
 950                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 951                 ret = -EINVAL;
 952                 goto err_mmio;
 953         }
 954
 955         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 956                 dev_priv->card_type, reg0);
 957
 958         ret = nouveau_remove_conflicting_drivers(dev);
 959         if (ret)
 960                 goto err_mmio;
 961
 962         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
 963         if (dev_priv->card_type >= NV_40) {
 964                 int ramin_bar = 2;
 965                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 966                         ramin_bar = 3;
 967
 968                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 969                 dev_priv->ramin =
 970                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 971                                 dev_priv->ramin_size);
 972                 if (!dev_priv->ramin) {
 973                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 974                         ret = -ENOMEM;
 975                         goto err_mmio;
 976                 }
 977         } else {
 978                 dev_priv->ramin_size = 1 * 1024 * 1024;
 979                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 980                                           dev_priv->ramin_size);
 981                 if (!dev_priv->ramin) {
 982                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 983                         ret = -ENOMEM;
 984                         goto err_mmio;
 985                 }
 986         }
 987
 988         nouveau_OF_copy_vbios_to_ramin(dev);
 989
 990         /* Special flags */
 991         if (dev->pci_device == 0x01a0)
 992                 dev_priv->flags |= NV_NFORCE;
 993         else if (dev->pci_device == 0x01f0)
 994                 dev_priv->flags |= NV_NFORCE2;
 995
 996         /* For kernel modesetting, init card now and bring up fbcon */
 997         ret = nouveau_card_init(dev);
 998         if (ret)
 999                 goto err_ramin;
1000
1001         return 0;
1002
1003 err_ramin:
1004         iounmap(dev_priv->ramin);
1005 err_mmio:
1006         iounmap(dev_priv->mmio);
1007 err_priv:
1008         kfree(dev_priv);
1009         dev->dev_private = NULL;
1010 err_out:
1011         return ret;
1012 }
1013
1014 void nouveau_lastclose(struct drm_device *dev)
1015 {
1016         vga_switcheroo_process_delayed_switch();
1017 }
1018
1019 int nouveau_unload(struct drm_device *dev)
1020 {
1021         struct drm_nouveau_private *dev_priv = dev->dev_private;
1022         struct nouveau_engine *engine = &dev_priv->engine;
1023
1024         drm_kms_helper_poll_fini(dev);
1025         nouveau_fbcon_fini(dev);
1026         engine->display.destroy(dev);
1027         nouveau_card_takedown(dev);
1028
1029         iounmap(dev_priv->mmio);
1030         iounmap(dev_priv->ramin);
1031
1032         kfree(dev_priv);
1033         dev->dev_private = NULL;
1034         return 0;
1035 }
1036
1037 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1038                                                 struct drm_file *file_priv)
1039 {
1040         struct drm_nouveau_private *dev_priv = dev->dev_private;
1041         struct drm_nouveau_getparam *getparam = data;
1042
1043         switch (getparam->param) {
1044         case NOUVEAU_GETPARAM_CHIPSET_ID:
1045                 getparam->value = dev_priv->chipset;
1046                 break;
1047         case NOUVEAU_GETPARAM_PCI_VENDOR:
1048                 getparam->value = dev->pci_vendor;
1049                 break;
1050         case NOUVEAU_GETPARAM_PCI_DEVICE:
1051                 getparam->value = dev->pci_device;
1052                 break;
1053         case NOUVEAU_GETPARAM_BUS_TYPE:
1054                 if (drm_pci_device_is_agp(dev))
1055                         getparam->value = NV_AGP;
1056                 else if (drm_pci_device_is_pcie(dev))
1057                         getparam->value = NV_PCIE;
1058                 else
1059                         getparam->value = NV_PCI;
1060                 break;
1061         case NOUVEAU_GETPARAM_FB_SIZE:
1062                 getparam->value = dev_priv->fb_available_size;
1063                 break;
1064         case NOUVEAU_GETPARAM_AGP_SIZE:
1065                 getparam->value = dev_priv->gart_info.aper_size;
1066                 break;
1067         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1068                 getparam->value = 0; /* deprecated */
1069                 break;
1070         case NOUVEAU_GETPARAM_PTIMER_TIME:
1071                 getparam->value = dev_priv->engine.timer.read(dev);
1072                 break;
1073         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1074                 getparam->value = 1;
1075                 break;
1076         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1077                 getparam->value = 1;
1078                 break;
1079         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1080                 /* NV40 and NV50 versions are quite different, but register
1081                  * address is the same. User is supposed to know the card
1082                  * family anyway... */
1083                 if (dev_priv->chipset >= 0x40) {
1084                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1085                         break;
1086                 }
1087                 /* FALLTHRU */
1088         default:
1089                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1090                 return -EINVAL;
1091         }
1092
1093         return 0;
1094 }
1095
1096 int
1097 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1098                        struct drm_file *file_priv)
1099 {
1100         struct drm_nouveau_setparam *setparam = data;
1101
1102         switch (setparam->param) {
1103         default:
1104                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1105                 return -EINVAL;
1106         }
1107
1108         return 0;
1109 }
1110
1111 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1112 bool
1113 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1114                 uint32_t reg, uint32_t mask, uint32_t val)
1115 {
1116         struct drm_nouveau_private *dev_priv = dev->dev_private;
1117         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1118         uint64_t start = ptimer->read(dev);
1119
1120         do {
1121                 if ((nv_rd32(dev, reg) & mask) == val)
1122                         return true;
1123         } while (ptimer->read(dev) - start < timeout);
1124
1125         return false;
1126 }
1127
1128 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1129 bool
1130 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1131                 uint32_t reg, uint32_t mask, uint32_t val)
1132 {
1133         struct drm_nouveau_private *dev_priv = dev->dev_private;
1134         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1135         uint64_t start = ptimer->read(dev);
1136
1137         do {
1138                 if ((nv_rd32(dev, reg) & mask) != val)
1139                         return true;
1140         } while (ptimer->read(dev) - start < timeout);
1141
1142         return false;
1143 }
1144
1145 /* Waits for PGRAPH to go completely idle */
1146 bool nouveau_wait_for_idle(struct drm_device *dev)
1147 {
1148         struct drm_nouveau_private *dev_priv = dev->dev_private;
1149         uint32_t mask = ~0;
1150
1151         if (dev_priv->card_type == NV_40)
1152                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1153
1154         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1155                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1156                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1157                 return false;
1158         }
1159
1160         return true;
1161 }
1162