drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nv50_display.h"
  39
  40 static void nouveau_stub_takedown(struct drm_device *dev) {}
  41
  42 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  43 {
  44         struct drm_nouveau_private *dev_priv = dev->dev_private;
  45         struct nouveau_engine *engine = &dev_priv->engine;
  46
  47         switch (dev_priv->chipset & 0xf0) {
  48         case 0x00:
  49                 engine->instmem.init            = nv04_instmem_init;
  50                 engine->instmem.takedown        = nv04_instmem_takedown;
  51                 engine->instmem.suspend         = nv04_instmem_suspend;
  52                 engine->instmem.resume          = nv04_instmem_resume;
  53                 engine->instmem.populate        = nv04_instmem_populate;
  54                 engine->instmem.clear           = nv04_instmem_clear;
  55                 engine->instmem.bind            = nv04_instmem_bind;
  56                 engine->instmem.unbind          = nv04_instmem_unbind;
  57                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  58                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  59                 engine->mc.init                 = nv04_mc_init;
  60                 engine->mc.takedown             = nv04_mc_takedown;
  61                 engine->timer.init              = nv04_timer_init;
  62                 engine->timer.read              = nv04_timer_read;
  63                 engine->timer.takedown          = nv04_timer_takedown;
  64                 engine->fb.init                 = nv04_fb_init;
  65                 engine->fb.takedown             = nv04_fb_takedown;
  66                 engine->graph.grclass           = nv04_graph_grclass;
  67                 engine->graph.init              = nv04_graph_init;
  68                 engine->graph.takedown          = nv04_graph_takedown;
  69                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  70                 engine->graph.channel           = nv04_graph_channel;
  71                 engine->graph.create_context    = nv04_graph_create_context;
  72                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  73                 engine->graph.load_context      = nv04_graph_load_context;
  74                 engine->graph.unload_context    = nv04_graph_unload_context;
  75                 engine->fifo.channels           = 16;
  76                 engine->fifo.init               = nv04_fifo_init;
  77                 engine->fifo.takedown           = nouveau_stub_takedown;
  78                 engine->fifo.disable            = nv04_fifo_disable;
  79                 engine->fifo.enable             = nv04_fifo_enable;
  80                 engine->fifo.reassign           = nv04_fifo_reassign;
  81                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
  82                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  83                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  84                 engine->fifo.create_context     = nv04_fifo_create_context;
  85                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  86                 engine->fifo.load_context       = nv04_fifo_load_context;
  87                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  88                 break;
  89         case 0x10:
  90                 engine->instmem.init            = nv04_instmem_init;
  91                 engine->instmem.takedown        = nv04_instmem_takedown;
  92                 engine->instmem.suspend         = nv04_instmem_suspend;
  93                 engine->instmem.resume          = nv04_instmem_resume;
  94                 engine->instmem.populate        = nv04_instmem_populate;
  95                 engine->instmem.clear           = nv04_instmem_clear;
  96                 engine->instmem.bind            = nv04_instmem_bind;
  97                 engine->instmem.unbind          = nv04_instmem_unbind;
  98                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  99                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 100                 engine->mc.init                 = nv04_mc_init;
 101                 engine->mc.takedown             = nv04_mc_takedown;
 102                 engine->timer.init              = nv04_timer_init;
 103                 engine->timer.read              = nv04_timer_read;
 104                 engine->timer.takedown          = nv04_timer_takedown;
 105                 engine->fb.init                 = nv10_fb_init;
 106                 engine->fb.takedown             = nv10_fb_takedown;
 107                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 108                 engine->graph.grclass           = nv10_graph_grclass;
 109                 engine->graph.init              = nv10_graph_init;
 110                 engine->graph.takedown          = nv10_graph_takedown;
 111                 engine->graph.channel           = nv10_graph_channel;
 112                 engine->graph.create_context    = nv10_graph_create_context;
 113                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 114                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 115                 engine->graph.load_context      = nv10_graph_load_context;
 116                 engine->graph.unload_context    = nv10_graph_unload_context;
 117                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 118                 engine->fifo.channels           = 32;
 119                 engine->fifo.init               = nv10_fifo_init;
 120                 engine->fifo.takedown           = nouveau_stub_takedown;
 121                 engine->fifo.disable            = nv04_fifo_disable;
 122                 engine->fifo.enable             = nv04_fifo_enable;
 123                 engine->fifo.reassign           = nv04_fifo_reassign;
 124                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 125                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 126                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 127                 engine->fifo.create_context     = nv10_fifo_create_context;
 128                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 129                 engine->fifo.load_context       = nv10_fifo_load_context;
 130                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 131                 break;
 132         case 0x20:
 133                 engine->instmem.init            = nv04_instmem_init;
 134                 engine->instmem.takedown        = nv04_instmem_takedown;
 135                 engine->instmem.suspend         = nv04_instmem_suspend;
 136                 engine->instmem.resume          = nv04_instmem_resume;
 137                 engine->instmem.populate        = nv04_instmem_populate;
 138                 engine->instmem.clear           = nv04_instmem_clear;
 139                 engine->instmem.bind            = nv04_instmem_bind;
 140                 engine->instmem.unbind          = nv04_instmem_unbind;
 141                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 142                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 143                 engine->mc.init                 = nv04_mc_init;
 144                 engine->mc.takedown             = nv04_mc_takedown;
 145                 engine->timer.init              = nv04_timer_init;
 146                 engine->timer.read              = nv04_timer_read;
 147                 engine->timer.takedown          = nv04_timer_takedown;
 148                 engine->fb.init                 = nv10_fb_init;
 149                 engine->fb.takedown             = nv10_fb_takedown;
 150                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 151                 engine->graph.grclass           = nv20_graph_grclass;
 152                 engine->graph.init              = nv20_graph_init;
 153                 engine->graph.takedown          = nv20_graph_takedown;
 154                 engine->graph.channel           = nv10_graph_channel;
 155                 engine->graph.create_context    = nv20_graph_create_context;
 156                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 157                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 158                 engine->graph.load_context      = nv20_graph_load_context;
 159                 engine->graph.unload_context    = nv20_graph_unload_context;
 160                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 161                 engine->fifo.channels           = 32;
 162                 engine->fifo.init               = nv10_fifo_init;
 163                 engine->fifo.takedown           = nouveau_stub_takedown;
 164                 engine->fifo.disable            = nv04_fifo_disable;
 165                 engine->fifo.enable             = nv04_fifo_enable;
 166                 engine->fifo.reassign           = nv04_fifo_reassign;
 167                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 168                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 169                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 170                 engine->fifo.create_context     = nv10_fifo_create_context;
 171                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 172                 engine->fifo.load_context       = nv10_fifo_load_context;
 173                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 174                 break;
 175         case 0x30:
 176                 engine->instmem.init            = nv04_instmem_init;
 177                 engine->instmem.takedown        = nv04_instmem_takedown;
 178                 engine->instmem.suspend         = nv04_instmem_suspend;
 179                 engine->instmem.resume          = nv04_instmem_resume;
 180                 engine->instmem.populate        = nv04_instmem_populate;
 181                 engine->instmem.clear           = nv04_instmem_clear;
 182                 engine->instmem.bind            = nv04_instmem_bind;
 183                 engine->instmem.unbind          = nv04_instmem_unbind;
 184                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 185                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 186                 engine->mc.init                 = nv04_mc_init;
 187                 engine->mc.takedown             = nv04_mc_takedown;
 188                 engine->timer.init              = nv04_timer_init;
 189                 engine->timer.read              = nv04_timer_read;
 190                 engine->timer.takedown          = nv04_timer_takedown;
 191                 engine->fb.init                 = nv10_fb_init;
 192                 engine->fb.takedown             = nv10_fb_takedown;
 193                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 194                 engine->graph.grclass           = nv30_graph_grclass;
 195                 engine->graph.init              = nv30_graph_init;
 196                 engine->graph.takedown          = nv20_graph_takedown;
 197                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 198                 engine->graph.channel           = nv10_graph_channel;
 199                 engine->graph.create_context    = nv20_graph_create_context;
 200                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 201                 engine->graph.load_context      = nv20_graph_load_context;
 202                 engine->graph.unload_context    = nv20_graph_unload_context;
 203                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 204                 engine->fifo.channels           = 32;
 205                 engine->fifo.init               = nv10_fifo_init;
 206                 engine->fifo.takedown           = nouveau_stub_takedown;
 207                 engine->fifo.disable            = nv04_fifo_disable;
 208                 engine->fifo.enable             = nv04_fifo_enable;
 209                 engine->fifo.reassign           = nv04_fifo_reassign;
 210                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 211                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 212                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 213                 engine->fifo.create_context     = nv10_fifo_create_context;
 214                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 215                 engine->fifo.load_context       = nv10_fifo_load_context;
 216                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 217                 break;
 218         case 0x40:
 219         case 0x60:
 220                 engine->instmem.init            = nv04_instmem_init;
 221                 engine->instmem.takedown        = nv04_instmem_takedown;
 222                 engine->instmem.suspend         = nv04_instmem_suspend;
 223                 engine->instmem.resume          = nv04_instmem_resume;
 224                 engine->instmem.populate        = nv04_instmem_populate;
 225                 engine->instmem.clear           = nv04_instmem_clear;
 226                 engine->instmem.bind            = nv04_instmem_bind;
 227                 engine->instmem.unbind          = nv04_instmem_unbind;
 228                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 229                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 230                 engine->mc.init                 = nv40_mc_init;
 231                 engine->mc.takedown             = nv40_mc_takedown;
 232                 engine->timer.init              = nv04_timer_init;
 233                 engine->timer.read              = nv04_timer_read;
 234                 engine->timer.takedown          = nv04_timer_takedown;
 235                 engine->fb.init                 = nv40_fb_init;
 236                 engine->fb.takedown             = nv40_fb_takedown;
 237                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 238                 engine->graph.grclass           = nv40_graph_grclass;
 239                 engine->graph.init              = nv40_graph_init;
 240                 engine->graph.takedown          = nv40_graph_takedown;
 241                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 242                 engine->graph.channel           = nv40_graph_channel;
 243                 engine->graph.create_context    = nv40_graph_create_context;
 244                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 245                 engine->graph.load_context      = nv40_graph_load_context;
 246                 engine->graph.unload_context    = nv40_graph_unload_context;
 247                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 248                 engine->fifo.channels           = 32;
 249                 engine->fifo.init               = nv40_fifo_init;
 250                 engine->fifo.takedown           = nouveau_stub_takedown;
 251                 engine->fifo.disable            = nv04_fifo_disable;
 252                 engine->fifo.enable             = nv04_fifo_enable;
 253                 engine->fifo.reassign           = nv04_fifo_reassign;
 254                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 255                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 256                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 257                 engine->fifo.create_context     = nv40_fifo_create_context;
 258                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 259                 engine->fifo.load_context       = nv40_fifo_load_context;
 260                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 261                 break;
 262         case 0x50:
 263         case 0x80: /* gotta love NVIDIA's consistency.. */
 264         case 0x90:
 265         case 0xA0:
 266                 engine->instmem.init            = nv50_instmem_init;
 267                 engine->instmem.takedown        = nv50_instmem_takedown;
 268                 engine->instmem.suspend         = nv50_instmem_suspend;
 269                 engine->instmem.resume          = nv50_instmem_resume;
 270                 engine->instmem.populate        = nv50_instmem_populate;
 271                 engine->instmem.clear           = nv50_instmem_clear;
 272                 engine->instmem.bind            = nv50_instmem_bind;
 273                 engine->instmem.unbind          = nv50_instmem_unbind;
 274                 engine->instmem.prepare_access  = nv50_instmem_prepare_access;
 275                 engine->instmem.finish_access   = nv50_instmem_finish_access;
 276                 engine->mc.init                 = nv50_mc_init;
 277                 engine->mc.takedown             = nv50_mc_takedown;
 278                 engine->timer.init              = nv04_timer_init;
 279                 engine->timer.read              = nv04_timer_read;
 280                 engine->timer.takedown          = nv04_timer_takedown;
 281                 engine->fb.init                 = nv50_fb_init;
 282                 engine->fb.takedown             = nv50_fb_takedown;
 283                 engine->graph.grclass           = nv50_graph_grclass;
 284                 engine->graph.init              = nv50_graph_init;
 285                 engine->graph.takedown          = nv50_graph_takedown;
 286                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 287                 engine->graph.channel           = nv50_graph_channel;
 288                 engine->graph.create_context    = nv50_graph_create_context;
 289                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 290                 engine->graph.load_context      = nv50_graph_load_context;
 291                 engine->graph.unload_context    = nv50_graph_unload_context;
 292                 engine->fifo.channels           = 128;
 293                 engine->fifo.init               = nv50_fifo_init;
 294                 engine->fifo.takedown           = nv50_fifo_takedown;
 295                 engine->fifo.disable            = nv04_fifo_disable;
 296                 engine->fifo.enable             = nv04_fifo_enable;
 297                 engine->fifo.reassign           = nv04_fifo_reassign;
 298                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 299                 engine->fifo.create_context     = nv50_fifo_create_context;
 300                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 301                 engine->fifo.load_context       = nv50_fifo_load_context;
 302                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 303                 break;
 304         default:
 305                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 306                 return 1;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static unsigned int
 313 nouveau_vga_set_decode(void *priv, bool state)
 314 {
 315         struct drm_device *dev = priv;
 316         struct drm_nouveau_private *dev_priv = dev->dev_private;
 317
 318         if (dev_priv->chipset >= 0x40)
 319                 nv_wr32(dev, 0x88054, state);
 320         else
 321                 nv_wr32(dev, 0x1854, state);
 322
 323         if (state)
 324                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 325                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 326         else
 327                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 328 }
 329
 330 static int
 331 nouveau_card_init_channel(struct drm_device *dev)
 332 {
 333         struct drm_nouveau_private *dev_priv = dev->dev_private;
 334         struct nouveau_gpuobj *gpuobj;
 335         int ret;
 336
 337         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 338                                     (struct drm_file *)-2,
 339                                     NvDmaFB, NvDmaTT);
 340         if (ret)
 341                 return ret;
 342
 343         gpuobj = NULL;
 344         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 345                                      0, dev_priv->vram_size,
 346                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 347                                      &gpuobj);
 348         if (ret)
 349                 goto out_err;
 350
 351         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
 352                                      gpuobj, NULL);
 353         if (ret)
 354                 goto out_err;
 355
 356         gpuobj = NULL;
 357         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 358                                           dev_priv->gart_info.aper_size,
 359                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 360         if (ret)
 361                 goto out_err;
 362
 363         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
 364                                      gpuobj, NULL);
 365         if (ret)
 366                 goto out_err;
 367
 368         return 0;
 369 out_err:
 370         nouveau_gpuobj_del(dev, &gpuobj);
 371         nouveau_channel_free(dev_priv->channel);
 372         dev_priv->channel = NULL;
 373         return ret;
 374 }
 375
 376 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 377                                          enum vga_switcheroo_state state)
 378 {
 379         struct drm_device *dev = pci_get_drvdata(pdev);
 380         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 381         if (state == VGA_SWITCHEROO_ON) {
 382                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 383                 nouveau_pci_resume(pdev);
 384                 drm_kms_helper_poll_enable(dev);
 385         } else {
 386                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 387                 drm_kms_helper_poll_disable(dev);
 388                 nouveau_pci_suspend(pdev, pmm);
 389         }
 390 }
 391
 392 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 393 {
 394         struct drm_device *dev = pci_get_drvdata(pdev);
 395         bool can_switch;
 396
 397         spin_lock(&dev->count_lock);
 398         can_switch = (dev->open_count == 0);
 399         spin_unlock(&dev->count_lock);
 400         return can_switch;
 401 }
 402
 403 int
 404 nouveau_card_init(struct drm_device *dev)
 405 {
 406         struct drm_nouveau_private *dev_priv = dev->dev_private;
 407         struct nouveau_engine *engine;
 408         int ret;
 409
 410         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 411
 412         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
 413                 return 0;
 414
 415         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 416         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 417                                        nouveau_switcheroo_can_switch);
 418
 419         /* Initialise internal driver API hooks */
 420         ret = nouveau_init_engine_ptrs(dev);
 421         if (ret)
 422                 goto out;
 423         engine = &dev_priv->engine;
 424         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 425         spin_lock_init(&dev_priv->context_switch_lock);
 426
 427         /* Parse BIOS tables / Run init tables if card not POSTed */
 428         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 429                 ret = nouveau_bios_init(dev);
 430                 if (ret)
 431                         goto out;
 432         }
 433
 434         ret = nouveau_mem_detect(dev);
 435         if (ret)
 436                 goto out_bios;
 437
 438         ret = nouveau_gpuobj_early_init(dev);
 439         if (ret)
 440                 goto out_bios;
 441
 442         /* Initialise instance memory, must happen before mem_init so we
 443          * know exactly how much VRAM we're able to use for "normal"
 444          * purposes.
 445          */
 446         ret = engine->instmem.init(dev);
 447         if (ret)
 448                 goto out_gpuobj_early;
 449
 450         /* Setup the memory manager */
 451         ret = nouveau_mem_init(dev);
 452         if (ret)
 453                 goto out_instmem;
 454
 455         ret = nouveau_gpuobj_init(dev);
 456         if (ret)
 457                 goto out_mem;
 458
 459         /* PMC */
 460         ret = engine->mc.init(dev);
 461         if (ret)
 462                 goto out_gpuobj;
 463
 464         /* PTIMER */
 465         ret = engine->timer.init(dev);
 466         if (ret)
 467                 goto out_mc;
 468
 469         /* PFB */
 470         ret = engine->fb.init(dev);
 471         if (ret)
 472                 goto out_timer;
 473
 474         if (nouveau_noaccel)
 475                 engine->graph.accel_blocked = true;
 476         else {
 477                 /* PGRAPH */
 478                 ret = engine->graph.init(dev);
 479                 if (ret)
 480                         goto out_fb;
 481
 482                 /* PFIFO */
 483                 ret = engine->fifo.init(dev);
 484                 if (ret)
 485                         goto out_graph;
 486         }
 487
 488         /* this call irq_preinstall, register irq handler and
 489          * call irq_postinstall
 490          */
 491         ret = drm_irq_install(dev);
 492         if (ret)
 493                 goto out_fifo;
 494
 495         ret = drm_vblank_init(dev, 0);
 496         if (ret)
 497                 goto out_irq;
 498
 499         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 500
 501         if (!engine->graph.accel_blocked) {
 502                 ret = nouveau_card_init_channel(dev);
 503                 if (ret)
 504                         goto out_irq;
 505         }
 506
 507         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 508                 if (dev_priv->card_type >= NV_50)
 509                         ret = nv50_display_create(dev);
 510                 else
 511                         ret = nv04_display_create(dev);
 512                 if (ret)
 513                         goto out_channel;
 514         }
 515
 516         ret = nouveau_backlight_init(dev);
 517         if (ret)
 518                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 519
 520         dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
 521
 522         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 523                 nouveau_fbcon_init(dev);
 524                 drm_kms_helper_poll_init(dev);
 525         }
 526
 527         return 0;
 528
 529 out_channel:
 530         if (dev_priv->channel) {
 531                 nouveau_channel_free(dev_priv->channel);
 532                 dev_priv->channel = NULL;
 533         }
 534 out_irq:
 535         drm_irq_uninstall(dev);
 536 out_fifo:
 537         if (!nouveau_noaccel)
 538                 engine->fifo.takedown(dev);
 539 out_graph:
 540         if (!nouveau_noaccel)
 541                 engine->graph.takedown(dev);
 542 out_fb:
 543         engine->fb.takedown(dev);
 544 out_timer:
 545         engine->timer.takedown(dev);
 546 out_mc:
 547         engine->mc.takedown(dev);
 548 out_gpuobj:
 549         nouveau_gpuobj_takedown(dev);
 550 out_mem:
 551         nouveau_sgdma_takedown(dev);
 552         nouveau_mem_close(dev);
 553 out_instmem:
 554         engine->instmem.takedown(dev);
 555 out_gpuobj_early:
 556         nouveau_gpuobj_late_takedown(dev);
 557 out_bios:
 558         nouveau_bios_takedown(dev);
 559 out:
 560         vga_client_register(dev->pdev, NULL, NULL, NULL);
 561         return ret;
 562 }
 563
 564 static void nouveau_card_takedown(struct drm_device *dev)
 565 {
 566         struct drm_nouveau_private *dev_priv = dev->dev_private;
 567         struct nouveau_engine *engine = &dev_priv->engine;
 568
 569         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 570
 571         if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
 572
 573                 nouveau_backlight_exit(dev);
 574
 575                 if (dev_priv->channel) {
 576                         nouveau_channel_free(dev_priv->channel);
 577                         dev_priv->channel = NULL;
 578                 }
 579
 580                 if (!nouveau_noaccel) {
 581                         engine->fifo.takedown(dev);
 582                         engine->graph.takedown(dev);
 583                 }
 584                 engine->fb.takedown(dev);
 585                 engine->timer.takedown(dev);
 586                 engine->mc.takedown(dev);
 587
 588                 mutex_lock(&dev->struct_mutex);
 589                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 590                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 591                 mutex_unlock(&dev->struct_mutex);
 592                 nouveau_sgdma_takedown(dev);
 593
 594                 nouveau_gpuobj_takedown(dev);
 595                 nouveau_mem_close(dev);
 596                 engine->instmem.takedown(dev);
 597
 598                 if (drm_core_check_feature(dev, DRIVER_MODESET))
 599                         drm_irq_uninstall(dev);
 600
 601                 nouveau_gpuobj_late_takedown(dev);
 602                 nouveau_bios_takedown(dev);
 603
 604                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 605
 606                 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 607         }
 608 }
 609
 610 /* here a client dies, release the stuff that was allocated for its
 611  * file_priv */
 612 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 613 {
 614         nouveau_channel_cleanup(dev, file_priv);
 615 }
 616
 617 /* first module load, setup the mmio/fb mapping */
 618 /* KMS: we need mmio at load time, not when the first drm client opens. */
 619 int nouveau_firstopen(struct drm_device *dev)
 620 {
 621         return 0;
 622 }
 623
 624 /* if we have an OF card, copy vbios to RAMIN */
 625 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 626 {
 627 #if defined(__powerpc__)
 628         int size, i;
 629         const uint32_t *bios;
 630         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 631         if (!dn) {
 632                 NV_INFO(dev, "Unable to get the OF node\n");
 633                 return;
 634         }
 635
 636         bios = of_get_property(dn, "NVDA,BMP", &size);
 637         if (bios) {
 638                 for (i = 0; i < size; i += 4)
 639                         nv_wi32(dev, i, bios[i/4]);
 640                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 641         } else {
 642                 NV_INFO(dev, "Unable to get the OF bios\n");
 643         }
 644 #endif
 645 }
 646
 647 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 648 {
 649         struct pci_dev *pdev = dev->pdev;
 650         struct apertures_struct *aper = alloc_apertures(3);
 651         if (!aper)
 652                 return NULL;
 653
 654         aper->ranges[0].base = pci_resource_start(pdev, 1);
 655         aper->ranges[0].size = pci_resource_len(pdev, 1);
 656         aper->count = 1;
 657
 658         if (pci_resource_len(pdev, 2)) {
 659                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 660                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 661                 aper->count++;
 662         }
 663
 664         if (pci_resource_len(pdev, 3)) {
 665                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 666                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 667                 aper->count++;
 668         }
 669
 670         return aper;
 671 }
 672
 673 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 674 {
 675         struct drm_nouveau_private *dev_priv = dev->dev_private;
 676         bool primary = false;
 677         dev_priv->apertures = nouveau_get_apertures(dev);
 678         if (!dev_priv->apertures)
 679                 return -ENOMEM;
 680
 681 #ifdef CONFIG_X86
 682         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 683 #endif
 684
 685         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 686         return 0;
 687 }
 688
 689 int nouveau_load(struct drm_device *dev, unsigned long flags)
 690 {
 691         struct drm_nouveau_private *dev_priv;
 692         uint32_t reg0;
 693         resource_size_t mmio_start_offs;
 694
 695         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 696         if (!dev_priv)
 697                 return -ENOMEM;
 698         dev->dev_private = dev_priv;
 699         dev_priv->dev = dev;
 700
 701         dev_priv->flags = flags & NOUVEAU_FLAGS;
 702         dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 703
 704         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 705                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 706
 707         dev_priv->wq = create_workqueue("nouveau");
 708         if (!dev_priv->wq)
 709                 return -EINVAL;
 710
 711         /* resource 0 is mmio regs */
 712         /* resource 1 is linear FB */
 713         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 714         /* resource 6 is bios */
 715
 716         /* map the mmio regs */
 717         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 718         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 719         if (!dev_priv->mmio) {
 720                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 721                          "Please report your setup to " DRIVER_EMAIL "\n");
 722                 return -EINVAL;
 723         }
 724         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 725                                         (unsigned long long)mmio_start_offs);
 726
 727 #ifdef __BIG_ENDIAN
 728         /* Put the card in BE mode if it's not */
 729         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 730                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 731
 732         DRM_MEMORYBARRIER();
 733 #endif
 734
 735         /* Time to determine the card architecture */
 736         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 737
 738         /* We're dealing with >=NV10 */
 739         if ((reg0 & 0x0f000000) > 0) {
 740                 /* Bit 27-20 contain the architecture in hex */
 741                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 742         /* NV04 or NV05 */
 743         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 744                 if (reg0 & 0x00f00000)
 745                         dev_priv->chipset = 0x05;
 746                 else
 747                         dev_priv->chipset = 0x04;
 748         } else
 749                 dev_priv->chipset = 0xff;
 750
 751         switch (dev_priv->chipset & 0xf0) {
 752         case 0x00:
 753         case 0x10:
 754         case 0x20:
 755         case 0x30:
 756                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 757                 break;
 758         case 0x40:
 759         case 0x60:
 760                 dev_priv->card_type = NV_40;
 761                 break;
 762         case 0x50:
 763         case 0x80:
 764         case 0x90:
 765         case 0xa0:
 766                 dev_priv->card_type = NV_50;
 767                 break;
 768         default:
 769                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 770                 return -EINVAL;
 771         }
 772
 773         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 774                 dev_priv->card_type, reg0);
 775
 776         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 777                 int ret = nouveau_remove_conflicting_drivers(dev);
 778                 if (ret)
 779                         return ret;
 780         }
 781
 782         /* map larger RAMIN aperture on NV40 cards */
 783         dev_priv->ramin  = NULL;
 784         if (dev_priv->card_type >= NV_40) {
 785                 int ramin_bar = 2;
 786                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 787                         ramin_bar = 3;
 788
 789                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 790                 dev_priv->ramin = ioremap(
 791                                 pci_resource_start(dev->pdev, ramin_bar),
 792                                 dev_priv->ramin_size);
 793                 if (!dev_priv->ramin) {
 794                         NV_ERROR(dev, "Failed to init RAMIN mapping, "
 795                                       "limited instance memory available\n");
 796                 }
 797         }
 798
 799         /* On older cards (or if the above failed), create a map covering
 800          * the BAR0 PRAMIN aperture */
 801         if (!dev_priv->ramin) {
 802                 dev_priv->ramin_size = 1 * 1024 * 1024;
 803                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 804                                                         dev_priv->ramin_size);
 805                 if (!dev_priv->ramin) {
 806                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 807                         return -ENOMEM;
 808                 }
 809         }
 810
 811         nouveau_OF_copy_vbios_to_ramin(dev);
 812
 813         /* Special flags */
 814         if (dev->pci_device == 0x01a0)
 815                 dev_priv->flags |= NV_NFORCE;
 816         else if (dev->pci_device == 0x01f0)
 817                 dev_priv->flags |= NV_NFORCE2;
 818
 819         /* For kernel modesetting, init card now and bring up fbcon */
 820         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 821                 int ret = nouveau_card_init(dev);
 822                 if (ret)
 823                         return ret;
 824         }
 825
 826         return 0;
 827 }
 828
 829 static void nouveau_close(struct drm_device *dev)
 830 {
 831         struct drm_nouveau_private *dev_priv = dev->dev_private;
 832
 833         /* In the case of an error dev_priv may not be allocated yet */
 834         if (dev_priv)
 835                 nouveau_card_takedown(dev);
 836 }
 837
 838 /* KMS: we need mmio at load time, not when the first drm client opens. */
 839 void nouveau_lastclose(struct drm_device *dev)
 840 {
 841         if (drm_core_check_feature(dev, DRIVER_MODESET))
 842                 return;
 843
 844         nouveau_close(dev);
 845 }
 846
 847 int nouveau_unload(struct drm_device *dev)
 848 {
 849         struct drm_nouveau_private *dev_priv = dev->dev_private;
 850
 851         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 852                 drm_kms_helper_poll_fini(dev);
 853                 nouveau_fbcon_fini(dev);
 854                 if (dev_priv->card_type >= NV_50)
 855                         nv50_display_destroy(dev);
 856                 else
 857                         nv04_display_destroy(dev);
 858                 nouveau_close(dev);
 859         }
 860
 861         iounmap(dev_priv->mmio);
 862         iounmap(dev_priv->ramin);
 863
 864         kfree(dev_priv);
 865         dev->dev_private = NULL;
 866         return 0;
 867 }
 868
 869 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 870                                                 struct drm_file *file_priv)
 871 {
 872         struct drm_nouveau_private *dev_priv = dev->dev_private;
 873         struct drm_nouveau_getparam *getparam = data;
 874
 875         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 876
 877         switch (getparam->param) {
 878         case NOUVEAU_GETPARAM_CHIPSET_ID:
 879                 getparam->value = dev_priv->chipset;
 880                 break;
 881         case NOUVEAU_GETPARAM_PCI_VENDOR:
 882                 getparam->value = dev->pci_vendor;
 883                 break;
 884         case NOUVEAU_GETPARAM_PCI_DEVICE:
 885                 getparam->value = dev->pci_device;
 886                 break;
 887         case NOUVEAU_GETPARAM_BUS_TYPE:
 888                 if (drm_device_is_agp(dev))
 889                         getparam->value = NV_AGP;
 890                 else if (drm_device_is_pcie(dev))
 891                         getparam->value = NV_PCIE;
 892                 else
 893                         getparam->value = NV_PCI;
 894                 break;
 895         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 896                 getparam->value = dev_priv->fb_phys;
 897                 break;
 898         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 899                 getparam->value = dev_priv->gart_info.aper_base;
 900                 break;
 901         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
 902                 if (dev->sg) {
 903                         getparam->value = (unsigned long)dev->sg->virtual;
 904                 } else {
 905                         NV_ERROR(dev, "Requested PCIGART address, "
 906                                         "while no PCIGART was created\n");
 907                         return -EINVAL;
 908                 }
 909                 break;
 910         case NOUVEAU_GETPARAM_FB_SIZE:
 911                 getparam->value = dev_priv->fb_available_size;
 912                 break;
 913         case NOUVEAU_GETPARAM_AGP_SIZE:
 914                 getparam->value = dev_priv->gart_info.aper_size;
 915                 break;
 916         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
 917                 getparam->value = dev_priv->vm_vram_base;
 918                 break;
 919         case NOUVEAU_GETPARAM_PTIMER_TIME:
 920                 getparam->value = dev_priv->engine.timer.read(dev);
 921                 break;
 922         case NOUVEAU_GETPARAM_GRAPH_UNITS:
 923                 /* NV40 and NV50 versions are quite different, but register
 924                  * address is the same. User is supposed to know the card
 925                  * family anyway... */
 926                 if (dev_priv->chipset >= 0x40) {
 927                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
 928                         break;
 929                 }
 930                 /* FALLTHRU */
 931         default:
 932                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
 933                 return -EINVAL;
 934         }
 935
 936         return 0;
 937 }
 938
 939 int
 940 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
 941                        struct drm_file *file_priv)
 942 {
 943         struct drm_nouveau_setparam *setparam = data;
 944
 945         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 946
 947         switch (setparam->param) {
 948         default:
 949                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
 950                 return -EINVAL;
 951         }
 952
 953         return 0;
 954 }
 955
 956 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 957 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 958                         uint32_t reg, uint32_t mask, uint32_t val)
 959 {
 960         struct drm_nouveau_private *dev_priv = dev->dev_private;
 961         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 962         uint64_t start = ptimer->read(dev);
 963
 964         do {
 965                 if ((nv_rd32(dev, reg) & mask) == val)
 966                         return true;
 967         } while (ptimer->read(dev) - start < timeout);
 968
 969         return false;
 970 }
 971
 972 /* Waits for PGRAPH to go completely idle */
 973 bool nouveau_wait_for_idle(struct drm_device *dev)
 974 {
 975         if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
 976                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
 977                          nv_rd32(dev, NV04_PGRAPH_STATUS));
 978                 return false;
 979         }
 980
 981         return true;
 982 }
 983