drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.get             = nv04_instmem_get;
  57                 engine->instmem.put             = nv04_instmem_put;
  58                 engine->instmem.map             = nv04_instmem_map;
  59                 engine->instmem.unmap           = nv04_instmem_unmap;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->fifo.channels           = 16;
  69                 engine->fifo.init               = nv04_fifo_init;
  70                 engine->fifo.takedown           = nv04_fifo_fini;
  71                 engine->fifo.disable            = nv04_fifo_disable;
  72                 engine->fifo.enable             = nv04_fifo_enable;
  73                 engine->fifo.reassign           = nv04_fifo_reassign;
  74                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  75                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  76                 engine->fifo.create_context     = nv04_fifo_create_context;
  77                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  78                 engine->fifo.load_context       = nv04_fifo_load_context;
  79                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  80                 engine->display.early_init      = nv04_display_early_init;
  81                 engine->display.late_takedown   = nv04_display_late_takedown;
  82                 engine->display.create          = nv04_display_create;
  83                 engine->display.init            = nv04_display_init;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->gpio.init               = nouveau_stub_init;
  86                 engine->gpio.takedown           = nouveau_stub_takedown;
  87                 engine->gpio.get                = NULL;
  88                 engine->gpio.set                = NULL;
  89                 engine->gpio.irq_enable         = NULL;
  90                 engine->pm.clock_get            = nv04_pm_clock_get;
  91                 engine->pm.clock_pre            = nv04_pm_clock_pre;
  92                 engine->pm.clock_set            = nv04_pm_clock_set;
  93                 engine->vram.init               = nouveau_mem_detect;
  94                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  95                 break;
  96         case 0x10:
  97                 engine->instmem.init            = nv04_instmem_init;
  98                 engine->instmem.takedown        = nv04_instmem_takedown;
  99                 engine->instmem.suspend         = nv04_instmem_suspend;
 100                 engine->instmem.resume          = nv04_instmem_resume;
 101                 engine->instmem.get             = nv04_instmem_get;
 102                 engine->instmem.put             = nv04_instmem_put;
 103                 engine->instmem.map             = nv04_instmem_map;
 104                 engine->instmem.unmap           = nv04_instmem_unmap;
 105                 engine->instmem.flush           = nv04_instmem_flush;
 106                 engine->mc.init                 = nv04_mc_init;
 107                 engine->mc.takedown             = nv04_mc_takedown;
 108                 engine->timer.init              = nv04_timer_init;
 109                 engine->timer.read              = nv04_timer_read;
 110                 engine->timer.takedown          = nv04_timer_takedown;
 111                 engine->fb.init                 = nv10_fb_init;
 112                 engine->fb.takedown             = nv10_fb_takedown;
 113                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 114                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 115                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 116                 engine->fifo.channels           = 32;
 117                 engine->fifo.init               = nv10_fifo_init;
 118                 engine->fifo.takedown           = nv04_fifo_fini;
 119                 engine->fifo.disable            = nv04_fifo_disable;
 120                 engine->fifo.enable             = nv04_fifo_enable;
 121                 engine->fifo.reassign           = nv04_fifo_reassign;
 122                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 123                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 124                 engine->fifo.create_context     = nv10_fifo_create_context;
 125                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 126                 engine->fifo.load_context       = nv10_fifo_load_context;
 127                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 128                 engine->display.early_init      = nv04_display_early_init;
 129                 engine->display.late_takedown   = nv04_display_late_takedown;
 130                 engine->display.create          = nv04_display_create;
 131                 engine->display.init            = nv04_display_init;
 132                 engine->display.destroy         = nv04_display_destroy;
 133                 engine->gpio.init               = nouveau_stub_init;
 134                 engine->gpio.takedown           = nouveau_stub_takedown;
 135                 engine->gpio.get                = nv10_gpio_get;
 136                 engine->gpio.set                = nv10_gpio_set;
 137                 engine->gpio.irq_enable         = NULL;
 138                 engine->pm.clock_get            = nv04_pm_clock_get;
 139                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 140                 engine->pm.clock_set            = nv04_pm_clock_set;
 141                 engine->vram.init               = nouveau_mem_detect;
 142                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 143                 break;
 144         case 0x20:
 145                 engine->instmem.init            = nv04_instmem_init;
 146                 engine->instmem.takedown        = nv04_instmem_takedown;
 147                 engine->instmem.suspend         = nv04_instmem_suspend;
 148                 engine->instmem.resume          = nv04_instmem_resume;
 149                 engine->instmem.get             = nv04_instmem_get;
 150                 engine->instmem.put             = nv04_instmem_put;
 151                 engine->instmem.map             = nv04_instmem_map;
 152                 engine->instmem.unmap           = nv04_instmem_unmap;
 153                 engine->instmem.flush           = nv04_instmem_flush;
 154                 engine->mc.init                 = nv04_mc_init;
 155                 engine->mc.takedown             = nv04_mc_takedown;
 156                 engine->timer.init              = nv04_timer_init;
 157                 engine->timer.read              = nv04_timer_read;
 158                 engine->timer.takedown          = nv04_timer_takedown;
 159                 engine->fb.init                 = nv10_fb_init;
 160                 engine->fb.takedown             = nv10_fb_takedown;
 161                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 162                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 163                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 164                 engine->fifo.channels           = 32;
 165                 engine->fifo.init               = nv10_fifo_init;
 166                 engine->fifo.takedown           = nv04_fifo_fini;
 167                 engine->fifo.disable            = nv04_fifo_disable;
 168                 engine->fifo.enable             = nv04_fifo_enable;
 169                 engine->fifo.reassign           = nv04_fifo_reassign;
 170                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 171                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 172                 engine->fifo.create_context     = nv10_fifo_create_context;
 173                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 174                 engine->fifo.load_context       = nv10_fifo_load_context;
 175                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 176                 engine->display.early_init      = nv04_display_early_init;
 177                 engine->display.late_takedown   = nv04_display_late_takedown;
 178                 engine->display.create          = nv04_display_create;
 179                 engine->display.init            = nv04_display_init;
 180                 engine->display.destroy         = nv04_display_destroy;
 181                 engine->gpio.init               = nouveau_stub_init;
 182                 engine->gpio.takedown           = nouveau_stub_takedown;
 183                 engine->gpio.get                = nv10_gpio_get;
 184                 engine->gpio.set                = nv10_gpio_set;
 185                 engine->gpio.irq_enable         = NULL;
 186                 engine->pm.clock_get            = nv04_pm_clock_get;
 187                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 188                 engine->pm.clock_set            = nv04_pm_clock_set;
 189                 engine->vram.init               = nouveau_mem_detect;
 190                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 191                 break;
 192         case 0x30:
 193                 engine->instmem.init            = nv04_instmem_init;
 194                 engine->instmem.takedown        = nv04_instmem_takedown;
 195                 engine->instmem.suspend         = nv04_instmem_suspend;
 196                 engine->instmem.resume          = nv04_instmem_resume;
 197                 engine->instmem.get             = nv04_instmem_get;
 198                 engine->instmem.put             = nv04_instmem_put;
 199                 engine->instmem.map             = nv04_instmem_map;
 200                 engine->instmem.unmap           = nv04_instmem_unmap;
 201                 engine->instmem.flush           = nv04_instmem_flush;
 202                 engine->mc.init                 = nv04_mc_init;
 203                 engine->mc.takedown             = nv04_mc_takedown;
 204                 engine->timer.init              = nv04_timer_init;
 205                 engine->timer.read              = nv04_timer_read;
 206                 engine->timer.takedown          = nv04_timer_takedown;
 207                 engine->fb.init                 = nv30_fb_init;
 208                 engine->fb.takedown             = nv30_fb_takedown;
 209                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 210                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 211                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 212                 engine->fifo.channels           = 32;
 213                 engine->fifo.init               = nv10_fifo_init;
 214                 engine->fifo.takedown           = nv04_fifo_fini;
 215                 engine->fifo.disable            = nv04_fifo_disable;
 216                 engine->fifo.enable             = nv04_fifo_enable;
 217                 engine->fifo.reassign           = nv04_fifo_reassign;
 218                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 219                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 220                 engine->fifo.create_context     = nv10_fifo_create_context;
 221                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 222                 engine->fifo.load_context       = nv10_fifo_load_context;
 223                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 224                 engine->display.early_init      = nv04_display_early_init;
 225                 engine->display.late_takedown   = nv04_display_late_takedown;
 226                 engine->display.create          = nv04_display_create;
 227                 engine->display.init            = nv04_display_init;
 228                 engine->display.destroy         = nv04_display_destroy;
 229                 engine->gpio.init               = nouveau_stub_init;
 230                 engine->gpio.takedown           = nouveau_stub_takedown;
 231                 engine->gpio.get                = nv10_gpio_get;
 232                 engine->gpio.set                = nv10_gpio_set;
 233                 engine->gpio.irq_enable         = NULL;
 234                 engine->pm.clock_get            = nv04_pm_clock_get;
 235                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 236                 engine->pm.clock_set            = nv04_pm_clock_set;
 237                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 238                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 239                 engine->vram.init               = nouveau_mem_detect;
 240                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 241                 break;
 242         case 0x40:
 243         case 0x60:
 244                 engine->instmem.init            = nv04_instmem_init;
 245                 engine->instmem.takedown        = nv04_instmem_takedown;
 246                 engine->instmem.suspend         = nv04_instmem_suspend;
 247                 engine->instmem.resume          = nv04_instmem_resume;
 248                 engine->instmem.get             = nv04_instmem_get;
 249                 engine->instmem.put             = nv04_instmem_put;
 250                 engine->instmem.map             = nv04_instmem_map;
 251                 engine->instmem.unmap           = nv04_instmem_unmap;
 252                 engine->instmem.flush           = nv04_instmem_flush;
 253                 engine->mc.init                 = nv40_mc_init;
 254                 engine->mc.takedown             = nv40_mc_takedown;
 255                 engine->timer.init              = nv04_timer_init;
 256                 engine->timer.read              = nv04_timer_read;
 257                 engine->timer.takedown          = nv04_timer_takedown;
 258                 engine->fb.init                 = nv40_fb_init;
 259                 engine->fb.takedown             = nv40_fb_takedown;
 260                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 261                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 262                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 263                 engine->fifo.channels           = 32;
 264                 engine->fifo.init               = nv40_fifo_init;
 265                 engine->fifo.takedown           = nv04_fifo_fini;
 266                 engine->fifo.disable            = nv04_fifo_disable;
 267                 engine->fifo.enable             = nv04_fifo_enable;
 268                 engine->fifo.reassign           = nv04_fifo_reassign;
 269                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 270                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 271                 engine->fifo.create_context     = nv40_fifo_create_context;
 272                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 273                 engine->fifo.load_context       = nv40_fifo_load_context;
 274                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 275                 engine->display.early_init      = nv04_display_early_init;
 276                 engine->display.late_takedown   = nv04_display_late_takedown;
 277                 engine->display.create          = nv04_display_create;
 278                 engine->display.init            = nv04_display_init;
 279                 engine->display.destroy         = nv04_display_destroy;
 280                 engine->gpio.init               = nouveau_stub_init;
 281                 engine->gpio.takedown           = nouveau_stub_takedown;
 282                 engine->gpio.get                = nv10_gpio_get;
 283                 engine->gpio.set                = nv10_gpio_set;
 284                 engine->gpio.irq_enable         = NULL;
 285                 engine->pm.clock_get            = nv04_pm_clock_get;
 286                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 287                 engine->pm.clock_set            = nv04_pm_clock_set;
 288                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 289                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 290                 engine->pm.temp_get             = nv40_temp_get;
 291                 engine->vram.init               = nouveau_mem_detect;
 292                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 293                 break;
 294         case 0x50:
 295         case 0x80: /* gotta love NVIDIA's consistency.. */
 296         case 0x90:
 297         case 0xA0:
 298                 engine->instmem.init            = nv50_instmem_init;
 299                 engine->instmem.takedown        = nv50_instmem_takedown;
 300                 engine->instmem.suspend         = nv50_instmem_suspend;
 301                 engine->instmem.resume          = nv50_instmem_resume;
 302                 engine->instmem.get             = nv50_instmem_get;
 303                 engine->instmem.put             = nv50_instmem_put;
 304                 engine->instmem.map             = nv50_instmem_map;
 305                 engine->instmem.unmap           = nv50_instmem_unmap;
 306                 if (dev_priv->chipset == 0x50)
 307                         engine->instmem.flush   = nv50_instmem_flush;
 308                 else
 309                         engine->instmem.flush   = nv84_instmem_flush;
 310                 engine->mc.init                 = nv50_mc_init;
 311                 engine->mc.takedown             = nv50_mc_takedown;
 312                 engine->timer.init              = nv04_timer_init;
 313                 engine->timer.read              = nv04_timer_read;
 314                 engine->timer.takedown          = nv04_timer_takedown;
 315                 engine->fb.init                 = nv50_fb_init;
 316                 engine->fb.takedown             = nv50_fb_takedown;
 317                 engine->fifo.channels           = 128;
 318                 engine->fifo.init               = nv50_fifo_init;
 319                 engine->fifo.takedown           = nv50_fifo_takedown;
 320                 engine->fifo.disable            = nv04_fifo_disable;
 321                 engine->fifo.enable             = nv04_fifo_enable;
 322                 engine->fifo.reassign           = nv04_fifo_reassign;
 323                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 324                 engine->fifo.create_context     = nv50_fifo_create_context;
 325                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 326                 engine->fifo.load_context       = nv50_fifo_load_context;
 327                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 328                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 329                 engine->display.early_init      = nv50_display_early_init;
 330                 engine->display.late_takedown   = nv50_display_late_takedown;
 331                 engine->display.create          = nv50_display_create;
 332                 engine->display.init            = nv50_display_init;
 333                 engine->display.destroy         = nv50_display_destroy;
 334                 engine->gpio.init               = nv50_gpio_init;
 335                 engine->gpio.takedown           = nv50_gpio_fini;
 336                 engine->gpio.get                = nv50_gpio_get;
 337                 engine->gpio.set                = nv50_gpio_set;
 338                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 339                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 340                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 341                 switch (dev_priv->chipset) {
 342                 case 0x84:
 343                 case 0x86:
 344                 case 0x92:
 345                 case 0x94:
 346                 case 0x96:
 347                 case 0x98:
 348                 case 0xa0:
 349                 case 0xaa:
 350                 case 0xac:
 351                 case 0x50:
 352                         engine->pm.clock_get    = nv50_pm_clock_get;
 353                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 354                         engine->pm.clock_set    = nv50_pm_clock_set;
 355                         break;
 356                 default:
 357                         engine->pm.clock_get    = nva3_pm_clock_get;
 358                         engine->pm.clock_pre    = nva3_pm_clock_pre;
 359                         engine->pm.clock_set    = nva3_pm_clock_set;
 360                         break;
 361                 }
 362                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 363                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 364                 if (dev_priv->chipset >= 0x84)
 365                         engine->pm.temp_get     = nv84_temp_get;
 366                 else
 367                         engine->pm.temp_get     = nv40_temp_get;
 368                 engine->vram.init               = nv50_vram_init;
 369                 engine->vram.get                = nv50_vram_new;
 370                 engine->vram.put                = nv50_vram_del;
 371                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 372                 break;
 373         case 0xC0:
 374         case 0xD0:
 375                 engine->instmem.init            = nvc0_instmem_init;
 376                 engine->instmem.takedown        = nvc0_instmem_takedown;
 377                 engine->instmem.suspend         = nvc0_instmem_suspend;
 378                 engine->instmem.resume          = nvc0_instmem_resume;
 379                 engine->instmem.get             = nv50_instmem_get;
 380                 engine->instmem.put             = nv50_instmem_put;
 381                 engine->instmem.map             = nv50_instmem_map;
 382                 engine->instmem.unmap           = nv50_instmem_unmap;
 383                 engine->instmem.flush           = nv84_instmem_flush;
 384                 engine->mc.init                 = nv50_mc_init;
 385                 engine->mc.takedown             = nv50_mc_takedown;
 386                 engine->timer.init              = nv04_timer_init;
 387                 engine->timer.read              = nv04_timer_read;
 388                 engine->timer.takedown          = nv04_timer_takedown;
 389                 engine->fb.init                 = nvc0_fb_init;
 390                 engine->fb.takedown             = nvc0_fb_takedown;
 391                 engine->fifo.channels           = 128;
 392                 engine->fifo.init               = nvc0_fifo_init;
 393                 engine->fifo.takedown           = nvc0_fifo_takedown;
 394                 engine->fifo.disable            = nvc0_fifo_disable;
 395                 engine->fifo.enable             = nvc0_fifo_enable;
 396                 engine->fifo.reassign           = nvc0_fifo_reassign;
 397                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 398                 engine->fifo.create_context     = nvc0_fifo_create_context;
 399                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 400                 engine->fifo.load_context       = nvc0_fifo_load_context;
 401                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 402                 engine->display.early_init      = nv50_display_early_init;
 403                 engine->display.late_takedown   = nv50_display_late_takedown;
 404                 engine->display.create          = nv50_display_create;
 405                 engine->display.init            = nv50_display_init;
 406                 engine->display.destroy         = nv50_display_destroy;
 407                 engine->gpio.init               = nv50_gpio_init;
 408                 engine->gpio.takedown           = nouveau_stub_takedown;
 409                 engine->gpio.get                = nv50_gpio_get;
 410                 engine->gpio.set                = nv50_gpio_set;
 411                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 412                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 413                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 414                 engine->vram.init               = nvc0_vram_init;
 415                 engine->vram.get                = nvc0_vram_new;
 416                 engine->vram.put                = nv50_vram_del;
 417                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 418                 break;
 419         default:
 420                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 421                 return 1;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static unsigned int
 428 nouveau_vga_set_decode(void *priv, bool state)
 429 {
 430         struct drm_device *dev = priv;
 431         struct drm_nouveau_private *dev_priv = dev->dev_private;
 432
 433         if (dev_priv->chipset >= 0x40)
 434                 nv_wr32(dev, 0x88054, state);
 435         else
 436                 nv_wr32(dev, 0x1854, state);
 437
 438         if (state)
 439                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 440                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 441         else
 442                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 443 }
 444
 445 static int
 446 nouveau_card_init_channel(struct drm_device *dev)
 447 {
 448         struct drm_nouveau_private *dev_priv = dev->dev_private;
 449         int ret;
 450
 451         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 452                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 453         if (ret)
 454                 return ret;
 455
 456         mutex_unlock(&dev_priv->channel->mutex);
 457         return 0;
 458 }
 459
 460 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 461                                          enum vga_switcheroo_state state)
 462 {
 463         struct drm_device *dev = pci_get_drvdata(pdev);
 464         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 465         if (state == VGA_SWITCHEROO_ON) {
 466                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 467                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 468                 nouveau_pci_resume(pdev);
 469                 drm_kms_helper_poll_enable(dev);
 470                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 471         } else {
 472                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 473                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 474                 drm_kms_helper_poll_disable(dev);
 475                 nouveau_pci_suspend(pdev, pmm);
 476                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 477         }
 478 }
 479
 480 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 481 {
 482         struct drm_device *dev = pci_get_drvdata(pdev);
 483         nouveau_fbcon_output_poll_changed(dev);
 484 }
 485
 486 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 487 {
 488         struct drm_device *dev = pci_get_drvdata(pdev);
 489         bool can_switch;
 490
 491         spin_lock(&dev->count_lock);
 492         can_switch = (dev->open_count == 0);
 493         spin_unlock(&dev->count_lock);
 494         return can_switch;
 495 }
 496
 497 int
 498 nouveau_card_init(struct drm_device *dev)
 499 {
 500         struct drm_nouveau_private *dev_priv = dev->dev_private;
 501         struct nouveau_engine *engine;
 502         int ret, e = 0;
 503
 504         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 505         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 506                                        nouveau_switcheroo_reprobe,
 507                                        nouveau_switcheroo_can_switch);
 508
 509         /* Initialise internal driver API hooks */
 510         ret = nouveau_init_engine_ptrs(dev);
 511         if (ret)
 512                 goto out;
 513         engine = &dev_priv->engine;
 514         spin_lock_init(&dev_priv->channels.lock);
 515         spin_lock_init(&dev_priv->tile.lock);
 516         spin_lock_init(&dev_priv->context_switch_lock);
 517         spin_lock_init(&dev_priv->vm_lock);
 518
 519         /* Make the CRTCs and I2C buses accessible */
 520         ret = engine->display.early_init(dev);
 521         if (ret)
 522                 goto out;
 523
 524         /* Parse BIOS tables / Run init tables if card not POSTed */
 525         ret = nouveau_bios_init(dev);
 526         if (ret)
 527                 goto out_display_early;
 528
 529         nouveau_pm_init(dev);
 530
 531         ret = nouveau_mem_vram_init(dev);
 532         if (ret)
 533                 goto out_bios;
 534
 535         ret = nouveau_gpuobj_init(dev);
 536         if (ret)
 537                 goto out_vram;
 538
 539         ret = engine->instmem.init(dev);
 540         if (ret)
 541                 goto out_gpuobj;
 542
 543         ret = nouveau_mem_gart_init(dev);
 544         if (ret)
 545                 goto out_instmem;
 546
 547         /* PMC */
 548         ret = engine->mc.init(dev);
 549         if (ret)
 550                 goto out_gart;
 551
 552         /* PGPIO */
 553         ret = engine->gpio.init(dev);
 554         if (ret)
 555                 goto out_mc;
 556
 557         /* PTIMER */
 558         ret = engine->timer.init(dev);
 559         if (ret)
 560                 goto out_gpio;
 561
 562         /* PFB */
 563         ret = engine->fb.init(dev);
 564         if (ret)
 565                 goto out_timer;
 566
 567         if (!nouveau_noaccel) {
 568                 switch (dev_priv->card_type) {
 569                 case NV_04:
 570                         nv04_graph_create(dev);
 571                         break;
 572                 case NV_10:
 573                         nv10_graph_create(dev);
 574                         break;
 575                 case NV_20:
 576                 case NV_30:
 577                         nv20_graph_create(dev);
 578                         break;
 579                 case NV_40:
 580                         nv40_graph_create(dev);
 581                         break;
 582                 case NV_50:
 583                         nv50_graph_create(dev);
 584                         break;
 585                 case NV_C0:
 586                         nvc0_graph_create(dev);
 587                         break;
 588                 default:
 589                         break;
 590                 }
 591
 592                 switch (dev_priv->chipset) {
 593                 case 0x84:
 594                 case 0x86:
 595                 case 0x92:
 596                 case 0x94:
 597                 case 0x96:
 598                 case 0xa0:
 599                         nv84_crypt_create(dev);
 600                         break;
 601                 }
 602
 603                 switch (dev_priv->card_type) {
 604                 case NV_50:
 605                         switch (dev_priv->chipset) {
 606                         case 0xa3:
 607                         case 0xa5:
 608                         case 0xa8:
 609                         case 0xaf:
 610                                 nva3_copy_create(dev);
 611                                 break;
 612                         }
 613                         break;
 614                 case NV_C0:
 615                         nvc0_copy_create(dev, 0);
 616                         nvc0_copy_create(dev, 1);
 617                         break;
 618                 default:
 619                         break;
 620                 }
 621
 622                 if (dev_priv->card_type == NV_40)
 623                         nv40_mpeg_create(dev);
 624                 else
 625                 if (dev_priv->card_type == NV_50 &&
 626                     (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
 627                         nv50_mpeg_create(dev);
 628
 629                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 630                         if (dev_priv->eng[e]) {
 631                                 ret = dev_priv->eng[e]->init(dev, e);
 632                                 if (ret)
 633                                         goto out_engine;
 634                         }
 635                 }
 636
 637                 /* PFIFO */
 638                 ret = engine->fifo.init(dev);
 639                 if (ret)
 640                         goto out_engine;
 641         }
 642
 643         ret = engine->display.create(dev);
 644         if (ret)
 645                 goto out_fifo;
 646
 647         ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
 648         if (ret)
 649                 goto out_vblank;
 650
 651         ret = nouveau_irq_init(dev);
 652         if (ret)
 653                 goto out_vblank;
 654
 655         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 656
 657         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 658                 ret = nouveau_fence_init(dev);
 659                 if (ret)
 660                         goto out_irq;
 661
 662                 ret = nouveau_card_init_channel(dev);
 663                 if (ret)
 664                         goto out_fence;
 665         }
 666
 667         nouveau_fbcon_init(dev);
 668         drm_kms_helper_poll_init(dev);
 669         return 0;
 670
 671 out_fence:
 672         nouveau_fence_fini(dev);
 673 out_irq:
 674         nouveau_irq_fini(dev);
 675 out_vblank:
 676         drm_vblank_cleanup(dev);
 677         engine->display.destroy(dev);
 678 out_fifo:
 679         if (!nouveau_noaccel)
 680                 engine->fifo.takedown(dev);
 681 out_engine:
 682         if (!nouveau_noaccel) {
 683                 for (e = e - 1; e >= 0; e--) {
 684                         if (!dev_priv->eng[e])
 685                                 continue;
 686                         dev_priv->eng[e]->fini(dev, e);
 687                         dev_priv->eng[e]->destroy(dev,e );
 688                 }
 689         }
 690
 691         engine->fb.takedown(dev);
 692 out_timer:
 693         engine->timer.takedown(dev);
 694 out_gpio:
 695         engine->gpio.takedown(dev);
 696 out_mc:
 697         engine->mc.takedown(dev);
 698 out_gart:
 699         nouveau_mem_gart_fini(dev);
 700 out_instmem:
 701         engine->instmem.takedown(dev);
 702 out_gpuobj:
 703         nouveau_gpuobj_takedown(dev);
 704 out_vram:
 705         nouveau_mem_vram_fini(dev);
 706 out_bios:
 707         nouveau_pm_fini(dev);
 708         nouveau_bios_takedown(dev);
 709 out_display_early:
 710         engine->display.late_takedown(dev);
 711 out:
 712         vga_client_register(dev->pdev, NULL, NULL, NULL);
 713         return ret;
 714 }
 715
 716 static void nouveau_card_takedown(struct drm_device *dev)
 717 {
 718         struct drm_nouveau_private *dev_priv = dev->dev_private;
 719         struct nouveau_engine *engine = &dev_priv->engine;
 720         int e;
 721
 722         if (dev_priv->channel) {
 723                 nouveau_fence_fini(dev);
 724                 nouveau_channel_put_unlocked(&dev_priv->channel);
 725         }
 726
 727         if (!nouveau_noaccel) {
 728                 engine->fifo.takedown(dev);
 729                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 730                         if (dev_priv->eng[e]) {
 731                                 dev_priv->eng[e]->fini(dev, e);
 732                                 dev_priv->eng[e]->destroy(dev,e );
 733                         }
 734                 }
 735         }
 736         engine->fb.takedown(dev);
 737         engine->timer.takedown(dev);
 738         engine->gpio.takedown(dev);
 739         engine->mc.takedown(dev);
 740         engine->display.late_takedown(dev);
 741
 742         if (dev_priv->vga_ram) {
 743                 nouveau_bo_unpin(dev_priv->vga_ram);
 744                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 745         }
 746
 747         mutex_lock(&dev->struct_mutex);
 748         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 749         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 750         mutex_unlock(&dev->struct_mutex);
 751         nouveau_mem_gart_fini(dev);
 752
 753         engine->instmem.takedown(dev);
 754         nouveau_gpuobj_takedown(dev);
 755         nouveau_mem_vram_fini(dev);
 756
 757         nouveau_irq_fini(dev);
 758         drm_vblank_cleanup(dev);
 759
 760         nouveau_pm_fini(dev);
 761         nouveau_bios_takedown(dev);
 762
 763         vga_client_register(dev->pdev, NULL, NULL, NULL);
 764 }
 765
 766 /* here a client dies, release the stuff that was allocated for its
 767  * file_priv */
 768 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 769 {
 770         nouveau_channel_cleanup(dev, file_priv);
 771 }
 772
 773 /* first module load, setup the mmio/fb mapping */
 774 /* KMS: we need mmio at load time, not when the first drm client opens. */
 775 int nouveau_firstopen(struct drm_device *dev)
 776 {
 777         return 0;
 778 }
 779
 780 /* if we have an OF card, copy vbios to RAMIN */
 781 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 782 {
 783 #if defined(__powerpc__)
 784         int size, i;
 785         const uint32_t *bios;
 786         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 787         if (!dn) {
 788                 NV_INFO(dev, "Unable to get the OF node\n");
 789                 return;
 790         }
 791
 792         bios = of_get_property(dn, "NVDA,BMP", &size);
 793         if (bios) {
 794                 for (i = 0; i < size; i += 4)
 795                         nv_wi32(dev, i, bios[i/4]);
 796                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 797         } else {
 798                 NV_INFO(dev, "Unable to get the OF bios\n");
 799         }
 800 #endif
 801 }
 802
 803 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 804 {
 805         struct pci_dev *pdev = dev->pdev;
 806         struct apertures_struct *aper = alloc_apertures(3);
 807         if (!aper)
 808                 return NULL;
 809
 810         aper->ranges[0].base = pci_resource_start(pdev, 1);
 811         aper->ranges[0].size = pci_resource_len(pdev, 1);
 812         aper->count = 1;
 813
 814         if (pci_resource_len(pdev, 2)) {
 815                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 816                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 817                 aper->count++;
 818         }
 819
 820         if (pci_resource_len(pdev, 3)) {
 821                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 822                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 823                 aper->count++;
 824         }
 825
 826         return aper;
 827 }
 828
 829 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 830 {
 831         struct drm_nouveau_private *dev_priv = dev->dev_private;
 832         bool primary = false;
 833         dev_priv->apertures = nouveau_get_apertures(dev);
 834         if (!dev_priv->apertures)
 835                 return -ENOMEM;
 836
 837 #ifdef CONFIG_X86
 838         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 839 #endif
 840
 841         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 842         return 0;
 843 }
 844
 845 int nouveau_load(struct drm_device *dev, unsigned long flags)
 846 {
 847         struct drm_nouveau_private *dev_priv;
 848         uint32_t reg0;
 849         resource_size_t mmio_start_offs;
 850         int ret;
 851
 852         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 853         if (!dev_priv) {
 854                 ret = -ENOMEM;
 855                 goto err_out;
 856         }
 857         dev->dev_private = dev_priv;
 858         dev_priv->dev = dev;
 859
 860         dev_priv->flags = flags & NOUVEAU_FLAGS;
 861
 862         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 863                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 864
 865         /* resource 0 is mmio regs */
 866         /* resource 1 is linear FB */
 867         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 868         /* resource 6 is bios */
 869
 870         /* map the mmio regs */
 871         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 872         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 873         if (!dev_priv->mmio) {
 874                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 875                          "Please report your setup to " DRIVER_EMAIL "\n");
 876                 ret = -EINVAL;
 877                 goto err_priv;
 878         }
 879         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 880                                         (unsigned long long)mmio_start_offs);
 881
 882 #ifdef __BIG_ENDIAN
 883         /* Put the card in BE mode if it's not */
 884         if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
 885                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
 886
 887         DRM_MEMORYBARRIER();
 888 #endif
 889
 890         /* Time to determine the card architecture */
 891         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 892         dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
 893
 894         /* We're dealing with >=NV10 */
 895         if ((reg0 & 0x0f000000) > 0) {
 896                 /* Bit 27-20 contain the architecture in hex */
 897                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 898                 dev_priv->stepping = (reg0 & 0xff);
 899         /* NV04 or NV05 */
 900         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 901                 if (reg0 & 0x00f00000)
 902                         dev_priv->chipset = 0x05;
 903                 else
 904                         dev_priv->chipset = 0x04;
 905         } else
 906                 dev_priv->chipset = 0xff;
 907
 908         switch (dev_priv->chipset & 0xf0) {
 909         case 0x00:
 910         case 0x10:
 911         case 0x20:
 912         case 0x30:
 913                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 914                 break;
 915         case 0x40:
 916         case 0x60:
 917                 dev_priv->card_type = NV_40;
 918                 break;
 919         case 0x50:
 920         case 0x80:
 921         case 0x90:
 922         case 0xa0:
 923                 dev_priv->card_type = NV_50;
 924                 break;
 925         case 0xc0:
 926         case 0xd0:
 927                 dev_priv->card_type = NV_C0;
 928                 break;
 929         default:
 930                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 931                 ret = -EINVAL;
 932                 goto err_mmio;
 933         }
 934
 935         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 936                 dev_priv->card_type, reg0);
 937
 938         ret = nouveau_remove_conflicting_drivers(dev);
 939         if (ret)
 940                 goto err_mmio;
 941
 942         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
 943         if (dev_priv->card_type >= NV_40) {
 944                 int ramin_bar = 2;
 945                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 946                         ramin_bar = 3;
 947
 948                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 949                 dev_priv->ramin =
 950                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 951                                 dev_priv->ramin_size);
 952                 if (!dev_priv->ramin) {
 953                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 954                         ret = -ENOMEM;
 955                         goto err_mmio;
 956                 }
 957         } else {
 958                 dev_priv->ramin_size = 1 * 1024 * 1024;
 959                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 960                                           dev_priv->ramin_size);
 961                 if (!dev_priv->ramin) {
 962                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 963                         ret = -ENOMEM;
 964                         goto err_mmio;
 965                 }
 966         }
 967
 968         nouveau_OF_copy_vbios_to_ramin(dev);
 969
 970         /* Special flags */
 971         if (dev->pci_device == 0x01a0)
 972                 dev_priv->flags |= NV_NFORCE;
 973         else if (dev->pci_device == 0x01f0)
 974                 dev_priv->flags |= NV_NFORCE2;
 975
 976         /* For kernel modesetting, init card now and bring up fbcon */
 977         ret = nouveau_card_init(dev);
 978         if (ret)
 979                 goto err_ramin;
 980
 981         return 0;
 982
 983 err_ramin:
 984         iounmap(dev_priv->ramin);
 985 err_mmio:
 986         iounmap(dev_priv->mmio);
 987 err_priv:
 988         kfree(dev_priv);
 989         dev->dev_private = NULL;
 990 err_out:
 991         return ret;
 992 }
 993
 994 void nouveau_lastclose(struct drm_device *dev)
 995 {
 996         vga_switcheroo_process_delayed_switch();
 997 }
 998
 999 int nouveau_unload(struct drm_device *dev)
1000 {
1001         struct drm_nouveau_private *dev_priv = dev->dev_private;
1002         struct nouveau_engine *engine = &dev_priv->engine;
1003
1004         drm_kms_helper_poll_fini(dev);
1005         nouveau_fbcon_fini(dev);
1006         engine->display.destroy(dev);
1007         nouveau_card_takedown(dev);
1008
1009         iounmap(dev_priv->mmio);
1010         iounmap(dev_priv->ramin);
1011
1012         kfree(dev_priv);
1013         dev->dev_private = NULL;
1014         return 0;
1015 }
1016
1017 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1018                                                 struct drm_file *file_priv)
1019 {
1020         struct drm_nouveau_private *dev_priv = dev->dev_private;
1021         struct drm_nouveau_getparam *getparam = data;
1022
1023         switch (getparam->param) {
1024         case NOUVEAU_GETPARAM_CHIPSET_ID:
1025                 getparam->value = dev_priv->chipset;
1026                 break;
1027         case NOUVEAU_GETPARAM_PCI_VENDOR:
1028                 getparam->value = dev->pci_vendor;
1029                 break;
1030         case NOUVEAU_GETPARAM_PCI_DEVICE:
1031                 getparam->value = dev->pci_device;
1032                 break;
1033         case NOUVEAU_GETPARAM_BUS_TYPE:
1034                 if (drm_pci_device_is_agp(dev))
1035                         getparam->value = NV_AGP;
1036                 else if (drm_pci_device_is_pcie(dev))
1037                         getparam->value = NV_PCIE;
1038                 else
1039                         getparam->value = NV_PCI;
1040                 break;
1041         case NOUVEAU_GETPARAM_FB_SIZE:
1042                 getparam->value = dev_priv->fb_available_size;
1043                 break;
1044         case NOUVEAU_GETPARAM_AGP_SIZE:
1045                 getparam->value = dev_priv->gart_info.aper_size;
1046                 break;
1047         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1048                 getparam->value = 0; /* deprecated */
1049                 break;
1050         case NOUVEAU_GETPARAM_PTIMER_TIME:
1051                 getparam->value = dev_priv->engine.timer.read(dev);
1052                 break;
1053         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1054                 getparam->value = 1;
1055                 break;
1056         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1057                 getparam->value = 1;
1058                 break;
1059         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1060                 /* NV40 and NV50 versions are quite different, but register
1061                  * address is the same. User is supposed to know the card
1062                  * family anyway... */
1063                 if (dev_priv->chipset >= 0x40) {
1064                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1065                         break;
1066                 }
1067                 /* FALLTHRU */
1068         default:
1069                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1070                 return -EINVAL;
1071         }
1072
1073         return 0;
1074 }
1075
1076 int
1077 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1078                        struct drm_file *file_priv)
1079 {
1080         struct drm_nouveau_setparam *setparam = data;
1081
1082         switch (setparam->param) {
1083         default:
1084                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1085                 return -EINVAL;
1086         }
1087
1088         return 0;
1089 }
1090
1091 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1092 bool
1093 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1094                 uint32_t reg, uint32_t mask, uint32_t val)
1095 {
1096         struct drm_nouveau_private *dev_priv = dev->dev_private;
1097         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1098         uint64_t start = ptimer->read(dev);
1099
1100         do {
1101                 if ((nv_rd32(dev, reg) & mask) == val)
1102                         return true;
1103         } while (ptimer->read(dev) - start < timeout);
1104
1105         return false;
1106 }
1107
1108 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1109 bool
1110 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1111                 uint32_t reg, uint32_t mask, uint32_t val)
1112 {
1113         struct drm_nouveau_private *dev_priv = dev->dev_private;
1114         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1115         uint64_t start = ptimer->read(dev);
1116
1117         do {
1118                 if ((nv_rd32(dev, reg) & mask) != val)
1119                         return true;
1120         } while (ptimer->read(dev) - start < timeout);
1121
1122         return false;
1123 }
1124
1125 /* Waits for PGRAPH to go completely idle */
1126 bool nouveau_wait_for_idle(struct drm_device *dev)
1127 {
1128         struct drm_nouveau_private *dev_priv = dev->dev_private;
1129         uint32_t mask = ~0;
1130
1131         if (dev_priv->card_type == NV_40)
1132                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1133
1134         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1135                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1136                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1137                 return false;
1138         }
1139
1140         return true;
1141 }
1142