drivers/gpu/drm/nouveau/nouveau_perf.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_pm.h"
  29
  30 static void
  31 legacy_perf_init(struct drm_device *dev)
  32 {
  33         struct drm_nouveau_private *dev_priv = dev->dev_private;
  34         struct nvbios *bios = &dev_priv->vbios;
  35         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
  36         char *perf, *entry, *bmp = &bios->data[bios->offset];
  37         int headerlen, use_straps;
  38
  39         if (bmp[5] < 0x5 || bmp[6] < 0x14) {
  40                 NV_DEBUG(dev, "BMP version too old for perf\n");
  41                 return;
  42         }
  43
  44         perf = ROMPTR(bios, bmp[0x73]);
  45         if (!perf) {
  46                 NV_DEBUG(dev, "No memclock table pointer found.\n");
  47                 return;
  48         }
  49
  50         switch (perf[0]) {
  51         case 0x12:
  52         case 0x14:
  53         case 0x18:
  54                 use_straps = 0;
  55                 headerlen = 1;
  56                 break;
  57         case 0x01:
  58                 use_straps = perf[1] & 1;
  59                 headerlen = (use_straps ? 8 : 2);
  60                 break;
  61         default:
  62                 NV_WARN(dev, "Unknown memclock table version %x.\n", perf[0]);
  63                 return;
  64         }
  65
  66         entry = perf + headerlen;
  67         if (use_straps)
  68                 entry += (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
  69
  70         sprintf(pm->perflvl[0].name, "performance_level_0");
  71         pm->perflvl[0].memory = ROM16(entry[0]) * 20;
  72         pm->nr_perflvl = 1;
  73 }
  74
  75 static struct nouveau_pm_memtiming *
  76 nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
  77                     u16 memclk, u8 *entry, u8 recordlen, u8 entries)
  78 {
  79         struct drm_nouveau_private *dev_priv = dev->dev_private;
  80         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
  81         struct nvbios *bios = &dev_priv->vbios;
  82         u8 ramcfg;
  83         int i;
  84
  85         /* perf v2 has a separate "timing map" table, we have to match
  86          * the target memory clock to a specific entry, *then* use
  87          * ramcfg to select the correct subentry
  88          */
  89         if (P->version == 2) {
  90                 u8 *tmap = ROMPTR(bios, P->data[4]);
  91                 if (!tmap) {
  92                         NV_DEBUG(dev, "no timing map pointer\n");
  93                         return NULL;
  94                 }
  95
  96                 if (tmap[0] != 0x10) {
  97                         NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
  98                         return NULL;
  99                 }
 100
 101                 entry = tmap + tmap[1];
 102                 recordlen = tmap[2] + (tmap[4] * tmap[3]);
 103                 for (i = 0; i < tmap[5]; i++, entry += recordlen) {
 104                         if (memclk >= ROM16(entry[0]) &&
 105                             memclk <= ROM16(entry[2]))
 106                                 break;
 107                 }
 108
 109                 if (i == tmap[5]) {
 110                         NV_WARN(dev, "no match in timing map table\n");
 111                         return NULL;
 112                 }
 113
 114                 entry += tmap[2];
 115                 recordlen = tmap[3];
 116                 entries   = tmap[4];
 117         }
 118
 119         ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
 120         if (bios->ram_restrict_tbl_ptr)
 121                 ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
 122
 123         if (ramcfg >= entries) {
 124                 NV_WARN(dev, "ramcfg strap out of bounds!\n");
 125                 return NULL;
 126         }
 127
 128         entry += ramcfg * recordlen;
 129         if (entry[1] >= pm->memtimings.nr_timing) {
 130                 if (entry[1] != 0xff)
 131                         NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
 132                 return NULL;
 133         }
 134
 135         return &pm->memtimings.timing[entry[1]];
 136 }
 137
 138 static void
 139 nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P,
 140                      struct nouveau_pm_level *perflvl)
 141 {
 142         struct drm_nouveau_private *dev_priv = dev->dev_private;
 143         struct nvbios *bios = &dev_priv->vbios;
 144         u8 *vmap;
 145         int id;
 146
 147         id = perflvl->volt_min;
 148         perflvl->volt_min = 0;
 149
 150         /* boards using voltage table version <0x40 store the voltage
 151          * level directly in the perflvl entry as a multiple of 10mV
 152          */
 153         if (dev_priv->engine.pm.voltage.version < 0x40) {
 154                 perflvl->volt_min = id * 10000;
 155                 perflvl->volt_max = perflvl->volt_min;
 156                 return;
 157         }
 158
 159         /* on newer ones, the perflvl stores an index into yet another
 160          * vbios table containing a min/max voltage value for the perflvl
 161          */
 162         if (P->version != 2 || P->length < 34) {
 163                 NV_DEBUG(dev, "where's our volt map table ptr? %d %d\n",
 164                          P->version, P->length);
 165                 return;
 166         }
 167
 168         vmap = ROMPTR(bios, P->data[32]);
 169         if (!vmap) {
 170                 NV_DEBUG(dev, "volt map table pointer invalid\n");
 171                 return;
 172         }
 173
 174         if (id < vmap[3]) {
 175                 vmap += vmap[1] + (vmap[2] * id);
 176                 perflvl->volt_min = ROM32(vmap[0]);
 177                 perflvl->volt_max = ROM32(vmap[4]);
 178         }
 179 }
 180
 181 void
 182 nouveau_perf_init(struct drm_device *dev)
 183 {
 184         struct drm_nouveau_private *dev_priv = dev->dev_private;
 185         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 186         struct nvbios *bios = &dev_priv->vbios;
 187         struct bit_entry P;
 188         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 189         struct nouveau_pm_tbl_header mt_hdr;
 190         u8 version, headerlen, recordlen, entries;
 191         u8 *perf, *entry;
 192         int vid, i;
 193
 194         if (bios->type == NVBIOS_BIT) {
 195                 if (bit_table(dev, 'P', &P))
 196                         return;
 197
 198                 if (P.version != 1 && P.version != 2) {
 199                         NV_WARN(dev, "unknown perf for BIT P %d\n", P.version);
 200                         return;
 201                 }
 202
 203                 perf = ROMPTR(bios, P.data[0]);
 204                 version   = perf[0];
 205                 headerlen = perf[1];
 206                 if (version < 0x40) {
 207                         recordlen = perf[3] + (perf[4] * perf[5]);
 208                         entries   = perf[2];
 209                 } else {
 210                         recordlen = perf[2] + (perf[3] * perf[4]);
 211                         entries   = perf[5];
 212                 }
 213         } else {
 214                 if (bios->data[bios->offset + 6] < 0x25) {
 215                         legacy_perf_init(dev);
 216                         return;
 217                 }
 218
 219                 perf = ROMPTR(bios, bios->data[bios->offset + 0x94]);
 220                 if (!perf) {
 221                         NV_DEBUG(dev, "perf table pointer invalid\n");
 222                         return;
 223                 }
 224
 225                 version   = perf[1];
 226                 headerlen = perf[0];
 227                 recordlen = perf[3];
 228                 entries   = perf[2];
 229         }
 230
 231         if (entries > NOUVEAU_PM_MAX_LEVEL) {
 232                 NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
 233                 entries = NOUVEAU_PM_MAX_LEVEL;
 234         }
 235
 236         entry = perf + headerlen;
 237
 238         /* For version 0x15, initialize memtiming table */
 239         if(version == 0x15) {
 240                 memtimings->timing =
 241                                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
 242                 if (!memtimings->timing) {
 243                         NV_WARN(dev,"Could not allocate memtiming table\n");
 244                         return;
 245                 }
 246
 247                 mt_hdr.entry_cnt = entries;
 248                 mt_hdr.entry_len = 14;
 249                 mt_hdr.version = version;
 250                 mt_hdr.header_len = 4;
 251         }
 252
 253         for (i = 0; i < entries; i++) {
 254                 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
 255
 256                 perflvl->timing = NULL;
 257
 258                 if (entry[0] == 0xff) {
 259                         entry += recordlen;
 260                         continue;
 261                 }
 262
 263                 switch (version) {
 264                 case 0x12:
 265                 case 0x13:
 266                 case 0x15:
 267                         perflvl->fanspeed = entry[55];
 268                         if (recordlen > 56)
 269                                 perflvl->volt_min = entry[56];
 270                         perflvl->core = ROM32(entry[1]) * 10;
 271                         perflvl->memory = ROM32(entry[5]) * 20;
 272                         break;
 273                 case 0x21:
 274                 case 0x23:
 275                 case 0x24:
 276                         perflvl->fanspeed = entry[4];
 277                         perflvl->volt_min = entry[5];
 278                         perflvl->shader = ROM16(entry[6]) * 1000;
 279                         perflvl->core = perflvl->shader;
 280                         perflvl->core += (signed char)entry[8] * 1000;
 281                         if (dev_priv->chipset == 0x49 ||
 282                             dev_priv->chipset == 0x4b)
 283                                 perflvl->memory = ROM16(entry[11]) * 1000;
 284                         else
 285                                 perflvl->memory = ROM16(entry[11]) * 2000;
 286
 287                         break;
 288                 case 0x25:
 289                         perflvl->fanspeed = entry[4];
 290                         perflvl->volt_min = entry[5];
 291                         perflvl->core = ROM16(entry[6]) * 1000;
 292                         perflvl->shader = ROM16(entry[10]) * 1000;
 293                         perflvl->memory = ROM16(entry[12]) * 1000;
 294                         break;
 295                 case 0x30:
 296                         perflvl->memscript = ROM16(entry[2]);
 297                 case 0x35:
 298                         perflvl->fanspeed = entry[6];
 299                         perflvl->volt_min = entry[7];
 300                         perflvl->core = ROM16(entry[8]) * 1000;
 301                         perflvl->shader = ROM16(entry[10]) * 1000;
 302                         perflvl->memory = ROM16(entry[12]) * 1000;
 303                         /*XXX: confirm on 0x35 */
 304                         perflvl->unk05 = ROM16(entry[16]) * 1000;
 305                         break;
 306                 case 0x40:
 307 #define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000
 308                         perflvl->fanspeed = 0; /*XXX*/
 309                         perflvl->volt_min = entry[2];
 310                         if (dev_priv->card_type == NV_50) {
 311                                 perflvl->core   = subent(0);
 312                                 perflvl->shader = subent(1);
 313                                 perflvl->memory = subent(2);
 314                                 perflvl->vdec   = subent(3);
 315                                 perflvl->unka0  = subent(4);
 316                         } else {
 317                                 perflvl->hub06  = subent(0);
 318                                 perflvl->hub01  = subent(1);
 319                                 perflvl->copy   = subent(2);
 320                                 perflvl->shader = subent(3);
 321                                 perflvl->rop    = subent(4);
 322                                 perflvl->memory = subent(5);
 323                                 perflvl->vdec   = subent(6);
 324                                 perflvl->daemon = subent(10);
 325                                 perflvl->hub07  = subent(11);
 326                                 perflvl->core   = perflvl->shader / 2;
 327                         }
 328                         break;
 329                 }
 330
 331                 /* make sure vid is valid */
 332                 nouveau_perf_voltage(dev, &P, perflvl);
 333                 if (pm->voltage.supported && perflvl->volt_min) {
 334                         vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
 335                         if (vid < 0) {
 336                                 NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i);
 337                                 entry += recordlen;
 338                                 continue;
 339                         }
 340                 }
 341
 342                 /* get the corresponding memory timings */
 343                 if (version == 0x15) {
 344                         memtimings->timing[i].id = i;
 345                         nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]);
 346                         perflvl->timing = &memtimings->timing[i];
 347                 } else if (version > 0x15) {
 348                         /* last 3 args are for < 0x40, ignored for >= 0x40 */
 349                         perflvl->timing =
 350                                 nouveau_perf_timing(dev, &P,
 351                                                     perflvl->memory / 1000,
 352                                                     entry + perf[3],
 353                                                     perf[5], perf[4]);
 354                 }
 355
 356                 snprintf(perflvl->name, sizeof(perflvl->name),
 357                          "performance_level_%d", i);
 358                 perflvl->id = i;
 359                 pm->nr_perflvl++;
 360
 361                 entry += recordlen;
 362         }
 363 }
 364
 365 void
 366 nouveau_perf_fini(struct drm_device *dev)
 367 {
 368 }