drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36 #include "nouveau_drv.h"
  37
  38 static struct mem_block *
  39 split_block(struct mem_block *p, uint64_t start, uint64_t size,
  40             struct drm_file *file_priv)
  41 {
  42         /* Maybe cut off the start of an existing block */
  43         if (start > p->start) {
  44                 struct mem_block *newblock =
  45                         kmalloc(sizeof(*newblock), GFP_KERNEL);
  46                 if (!newblock)
  47                         goto out;
  48                 newblock->start = start;
  49                 newblock->size = p->size - (start - p->start);
  50                 newblock->file_priv = NULL;
  51                 newblock->next = p->next;
  52                 newblock->prev = p;
  53                 p->next->prev = newblock;
  54                 p->next = newblock;
  55                 p->size -= newblock->size;
  56                 p = newblock;
  57         }
  58
  59         /* Maybe cut off the end of an existing block */
  60         if (size < p->size) {
  61                 struct mem_block *newblock =
  62                         kmalloc(sizeof(*newblock), GFP_KERNEL);
  63                 if (!newblock)
  64                         goto out;
  65                 newblock->start = start + size;
  66                 newblock->size = p->size - size;
  67                 newblock->file_priv = NULL;
  68                 newblock->next = p->next;
  69                 newblock->prev = p;
  70                 p->next->prev = newblock;
  71                 p->next = newblock;
  72                 p->size = size;
  73         }
  74
  75 out:
  76         /* Our block is in the middle */
  77         p->file_priv = file_priv;
  78         return p;
  79 }
  80
  81 struct mem_block *
  82 nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size,
  83                         int align2, struct drm_file *file_priv, int tail)
  84 {
  85         struct mem_block *p;
  86         uint64_t mask = (1 << align2) - 1;
  87
  88         if (!heap)
  89                 return NULL;
  90
  91         if (tail) {
  92                 list_for_each_prev(p, heap) {
  93                         uint64_t start = ((p->start + p->size) - size) & ~mask;
  94
  95                         if (p->file_priv == NULL && start >= p->start &&
  96                             start + size <= p->start + p->size)
  97                                 return split_block(p, start, size, file_priv);
  98                 }
  99         } else {
 100                 list_for_each(p, heap) {
 101                         uint64_t start = (p->start + mask) & ~mask;
 102
 103                         if (p->file_priv == NULL &&
 104                             start + size <= p->start + p->size)
 105                                 return split_block(p, start, size, file_priv);
 106                 }
 107         }
 108
 109         return NULL;
 110 }
 111
 112 void nouveau_mem_free_block(struct mem_block *p)
 113 {
 114         p->file_priv = NULL;
 115
 116         /* Assumes a single contiguous range.  Needs a special file_priv in
 117          * 'heap' to stop it being subsumed.
 118          */
 119         if (p->next->file_priv == NULL) {
 120                 struct mem_block *q = p->next;
 121                 p->size += q->size;
 122                 p->next = q->next;
 123                 p->next->prev = p;
 124                 kfree(q);
 125         }
 126
 127         if (p->prev->file_priv == NULL) {
 128                 struct mem_block *q = p->prev;
 129                 q->size += p->size;
 130                 q->next = p->next;
 131                 q->next->prev = q;
 132                 kfree(p);
 133         }
 134 }
 135
 136 /* Initialize.  How to check for an uninitialized heap?
 137  */
 138 int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start,
 139                           uint64_t size)
 140 {
 141         struct mem_block *blocks = kmalloc(sizeof(*blocks), GFP_KERNEL);
 142
 143         if (!blocks)
 144                 return -ENOMEM;
 145
 146         *heap = kmalloc(sizeof(**heap), GFP_KERNEL);
 147         if (!*heap) {
 148                 kfree(blocks);
 149                 return -ENOMEM;
 150         }
 151
 152         blocks->start = start;
 153         blocks->size = size;
 154         blocks->file_priv = NULL;
 155         blocks->next = blocks->prev = *heap;
 156
 157         memset(*heap, 0, sizeof(**heap));
 158         (*heap)->file_priv = (struct drm_file *) -1;
 159         (*heap)->next = (*heap)->prev = blocks;
 160         return 0;
 161 }
 162
 163 /*
 164  * Free all blocks associated with the releasing file_priv
 165  */
 166 void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
 167 {
 168         struct mem_block *p;
 169
 170         if (!heap || !heap->next)
 171                 return;
 172
 173         list_for_each(p, heap) {
 174                 if (p->file_priv == file_priv)
 175                         p->file_priv = NULL;
 176         }
 177
 178         /* Assumes a single contiguous range.  Needs a special file_priv in
 179          * 'heap' to stop it being subsumed.
 180          */
 181         list_for_each(p, heap) {
 182                 while ((p->file_priv == NULL) &&
 183                                         (p->next->file_priv == NULL) &&
 184                                         (p->next != heap)) {
 185                         struct mem_block *q = p->next;
 186                         p->size += q->size;
 187                         p->next = q->next;
 188                         p->next->prev = p;
 189                         kfree(q);
 190                 }
 191         }
 192 }
 193
 194 /*
 195  * NV10-NV40 tiling helpers
 196  */
 197
 198 static void
 199 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
 200                            uint32_t size, uint32_t pitch)
 201 {
 202         struct drm_nouveau_private *dev_priv = dev->dev_private;
 203         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 204         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 205         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 206         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 207
 208         tile->addr = addr;
 209         tile->size = size;
 210         tile->used = !!pitch;
 211         nouveau_fence_unref((void **)&tile->fence);
 212
 213         if (!pfifo->cache_flush(dev))
 214                 return;
 215
 216         pfifo->reassign(dev, false);
 217         pfifo->cache_flush(dev);
 218         pfifo->cache_pull(dev, false);
 219
 220         nouveau_wait_for_idle(dev);
 221
 222         pgraph->set_region_tiling(dev, i, addr, size, pitch);
 223         pfb->set_region_tiling(dev, i, addr, size, pitch);
 224
 225         pfifo->cache_pull(dev, true);
 226         pfifo->reassign(dev, true);
 227 }
 228
 229 struct nouveau_tile_reg *
 230 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 231                     uint32_t pitch)
 232 {
 233         struct drm_nouveau_private *dev_priv = dev->dev_private;
 234         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 235         struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
 236         int i;
 237
 238         spin_lock(&dev_priv->tile.lock);
 239
 240         for (i = 0; i < pfb->num_tiles; i++) {
 241                 if (tile[i].used)
 242                         /* Tile region in use. */
 243                         continue;
 244
 245                 if (tile[i].fence &&
 246                     !nouveau_fence_signalled(tile[i].fence, NULL))
 247                         /* Pending tile region. */
 248                         continue;
 249
 250                 if (max(tile[i].addr, addr) <
 251                     min(tile[i].addr + tile[i].size, addr + size))
 252                         /* Kill an intersecting tile region. */
 253                         nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
 254
 255                 if (pitch && !found) {
 256                         /* Free tile region. */
 257                         nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
 258                         found = &tile[i];
 259                 }
 260         }
 261
 262         spin_unlock(&dev_priv->tile.lock);
 263
 264         return found;
 265 }
 266
 267 void
 268 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
 269                        struct nouveau_fence *fence)
 270 {
 271         if (fence) {
 272                 /* Mark it as pending. */
 273                 tile->fence = fence;
 274                 nouveau_fence_ref(fence);
 275         }
 276
 277         tile->used = false;
 278 }
 279
 280 /*
 281  * NV50 VM helpers
 282  */
 283 int
 284 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 285                         uint32_t flags, uint64_t phys)
 286 {
 287         struct drm_nouveau_private *dev_priv = dev->dev_private;
 288         struct nouveau_gpuobj **pgt;
 289         unsigned psz, pfl, pages;
 290
 291         if (virt >= dev_priv->vm_gart_base &&
 292             (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) {
 293                 psz = 12;
 294                 pgt = &dev_priv->gart_info.sg_ctxdma;
 295                 pfl = 0x21;
 296                 virt -= dev_priv->vm_gart_base;
 297         } else
 298         if (virt >= dev_priv->vm_vram_base &&
 299             (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) {
 300                 psz = 16;
 301                 pgt = dev_priv->vm_vram_pt;
 302                 pfl = 0x01;
 303                 virt -= dev_priv->vm_vram_base;
 304         } else {
 305                 NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
 306                          virt, virt + size - 1);
 307                 return -EINVAL;
 308         }
 309
 310         pages = size >> psz;
 311
 312         dev_priv->engine.instmem.prepare_access(dev, true);
 313         if (flags & 0x80000000) {
 314                 while (pages--) {
 315                         struct nouveau_gpuobj *pt = pgt[virt >> 29];
 316                         unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
 317
 318                         nv_wo32(dev, pt, pte++, 0x00000000);
 319                         nv_wo32(dev, pt, pte++, 0x00000000);
 320
 321                         virt += (1 << psz);
 322                 }
 323         } else {
 324                 while (pages--) {
 325                         struct nouveau_gpuobj *pt = pgt[virt >> 29];
 326                         unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
 327                         unsigned offset_h = upper_32_bits(phys) & 0xff;
 328                         unsigned offset_l = lower_32_bits(phys);
 329
 330                         nv_wo32(dev, pt, pte++, offset_l | pfl);
 331                         nv_wo32(dev, pt, pte++, offset_h | flags);
 332
 333                         phys += (1 << psz);
 334                         virt += (1 << psz);
 335                 }
 336         }
 337         dev_priv->engine.instmem.finish_access(dev);
 338
 339         nv_wr32(dev, 0x100c80, 0x00050001);
 340         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
 341                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
 342                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
 343                 return -EBUSY;
 344         }
 345
 346         nv_wr32(dev, 0x100c80, 0x00000001);
 347         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
 348                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
 349                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
 350                 return -EBUSY;
 351         }
 352
 353         return 0;
 354 }
 355
 356 void
 357 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
 358 {
 359         nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0);
 360 }
 361
 362 /*
 363  * Cleanup everything
 364  */
 365 void nouveau_mem_takedown(struct mem_block **heap)
 366 {
 367         struct mem_block *p;
 368
 369         if (!*heap)
 370                 return;
 371
 372         for (p = (*heap)->next; p != *heap;) {
 373                 struct mem_block *q = p;
 374                 p = p->next;
 375                 kfree(q);
 376         }
 377
 378         kfree(*heap);
 379         *heap = NULL;
 380 }
 381
 382 void nouveau_mem_close(struct drm_device *dev)
 383 {
 384         struct drm_nouveau_private *dev_priv = dev->dev_private;
 385
 386         if (dev_priv->ttm.bdev.man[TTM_PL_PRIV0].has_type)
 387                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_PRIV0);
 388         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 389
 390         ttm_bo_device_release(&dev_priv->ttm.bdev);
 391
 392         nouveau_ttm_global_release(dev_priv);
 393
 394         if (drm_core_has_AGP(dev) && dev->agp &&
 395             drm_core_check_feature(dev, DRIVER_MODESET)) {
 396                 struct drm_agp_mem *entry, *tempe;
 397
 398                 /* Remove AGP resources, but leave dev->agp
 399                    intact until drv_cleanup is called. */
 400                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 401                         if (entry->bound)
 402                                 drm_unbind_agp(entry->memory);
 403                         drm_free_agp(entry->memory, entry->pages);
 404                         kfree(entry);
 405                 }
 406                 INIT_LIST_HEAD(&dev->agp->memory);
 407
 408                 if (dev->agp->acquired)
 409                         drm_agp_release(dev);
 410
 411                 dev->agp->acquired = 0;
 412                 dev->agp->enabled = 0;
 413         }
 414
 415         if (dev_priv->fb_mtrr) {
 416                 drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),
 417                              drm_get_resource_len(dev, 1), DRM_MTRR_WC);
 418                 dev_priv->fb_mtrr = 0;
 419         }
 420 }
 421
 422 /*XXX won't work on BSD because of pci_read_config_dword */
 423 static uint32_t
 424 nouveau_mem_fb_amount_igp(struct drm_device *dev)
 425 {
 426         struct drm_nouveau_private *dev_priv = dev->dev_private;
 427         struct pci_dev *bridge;
 428         uint32_t mem;
 429
 430         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 431         if (!bridge) {
 432                 NV_ERROR(dev, "no bridge device\n");
 433                 return 0;
 434         }
 435
 436         if (dev_priv->flags&NV_NFORCE) {
 437                 pci_read_config_dword(bridge, 0x7C, &mem);
 438                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 439         } else
 440         if (dev_priv->flags&NV_NFORCE2) {
 441                 pci_read_config_dword(bridge, 0x84, &mem);
 442                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 443         }
 444
 445         NV_ERROR(dev, "impossible!\n");
 446         return 0;
 447 }
 448
 449 /* returns the amount of FB ram in bytes */
 450 uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
 451 {
 452         struct drm_nouveau_private *dev_priv = dev->dev_private;
 453         uint32_t boot0;
 454
 455         switch (dev_priv->card_type) {
 456         case NV_04:
 457                 boot0 = nv_rd32(dev, NV03_BOOT_0);
 458                 if (boot0 & 0x00000100)
 459                         return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 460
 461                 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
 462                 case NV04_BOOT_0_RAM_AMOUNT_32MB:
 463                         return 32 * 1024 * 1024;
 464                 case NV04_BOOT_0_RAM_AMOUNT_16MB:
 465                         return 16 * 1024 * 1024;
 466                 case NV04_BOOT_0_RAM_AMOUNT_8MB:
 467                         return 8 * 1024 * 1024;
 468                 case NV04_BOOT_0_RAM_AMOUNT_4MB:
 469                         return 4 * 1024 * 1024;
 470                 }
 471                 break;
 472         case NV_10:
 473         case NV_20:
 474         case NV_30:
 475         case NV_40:
 476         case NV_50:
 477         default:
 478                 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 479                         return nouveau_mem_fb_amount_igp(dev);
 480                 } else {
 481                         uint64_t mem;
 482                         mem = (nv_rd32(dev, NV04_FIFO_DATA) &
 483                                         NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
 484                                         NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
 485                         return mem * 1024 * 1024;
 486                 }
 487                 break;
 488         }
 489
 490         NV_ERROR(dev,
 491                 "Unable to detect video ram size. Please report your setup to "
 492                                                         DRIVER_EMAIL "\n");
 493         return 0;
 494 }
 495
 496 #if __OS_HAS_AGP
 497 static void nouveau_mem_reset_agp(struct drm_device *dev)
 498 {
 499         uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
 500
 501         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 502         saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19);
 503
 504         /* clear busmaster bit */
 505         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 506         /* clear SBA and AGP bits */
 507         nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);
 508
 509         /* power cycle pgraph, if enabled */
 510         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 511         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 512                 nv_wr32(dev, NV03_PMC_ENABLE,
 513                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 514                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 515                                 NV_PMC_ENABLE_PGRAPH);
 516         }
 517
 518         /* and restore (gives effect of resetting AGP) */
 519         nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
 520         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 521 }
 522 #endif
 523
 524 int
 525 nouveau_mem_init_agp(struct drm_device *dev)
 526 {
 527 #if __OS_HAS_AGP
 528         struct drm_nouveau_private *dev_priv = dev->dev_private;
 529         struct drm_agp_info info;
 530         struct drm_agp_mode mode;
 531         int ret;
 532
 533         if (nouveau_noagp)
 534                 return 0;
 535
 536         nouveau_mem_reset_agp(dev);
 537
 538         if (!dev->agp->acquired) {
 539                 ret = drm_agp_acquire(dev);
 540                 if (ret) {
 541                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 542                         return ret;
 543                 }
 544         }
 545
 546         ret = drm_agp_info(dev, &info);
 547         if (ret) {
 548                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 549                 return ret;
 550         }
 551
 552         /* see agp.h for the AGPSTAT_* modes available */
 553         mode.mode = info.mode;
 554         ret = drm_agp_enable(dev, mode);
 555         if (ret) {
 556                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 557                 return ret;
 558         }
 559
 560         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 561         dev_priv->gart_info.aper_base   = info.aperture_base;
 562         dev_priv->gart_info.aper_size   = info.aperture_size;
 563 #endif
 564         return 0;
 565 }
 566
 567 int
 568 nouveau_mem_init(struct drm_device *dev)
 569 {
 570         struct drm_nouveau_private *dev_priv = dev->dev_private;
 571         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 572         int ret, dma_bits = 32;
 573
 574         dev_priv->fb_phys = drm_get_resource_start(dev, 1);
 575         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 576
 577         if (dev_priv->card_type >= NV_50 &&
 578             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 579                 dma_bits = 40;
 580
 581         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 582         if (ret) {
 583                 NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
 584                 return ret;
 585         }
 586
 587         ret = nouveau_ttm_global_init(dev_priv);
 588         if (ret)
 589                 return ret;
 590
 591         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 592                                  dev_priv->ttm.bo_global_ref.ref.object,
 593                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 594                                  dma_bits <= 32 ? true : false);
 595         if (ret) {
 596                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 597                 return ret;
 598         }
 599
 600         INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
 601         spin_lock_init(&dev_priv->ttm.bo_list_lock);
 602         spin_lock_init(&dev_priv->tile.lock);
 603
 604         dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);
 605
 606         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 607         if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1))
 608                 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1);
 609         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 610
 611         NV_INFO(dev, "%d MiB VRAM\n", (int)(dev_priv->fb_available_size >> 20));
 612
 613         /* remove reserved space at end of vram from available amount */
 614         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 615         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 616
 617         /* mappable vram */
 618         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 619                              dev_priv->fb_available_size >> PAGE_SHIFT);
 620         if (ret) {
 621                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 622                 return ret;
 623         }
 624
 625         /* GART */
 626 #if !defined(__powerpc__) && !defined(__ia64__)
 627         if (drm_device_is_agp(dev) && dev->agp) {
 628                 ret = nouveau_mem_init_agp(dev);
 629                 if (ret)
 630                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 631         }
 632 #endif
 633
 634         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 635                 ret = nouveau_sgdma_init(dev);
 636                 if (ret) {
 637                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 638                         return ret;
 639                 }
 640         }
 641
 642         NV_INFO(dev, "%d MiB GART (aperture)\n",
 643                 (int)(dev_priv->gart_info.aper_size >> 20));
 644         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 645
 646         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 647                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 648         if (ret) {
 649                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 650                 return ret;
 651         }
 652
 653         dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1),
 654                                          drm_get_resource_len(dev, 1),
 655                                          DRM_MTRR_WC);
 656         return 0;
 657 }
 658
 659