drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36
  37 #include "nouveau_drv.h"
  38 #include "nouveau_pm.h"
  39 #include "nouveau_mm.h"
  40 #include "nouveau_vm.h"
  41
  42 /*
  43  * NV10-NV40 tiling helpers
  44  */
  45
  46 static void
  47 nv10_mem_update_tile_region(struct drm_device *dev,
  48                             struct nouveau_tile_reg *tile, uint32_t addr,
  49                             uint32_t size, uint32_t pitch, uint32_t flags)
  50 {
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  53         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  54         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  55         int i = tile - dev_priv->tile.reg;
  56         unsigned long save;
  57
  58         nouveau_fence_unref(&tile->fence);
  59
  60         if (tile->pitch)
  61                 pfb->free_tile_region(dev, i);
  62
  63         if (pitch)
  64                 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  65
  66         spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  67         pfifo->reassign(dev, false);
  68         pfifo->cache_pull(dev, false);
  69
  70         nouveau_wait_for_idle(dev);
  71
  72         pfb->set_tile_region(dev, i);
  73         pgraph->set_tile_region(dev, i);
  74
  75         pfifo->cache_pull(dev, true);
  76         pfifo->reassign(dev, true);
  77         spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  78 }
  79
  80 static struct nouveau_tile_reg *
  81 nv10_mem_get_tile_region(struct drm_device *dev, int i)
  82 {
  83         struct drm_nouveau_private *dev_priv = dev->dev_private;
  84         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  85
  86         spin_lock(&dev_priv->tile.lock);
  87
  88         if (!tile->used &&
  89             (!tile->fence || nouveau_fence_signalled(tile->fence)))
  90                 tile->used = true;
  91         else
  92                 tile = NULL;
  93
  94         spin_unlock(&dev_priv->tile.lock);
  95         return tile;
  96 }
  97
  98 void
  99 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
 100                          struct nouveau_fence *fence)
 101 {
 102         struct drm_nouveau_private *dev_priv = dev->dev_private;
 103
 104         if (tile) {
 105                 spin_lock(&dev_priv->tile.lock);
 106                 if (fence) {
 107                         /* Mark it as pending. */
 108                         tile->fence = fence;
 109                         nouveau_fence_ref(fence);
 110                 }
 111
 112                 tile->used = false;
 113                 spin_unlock(&dev_priv->tile.lock);
 114         }
 115 }
 116
 117 struct nouveau_tile_reg *
 118 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 119                     uint32_t pitch, uint32_t flags)
 120 {
 121         struct drm_nouveau_private *dev_priv = dev->dev_private;
 122         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 123         struct nouveau_tile_reg *tile, *found = NULL;
 124         int i;
 125
 126         for (i = 0; i < pfb->num_tiles; i++) {
 127                 tile = nv10_mem_get_tile_region(dev, i);
 128
 129                 if (pitch && !found) {
 130                         found = tile;
 131                         continue;
 132
 133                 } else if (tile && tile->pitch) {
 134                         /* Kill an unused tile region. */
 135                         nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
 136                 }
 137
 138                 nv10_mem_put_tile_region(dev, tile, NULL);
 139         }
 140
 141         if (found)
 142                 nv10_mem_update_tile_region(dev, found, addr, size,
 143                                             pitch, flags);
 144         return found;
 145 }
 146
 147 /*
 148  * Cleanup everything
 149  */
 150 void
 151 nouveau_mem_vram_fini(struct drm_device *dev)
 152 {
 153         struct drm_nouveau_private *dev_priv = dev->dev_private;
 154
 155         nouveau_bo_unpin(dev_priv->vga_ram);
 156         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 157
 158         ttm_bo_device_release(&dev_priv->ttm.bdev);
 159
 160         nouveau_ttm_global_release(dev_priv);
 161
 162         if (dev_priv->fb_mtrr >= 0) {
 163                 drm_mtrr_del(dev_priv->fb_mtrr,
 164                              pci_resource_start(dev->pdev, 1),
 165                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 166                 dev_priv->fb_mtrr = -1;
 167         }
 168 }
 169
 170 void
 171 nouveau_mem_gart_fini(struct drm_device *dev)
 172 {
 173         nouveau_sgdma_takedown(dev);
 174
 175         if (drm_core_has_AGP(dev) && dev->agp) {
 176                 struct drm_agp_mem *entry, *tempe;
 177
 178                 /* Remove AGP resources, but leave dev->agp
 179                    intact until drv_cleanup is called. */
 180                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 181                         if (entry->bound)
 182                                 drm_unbind_agp(entry->memory);
 183                         drm_free_agp(entry->memory, entry->pages);
 184                         kfree(entry);
 185                 }
 186                 INIT_LIST_HEAD(&dev->agp->memory);
 187
 188                 if (dev->agp->acquired)
 189                         drm_agp_release(dev);
 190
 191                 dev->agp->acquired = 0;
 192                 dev->agp->enabled = 0;
 193         }
 194 }
 195
 196 static uint32_t
 197 nouveau_mem_detect_nv04(struct drm_device *dev)
 198 {
 199         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 200
 201         if (boot0 & 0x00000100)
 202                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 203
 204         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 205         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 206                 return 32 * 1024 * 1024;
 207         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 208                 return 16 * 1024 * 1024;
 209         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 210                 return 8 * 1024 * 1024;
 211         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 212                 return 4 * 1024 * 1024;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static uint32_t
 219 nouveau_mem_detect_nforce(struct drm_device *dev)
 220 {
 221         struct drm_nouveau_private *dev_priv = dev->dev_private;
 222         struct pci_dev *bridge;
 223         uint32_t mem;
 224
 225         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 226         if (!bridge) {
 227                 NV_ERROR(dev, "no bridge device\n");
 228                 return 0;
 229         }
 230
 231         if (dev_priv->flags & NV_NFORCE) {
 232                 pci_read_config_dword(bridge, 0x7C, &mem);
 233                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 234         } else
 235         if (dev_priv->flags & NV_NFORCE2) {
 236                 pci_read_config_dword(bridge, 0x84, &mem);
 237                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 238         }
 239
 240         NV_ERROR(dev, "impossible!\n");
 241         return 0;
 242 }
 243
 244 int
 245 nouveau_mem_detect(struct drm_device *dev)
 246 {
 247         struct drm_nouveau_private *dev_priv = dev->dev_private;
 248
 249         if (dev_priv->card_type == NV_04) {
 250                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 251         } else
 252         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 253                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 254         } else
 255         if (dev_priv->card_type < NV_50) {
 256                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 257                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 258         }
 259
 260         if (dev_priv->vram_size)
 261                 return 0;
 262         return -ENOMEM;
 263 }
 264
 265 bool
 266 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
 267 {
 268         if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
 269                 return true;
 270
 271         return false;
 272 }
 273
 274 #if __OS_HAS_AGP
 275 static unsigned long
 276 get_agp_mode(struct drm_device *dev, unsigned long mode)
 277 {
 278         struct drm_nouveau_private *dev_priv = dev->dev_private;
 279
 280         /*
 281          * FW seems to be broken on nv18, it makes the card lock up
 282          * randomly.
 283          */
 284         if (dev_priv->chipset == 0x18)
 285                 mode &= ~PCI_AGP_COMMAND_FW;
 286
 287         /*
 288          * AGP mode set in the command line.
 289          */
 290         if (nouveau_agpmode > 0) {
 291                 bool agpv3 = mode & 0x8;
 292                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 293
 294                 mode = (mode & ~0x7) | (rate & 0x7);
 295         }
 296
 297         return mode;
 298 }
 299 #endif
 300
 301 int
 302 nouveau_mem_reset_agp(struct drm_device *dev)
 303 {
 304 #if __OS_HAS_AGP
 305         uint32_t saved_pci_nv_1, pmc_enable;
 306         int ret;
 307
 308         /* First of all, disable fast writes, otherwise if it's
 309          * already enabled in the AGP bridge and we disable the card's
 310          * AGP controller we might be locking ourselves out of it. */
 311         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 312              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 313                 struct drm_agp_info info;
 314                 struct drm_agp_mode mode;
 315
 316                 ret = drm_agp_info(dev, &info);
 317                 if (ret)
 318                         return ret;
 319
 320                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 321                 ret = drm_agp_enable(dev, mode);
 322                 if (ret)
 323                         return ret;
 324         }
 325
 326         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 327
 328         /* clear busmaster bit */
 329         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 330         /* disable AGP */
 331         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 332
 333         /* power cycle pgraph, if enabled */
 334         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 335         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 336                 nv_wr32(dev, NV03_PMC_ENABLE,
 337                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 338                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 339                                 NV_PMC_ENABLE_PGRAPH);
 340         }
 341
 342         /* and restore (gives effect of resetting AGP) */
 343         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 344 #endif
 345
 346         return 0;
 347 }
 348
 349 int
 350 nouveau_mem_init_agp(struct drm_device *dev)
 351 {
 352 #if __OS_HAS_AGP
 353         struct drm_nouveau_private *dev_priv = dev->dev_private;
 354         struct drm_agp_info info;
 355         struct drm_agp_mode mode;
 356         int ret;
 357
 358         if (!dev->agp->acquired) {
 359                 ret = drm_agp_acquire(dev);
 360                 if (ret) {
 361                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 362                         return ret;
 363                 }
 364         }
 365
 366         nouveau_mem_reset_agp(dev);
 367
 368         ret = drm_agp_info(dev, &info);
 369         if (ret) {
 370                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 371                 return ret;
 372         }
 373
 374         /* see agp.h for the AGPSTAT_* modes available */
 375         mode.mode = get_agp_mode(dev, info.mode);
 376         ret = drm_agp_enable(dev, mode);
 377         if (ret) {
 378                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 379                 return ret;
 380         }
 381
 382         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 383         dev_priv->gart_info.aper_base   = info.aperture_base;
 384         dev_priv->gart_info.aper_size   = info.aperture_size;
 385 #endif
 386         return 0;
 387 }
 388
 389 int
 390 nouveau_mem_vram_init(struct drm_device *dev)
 391 {
 392         struct drm_nouveau_private *dev_priv = dev->dev_private;
 393         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 394         int ret, dma_bits;
 395
 396         if (dev_priv->card_type >= NV_50 &&
 397             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 398                 dma_bits = 40;
 399         else
 400                 dma_bits = 32;
 401
 402         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 403         if (ret)
 404                 return ret;
 405
 406         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 407
 408         ret = nouveau_ttm_global_init(dev_priv);
 409         if (ret)
 410                 return ret;
 411
 412         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 413                                  dev_priv->ttm.bo_global_ref.ref.object,
 414                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 415                                  dma_bits <= 32 ? true : false);
 416         if (ret) {
 417                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 418                 return ret;
 419         }
 420
 421         /* reserve space at end of VRAM for PRAMIN */
 422         if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
 423             dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
 424                 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
 425         else
 426         if (dev_priv->card_type >= NV_40)
 427                 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
 428         else
 429                 dev_priv->ramin_rsvd_vram = (512 * 1024);
 430
 431         ret = dev_priv->engine.vram.init(dev);
 432         if (ret)
 433                 return ret;
 434
 435         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 436         if (dev_priv->vram_sys_base) {
 437                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 438                         dev_priv->vram_sys_base);
 439         }
 440
 441         dev_priv->fb_available_size = dev_priv->vram_size;
 442         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 443         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 444                 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
 445         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 446
 447         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 448         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 449
 450         /* mappable vram */
 451         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 452                              dev_priv->fb_available_size >> PAGE_SHIFT);
 453         if (ret) {
 454                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 455                 return ret;
 456         }
 457
 458         ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
 459                              0, 0, true, true, &dev_priv->vga_ram);
 460         if (ret == 0)
 461                 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
 462         if (ret) {
 463                 NV_WARN(dev, "failed to reserve VGA memory\n");
 464                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 465         }
 466
 467         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 468                                          pci_resource_len(dev->pdev, 1),
 469                                          DRM_MTRR_WC);
 470         return 0;
 471 }
 472
 473 int
 474 nouveau_mem_gart_init(struct drm_device *dev)
 475 {
 476         struct drm_nouveau_private *dev_priv = dev->dev_private;
 477         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 478         int ret;
 479
 480         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 481
 482 #if !defined(__powerpc__) && !defined(__ia64__)
 483         if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 484                 ret = nouveau_mem_init_agp(dev);
 485                 if (ret)
 486                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 487         }
 488 #endif
 489
 490         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 491                 ret = nouveau_sgdma_init(dev);
 492                 if (ret) {
 493                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 494                         return ret;
 495                 }
 496         }
 497
 498         NV_INFO(dev, "%d MiB GART (aperture)\n",
 499                 (int)(dev_priv->gart_info.aper_size >> 20));
 500         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 501
 502         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 503                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 504         if (ret) {
 505                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 506                 return ret;
 507         }
 508
 509         return 0;
 510 }
 511
 512 void
 513 nouveau_mem_timing_init(struct drm_device *dev)
 514 {
 515         /* cards < NVC0 only */
 516         struct drm_nouveau_private *dev_priv = dev->dev_private;
 517         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 518         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 519         struct nvbios *bios = &dev_priv->vbios;
 520         struct bit_entry P;
 521         u8 tUNK_0, tUNK_1, tUNK_2;
 522         u8 tRP;         /* Byte 3 */
 523         u8 tRAS;        /* Byte 5 */
 524         u8 tRFC;        /* Byte 7 */
 525         u8 tRC;         /* Byte 9 */
 526         u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
 527         u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
 528         u8 *mem = NULL, *entry;
 529         int i, recordlen, entries;
 530
 531         if (bios->type == NVBIOS_BIT) {
 532                 if (bit_table(dev, 'P', &P))
 533                         return;
 534
 535                 if (P.version == 1)
 536                         mem = ROMPTR(bios, P.data[4]);
 537                 else
 538                 if (P.version == 2)
 539                         mem = ROMPTR(bios, P.data[8]);
 540                 else {
 541                         NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
 542                 }
 543         } else {
 544                 NV_DEBUG(dev, "BMP version too old for memory\n");
 545                 return;
 546         }
 547
 548         if (!mem) {
 549                 NV_DEBUG(dev, "memory timing table pointer invalid\n");
 550                 return;
 551         }
 552
 553         if (mem[0] != 0x10) {
 554                 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
 555                 return;
 556         }
 557
 558         /* validate record length */
 559         entries   = mem[2];
 560         recordlen = mem[3];
 561         if (recordlen < 15) {
 562                 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
 563                 return;
 564         }
 565
 566         /* parse vbios entries into common format */
 567         memtimings->timing =
 568                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
 569         if (!memtimings->timing)
 570                 return;
 571
 572         entry = mem + mem[1];
 573         for (i = 0; i < entries; i++, entry += recordlen) {
 574                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
 575                 if (entry[0] == 0)
 576                         continue;
 577
 578                 tUNK_18 = 1;
 579                 tUNK_19 = 1;
 580                 tUNK_20 = 0;
 581                 tUNK_21 = 0;
 582                 switch (min(recordlen, 22)) {
 583                 case 22:
 584                         tUNK_21 = entry[21];
 585                 case 21:
 586                         tUNK_20 = entry[20];
 587                 case 20:
 588                         tUNK_19 = entry[19];
 589                 case 19:
 590                         tUNK_18 = entry[18];
 591                 default:
 592                         tUNK_0  = entry[0];
 593                         tUNK_1  = entry[1];
 594                         tUNK_2  = entry[2];
 595                         tRP     = entry[3];
 596                         tRAS    = entry[5];
 597                         tRFC    = entry[7];
 598                         tRC     = entry[9];
 599                         tUNK_10 = entry[10];
 600                         tUNK_11 = entry[11];
 601                         tUNK_12 = entry[12];
 602                         tUNK_13 = entry[13];
 603                         tUNK_14 = entry[14];
 604                         break;
 605                 }
 606
 607                 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
 608
 609                 /* XXX: I don't trust the -1's and +1's... they must come
 610                  *      from somewhere! */
 611                 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
 612                                       tUNK_18 << 16 |
 613                                       (tUNK_1 + tUNK_19 + 1) << 8 |
 614                                       (tUNK_2 - 1));
 615
 616                 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
 617                 if(recordlen > 19) {
 618                         timing->reg_100228 += (tUNK_19 - 1) << 24;
 619                 }/* I cannot back-up this else-statement right now
 620                          else {
 621                         timing->reg_100228 += tUNK_12 << 24;
 622                 }*/
 623
 624                 /* XXX: reg_10022c */
 625                 timing->reg_10022c = tUNK_2 - 1;
 626
 627                 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
 628                                       tUNK_13 << 8  | tUNK_13);
 629
 630                 /* XXX: +6? */
 631                 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
 632                 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
 633
 634                 /* XXX; reg_100238, reg_10023c
 635                  * reg: 0x00??????
 636                  * reg_10023c:
 637                  *      0 for pre-NV50 cards
 638                  *      0x????0202 for NV50+ cards (empirical evidence) */
 639                 if(dev_priv->card_type >= NV_50) {
 640                         timing->reg_10023c = 0x202;
 641                 }
 642
 643                 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
 644                          timing->reg_100220, timing->reg_100224,
 645                          timing->reg_100228, timing->reg_10022c);
 646                 NV_DEBUG(dev, "         230: %08x %08x %08x %08x\n",
 647                          timing->reg_100230, timing->reg_100234,
 648                          timing->reg_100238, timing->reg_10023c);
 649         }
 650
 651         memtimings->nr_timing  = entries;
 652         memtimings->supported = true;
 653 }
 654
 655 void
 656 nouveau_mem_timing_fini(struct drm_device *dev)
 657 {
 658         struct drm_nouveau_private *dev_priv = dev->dev_private;
 659         struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
 660
 661         kfree(mem->timing);
 662 }
 663
 664 static int
 665 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long p_size)
 666 {
 667         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 668         struct nouveau_mm *mm;
 669         u32 b_size;
 670         int ret;
 671
 672         p_size = (p_size << PAGE_SHIFT) >> 12;
 673         b_size = dev_priv->vram_rblock_size >> 12;
 674
 675         ret = nouveau_mm_init(&mm, 0, p_size, b_size);
 676         if (ret)
 677                 return ret;
 678
 679         man->priv = mm;
 680         return 0;
 681 }
 682
 683 static int
 684 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
 685 {
 686         struct nouveau_mm *mm = man->priv;
 687         int ret;
 688
 689         ret = nouveau_mm_fini(&mm);
 690         if (ret)
 691                 return ret;
 692
 693         man->priv = NULL;
 694         return 0;
 695 }
 696
 697 static void
 698 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
 699                          struct ttm_mem_reg *mem)
 700 {
 701         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 702         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 703         struct drm_device *dev = dev_priv->dev;
 704
 705         vram->put(dev, (struct nouveau_vram **)&mem->mm_node);
 706 }
 707
 708 static int
 709 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 710                          struct ttm_buffer_object *bo,
 711                          struct ttm_placement *placement,
 712                          struct ttm_mem_reg *mem)
 713 {
 714         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 715         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 716         struct drm_device *dev = dev_priv->dev;
 717         struct nouveau_bo *nvbo = nouveau_bo(bo);
 718         struct nouveau_vram *node;
 719         u32 size_nc = 0;
 720         int ret;
 721
 722         if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
 723                 size_nc = 1 << nvbo->vma.node->type;
 724
 725         ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
 726                         mem->page_alignment << PAGE_SHIFT, size_nc,
 727                         (nvbo->tile_flags >> 8) & 0xff, &node);
 728         if (ret) {
 729                 mem->mm_node = NULL;
 730                 return (ret == -ENOSPC) ? 0 : ret;
 731         }
 732
 733         node->page_shift = 12;
 734         if (nvbo->vma.node)
 735                 node->page_shift = nvbo->vma.node->type;
 736
 737         mem->mm_node = node;
 738         mem->start   = node->offset >> PAGE_SHIFT;
 739         return 0;
 740 }
 741
 742 void
 743 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 744 {
 745         struct nouveau_mm *mm = man->priv;
 746         struct nouveau_mm_node *r;
 747         u32 total = 0, free = 0;
 748
 749         mutex_lock(&mm->mutex);
 750         list_for_each_entry(r, &mm->nodes, nl_entry) {
 751                 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
 752                        prefix, r->type, ((u64)r->offset << 12),
 753                        (((u64)r->offset + r->length) << 12));
 754
 755                 total += r->length;
 756                 if (!r->type)
 757                         free += r->length;
 758         }
 759         mutex_unlock(&mm->mutex);
 760
 761         printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
 762                prefix, (u64)total << 12, (u64)free << 12);
 763         printk(KERN_DEBUG "%s  block: 0x%08x\n",
 764                prefix, mm->block_size << 12);
 765 }
 766
 767 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
 768         nouveau_vram_manager_init,
 769         nouveau_vram_manager_fini,
 770         nouveau_vram_manager_new,
 771         nouveau_vram_manager_del,
 772         nouveau_vram_manager_debug
 773 };