drivers/gpu/drm/i915/intel_sdvo.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2007 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  */
  28 #include <linux/i2c.h>
  29 #include <linux/delay.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "intel_drv.h"
  34 #include "drm_edid.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "intel_sdvo_regs.h"
  38
  39 #undef SDVO_DEBUG
  40 #define I915_SDVO       "i915_sdvo"
  41 struct intel_sdvo_priv {
  42         u8 slave_addr;
  43
  44         /* Register for the SDVO device: SDVOB or SDVOC */
  45         int output_device;
  46
  47         /* Active outputs controlled by this SDVO output */
  48         uint16_t controlled_output;
  49
  50         /*
  51          * Capabilities of the SDVO device returned by
  52          * i830_sdvo_get_capabilities()
  53          */
  54         struct intel_sdvo_caps caps;
  55
  56         /* Pixel clock limitations reported by the SDVO device, in kHz */
  57         int pixel_clock_min, pixel_clock_max;
  58
  59         /*
  60         * For multiple function SDVO device,
  61         * this is for current attached outputs.
  62         */
  63         uint16_t attached_output;
  64
  65         /**
  66          * This is set if we're going to treat the device as TV-out.
  67          *
  68          * While we have these nice friendly flags for output types that ought
  69          * to decide this for us, the S-Video output on our HDMI+S-Video card
  70          * shows up as RGB1 (VGA).
  71          */
  72         bool is_tv;
  73
  74         /**
  75          * This is set if we treat the device as HDMI, instead of DVI.
  76          */
  77         bool is_hdmi;
  78
  79         /**
  80          * This is set if we detect output of sdvo device as LVDS.
  81          */
  82         bool is_lvds;
  83
  84         /**
  85          * This is sdvo flags for input timing.
  86          */
  87         uint8_t sdvo_flags;
  88
  89         /**
  90          * This is sdvo fixed pannel mode pointer
  91          */
  92         struct drm_display_mode *sdvo_lvds_fixed_mode;
  93
  94         /**
  95          * Returned SDTV resolutions allowed for the current format, if the
  96          * device reported it.
  97          */
  98         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  99
 100         /**
 101          * Current selected TV format.
 102          *
 103          * This is stored in the same structure that's passed to the device, for
 104          * convenience.
 105          */
 106         struct intel_sdvo_tv_format tv_format;
 107
 108         /*
 109          * supported encoding mode, used to determine whether HDMI is
 110          * supported
 111          */
 112         struct intel_sdvo_encode encode;
 113
 114         /* DDC bus used by this SDVO output */
 115         uint8_t ddc_bus;
 116
 117         int save_sdvo_mult;
 118         u16 save_active_outputs;
 119         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
 120         struct intel_sdvo_dtd save_output_dtd[16];
 121         u32 save_SDVOX;
 122 };
 123
 124 static bool
 125 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
 126
 127 /**
 128  * Writes the SDVOB or SDVOC with the given value, but always writes both
 129  * SDVOB and SDVOC to work around apparent hardware issues (according to
 130  * comments in the BIOS).
 131  */
 132 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
 133 {
 134         struct drm_device *dev = intel_output->base.dev;
 135         struct drm_i915_private *dev_priv = dev->dev_private;
 136         struct intel_sdvo_priv   *sdvo_priv = intel_output->dev_priv;
 137         u32 bval = val, cval = val;
 138         int i;
 139
 140         if (sdvo_priv->output_device == SDVOB) {
 141                 cval = I915_READ(SDVOC);
 142         } else {
 143                 bval = I915_READ(SDVOB);
 144         }
 145         /*
 146          * Write the registers twice for luck. Sometimes,
 147          * writing them only once doesn't appear to 'stick'.
 148          * The BIOS does this too. Yay, magic
 149          */
 150         for (i = 0; i < 2; i++)
 151         {
 152                 I915_WRITE(SDVOB, bval);
 153                 I915_READ(SDVOB);
 154                 I915_WRITE(SDVOC, cval);
 155                 I915_READ(SDVOC);
 156         }
 157 }
 158
 159 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 160                                  u8 *ch)
 161 {
 162         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 163         u8 out_buf[2];
 164         u8 buf[2];
 165         int ret;
 166
 167         struct i2c_msg msgs[] = {
 168                 {
 169                         .addr = sdvo_priv->slave_addr >> 1,
 170                         .flags = 0,
 171                         .len = 1,
 172                         .buf = out_buf,
 173                 },
 174                 {
 175                         .addr = sdvo_priv->slave_addr >> 1,
 176                         .flags = I2C_M_RD,
 177                         .len = 1,
 178                         .buf = buf,
 179                 }
 180         };
 181
 182         out_buf[0] = addr;
 183         out_buf[1] = 0;
 184
 185         if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
 186         {
 187                 *ch = buf[0];
 188                 return true;
 189         }
 190
 191         DRM_DEBUG("i2c transfer returned %d\n", ret);
 192         return false;
 193 }
 194
 195 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
 196                                   u8 ch)
 197 {
 198         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 199         u8 out_buf[2];
 200         struct i2c_msg msgs[] = {
 201                 {
 202                         .addr = sdvo_priv->slave_addr >> 1,
 203                         .flags = 0,
 204                         .len = 2,
 205                         .buf = out_buf,
 206                 }
 207         };
 208
 209         out_buf[0] = addr;
 210         out_buf[1] = ch;
 211
 212         if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
 213         {
 214                 return true;
 215         }
 216         return false;
 217 }
 218
 219 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 220 /** Mapping of command numbers to names, for debug output */
 221 static const struct _sdvo_cmd_name {
 222         u8 cmd;
 223         char *name;
 224 } sdvo_cmd_names[] = {
 225     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 226     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 227     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 228     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 229     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 230     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 231     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 232     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 233     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 234     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 235     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 236     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 237     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 238     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 239     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 240     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 241     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 242     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 243     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 244     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 245     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 246     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 247     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 248     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 249     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 250     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 251     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 252     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 253     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 254     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 255     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 256     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 257     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 258     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 259     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 260     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 261     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 262     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 263     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 264     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 265     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 266     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 267     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 268     /* HDMI op code */
 269     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 270     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 271     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 272     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 273     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 274     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 275     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 276     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 277     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 278     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 279     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 280     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 281     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 282     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 283     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 284     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 285     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 286     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 287     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 288     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 289 };
 290
 291 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
 292 #define SDVO_PRIV(output)   ((struct intel_sdvo_priv *) (output)->dev_priv)
 293
 294 #ifdef SDVO_DEBUG
 295 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
 296                                    void *args, int args_len)
 297 {
 298         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 299         int i;
 300
 301         DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
 302                                 SDVO_NAME(sdvo_priv), cmd);
 303         for (i = 0; i < args_len; i++)
 304                 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
 305         for (; i < 8; i++)
 306                 DRM_LOG_KMS("   ");
 307         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
 308                 if (cmd == sdvo_cmd_names[i].cmd) {
 309                         DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
 310                         break;
 311                 }
 312         }
 313         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
 314                 DRM_LOG_KMS("(%02X)", cmd);
 315         DRM_LOG_KMS("\n");
 316 }
 317 #else
 318 #define intel_sdvo_debug_write(o, c, a, l)
 319 #endif
 320
 321 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
 322                                  void *args, int args_len)
 323 {
 324         int i;
 325
 326         intel_sdvo_debug_write(intel_output, cmd, args, args_len);
 327
 328         for (i = 0; i < args_len; i++) {
 329                 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
 330                                       ((u8*)args)[i]);
 331         }
 332
 333         intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
 334 }
 335
 336 #ifdef SDVO_DEBUG
 337 static const char *cmd_status_names[] = {
 338         "Power on",
 339         "Success",
 340         "Not supported",
 341         "Invalid arg",
 342         "Pending",
 343         "Target not specified",
 344         "Scaling not supported"
 345 };
 346
 347 static void intel_sdvo_debug_response(struct intel_output *intel_output,
 348                                       void *response, int response_len,
 349                                       u8 status)
 350 {
 351         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 352         int i;
 353
 354         DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
 355         for (i = 0; i < response_len; i++)
 356                 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
 357         for (; i < 8; i++)
 358                 DRM_LOG_KMS("   ");
 359         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 360                 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
 361         else
 362                 DRM_LOG_KMS("(??? %d)", status);
 363         DRM_LOG_KMS("\n");
 364 }
 365 #else
 366 #define intel_sdvo_debug_response(o, r, l, s)
 367 #endif
 368
 369 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
 370                                    void *response, int response_len)
 371 {
 372         int i;
 373         u8 status;
 374         u8 retry = 50;
 375
 376         while (retry--) {
 377                 /* Read the command response */
 378                 for (i = 0; i < response_len; i++) {
 379                         intel_sdvo_read_byte(intel_output,
 380                                              SDVO_I2C_RETURN_0 + i,
 381                                              &((u8 *)response)[i]);
 382                 }
 383
 384                 /* read the return status */
 385                 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
 386                                      &status);
 387
 388                 intel_sdvo_debug_response(intel_output, response, response_len,
 389                                           status);
 390                 if (status != SDVO_CMD_STATUS_PENDING)
 391                         return status;
 392
 393                 mdelay(50);
 394         }
 395
 396         return status;
 397 }
 398
 399 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 400 {
 401         if (mode->clock >= 100000)
 402                 return 1;
 403         else if (mode->clock >= 50000)
 404                 return 2;
 405         else
 406                 return 4;
 407 }
 408
 409 /**
 410  * Don't check status code from this as it switches the bus back to the
 411  * SDVO chips which defeats the purpose of doing a bus switch in the first
 412  * place.
 413  */
 414 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
 415                                               u8 target)
 416 {
 417         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
 418 }
 419
 420 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
 421 {
 422         struct intel_sdvo_set_target_input_args targets = {0};
 423         u8 status;
 424
 425         if (target_0 && target_1)
 426                 return SDVO_CMD_STATUS_NOTSUPP;
 427
 428         if (target_1)
 429                 targets.target_1 = 1;
 430
 431         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
 432                              sizeof(targets));
 433
 434         status = intel_sdvo_read_response(intel_output, NULL, 0);
 435
 436         return (status == SDVO_CMD_STATUS_SUCCESS);
 437 }
 438
 439 /**
 440  * Return whether each input is trained.
 441  *
 442  * This function is making an assumption about the layout of the response,
 443  * which should be checked against the docs.
 444  */
 445 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
 446 {
 447         struct intel_sdvo_get_trained_inputs_response response;
 448         u8 status;
 449
 450         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
 451         status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
 452         if (status != SDVO_CMD_STATUS_SUCCESS)
 453                 return false;
 454
 455         *input_1 = response.input0_trained;
 456         *input_2 = response.input1_trained;
 457         return true;
 458 }
 459
 460 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
 461                                           u16 *outputs)
 462 {
 463         u8 status;
 464
 465         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
 466         status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
 467
 468         return (status == SDVO_CMD_STATUS_SUCCESS);
 469 }
 470
 471 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
 472                                           u16 outputs)
 473 {
 474         u8 status;
 475
 476         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
 477                              sizeof(outputs));
 478         status = intel_sdvo_read_response(intel_output, NULL, 0);
 479         return (status == SDVO_CMD_STATUS_SUCCESS);
 480 }
 481
 482 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
 483                                                int mode)
 484 {
 485         u8 status, state = SDVO_ENCODER_STATE_ON;
 486
 487         switch (mode) {
 488         case DRM_MODE_DPMS_ON:
 489                 state = SDVO_ENCODER_STATE_ON;
 490                 break;
 491         case DRM_MODE_DPMS_STANDBY:
 492                 state = SDVO_ENCODER_STATE_STANDBY;
 493                 break;
 494         case DRM_MODE_DPMS_SUSPEND:
 495                 state = SDVO_ENCODER_STATE_SUSPEND;
 496                 break;
 497         case DRM_MODE_DPMS_OFF:
 498                 state = SDVO_ENCODER_STATE_OFF;
 499                 break;
 500         }
 501
 502         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
 503                              sizeof(state));
 504         status = intel_sdvo_read_response(intel_output, NULL, 0);
 505
 506         return (status == SDVO_CMD_STATUS_SUCCESS);
 507 }
 508
 509 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
 510                                                    int *clock_min,
 511                                                    int *clock_max)
 512 {
 513         struct intel_sdvo_pixel_clock_range clocks;
 514         u8 status;
 515
 516         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 517                              NULL, 0);
 518
 519         status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
 520
 521         if (status != SDVO_CMD_STATUS_SUCCESS)
 522                 return false;
 523
 524         /* Convert the values from units of 10 kHz to kHz. */
 525         *clock_min = clocks.min * 10;
 526         *clock_max = clocks.max * 10;
 527
 528         return true;
 529 }
 530
 531 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
 532                                          u16 outputs)
 533 {
 534         u8 status;
 535
 536         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
 537                              sizeof(outputs));
 538
 539         status = intel_sdvo_read_response(intel_output, NULL, 0);
 540         return (status == SDVO_CMD_STATUS_SUCCESS);
 541 }
 542
 543 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
 544                                   struct intel_sdvo_dtd *dtd)
 545 {
 546         u8 status;
 547
 548         intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
 549         status = intel_sdvo_read_response(intel_output, &dtd->part1,
 550                                           sizeof(dtd->part1));
 551         if (status != SDVO_CMD_STATUS_SUCCESS)
 552                 return false;
 553
 554         intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
 555         status = intel_sdvo_read_response(intel_output, &dtd->part2,
 556                                           sizeof(dtd->part2));
 557         if (status != SDVO_CMD_STATUS_SUCCESS)
 558                 return false;
 559
 560         return true;
 561 }
 562
 563 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
 564                                          struct intel_sdvo_dtd *dtd)
 565 {
 566         return intel_sdvo_get_timing(intel_output,
 567                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 568 }
 569
 570 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
 571                                          struct intel_sdvo_dtd *dtd)
 572 {
 573         return intel_sdvo_get_timing(intel_output,
 574                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
 575 }
 576
 577 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
 578                                   struct intel_sdvo_dtd *dtd)
 579 {
 580         u8 status;
 581
 582         intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
 583         status = intel_sdvo_read_response(intel_output, NULL, 0);
 584         if (status != SDVO_CMD_STATUS_SUCCESS)
 585                 return false;
 586
 587         intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 588         status = intel_sdvo_read_response(intel_output, NULL, 0);
 589         if (status != SDVO_CMD_STATUS_SUCCESS)
 590                 return false;
 591
 592         return true;
 593 }
 594
 595 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
 596                                          struct intel_sdvo_dtd *dtd)
 597 {
 598         return intel_sdvo_set_timing(intel_output,
 599                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 600 }
 601
 602 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
 603                                          struct intel_sdvo_dtd *dtd)
 604 {
 605         return intel_sdvo_set_timing(intel_output,
 606                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 607 }
 608
 609 static bool
 610 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
 611                                          uint16_t clock,
 612                                          uint16_t width,
 613                                          uint16_t height)
 614 {
 615         struct intel_sdvo_preferred_input_timing_args args;
 616         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 617         uint8_t status;
 618
 619         memset(&args, 0, sizeof(args));
 620         args.clock = clock;
 621         args.width = width;
 622         args.height = height;
 623         args.interlace = 0;
 624
 625         if (sdvo_priv->is_lvds &&
 626            (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
 627             sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
 628                 args.scaled = 1;
 629
 630         intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 631                              &args, sizeof(args));
 632         status = intel_sdvo_read_response(output, NULL, 0);
 633         if (status != SDVO_CMD_STATUS_SUCCESS)
 634                 return false;
 635
 636         return true;
 637 }
 638
 639 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
 640                                                   struct intel_sdvo_dtd *dtd)
 641 {
 642         bool status;
 643
 644         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 645                              NULL, 0);
 646
 647         status = intel_sdvo_read_response(output, &dtd->part1,
 648                                           sizeof(dtd->part1));
 649         if (status != SDVO_CMD_STATUS_SUCCESS)
 650                 return false;
 651
 652         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 653                              NULL, 0);
 654
 655         status = intel_sdvo_read_response(output, &dtd->part2,
 656                                           sizeof(dtd->part2));
 657         if (status != SDVO_CMD_STATUS_SUCCESS)
 658                 return false;
 659
 660         return false;
 661 }
 662
 663 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
 664 {
 665         u8 response, status;
 666
 667         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
 668         status = intel_sdvo_read_response(intel_output, &response, 1);
 669
 670         if (status != SDVO_CMD_STATUS_SUCCESS) {
 671                 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
 672                 return SDVO_CLOCK_RATE_MULT_1X;
 673         } else {
 674                 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
 675         }
 676
 677         return response;
 678 }
 679
 680 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
 681 {
 682         u8 status;
 683
 684         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 685         status = intel_sdvo_read_response(intel_output, NULL, 0);
 686         if (status != SDVO_CMD_STATUS_SUCCESS)
 687                 return false;
 688
 689         return true;
 690 }
 691
 692 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 693                                          struct drm_display_mode *mode)
 694 {
 695         uint16_t width, height;
 696         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 697         uint16_t h_sync_offset, v_sync_offset;
 698
 699         width = mode->crtc_hdisplay;
 700         height = mode->crtc_vdisplay;
 701
 702         /* do some mode translations */
 703         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 704         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 705
 706         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 707         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 708
 709         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 710         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 711
 712         dtd->part1.clock = mode->clock / 10;
 713         dtd->part1.h_active = width & 0xff;
 714         dtd->part1.h_blank = h_blank_len & 0xff;
 715         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 716                 ((h_blank_len >> 8) & 0xf);
 717         dtd->part1.v_active = height & 0xff;
 718         dtd->part1.v_blank = v_blank_len & 0xff;
 719         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 720                 ((v_blank_len >> 8) & 0xf);
 721
 722         dtd->part2.h_sync_off = h_sync_offset & 0xff;
 723         dtd->part2.h_sync_width = h_sync_len & 0xff;
 724         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 725                 (v_sync_len & 0xf);
 726         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 727                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 728                 ((v_sync_len & 0x30) >> 4);
 729
 730         dtd->part2.dtd_flags = 0x18;
 731         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 732                 dtd->part2.dtd_flags |= 0x2;
 733         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 734                 dtd->part2.dtd_flags |= 0x4;
 735
 736         dtd->part2.sdvo_flags = 0;
 737         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 738         dtd->part2.reserved = 0;
 739 }
 740
 741 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
 742                                          struct intel_sdvo_dtd *dtd)
 743 {
 744         mode->hdisplay = dtd->part1.h_active;
 745         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 746         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
 747         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 748         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
 749         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 750         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
 751         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
 752
 753         mode->vdisplay = dtd->part1.v_active;
 754         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 755         mode->vsync_start = mode->vdisplay;
 756         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 757         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 758         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 759         mode->vsync_end = mode->vsync_start +
 760                 (dtd->part2.v_sync_off_width & 0xf);
 761         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 762         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
 763         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
 764
 765         mode->clock = dtd->part1.clock * 10;
 766
 767         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 768         if (dtd->part2.dtd_flags & 0x2)
 769                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
 770         if (dtd->part2.dtd_flags & 0x4)
 771                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
 772 }
 773
 774 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
 775                                        struct intel_sdvo_encode *encode)
 776 {
 777         uint8_t status;
 778
 779         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
 780         status = intel_sdvo_read_response(output, encode, sizeof(*encode));
 781         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
 782                 memset(encode, 0, sizeof(*encode));
 783                 return false;
 784         }
 785
 786         return true;
 787 }
 788
 789 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
 790 {
 791         uint8_t status;
 792
 793         intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
 794         status = intel_sdvo_read_response(output, NULL, 0);
 795
 796         return (status == SDVO_CMD_STATUS_SUCCESS);
 797 }
 798
 799 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
 800                                        uint8_t mode)
 801 {
 802         uint8_t status;
 803
 804         intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 805         status = intel_sdvo_read_response(output, NULL, 0);
 806
 807         return (status == SDVO_CMD_STATUS_SUCCESS);
 808 }
 809
 810 #if 0
 811 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
 812 {
 813         int i, j;
 814         uint8_t set_buf_index[2];
 815         uint8_t av_split;
 816         uint8_t buf_size;
 817         uint8_t buf[48];
 818         uint8_t *pos;
 819
 820         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
 821         intel_sdvo_read_response(output, &av_split, 1);
 822
 823         for (i = 0; i <= av_split; i++) {
 824                 set_buf_index[0] = i; set_buf_index[1] = 0;
 825                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
 826                                      set_buf_index, 2);
 827                 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 828                 intel_sdvo_read_response(output, &buf_size, 1);
 829
 830                 pos = buf;
 831                 for (j = 0; j <= buf_size; j += 8) {
 832                         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
 833                                              NULL, 0);
 834                         intel_sdvo_read_response(output, pos, 8);
 835                         pos += 8;
 836                 }
 837         }
 838 }
 839 #endif
 840
 841 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
 842                                 uint8_t *data, int8_t size, uint8_t tx_rate)
 843 {
 844     uint8_t set_buf_index[2];
 845
 846     set_buf_index[0] = index;
 847     set_buf_index[1] = 0;
 848
 849     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
 850
 851     for (; size > 0; size -= 8) {
 852         intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
 853         data += 8;
 854     }
 855
 856     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
 857 }
 858
 859 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
 860 {
 861         uint8_t csum = 0;
 862         int i;
 863
 864         for (i = 0; i < size; i++)
 865                 csum += data[i];
 866
 867         return 0x100 - csum;
 868 }
 869
 870 #define DIP_TYPE_AVI    0x82
 871 #define DIP_VERSION_AVI 0x2
 872 #define DIP_LEN_AVI     13
 873
 874 struct dip_infoframe {
 875         uint8_t type;
 876         uint8_t version;
 877         uint8_t len;
 878         uint8_t checksum;
 879         union {
 880                 struct {
 881                         /* Packet Byte #1 */
 882                         uint8_t S:2;
 883                         uint8_t B:2;
 884                         uint8_t A:1;
 885                         uint8_t Y:2;
 886                         uint8_t rsvd1:1;
 887                         /* Packet Byte #2 */
 888                         uint8_t R:4;
 889                         uint8_t M:2;
 890                         uint8_t C:2;
 891                         /* Packet Byte #3 */
 892                         uint8_t SC:2;
 893                         uint8_t Q:2;
 894                         uint8_t EC:3;
 895                         uint8_t ITC:1;
 896                         /* Packet Byte #4 */
 897                         uint8_t VIC:7;
 898                         uint8_t rsvd2:1;
 899                         /* Packet Byte #5 */
 900                         uint8_t PR:4;
 901                         uint8_t rsvd3:4;
 902                         /* Packet Byte #6~13 */
 903                         uint16_t top_bar_end;
 904                         uint16_t bottom_bar_start;
 905                         uint16_t left_bar_end;
 906                         uint16_t right_bar_start;
 907                 } avi;
 908                 struct {
 909                         /* Packet Byte #1 */
 910                         uint8_t channel_count:3;
 911                         uint8_t rsvd1:1;
 912                         uint8_t coding_type:4;
 913                         /* Packet Byte #2 */
 914                         uint8_t sample_size:2; /* SS0, SS1 */
 915                         uint8_t sample_frequency:3;
 916                         uint8_t rsvd2:3;
 917                         /* Packet Byte #3 */
 918                         uint8_t coding_type_private:5;
 919                         uint8_t rsvd3:3;
 920                         /* Packet Byte #4 */
 921                         uint8_t channel_allocation;
 922                         /* Packet Byte #5 */
 923                         uint8_t rsvd4:3;
 924                         uint8_t level_shift:4;
 925                         uint8_t downmix_inhibit:1;
 926                 } audio;
 927                 uint8_t payload[28];
 928         } __attribute__ ((packed)) u;
 929 } __attribute__((packed));
 930
 931 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
 932                                          struct drm_display_mode * mode)
 933 {
 934         struct dip_infoframe avi_if = {
 935                 .type = DIP_TYPE_AVI,
 936                 .version = DIP_VERSION_AVI,
 937                 .len = DIP_LEN_AVI,
 938         };
 939
 940         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
 941                                                     4 + avi_if.len);
 942         intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
 943                                 SDVO_HBUF_TX_VSYNC);
 944 }
 945
 946 static void intel_sdvo_set_tv_format(struct intel_output *output)
 947 {
 948         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 949         struct intel_sdvo_tv_format *format, unset;
 950         u8 status;
 951
 952         format = &sdvo_priv->tv_format;
 953         memset(&unset, 0, sizeof(unset));
 954         if (memcmp(format, &unset, sizeof(*format))) {
 955                 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
 956                                 SDVO_NAME(sdvo_priv));
 957                 format->ntsc_m = 1;
 958                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
 959                                 sizeof(*format));
 960                 status = intel_sdvo_read_response(output, NULL, 0);
 961                 if (status != SDVO_CMD_STATUS_SUCCESS)
 962                         DRM_DEBUG("%s: Failed to set TV format\n",
 963                                         SDVO_NAME(sdvo_priv));
 964         }
 965 }
 966
 967 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
 968                                   struct drm_display_mode *mode,
 969                                   struct drm_display_mode *adjusted_mode)
 970 {
 971         struct intel_output *output = enc_to_intel_output(encoder);
 972         struct intel_sdvo_priv *dev_priv = output->dev_priv;
 973
 974         if (dev_priv->is_tv) {
 975                 struct intel_sdvo_dtd output_dtd;
 976                 bool success;
 977
 978                 /* We need to construct preferred input timings based on our
 979                  * output timings.  To do that, we have to set the output
 980                  * timings, even though this isn't really the right place in
 981                  * the sequence to do it. Oh well.
 982                  */
 983
 984
 985                 /* Set output timings */
 986                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 987                 intel_sdvo_set_target_output(output,
 988                                              dev_priv->controlled_output);
 989                 intel_sdvo_set_output_timing(output, &output_dtd);
 990
 991                 /* Set the input timing to the screen. Assume always input 0. */
 992                 intel_sdvo_set_target_input(output, true, false);
 993
 994
 995                 success = intel_sdvo_create_preferred_input_timing(output,
 996                                                                    mode->clock / 10,
 997                                                                    mode->hdisplay,
 998                                                                    mode->vdisplay);
 999                 if (success) {
1000                         struct intel_sdvo_dtd input_dtd;
1001
1002                         intel_sdvo_get_preferred_input_timing(output,
1003                                                              &input_dtd);
1004                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1005                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1006
1007                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1008
1009                         mode->clock = adjusted_mode->clock;
1010
1011                         adjusted_mode->clock *=
1012                                 intel_sdvo_get_pixel_multiplier(mode);
1013                 } else {
1014                         return false;
1015                 }
1016         } else if (dev_priv->is_lvds) {
1017                 struct intel_sdvo_dtd output_dtd;
1018                 bool success;
1019
1020                 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1021                 /* Set output timings */
1022                 intel_sdvo_get_dtd_from_mode(&output_dtd,
1023                                 dev_priv->sdvo_lvds_fixed_mode);
1024
1025                 intel_sdvo_set_target_output(output,
1026                                              dev_priv->controlled_output);
1027                 intel_sdvo_set_output_timing(output, &output_dtd);
1028
1029                 /* Set the input timing to the screen. Assume always input 0. */
1030                 intel_sdvo_set_target_input(output, true, false);
1031
1032
1033                 success = intel_sdvo_create_preferred_input_timing(
1034                                 output,
1035                                 mode->clock / 10,
1036                                 mode->hdisplay,
1037                                 mode->vdisplay);
1038
1039                 if (success) {
1040                         struct intel_sdvo_dtd input_dtd;
1041
1042                         intel_sdvo_get_preferred_input_timing(output,
1043                                                              &input_dtd);
1044                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1045                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1046
1047                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1048
1049                         mode->clock = adjusted_mode->clock;
1050
1051                         adjusted_mode->clock *=
1052                                 intel_sdvo_get_pixel_multiplier(mode);
1053                 } else {
1054                         return false;
1055                 }
1056
1057         } else {
1058                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
1059                  * SDVO device will be told of the multiplier during mode_set.
1060                  */
1061                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1062         }
1063         return true;
1064 }
1065
1066 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1067                                 struct drm_display_mode *mode,
1068                                 struct drm_display_mode *adjusted_mode)
1069 {
1070         struct drm_device *dev = encoder->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         struct drm_crtc *crtc = encoder->crtc;
1073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1074         struct intel_output *output = enc_to_intel_output(encoder);
1075         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1076         u32 sdvox = 0;
1077         int sdvo_pixel_multiply;
1078         struct intel_sdvo_in_out_map in_out;
1079         struct intel_sdvo_dtd input_dtd;
1080         u8 status;
1081
1082         if (!mode)
1083                 return;
1084
1085         /* First, set the input mapping for the first input to our controlled
1086          * output. This is only correct if we're a single-input device, in
1087          * which case the first input is the output from the appropriate SDVO
1088          * channel on the motherboard.  In a two-input device, the first input
1089          * will be SDVOB and the second SDVOC.
1090          */
1091         in_out.in0 = sdvo_priv->controlled_output;
1092         in_out.in1 = 0;
1093
1094         intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1095                              &in_out, sizeof(in_out));
1096         status = intel_sdvo_read_response(output, NULL, 0);
1097
1098         if (sdvo_priv->is_hdmi) {
1099                 intel_sdvo_set_avi_infoframe(output, mode);
1100                 sdvox |= SDVO_AUDIO_ENABLE;
1101         }
1102
1103         /* We have tried to get input timing in mode_fixup, and filled into
1104            adjusted_mode */
1105         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1106                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1107                 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1108         } else
1109                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1110
1111         /* If it's a TV, we already set the output timing in mode_fixup.
1112          * Otherwise, the output timing is equal to the input timing.
1113          */
1114         if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1115                 /* Set the output timing to the screen */
1116                 intel_sdvo_set_target_output(output,
1117                                              sdvo_priv->controlled_output);
1118                 intel_sdvo_set_output_timing(output, &input_dtd);
1119         }
1120
1121         /* Set the input timing to the screen. Assume always input 0. */
1122         intel_sdvo_set_target_input(output, true, false);
1123
1124         if (sdvo_priv->is_tv)
1125                 intel_sdvo_set_tv_format(output);
1126
1127         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1128          * provide the device with a timing it can support, if it supports that
1129          * feature.  However, presumably we would need to adjust the CRTC to
1130          * output the preferred timing, and we don't support that currently.
1131          */
1132 #if 0
1133         success = intel_sdvo_create_preferred_input_timing(output, clock,
1134                                                            width, height);
1135         if (success) {
1136                 struct intel_sdvo_dtd *input_dtd;
1137
1138                 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1139                 intel_sdvo_set_input_timing(output, &input_dtd);
1140         }
1141 #else
1142         intel_sdvo_set_input_timing(output, &input_dtd);
1143 #endif
1144
1145         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1146         case 1:
1147                 intel_sdvo_set_clock_rate_mult(output,
1148                                                SDVO_CLOCK_RATE_MULT_1X);
1149                 break;
1150         case 2:
1151                 intel_sdvo_set_clock_rate_mult(output,
1152                                                SDVO_CLOCK_RATE_MULT_2X);
1153                 break;
1154         case 4:
1155                 intel_sdvo_set_clock_rate_mult(output,
1156                                                SDVO_CLOCK_RATE_MULT_4X);
1157                 break;
1158         }
1159
1160         /* Set the SDVO control regs. */
1161         if (IS_I965G(dev)) {
1162                 sdvox |= SDVO_BORDER_ENABLE |
1163                         SDVO_VSYNC_ACTIVE_HIGH |
1164                         SDVO_HSYNC_ACTIVE_HIGH;
1165         } else {
1166                 sdvox |= I915_READ(sdvo_priv->output_device);
1167                 switch (sdvo_priv->output_device) {
1168                 case SDVOB:
1169                         sdvox &= SDVOB_PRESERVE_MASK;
1170                         break;
1171                 case SDVOC:
1172                         sdvox &= SDVOC_PRESERVE_MASK;
1173                         break;
1174                 }
1175                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1176         }
1177         if (intel_crtc->pipe == 1)
1178                 sdvox |= SDVO_PIPE_B_SELECT;
1179
1180         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1181         if (IS_I965G(dev)) {
1182                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1183         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1184                 /* done in crtc_mode_set as it lives inside the dpll register */
1185         } else {
1186                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1187         }
1188
1189         if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1190                 sdvox |= SDVO_STALL_SELECT;
1191         intel_sdvo_write_sdvox(output, sdvox);
1192 }
1193
1194 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1195 {
1196         struct drm_device *dev = encoder->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         struct intel_output *intel_output = enc_to_intel_output(encoder);
1199         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1200         u32 temp;
1201
1202         if (mode != DRM_MODE_DPMS_ON) {
1203                 intel_sdvo_set_active_outputs(intel_output, 0);
1204                 if (0)
1205                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1206
1207                 if (mode == DRM_MODE_DPMS_OFF) {
1208                         temp = I915_READ(sdvo_priv->output_device);
1209                         if ((temp & SDVO_ENABLE) != 0) {
1210                                 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1211                         }
1212                 }
1213         } else {
1214                 bool input1, input2;
1215                 int i;
1216                 u8 status;
1217
1218                 temp = I915_READ(sdvo_priv->output_device);
1219                 if ((temp & SDVO_ENABLE) == 0)
1220                         intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1221                 for (i = 0; i < 2; i++)
1222                   intel_wait_for_vblank(dev);
1223
1224                 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1225                                                        &input2);
1226
1227
1228                 /* Warn if the device reported failure to sync.
1229                  * A lot of SDVO devices fail to notify of sync, but it's
1230                  * a given it the status is a success, we succeeded.
1231                  */
1232                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1233                         DRM_DEBUG("First %s output reported failure to sync\n",
1234                                    SDVO_NAME(sdvo_priv));
1235                 }
1236
1237                 if (0)
1238                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1239                 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1240         }
1241         return;
1242 }
1243
1244 static void intel_sdvo_save(struct drm_connector *connector)
1245 {
1246         struct drm_device *dev = connector->dev;
1247         struct drm_i915_private *dev_priv = dev->dev_private;
1248         struct intel_output *intel_output = to_intel_output(connector);
1249         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1250         int o;
1251
1252         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1253         intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1254
1255         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1256                 intel_sdvo_set_target_input(intel_output, true, false);
1257                 intel_sdvo_get_input_timing(intel_output,
1258                                             &sdvo_priv->save_input_dtd_1);
1259         }
1260
1261         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1262                 intel_sdvo_set_target_input(intel_output, false, true);
1263                 intel_sdvo_get_input_timing(intel_output,
1264                                             &sdvo_priv->save_input_dtd_2);
1265         }
1266
1267         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1268         {
1269                 u16  this_output = (1 << o);
1270                 if (sdvo_priv->caps.output_flags & this_output)
1271                 {
1272                         intel_sdvo_set_target_output(intel_output, this_output);
1273                         intel_sdvo_get_output_timing(intel_output,
1274                                                      &sdvo_priv->save_output_dtd[o]);
1275                 }
1276         }
1277         if (sdvo_priv->is_tv) {
1278                 /* XXX: Save TV format/enhancements. */
1279         }
1280
1281         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1282 }
1283
1284 static void intel_sdvo_restore(struct drm_connector *connector)
1285 {
1286         struct drm_device *dev = connector->dev;
1287         struct intel_output *intel_output = to_intel_output(connector);
1288         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1289         int o;
1290         int i;
1291         bool input1, input2;
1292         u8 status;
1293
1294         intel_sdvo_set_active_outputs(intel_output, 0);
1295
1296         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1297         {
1298                 u16  this_output = (1 << o);
1299                 if (sdvo_priv->caps.output_flags & this_output) {
1300                         intel_sdvo_set_target_output(intel_output, this_output);
1301                         intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1302                 }
1303         }
1304
1305         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1306                 intel_sdvo_set_target_input(intel_output, true, false);
1307                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1308         }
1309
1310         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1311                 intel_sdvo_set_target_input(intel_output, false, true);
1312                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1313         }
1314
1315         intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1316
1317         if (sdvo_priv->is_tv) {
1318                 /* XXX: Restore TV format/enhancements. */
1319         }
1320
1321         intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1322
1323         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1324         {
1325                 for (i = 0; i < 2; i++)
1326                         intel_wait_for_vblank(dev);
1327                 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1328                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1329                         DRM_DEBUG("First %s output reported failure to sync\n",
1330                                    SDVO_NAME(sdvo_priv));
1331         }
1332
1333         intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1334 }
1335
1336 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1337                                  struct drm_display_mode *mode)
1338 {
1339         struct intel_output *intel_output = to_intel_output(connector);
1340         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1341
1342         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1343                 return MODE_NO_DBLESCAN;
1344
1345         if (sdvo_priv->pixel_clock_min > mode->clock)
1346                 return MODE_CLOCK_LOW;
1347
1348         if (sdvo_priv->pixel_clock_max < mode->clock)
1349                 return MODE_CLOCK_HIGH;
1350
1351         if (sdvo_priv->is_lvds == true) {
1352                 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1353                         return MODE_PANEL;
1354
1355                 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1356                         return MODE_PANEL;
1357
1358                 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1359                         return MODE_PANEL;
1360         }
1361
1362         return MODE_OK;
1363 }
1364
1365 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1366 {
1367         u8 status;
1368
1369         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1370         status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1371         if (status != SDVO_CMD_STATUS_SUCCESS)
1372                 return false;
1373
1374         return true;
1375 }
1376
1377 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1378 {
1379         struct drm_connector *connector = NULL;
1380         struct intel_output *iout = NULL;
1381         struct intel_sdvo_priv *sdvo;
1382
1383         /* find the sdvo connector */
1384         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1385                 iout = to_intel_output(connector);
1386
1387                 if (iout->type != INTEL_OUTPUT_SDVO)
1388                         continue;
1389
1390                 sdvo = iout->dev_priv;
1391
1392                 if (sdvo->output_device == SDVOB && sdvoB)
1393                         return connector;
1394
1395                 if (sdvo->output_device == SDVOC && !sdvoB)
1396                         return connector;
1397
1398         }
1399
1400         return NULL;
1401 }
1402
1403 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1404 {
1405         u8 response[2];
1406         u8 status;
1407         struct intel_output *intel_output;
1408         DRM_DEBUG("\n");
1409
1410         if (!connector)
1411                 return 0;
1412
1413         intel_output = to_intel_output(connector);
1414
1415         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1416         status = intel_sdvo_read_response(intel_output, &response, 2);
1417
1418         if (response[0] !=0)
1419                 return 1;
1420
1421         return 0;
1422 }
1423
1424 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1425 {
1426         u8 response[2];
1427         u8 status;
1428         struct intel_output *intel_output = to_intel_output(connector);
1429
1430         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1431         intel_sdvo_read_response(intel_output, &response, 2);
1432
1433         if (on) {
1434                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1435                 status = intel_sdvo_read_response(intel_output, &response, 2);
1436
1437                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1438         } else {
1439                 response[0] = 0;
1440                 response[1] = 0;
1441                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1442         }
1443
1444         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1445         intel_sdvo_read_response(intel_output, &response, 2);
1446 }
1447
1448 static bool
1449 intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1450 {
1451         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1452         int caps = 0;
1453
1454         if (sdvo_priv->caps.output_flags &
1455                 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1456                 caps++;
1457         if (sdvo_priv->caps.output_flags &
1458                 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1459                 caps++;
1460         if (sdvo_priv->caps.output_flags &
1461                 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1462                 caps++;
1463         if (sdvo_priv->caps.output_flags &
1464                 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1465                 caps++;
1466         if (sdvo_priv->caps.output_flags &
1467                 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1468                 caps++;
1469
1470         if (sdvo_priv->caps.output_flags &
1471                 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1472                 caps++;
1473
1474         if (sdvo_priv->caps.output_flags &
1475                 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1476                 caps++;
1477
1478         return (caps > 1);
1479 }
1480
1481 enum drm_connector_status
1482 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1483 {
1484         struct intel_output *intel_output = to_intel_output(connector);
1485         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1486         enum drm_connector_status status = connector_status_connected;
1487         struct edid *edid = NULL;
1488
1489         edid = drm_get_edid(&intel_output->base,
1490                             intel_output->ddc_bus);
1491         if (edid != NULL) {
1492                 /* Don't report the output as connected if it's a DVI-I
1493                  * connector with a non-digital EDID coming out.
1494                  */
1495                 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1496                         if (edid->input & DRM_EDID_INPUT_DIGITAL)
1497                                 sdvo_priv->is_hdmi =
1498                                         drm_detect_hdmi_monitor(edid);
1499                         else
1500                                 status = connector_status_disconnected;
1501                 }
1502
1503                 kfree(edid);
1504                 intel_output->base.display_info.raw_edid = NULL;
1505
1506         } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1507                 status = connector_status_disconnected;
1508
1509         return status;
1510 }
1511
1512 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1513 {
1514         uint16_t response;
1515         u8 status;
1516         struct intel_output *intel_output = to_intel_output(connector);
1517         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1518
1519         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1520         status = intel_sdvo_read_response(intel_output, &response, 2);
1521
1522         DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8);
1523
1524         if (status != SDVO_CMD_STATUS_SUCCESS)
1525                 return connector_status_unknown;
1526
1527         if (response == 0)
1528                 return connector_status_disconnected;
1529
1530         if (intel_sdvo_multifunc_encoder(intel_output) &&
1531                 sdvo_priv->attached_output != response) {
1532                 if (sdvo_priv->controlled_output != response &&
1533                         intel_sdvo_output_setup(intel_output, response) != true)
1534                         return connector_status_unknown;
1535                 sdvo_priv->attached_output = response;
1536         }
1537         return intel_sdvo_hdmi_sink_detect(connector, response);
1538 }
1539
1540 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1541 {
1542         struct intel_output *intel_output = to_intel_output(connector);
1543
1544         /* set the bus switch and get the modes */
1545         intel_ddc_get_modes(intel_output);
1546
1547 #if 0
1548         struct drm_device *dev = encoder->dev;
1549         struct drm_i915_private *dev_priv = dev->dev_private;
1550         /* Mac mini hack.  On this device, I get DDC through the analog, which
1551          * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
1552          * but it does load-detect as connected.  So, just steal the DDC bits
1553          * from analog when we fail at finding it the right way.
1554          */
1555         crt = xf86_config->output[0];
1556         intel_output = crt->driver_private;
1557         if (intel_output->type == I830_OUTPUT_ANALOG &&
1558             crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1559                 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1560                 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1561                 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1562         }
1563         if (edid_mon) {
1564                 xf86OutputSetEDID(output, edid_mon);
1565                 modes = xf86OutputGetEDIDModes(output);
1566         }
1567 #endif
1568 }
1569
1570 /**
1571  * This function checks the current TV format, and chooses a default if
1572  * it hasn't been set.
1573  */
1574 static void
1575 intel_sdvo_check_tv_format(struct intel_output *output)
1576 {
1577         struct intel_sdvo_priv *dev_priv = output->dev_priv;
1578         struct intel_sdvo_tv_format format;
1579         uint8_t status;
1580
1581         intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1582         status = intel_sdvo_read_response(output, &format, sizeof(format));
1583         if (status != SDVO_CMD_STATUS_SUCCESS)
1584                 return;
1585
1586         memcpy(&dev_priv->tv_format, &format, sizeof(format));
1587 }
1588
1589 /*
1590  * Set of SDVO TV modes.
1591  * Note!  This is in reply order (see loop in get_tv_modes).
1592  * XXX: all 60Hz refresh?
1593  */
1594 struct drm_display_mode sdvo_tv_modes[] = {
1595         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1596                    416, 0, 200, 201, 232, 233, 0,
1597                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1598         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1599                    416, 0, 240, 241, 272, 273, 0,
1600                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1601         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1602                    496, 0, 300, 301, 332, 333, 0,
1603                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1604         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1605                    736, 0, 350, 351, 382, 383, 0,
1606                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1607         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1608                    736, 0, 400, 401, 432, 433, 0,
1609                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1610         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1611                    736, 0, 480, 481, 512, 513, 0,
1612                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1613         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1614                    800, 0, 480, 481, 512, 513, 0,
1615                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1616         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1617                    800, 0, 576, 577, 608, 609, 0,
1618                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1619         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1620                    816, 0, 350, 351, 382, 383, 0,
1621                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1622         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1623                    816, 0, 400, 401, 432, 433, 0,
1624                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1625         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1626                    816, 0, 480, 481, 512, 513, 0,
1627                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1628         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1629                    816, 0, 540, 541, 572, 573, 0,
1630                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1631         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1632                    816, 0, 576, 577, 608, 609, 0,
1633                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1634         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1635                    864, 0, 576, 577, 608, 609, 0,
1636                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1637         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1638                    896, 0, 600, 601, 632, 633, 0,
1639                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1640         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1641                    928, 0, 624, 625, 656, 657, 0,
1642                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1643         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1644                    1016, 0, 766, 767, 798, 799, 0,
1645                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1646         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1647                    1120, 0, 768, 769, 800, 801, 0,
1648                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1649         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1650                    1376, 0, 1024, 1025, 1056, 1057, 0,
1651                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1652 };
1653
1654 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1655 {
1656         struct intel_output *output = to_intel_output(connector);
1657         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1658         struct intel_sdvo_sdtv_resolution_request tv_res;
1659         uint32_t reply = 0;
1660         uint8_t status;
1661         int i = 0;
1662
1663         intel_sdvo_check_tv_format(output);
1664
1665         /* Read the list of supported input resolutions for the selected TV
1666          * format.
1667          */
1668         memset(&tv_res, 0, sizeof(tv_res));
1669         memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1670         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1671                              &tv_res, sizeof(tv_res));
1672         status = intel_sdvo_read_response(output, &reply, 3);
1673         if (status != SDVO_CMD_STATUS_SUCCESS)
1674                 return;
1675
1676         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1677                 if (reply & (1 << i)) {
1678                         struct drm_display_mode *nmode;
1679                         nmode = drm_mode_duplicate(connector->dev,
1680                                         &sdvo_tv_modes[i]);
1681                         if (nmode)
1682                                 drm_mode_probed_add(connector, nmode);
1683                 }
1684 }
1685
1686 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1687 {
1688         struct intel_output *intel_output = to_intel_output(connector);
1689         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1690         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1691         struct drm_display_mode *newmode;
1692
1693         /*
1694          * Attempt to get the mode list from DDC.
1695          * Assume that the preferred modes are
1696          * arranged in priority order.
1697          */
1698         intel_ddc_get_modes(intel_output);
1699         if (list_empty(&connector->probed_modes) == false)
1700                 goto end;
1701
1702         /* Fetch modes from VBT */
1703         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1704                 newmode = drm_mode_duplicate(connector->dev,
1705                                              dev_priv->sdvo_lvds_vbt_mode);
1706                 if (newmode != NULL) {
1707                         /* Guarantee the mode is preferred */
1708                         newmode->type = (DRM_MODE_TYPE_PREFERRED |
1709                                          DRM_MODE_TYPE_DRIVER);
1710                         drm_mode_probed_add(connector, newmode);
1711                 }
1712         }
1713
1714 end:
1715         list_for_each_entry(newmode, &connector->probed_modes, head) {
1716                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1717                         sdvo_priv->sdvo_lvds_fixed_mode =
1718                                 drm_mode_duplicate(connector->dev, newmode);
1719                         break;
1720                 }
1721         }
1722
1723 }
1724
1725 static int intel_sdvo_get_modes(struct drm_connector *connector)
1726 {
1727         struct intel_output *output = to_intel_output(connector);
1728         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1729
1730         if (sdvo_priv->is_tv)
1731                 intel_sdvo_get_tv_modes(connector);
1732         else if (sdvo_priv->is_lvds == true)
1733                 intel_sdvo_get_lvds_modes(connector);
1734         else
1735                 intel_sdvo_get_ddc_modes(connector);
1736
1737         if (list_empty(&connector->probed_modes))
1738                 return 0;
1739         return 1;
1740 }
1741
1742 static void intel_sdvo_destroy(struct drm_connector *connector)
1743 {
1744         struct intel_output *intel_output = to_intel_output(connector);
1745         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1746
1747         if (intel_output->i2c_bus)
1748                 intel_i2c_destroy(intel_output->i2c_bus);
1749         if (intel_output->ddc_bus)
1750                 intel_i2c_destroy(intel_output->ddc_bus);
1751
1752         if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1753                 drm_mode_destroy(connector->dev,
1754                                  sdvo_priv->sdvo_lvds_fixed_mode);
1755
1756         drm_sysfs_connector_remove(connector);
1757         drm_connector_cleanup(connector);
1758
1759         kfree(intel_output);
1760 }
1761
1762 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1763         .dpms = intel_sdvo_dpms,
1764         .mode_fixup = intel_sdvo_mode_fixup,
1765         .prepare = intel_encoder_prepare,
1766         .mode_set = intel_sdvo_mode_set,
1767         .commit = intel_encoder_commit,
1768 };
1769
1770 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1771         .dpms = drm_helper_connector_dpms,
1772         .save = intel_sdvo_save,
1773         .restore = intel_sdvo_restore,
1774         .detect = intel_sdvo_detect,
1775         .fill_modes = drm_helper_probe_single_connector_modes,
1776         .destroy = intel_sdvo_destroy,
1777 };
1778
1779 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1780         .get_modes = intel_sdvo_get_modes,
1781         .mode_valid = intel_sdvo_mode_valid,
1782         .best_encoder = intel_best_encoder,
1783 };
1784
1785 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1786 {
1787         drm_encoder_cleanup(encoder);
1788 }
1789
1790 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1791         .destroy = intel_sdvo_enc_destroy,
1792 };
1793
1794
1795 /**
1796  * Choose the appropriate DDC bus for control bus switch command for this
1797  * SDVO output based on the controlled output.
1798  *
1799  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1800  * outputs, then LVDS outputs.
1801  */
1802 static void
1803 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1804 {
1805         uint16_t mask = 0;
1806         unsigned int num_bits;
1807
1808         /* Make a mask of outputs less than or equal to our own priority in the
1809          * list.
1810          */
1811         switch (dev_priv->controlled_output) {
1812         case SDVO_OUTPUT_LVDS1:
1813                 mask |= SDVO_OUTPUT_LVDS1;
1814         case SDVO_OUTPUT_LVDS0:
1815                 mask |= SDVO_OUTPUT_LVDS0;
1816         case SDVO_OUTPUT_TMDS1:
1817                 mask |= SDVO_OUTPUT_TMDS1;
1818         case SDVO_OUTPUT_TMDS0:
1819                 mask |= SDVO_OUTPUT_TMDS0;
1820         case SDVO_OUTPUT_RGB1:
1821                 mask |= SDVO_OUTPUT_RGB1;
1822         case SDVO_OUTPUT_RGB0:
1823                 mask |= SDVO_OUTPUT_RGB0;
1824                 break;
1825         }
1826
1827         /* Count bits to find what number we are in the priority list. */
1828         mask &= dev_priv->caps.output_flags;
1829         num_bits = hweight16(mask);
1830         if (num_bits > 3) {
1831                 /* if more than 3 outputs, default to DDC bus 3 for now */
1832                 num_bits = 3;
1833         }
1834
1835         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1836         dev_priv->ddc_bus = 1 << num_bits;
1837 }
1838
1839 static bool
1840 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1841 {
1842         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1843         uint8_t status;
1844
1845         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1846
1847         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1848         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1849         if (status != SDVO_CMD_STATUS_SUCCESS)
1850                 return false;
1851         return true;
1852 }
1853
1854 static struct intel_output *
1855 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1856 {
1857         struct drm_device *dev = chan->drm_dev;
1858         struct drm_connector *connector;
1859         struct intel_output *intel_output = NULL;
1860
1861         list_for_each_entry(connector,
1862                         &dev->mode_config.connector_list, head) {
1863                 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
1864                         intel_output = to_intel_output(connector);
1865                         break;
1866                 }
1867         }
1868         return intel_output;
1869 }
1870
1871 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1872                                   struct i2c_msg msgs[], int num)
1873 {
1874         struct intel_output *intel_output;
1875         struct intel_sdvo_priv *sdvo_priv;
1876         struct i2c_algo_bit_data *algo_data;
1877         const struct i2c_algorithm *algo;
1878
1879         algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1880         intel_output =
1881                 intel_sdvo_chan_to_intel_output(
1882                                 (struct intel_i2c_chan *)(algo_data->data));
1883         if (intel_output == NULL)
1884                 return -EINVAL;
1885
1886         sdvo_priv = intel_output->dev_priv;
1887         algo = intel_output->i2c_bus->algo;
1888
1889         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1890         return algo->master_xfer(i2c_adap, msgs, num);
1891 }
1892
1893 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1894         .master_xfer    = intel_sdvo_master_xfer,
1895 };
1896
1897 static u8
1898 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1899 {
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         struct sdvo_device_mapping *my_mapping, *other_mapping;
1902
1903         if (output_device == SDVOB) {
1904                 my_mapping = &dev_priv->sdvo_mappings[0];
1905                 other_mapping = &dev_priv->sdvo_mappings[1];
1906         } else {
1907                 my_mapping = &dev_priv->sdvo_mappings[1];
1908                 other_mapping = &dev_priv->sdvo_mappings[0];
1909         }
1910
1911         /* If the BIOS described our SDVO device, take advantage of it. */
1912         if (my_mapping->slave_addr)
1913                 return my_mapping->slave_addr;
1914
1915         /* If the BIOS only described a different SDVO device, use the
1916          * address that it isn't using.
1917          */
1918         if (other_mapping->slave_addr) {
1919                 if (other_mapping->slave_addr == 0x70)
1920                         return 0x72;
1921                 else
1922                         return 0x70;
1923         }
1924
1925         /* No SDVO device info is found for another DVO port,
1926          * so use mapping assumption we had before BIOS parsing.
1927          */
1928         if (output_device == SDVOB)
1929                 return 0x70;
1930         else
1931                 return 0x72;
1932 }
1933
1934 static bool
1935 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1936 {
1937         struct drm_connector *connector = &intel_output->base;
1938         struct drm_encoder *encoder = &intel_output->enc;
1939         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1940         bool ret = true, registered = false;
1941
1942         sdvo_priv->is_tv = false;
1943         intel_output->needs_tv_clock = false;
1944         sdvo_priv->is_lvds = false;
1945
1946         if (device_is_registered(&connector->kdev)) {
1947                 drm_sysfs_connector_remove(connector);
1948                 registered = true;
1949         }
1950
1951         if (flags &
1952             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1953                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1954                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1955                 else
1956                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1957
1958                 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
1959                 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
1960
1961                 if (intel_sdvo_get_supp_encode(intel_output,
1962                                                &sdvo_priv->encode) &&
1963                     intel_sdvo_get_digital_encoding_mode(intel_output) &&
1964                     sdvo_priv->is_hdmi) {
1965                         /* enable hdmi encoding mode if supported */
1966                         intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1967                         intel_sdvo_set_colorimetry(intel_output,
1968                                                    SDVO_COLORIMETRY_RGB256);
1969                         connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
1970                         intel_output->clone_mask =
1971                                         (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
1972                                         (1 << INTEL_ANALOG_CLONE_BIT);
1973                 }
1974         } else if (flags & SDVO_OUTPUT_SVID0) {
1975
1976                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1977                 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
1978                 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1979                 sdvo_priv->is_tv = true;
1980                 intel_output->needs_tv_clock = true;
1981                 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
1982         } else if (flags & SDVO_OUTPUT_RGB0) {
1983
1984                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1985                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1986                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1987                 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
1988                                         (1 << INTEL_ANALOG_CLONE_BIT);
1989         } else if (flags & SDVO_OUTPUT_RGB1) {
1990
1991                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1992                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1993                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1994         } else if (flags & SDVO_OUTPUT_LVDS0) {
1995
1996                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1997                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1998                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1999                 sdvo_priv->is_lvds = true;
2000                 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2001                                         (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2002         } else if (flags & SDVO_OUTPUT_LVDS1) {
2003
2004                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2005                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2006                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2007                 sdvo_priv->is_lvds = true;
2008                 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2009                                         (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2010         } else {
2011
2012                 unsigned char bytes[2];
2013
2014                 sdvo_priv->controlled_output = 0;
2015                 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2016                 DRM_DEBUG_KMS(I915_SDVO,
2017                                 "%s: Unknown SDVO output type (0x%02x%02x)\n",
2018                                   SDVO_NAME(sdvo_priv),
2019                                   bytes[0], bytes[1]);
2020                 ret = false;
2021         }
2022         intel_output->crtc_mask = (1 << 0) | (1 << 1);
2023
2024         if (ret && registered)
2025                 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2026
2027
2028         return ret;
2029
2030 }
2031
2032 bool intel_sdvo_init(struct drm_device *dev, int output_device)
2033 {
2034         struct drm_connector *connector;
2035         struct intel_output *intel_output;
2036         struct intel_sdvo_priv *sdvo_priv;
2037
2038         u8 ch[0x40];
2039         int i;
2040
2041         intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2042         if (!intel_output) {
2043                 return false;
2044         }
2045
2046         sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
2047         sdvo_priv->output_device = output_device;
2048
2049         intel_output->dev_priv = sdvo_priv;
2050         intel_output->type = INTEL_OUTPUT_SDVO;
2051
2052         /* setup the DDC bus. */
2053         if (output_device == SDVOB)
2054                 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2055         else
2056                 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2057
2058         if (!intel_output->i2c_bus)
2059                 goto err_inteloutput;
2060
2061         sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
2062
2063         /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2064         intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
2065
2066         /* Read the regs to test if we can talk to the device */
2067         for (i = 0; i < 0x40; i++) {
2068                 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2069                         DRM_DEBUG_KMS(I915_SDVO,
2070                                         "No SDVO device found on SDVO%c\n",
2071                                         output_device == SDVOB ? 'B' : 'C');
2072                         goto err_i2c;
2073                 }
2074         }
2075
2076         /* setup the DDC bus. */
2077         if (output_device == SDVOB)
2078                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2079         else
2080                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2081
2082         if (intel_output->ddc_bus == NULL)
2083                 goto err_i2c;
2084
2085         /* Wrap with our custom algo which switches to DDC mode */
2086         intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2087
2088         /* In defaut case sdvo lvds is false */
2089         intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2090
2091         if (intel_sdvo_output_setup(intel_output,
2092                                     sdvo_priv->caps.output_flags) != true) {
2093                 DRM_DEBUG("SDVO output failed to setup on SDVO%c\n",
2094                           output_device == SDVOB ? 'B' : 'C');
2095                 goto err_i2c;
2096         }
2097
2098
2099         connector = &intel_output->base;
2100         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2101                            connector->connector_type);
2102
2103         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2104         connector->interlace_allowed = 0;
2105         connector->doublescan_allowed = 0;
2106         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2107
2108         drm_encoder_init(dev, &intel_output->enc,
2109                         &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2110
2111         drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2112
2113         drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2114         drm_sysfs_connector_add(connector);
2115
2116         intel_sdvo_select_ddc_bus(sdvo_priv);
2117
2118         /* Set the input timing to the screen. Assume always input 0. */
2119         intel_sdvo_set_target_input(intel_output, true, false);
2120
2121         intel_sdvo_get_input_pixel_clock_range(intel_output,
2122                                                &sdvo_priv->pixel_clock_min,
2123                                                &sdvo_priv->pixel_clock_max);
2124
2125
2126         DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
2127                         "clock range %dMHz - %dMHz, "
2128                         "input 1: %c, input 2: %c, "
2129                         "output 1: %c, output 2: %c\n",
2130                         SDVO_NAME(sdvo_priv),
2131                         sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2132                         sdvo_priv->caps.device_rev_id,
2133                         sdvo_priv->pixel_clock_min / 1000,
2134                         sdvo_priv->pixel_clock_max / 1000,
2135                         (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2136                         (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2137                         /* check currently supported outputs */
2138                         sdvo_priv->caps.output_flags &
2139                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2140                         sdvo_priv->caps.output_flags &
2141                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2142
2143         return true;
2144
2145 err_i2c:
2146         if (intel_output->ddc_bus != NULL)
2147                 intel_i2c_destroy(intel_output->ddc_bus);
2148         if (intel_output->i2c_bus != NULL)
2149                 intel_i2c_destroy(intel_output->i2c_bus);
2150 err_inteloutput:
2151         kfree(intel_output);
2152
2153         return false;
2154 }